Impedance controlled AFE

Abstract

An analog front end (AFE) for an impedance sensor that modulates differential inputs from an impedance-based sensor using digitally controlled impedance. A digitally controlled impedance may be coupled between the differential input and one or more reference voltages. In some embodiments, the use of digitally controlled impedance may allow a preamplifier to be omitted from the AFE, or allow for a reduction in the gain of the preamplifier, thereby reducing noise associated with the preamplifier.

Description

Technical Field

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of the filing date of U.S. Provisional Patent Application No. 63 / 267,260, filed on January 28, 2022, the disclosure of which is incorporated herein by reference. Background Art

[0003] The present disclosure relates generally to analog front end circuits for sensors, and more particularly to impedance controlled analog front end circuits.

[0004] The analog front end (AFE) is used to process sensor information from various sensors. In many cases, the sensor can be a capacitive sensor. Capacitive sensors can include MEMs capacitors or capacitors, such as in microphones, piezoelectric transducers, such as in various applications, or various electrode transmission devices, such as in the medical field. In some cases, other sensors can be used, such as resistive sensors, which can be in the form of piezoresistive silicon nanowires.

[0005] Sensor readout may include amplification of the signal from the sensor (eg, by a preamplifier), filtering and analog-to-digital conversion of the amplified signal, and possibly various digital operations on the digitized signal. Preamplifiers are often used to allow processing of low power signals provided by the sensor.

[0006] However, the amplification and analog-to-digital conversion of the signal may introduce noise into the signal from the sensor. Using a preamplifier with a higher gain can generally allow processing of lower power input signals, but may also produce excessive total harmonic distortion for higher power input signals. For example, for audio microphones, sensitive microphones with high gain preamplifiers may too often reach their acoustic overload point (sometimes considered to be at 10% total harmonic distortion). Summary of the invention

[0007] Some embodiments provide an impedance-controlled analog front end (AFE) for an impedance-based sensor, comprising: a filter having an input coupled to at least one output of the impedance-based sensor; an analog-to-digital converter (ADC) having an input coupled to the output of the filter, the ADC being configured to provide a digital output; and a digitally controlled impedance coupling the input of the filter to a reference voltage, the impedance of the digitally controlled impedance being based on the digital output of the ADC.

[0008] In some embodiments, the impedance-based sensor is a capacitive sensor and the digitally controlled impedance is a digitally controlled capacitor. In some embodiments, the digitally controlled capacitor includes a digitally controlled varactor. In some embodiments, the digitally controlled varactor includes a plurality of cells, each cell including a capacitor coupled between an output of the impedance-based sensor and one or more reference voltages. The one or more reference voltages include three reference voltages. In some embodiments, the digitally controlled capacitor includes a segmented charge digitally controlled impedance. In some embodiments, the ADC includes a quantizer. In some embodiments, the ADC includes a voltage controlled oscillator (VCO) quantizer. In some embodiments, the ADC includes a phase quantizer. In some embodiments, the filter includes an integrator. In some embodiments, the input of the filter is a differential input, wherein the digitally controlled impedance couples each differential input to a reference voltage.

[0009] These and other aspects of the invention are more fully understood after reading this disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram of a differential sensor coupled to an analog front end (AFE).

[0011] Figure 2 FIG. 4 is a block diagram of a differential capacitive sensor coupled to an AFE.

[0012] Figure 3 is a semi-schematic, semi-block diagram of a differential sensor coupled to a digitally controlled impedance AFE in accordance with aspects of the present invention.

[0013] Figure 4 is a semi-schematic, semi-block diagram of a differential capacitive sensor coupled to a digitally controlled impedance AFE in accordance with aspects of the present invention.

[0014] Figure 5 is a semi-schematic, semi-block diagram of a differential sensor coupled to a varactor digitally controlled impedance AFE in accordance with aspects of the present invention.

[0015] Figure 6 is a semi-schematic, semi-block diagram of a differential sensor coupled to a piecewise digitally controlled impedance AFE in accordance with aspects of the present invention.

[0016] Figure 7 is a semi-schematic, semi-block diagram of a differential sensor using a VCO quantizer coupled to a piecewise digitally controlled impedance AFE in accordance with aspects of the present invention.

[0017] Figure 8 is a semi-schematic, semi-block diagram of a differential sensor using a voltage-controlled delay loop and a phase quantizer coupled to a piecewise digitally controlled impedance AFE in accordance with aspects of the present invention.

[0018] Fig. 9 is a semi-schematic diagram of digitally controlled impedance using a static reference in accordance with aspects of the present invention.

[0019] Fig.10 is a semi-schematic diagram of a digitally controlled impedance using a static reference and including a pole in accordance with aspects of the present invention.

[0020] Fig.11 is a semi-schematic diagram of digitally controlled impedance using a follower reference in accordance with aspects of the present invention.

[0021] Fig.12 is a semi-schematic diagram of a digitally controlled impedance using a follower reference and including a pole in accordance with aspects of the present invention.

[0022] Fig.13 is a schematic diagram of an example of a switched capacitor high and low reference generator according to aspects of the present invention. DETAILED DESCRIPTION

[0023] Figure 1 1 is a block diagram of a differential sensor coupled to an analog front end (AFE). The differential sensor includes a pair of sensors 115a, b. The sensor is typically a capacitance-based sensor and can be, for example, a pressure detection sensor (such as an audio capacitor or a MEMs capacitance sensor), a piezoelectric sensor, or various electrode sensors used in the medical field. The sensor can be other types of sensors, such as resistance-based sensors, such as piezoresistive silicon nanowire sensors. The sensor provides a differential output to a readout circuit. In some embodiments, the pair of sensors can be replaced by a single sensor that provides a differential output. The readout circuit provides an analog front end (AFE) 113 for the sensor.

[0024] Figure 1 The AFE includes a preamplifier 117 for amplifying a low-level differential signal. The preamplifier may include, for example, a voltage follower circuit, a charge amplifier circuit, or some other amplification circuit system. The amplified signal is provided to a filter and an analog-to-digital converter 119, which filters and digitizes the amplified signal. The digital end 121 of the AFE can perform various functions, including filtering of digital signals, reshaping of digital signals, extraction of digital signals, or other functions. The digital end and the AFE as a whole provide an N-bit (or "bit") signal representing the input analog signal. The N-bit signal can be in the form of a pulse code modulation (PCM) signal, a pulse density modulation (PDM) signal, a time division multiplexing (TDM) signal, or a signal in some other format.

[0025] The preamplifier typically introduces noise into the signal, and the total noise may also increase with the input signal magnitude. A preamplifier with higher gain can effectively limit the effective dynamic range of the AFE.

[0026] Figure 2 2 is a block diagram of a differential capacitive sensor coupled to an AFE. The differential capacitive sensor includes a pair of capacitors 215a, b, wherein the differential capacitive sensor provides a differential output. In some embodiments, only a single capacitor may be used. In some embodiments, the sensor may be a single-ended sensor. The capacitor may be, for example, a MEMs capacitor.

[0027] like Figure 1 In the embodiment of the present invention, the AFE 213 providing the readout circuit system includes a preamplifier 217 for amplifying the low-level differential signal. The preamplifier may include, for example, a voltage follower circuit, a charge amplifier circuit, or some other amplification circuit system. The amplified signal is provided to a filter and an analog-to-digital converter 219, which filters and digitizes the amplified signal. The ADC may be, for example, a delta sigma ADC, a pipeline ADC, a successive approximation ADC, or some other ADC. The digital end 221 of the AFE may perform various functions, including filtering of digital signals, reshaping of digital signals, extraction of digital signals, or other functions. The digital end and the AFE as a whole provide an N-bit signal representing the input analog signal. The N-bit signal may be in the form of a pulse code modulation (PCM) signal, a pulse density modulation (PDM) signal, a time division multiplexing (TDM) signal, or a signal in some other format.

[0028] In various embodiments, the differential capacitive sensor can be used as an acoustic sensor, such as a microphone. Figure 1 As with any general transducer, the increased gain of the preamplifier can provide a microphone with greater sensitivity. The noise associated with higher gain can cause the microphone to reach its acoustic overload point, especially for larger input signals, thereby reducing the overall dynamic range of the microphone.

[0029] Figure 3 is a semi-schematic, semi-block diagram of a differential sensor coupled to a digitally controlled impedance AFE according to aspects of the present invention. Differential sensor 311 provides a differential output to AFE 315. Figure 3 The AFE includes a filter 317 and an ADC / quantizer, similar to Figure 1 and Figure 2 The filter filters the differential output of the differential sensor, and the ADC / quantizer converts the filtered signal into a quantized digital signal. In some embodiments, the ADC can be an oversampled Delta-Sigma (Δ∑) ADC. In various embodiments, and as Figure 3As shown in , the AFE does not include a preamplifier. In various embodiments, a preamplifier can be used between the sensor and the filter, but it is usually a preamplifier with a lower gain.

[0030] Figure 3 The AFE also includes a pair of controlled impedances 316a, b, each of which is coupled between a reference voltage and a corresponding one of the differential inputs from the differential sensor. The controlled impedances are coupled to the differential inputs before the filter in the signal processing chain. In some embodiments, the filter is an integrator. Each sensor of the differential sensor includes a capacitor and / or a resistor. The controlled impedance similarly includes a variable capacitor and / or a resistor. In most embodiments, the controlled impedance has the same type of impedance as each sensor of the differential sensor. In some embodiments, the sensor is a capacitive sensor. In some embodiments, the sensor is a resistive sensor. In some embodiments, when the sensor is a capacitive sensor, the impedance of the controlled impedance is capacitive. In some embodiments, when the sensor is a resistive sensor, the impedance of the controlled impedance is resistive.

[0031] The magnitude of the impedance of the controlled impedance varies based on the output of the ADC / quantizer. Figure 3 In some embodiments, the magnitude of the impedance of the controlled impedance is modulated by the output of the ADC / quantizer. In some embodiments, the impedance of the controlled impedance is modulated so that the input to the filter can be considered as a virtual ground.

[0032] Figure 4 is a semi-schematic, semi-block diagram of a differential capacitive sensor coupled to a digitally controlled impedance AFE in accordance with aspects of the present invention. Figure 4 The block diagram is similar to Figure 3 but with capacitors as the sensor and controlled impedance. Figure 4 In the embodiment, the sensor includes a pair of capacitive sensors, such as MEMs sensors, and the sensor provides a differential output V INP 、V INM The differential output is provided to the filter 317 of the AFE 415. The output of the filter is provided to the ADC / quantizer which digitizes its input signal into an N-bit output signal.

[0033] The digitally controlled impedances 416a, b are each coupled between a voltage reference and a corresponding one of the differential outputs of the sensor. Figure 4 , the digitally controlled impedance 416a is coupled to V INP differential output, and the digitally controlled impedance 416b is coupled to V INM In some embodiments, the digitally controlled impedance can be controllably coupled to the positive voltage reference V at different times. Ref , negative voltage reference -V Refor ground V Gnd , rather than just a single voltage reference. The digitally controlled impedance has a controllable impedance. The digitally controlled impedance is determined based on the N-bit digital output signal from the ADC / quantizer. The digitally controlled impedance, which may be referred to as a digital-to-z converter, includes a variable capacitor. Figure 3 Like the AFE of FIG. 4 , the N-bit digital output signal can be used to modulate the impedance of the digitally controlled impedance so that the input to the filter can be regarded as a virtual ground.

[0034] Figure 5 1 is a semi-schematic, semi-block diagram of a differential sensor coupled to a varactor digitally controlled impedance AFE according to aspects of the present invention. Figure 4 As shown, the differential sensor 411 is a capacitive sensor. Figure 4 As shown, the differential sensor provides a differential output to filter 317, which in turn provides a filtered signal to ADC / quantizer 323. Figure 4 , digitally controlled impedances 516a, b are each coupled between a voltage reference and a corresponding one of the differential outputs of the sensor.

[0035] exist Figure 5 In this paper, the digitally controlled impedance can be considered as a varactor digital-to-z converter (DZC). Figure 5 The variable capacitor DZC includes a plurality of units. In some embodiments, the number of the plurality of units is proportional to the desired acoustic overload point. Each unit may include a capacitor, which may be considered to have a capacitance C LSB The lowest effective capacitor. Each capacitor has one plate coupled to the corresponding differential output and one plate coupled to V REF 、V -REF or V GND In some embodiments, it is assumed that the sensor is used with V BIAS bias and the ADC has N quantization levels, then the capacitor C LSB Equal to (ΔC m_max / N)x(V BIAS / V REF ). As an example, with a 2pF sensor and 143dB SPL at -38dBV, the total DAC capacitance is 10pF, and for a 256-level quantizer, the capacitance of each capacitor is 39fF.

[0036] Figure 6 is a semi-schematic, semi-block diagram of a differential sensor coupled to a piecewise digitally controlled impedance AFE in accordance with aspects of the present invention. Figure 4 and 5 As shown, the differential sensor 411 is a capacitive sensor. Figure 4 and 5As shown, the differential sensor provides a differential output to filter 317, which in turn provides a filtered signal to ADC / quantizer 323. Figure 5 The digitally controlled impedances 616a, b are each coupled between the reference voltage and a corresponding one of the differential outputs of the sensor.

[0037] exist Figure 6 In the example, the digitally controlled impedance is the impedance that can be called segmented DZC. Segmented DZC is similar to Figure 5 In some embodiments, each segmented DZC includes 8 units. Each segmented DZC uses the output of the first-order difference block 618 to track the slope of the output of the ADC / quantizer. In operation, the segmented DZC operates as a varactor DZC until the capacitors of the segmented DZC are all charged to a maximum or minimum level. If the capacitors of the segmented DZC are all charged to a maximum or minimum level, a reset operation is performed to allow the segmented DZC to restart as a varactor DZC. Therefore, for small signals, the noise of the segmented DZC is substantially the same as the noise of the varactor DZC. However, in the case where the input signal strength is near the reset point, noise modulation may occur.

[0038] Figure 7 is a semi-schematic, semi-block diagram of a differential sensor coupled to a piecewise digitally controlled impedance AFE using a VCO quantizer according to aspects of the present invention. Using a VCO quantizer can be beneficial in reducing the signal-to-quantization-to-noise ratio in the AFE. Figure 7 In the example of , the VCO quantizer includes a voltage to phase integrator 755, whose output is operated by a phase quantizer 757. In some embodiments, the phase quantizer can be implemented using an N-level phase quantizer 761. The voltage to phase integrator operates on the filtered signal provided by the integrator 753. The integrator receives a signal, for example, from the differential capacitive sensor 411, which passes through an inverter 751. The signal lines from the differential capacitive sensor are also each coupled to the corresponding segment charge DZC 616a, b.

[0039] Alternatively, a voltage controlled delay loop may be used, e.g. Figure 8 As described in . Figure 8 is a semi-schematic, semi-block diagram of a differential sensor coupled to a piecewise digitally controlled impedance AFE using a voltage controlled delay loop (VCDL) and a phase quantizer according to aspects of the present invention. Figure 8 In the embodiment, VCDL includes a voltage-to-delay integrator 861 and a phase quantizer 757, wherein the voltage-to-delay integrator replaces Figure 7 The voltage goes to the phase integrator.

[0040] Fig. 9 is a semi-schematic diagram of a segmented digital impedance controlled unit using a static reference according to aspects of the present invention. The segmented DZC units 911a, b are respectively coupled to V INP and V INM , providing the output from the differential sensor. The capacitor has a first switch coupled to V INP or V INM and coupled to V through a second switch PBUF or V MBUF A board. PBUF or V MBUF can be coupled to V during reset operation INP or V INM The other plate of the capacitor is coupled to the voltage reference V through three corresponding switches. ref , 2xV ref Or one of the earth.

[0041] Fig. 9 The cells of may also be used for a varactor DZC cell without using the first and second switches, and in some embodiments without using an input buffer.

[0042] Fig.10 is a semi-schematic diagram of a unit for piecewise digitally controlled impedance using a static reference and including a pole according to aspects of the present invention. Fig.10 The units 1011a, b are generally as described with respect to Fig. 9 However, Fig.10 The unit also includes a pole. Fig.10 In the embodiment, the pole is provided by using capacitors 1013 on the voltage reference side plates of the capacitors of coupling units 1011a, b and a resistor between these plates and the voltage reference. Likewise, in some embodiments, Fig.10 A cell of may be used for a varactor DZC cell without using the first and second switches, and in some embodiments, without using an input buffer.

[0043] Fig.11 1 is a semi-schematic diagram of a unit for piecewise digitally controlled impedance using a follower reference according to aspects of the present invention. Units 1111a, b are as shown in FIG. Fig. 9 911a, b, but the voltage reference tracks the voltage of the output of the differential sensor, rather than a static reference. Fig. 9 The reference voltage is the reference V ref , 2xV ref and ground, but the corresponding reference voltage of unit 1111a can be V PBUF Subtract the static reference V ref 、V PBUF Plus the static reference Vref , and V ref Similarly, the corresponding reference voltage of unit 1111b can be V MBUF Subtract the static reference V ref 、V MBUF Plus the static reference V ref , and V ref A switched capacitor adder / subtractor can be used to generate V PBUF Subtract the static reference V ref 、V PBUF Plus the static reference V ref , and V MBUF Subtract the static reference V ref 、V MBUF Plus the static reference V ref In some embodiments, a dummy version may be used to maintain the same switch current loading the switched capacitor reference for linearity and noise purposes. And, likewise, in some embodiments, Fig.11 A cell of may be used for a varactor DZC cell without using the first and second switches, and in some embodiments, without using an input buffer.

[0044] Fig.12 is a semi-schematic diagram of a cell using a follower reference and including a digitally controlled impedance of a pole according to aspects of the present invention. Fig.12 The units 1211a, b are generally as described with respect to Fig.11 However, Fig.12 The unit also includes the pole. Fig.10 As shown, in Fig.12 In some embodiments, the pole is provided by using capacitor 1213 on the voltage reference side plates of the capacitors of coupling units 1011a, b and a resistor between these plates and the voltage reference. Fig.12 A cell of may be used for a varactor DZC cell without using the first and second switches, and in some embodiments, without using an input buffer.

[0045] Fig.13 is a schematic diagram of an example of a switched capacitor high and low reference generator according to aspects of the present invention. Fig.13 It also shows that V INP An example of an input buffer 1311 of FIG. 13. A switched capacitor topology 1313 is used to create a voltage reference that tracks the voltage of each output of the differential sensor.

[0046] While the invention has been discussed in terms of various embodiments, it should be recognized that the invention encompasses novel and non-obvious claims supported by this disclosure.

Claims

1. An impedance-controlled analog front end (AFE) for an impedance-based sensor, comprising: a filter having an input coupled to at least one output of the impedance-based sensor; an analog-to-digital converter ADC having an input coupled to the output of the filter, the ADC being configured to provide a digital output; as well as A digitally controlled impedance couples the input of the filter to a reference voltage, the impedance of the digitally controlled impedance being based on the digital output of the ADC.

2. The impedance controlled AFE of claim 1, wherein the impedance-based sensor is a capacitive sensor and the digitally controlled impedance is a digitally controlled capacitance. 3 . The impedance controlled AFE of claim 2 , wherein the digitally controlled capacitor comprises a digitally controlled varactor. 4 . The impedance controlled AFE of claim 3 , wherein the digitally controlled varactor comprises a plurality of cells, each cell comprising a capacitor coupled between an output of an impedance-based sensor and one or more reference voltages. 5 . The impedance controlled AFE of claim 4 , wherein the one or more reference voltages include three reference voltages.

6. The impedance controlled AFE of claim 2, wherein the digitally controlled capacitance comprises a segmented charge digitally controlled impedance.

7. The impedance controlled AFE of claim 1, wherein the ADC comprises a quantizer.

8. The impedance controlled AFE according to claim 1, wherein: The ADC includes a voltage controlled oscillator (VCO) quantizer.

9. The impedance controlled AFE of claim 1, wherein the ADC comprises a phase quantizer.

10. The impedance controlled AFE of claim 1, wherein the filter comprises an integrator.

11. The impedance controlled AFE of claim 1, wherein inputs to the filter are differential inputs, wherein a digitally controlled impedance couples each of the differential inputs to a reference voltage.

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