Monitoring techniques for active optical components

Abstract

A diagnostic monitoring device includes a diagnostic monitor circuit configured to monitor analog diagnostic monitoring information and configured to convert the analog diagnostic monitoring information to digital diagnostic monitoring information, the diagnostic monitor circuit including a first clock or a first oscillator. The diagnostic monitoring device further includes a microcontroller including a register map, where the microcontroller is configured to receive the digital diagnostic monitoring information, store the digital diagnostic monitoring information in the register map, and provide a clock disabling command to the diagnostic monitor circuit. The microcontroller further includes a communication link for communicating with an external system external to the diagnostic monitoring device. The diagnostic monitor circuit is configured to receive a clock disabling command from the microcontroller, and in response to receiving the clock disabling command, the diagnostic monitor circuit is configured to disable the first clock or the first oscillator.

Description

[0001] Related patents and priorities

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 267,527, filed on February 3, 2022. This application is also related to PCT Application No. PCT / US2022 / 013938, filed on January 26, 2022, which claims the benefit of U.S. Provisional Application No. 63 / 141,866, filed on January 26, 2021, all of which are hereby incorporated by reference in their entireties. Technical Field

[0003] The present disclosure relates generally to the field of active optical products (eg, cabling systems and assemblies, etc.), and more particularly, to active optical products that include or provide an interface for digital diagnostics and maintenance of optical systems. Background Art

[0004] Data rates between modules have increased, at least in the avionics field, due to the desire to provide high-definition digital video for in-flight entertainment systems, cockpit displays, AFDX (Avionics Full Duplex Switched Ethernet) interconnect protocols, and the like. As a result, avionics system and aircraft manufacturers wish to take advantage of the extremely high bandwidth and light weight, ease of wiring, and resistance to electromagnetic interference (EMI) provided by fiber optic transmission media. Therefore, there is a need for avionics rack assemblies and associated modules to accommodate fiber optic connections between them (e.g., with active optical cable (AOC) components). One approach that has been adopted on the module side of such systems is to employ optical converter components inside the module, which are mounted on a (fixed or flexible) printed circuit board. The foregoing examples of avionics modules are intended to be non-limiting, and it is noted that the problems described herein of implementing fiber optic interfaces in electronic modules are suitable for applications in many other fields, and therefore the usefulness of the embodiments described herein is not limited to the avionics industry.

[0005] Digital diagnostic monitoring interface (DDMI) systems monitor certain aspects of the cable and the systems in which it is used, but such systems can introduce noise, may lack a method for predicting future failure of the cable, and may use magnetic ferrous materials, requiring some circuitry to be offloaded to a printed circuit board outside the cable.

[0006] The USB-C connector is reversible in that the USB-C connector at the end of the cable can be plugged into a USB-C receptacle on a device in more than one orientation. When different types of signals are sent on different pins within the connector, the orientation of the USB-C connector relative to the receptacle may not be detected.

[0007] High-quality cabling utilizing DDMI is expensive, and cables are sometimes difficult to replace, and the downtime when cables need to be replaced can prevent important machinery from being used productively. Traditional cabling does not have dynamically updated statistical modeling. Instead, such modeling typically requires an expensive modeling system external to the cable. Summary of the invention

[0008] In one embodiment, a diagnostic monitoring device is disclosed. The diagnostic monitoring device includes a diagnostic monitoring circuit, the diagnostic monitoring circuit is configured to monitor analog diagnostic monitoring information, and is configured to convert the analog diagnostic monitoring information into digital diagnostic monitoring information, the diagnostic monitoring circuit includes at least one of a first clock and a first oscillator. The diagnostic monitoring device further includes a microcontroller, the microcontroller includes a register map, wherein the microcontroller is configured to receive the digital diagnostic monitoring information, store the digital diagnostic monitoring information in the register map, and provide a clock disable command to the diagnostic monitoring circuit. The microcontroller further includes a communication link for communicating with an external system external to the diagnostic monitoring device. The diagnostic monitoring circuit is configured to receive a clock disable command from the microcontroller, and in response to receiving the clock disable command, the diagnostic monitoring circuit is configured to disable at least one of the first clock and the first oscillator.

[0009] In one embodiment, a diagnostic monitoring device is disclosed. The diagnostic monitoring device includes a diagnostic monitor circuit, and the diagnostic monitor circuit is configured to monitor one or more electrical characteristics of an associated device based on diagnostic monitoring information received at the diagnostic monitor circuit. The diagnostic monitor circuit includes a first clock or a first oscillator, and a microcontroller, and the microcontroller is configured to receive processed diagnostic monitoring information from the diagnostic monitor circuit and provide a clock disable signal to the diagnostic monitor circuit. The diagnostic monitor circuit also includes a second clock, wherein the diagnostic monitor circuit is configured to receive a clock disable command, and disable one or more of the first clock, the first oscillator, and the second clock based on the clock disable command.

[0010] In one embodiment, a transceiver module is disclosed. The transceiver module includes: a diagnostic monitor circuit configured to monitor one or more electrical characteristics of an associated device based on diagnostic monitoring information received at the diagnostic monitor circuit; and a microcontroller including a register map. The microcontroller is configured to receive the diagnostic monitoring information. The microcontroller also includes a first internal bus and a second internal bus in opposite directions. The transceiver also includes a connector configured to be coupled to an external system via a socket capable of accommodating the connector in more than one direction. The connector has a first pin in a first row of pins and a second pin in a second row of pins, the second row of pins being opposite to the first row of pins, the first pin being located a plurality of pins away from the start of the first row, and the second pin being located the same number of pins away from the start of the second row, wherein the start of the first row and the start of the second row are on opposite ends of the connector. The transceiver also includes a direction detection module and an external bus coupled to the connector. The direction detection module is configured to detect whether data information is received on the first pin or on the second pin, activate the first internal bus if the data information is received on the first pin, activate the second internal bus if the data information is received on the second pin, and operatively couple the activated first internal bus or the activated second internal bus to the external bus.

[0011] In one embodiment, a cable is disclosed that includes a diagnostic monitoring device. The diagnostic monitoring device is configured to collect diagnostic monitoring information related to the cable, wherein the diagnostic monitoring information includes an electrical characteristic of a diagnostic information type of the cable, associate and store the diagnostic monitoring information with an alarm criterion based on the diagnostic information type, and determine whether the electrical characteristic meets the alarm criterion for the diagnostic information type. In response to a determination that the electrical characteristic meets the alarm criterion, the diagnostic monitoring device is configured to generate an alarm signal; and transmit the alarm signal to one or more output pins of the cable. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Exemplary embodiments are shown in the reference figures of the accompanying drawings.The embodiments and figures disclosed herein are intended to be illustrative rather than limiting.

[0013] Figure 1 is a block diagram of an AOC assembly with an embedded DDMI according to some implementations.

[0014] Figure 2A-2B is a block diagram of example pinouts for a receptacle and an AOC plug configured to carry DDMI data in accordance with some implementations.

[0015] Figure 3 is a block diagram of an AOC diagnostic monitoring system with an external DDMI according to some embodiments.

[0016] Figure 4A is a block diagram of an AOC diagnostic monitoring system with embedded DDMI configured to deliver a DDMI flag using a single connector pin, according to some embodiments.

[0017] Figure 4B is a block diagram of an AOC diagnostic monitoring system with embedded DDMI configured to convey DDMI data using two connector pins implementing I2C in a direction agnostic manner, according to some embodiments.

[0018] Figure 4C is a block diagram of an AOC diagnostic monitoring system with embedded DDMI configured to convey DDMI data using two connector pins implementing I2C in a direction-specific manner, according to some embodiments.

[0019] Figure 5A-Figure 5B According to some embodiments, Figure 4C A block diagram of a multiplexing circuit system for an AOC diagnostic monitoring system is described.

[0020] Figure 6 is a flow chart according to one aspect of the present disclosure.

[0021] Fig. 7A and Figure 7B is a flow chart according to one aspect of the present disclosure. DETAILED DESCRIPTION

[0022] The following description is presented to enable one of ordinary skill in the art to make and use the invention, and is provided in the context of a patent application and its requirements. Various modifications to the described embodiments will be readily apparent to those skilled in the art, and the general principles taught herein may be applicable to other embodiments. Therefore, the present disclosure is not intended to limit the embodiments shown, but to conform to the widest scope consistent with the principles and features described herein (including modifications and equivalents) as defined within the scope of the appended claims. It should be noted that the drawings are not drawn to scale and are essentially illustrated in a manner that is considered to best illustrate the features of interest. With respect to these descriptions, descriptive terms may be used, however, the purpose of having adopted the terms is to facilitate the reader's understanding and is not intended to be limiting. In addition, for clarity of illustration, the figures are not drawn to scale.

[0023] The active optical cable (AOC) devices and systems described in the present disclosure include non-magnetic pluggable active optical transceiver products. Such AOC products may include optoelectronic converter modules integrated with configurable cable wiring. In addition, the AOC product maintains the engagement of the optical interface and is characterized by a removable insertion feature that facilitates engagement, indexing, and alignment with a mating interconnect device. In various embodiments, the AOC product includes an electronic embedded optical component designed to convert an electrical signal into an optical signal or to convert an optical signal into an electrical signal. The various components of the AOC product may include metal components, one or more of which may have a magnetic permeability value that causes the corresponding metal component to be considered non-magnetic. In addition, the AOC product may include or provide a digital interface that allows real-time access to equipment operating parameters, and includes an alarm and warning sign system that issues an alarm to the host system when the operating parameters exceed the normal operating range (factory setting).

[0024] In some embodiments, one or more components described herein may be or include metal. Any such metal component may be composed of a base metal layer, a subplating metal layer, and a final electroplating metal layer. The materials of the base metal layer, the subplating metal layer, and the final electroplating metal layer may be selected from a list including or consisting of the following non-magnetic metals, non-magnetic stainless steels, and various alloy combinations thereof: aluminum, silver, tin, phosphor bronze, brass, copper, gold, lead, titanium, silicon bronze, cobalt-chromium, beryllium copper. In some embodiments, any metal component may have a non-magnetic magnetic permeability (e.g., a value less than 1.0B / H (or less than about 1.0B / H)). In addition, non-magnetic components may be treated with a passivation process to produce a micro-coating protection that resists corrosion. AOC components may use a variety of PCB technologies suitable for producing non-magnetic solutions, including but not limited to hot air surface leveling (HASL), chemical nickel immersion gold (ENIG), copper palladium immersion gold (CPIG), immersion silver (IS), and organic solder protection (OSP) processes.

[0025] AOC products or assemblies as described in the present disclosure may be deployed in an electronics rack assembly used in the field of avionics. The electronics rack assembly may define one or more positions, each position being configured to accommodate a module. The rack assembly may include a connection backplane, so that each module may include a complementary connection arrangement that is blind-mated to the connection backplane when each module is installed. In this way, a large number of interface connections may be established or disconnected simultaneously, so that each module may be conveniently installed and / or replaced.

[0026] Active optical cable (AOC) is a cabling technology that accepts the same electrical input as traditional copper cables, but uses optical fibers between connectors. AOC uses electrical to optical and optical to electrical conversion on the cable end to improve the speed and distance performance of the cable without sacrificing compatibility with standard electrical interfaces. The conversion between electrical and optical signals is achieved by transceiver modules in the cable end. Each transceiver module includes a transceiver engine that both (i) converts electrical signals received from external devices into optical signals for transmission through the cable using light emitting technology (e.g., vertical cavity surface emitting lasers (VCSELs)) and (ii) converts optical signals received through the cable into electrical signals for transmission to external devices using detectors.

[0027] In some embodiments, the AOC assembly includes an enhanced digital diagnostic monitoring interface ("DDMI") using a universal optical transceiver module or converter. The interface can be operatively connected to an optoelectronic converter and / or a circuit board assembly. The interface allows real-time access to equipment operating parameters and includes an alarm and warning flag system that alerts the host system when the operating parameters exceed the normal operating range, which in some embodiments is factory set. The interface can implement diagnostics, reporting, signal detection, and status information using proprietary components (such as embedded microcontrollers and non-volatile memory) and discrete electrical components. The interface can further allow subsystem adjustments based on reported real-time / runtime values, such as adjustable bias current control, including but not limited to: RX power monitoring, TX power monitoring, bias current monitoring, supply voltage monitoring, and temperature monitoring. The reporting mechanism can be designed for in-band and / or out-of-band (e.g., sideband) usage models. The transceiver generates this diagnostic data by digitizing internal analog signals. A design goal will be to provide alarms for faulty systems and provide real-time statistics for predictive maintenance.

[0028] Modern transceiver modules support standard digital diagnostic monitoring (DDM) functionality. This feature is also known as digital optical monitoring (DOM). This capability allows real-time monitoring of transceiver operating parameters using DDMI. Parameters that can be monitored using DDMI include, but are not limited to, optical output power, optical input power, temperature, laser bias current, transceiver supply voltage, soft control, etc. This information is typically made available via DDMI, which allows the end user to display diagnostic data and alarms for the fiber optic transceiver and can be used to diagnose why the transceiver is not working.

[0029] Although DDMI is traditionally implemented outside the cable, DDMI can be embedded within the AOC assembly. Embedded DDMI provides real-time access to diagnostic data on the cable itself, which is more efficient than requiring external circuitry to perform diagnostics. However, depending on the application in which the cable is used (for example, in certain industrial applications with sensitive components), the embedded DDMI circuitry may cause an increase in electromagnetic interference (EMI), thereby reducing the signal-to-noise ratio (SNR). When AOC cabling is used for imaging applications such as magnetic resonance imaging (MRI) machines, the reduced SNR may cause artifacts. One way to address the reduced SNR is to shorten the length of cabling that can be used in the system. However, shorter cables may be inconvenient or even impossible to use in some cases.

[0030] This discussion covers several implementations of AOC components with embedded DDMI ( Figure 1 ), Example pinouts for a socket and AOC plug configured to carry DDMI data ( Figure 2A-2B ), AOC transceiver implementation using external DDMI ( Figure 3 ), several AOC transceiver implementations with embedded DDMI (including implementations using a single connector pin to communicate the DDMI flag ( Figure 4A ), an implementation that uses two connector pins that implement I2C in a direction-agnostic manner to communicate DDMI data ( Figure 4B ), and an implementation using two connector pins implementing I2C in a specific direction to communicate DDMI data ( Figure 4C and Figure 5A-5B )).also, Figure 4B and Figure 4C The embodiments described in include a DDMI clock disable feature to address EMI and reduced SNR caused by DDMI circuitry.

[0031] The following discussion provides additional details regarding multiple implementations of an AOC component having a transceiver module having different combinations of (i) embedded DDMI circuitry, (ii) configurable DDMI clock disable, (iii) direction-agnostic I2C communications for embedded DDMI data, and (iv) direction-specific I2C communications for embedded DDMI data.

[0032] Turning now to the drawings, in which like parts are designated by like reference numerals throughout the various figures, it is immediately noted that Figure 1 , Figure 114 is a block diagram of an AOC assembly 1400 with an embedded DDMI according to some embodiments. The AOC assembly 1400 includes a cable 1432 having active optical components (e.g., transceiver engines 1422 and 1462), diagnostic circuitry (e.g., DDMI 1420 and 1460), and connectors 1414 and 1456 (also referred to as plugs) on each end. The first connector 1414 is configured to deliver power and data signals to and from the cable 1432 to a downstream-facing port (DFP) 1412 of a host. The second connector 1454 is configured to deliver power and data signals to and from the cable 1432 to an upstream-facing port (UFP) 1412 of a device (e.g., a device acting as a peripheral to a host). The two ends of the cable 1432 are interchangeable, having the same pinout, transceiver circuitry, and DDMI circuitry.

[0033] Cable 1432 includes a transceiver module on each end. Transceiver module A (labeled 1416 in the figure) and transceiver module B (labeled 1456 in the figure) include similar components. Therefore, for the sake of brevity, and in order not to obscure more relevant aspects of the present disclosure, the following discussion only describes transceiver module A (1416) in detail.

[0034] The transceiver module 1416 includes an embedded diagnostic circuit system DDMI 1420, a transceiver engine 1422, and an electronic tag chip (eMarker) module 1424 (eg, a chip that records or marks the speed and maximum current of the cable). Figures 4A-4C DDMI 1420 is described in more detail below. In some implementations, DDMI 1420 is configured to deliver diagnostic data and communicate with DFP 1412 via sideband buses SBU1 and / or SBU2.

[0035] The transceiver engine includes transmit (TX) and receive (RX) circuit systems configured to convert signals between electrical and optical forms. The transmit circuit systems (1422a and 1462a) can include any electronic optical signal transmitter, such as a laser (e.g., a vertical cavity surface emitting laser (VCSEL)) or an LED. A VCSEL is a type of laser diode that emits light from its surface. The circular beam of a VCSEL is easy to couple with a fiber. The receive circuit systems (1422b and 1462b) can include any electronic optical signal detector configured to detect optical data emitted by the transmit circuit system on the other side of the cable.

[0036] Thus, the transceiver engine 1422 is configured to convert electrical data received from the DFP 1412 into optical data, and transmit the optical data via the laser 1422a and the fiber cable to the transceiver engine 1462 at the other end of the cable, and the transceiver engine 1462 is configured to receive the optical data at the detector 1462b, and convert the optical data back to electrical data for delivery to the UFP 1452. The transceiver engine 1462 is further configured to convert electrical data received from the UFP 1452 into optical data, and transmit the optical data via the laser 1462a and the fiber cable to the transceiver engine 1422 at the other end of the cable, and the transceiver engine 1422 is further configured to receive the optical data at the detector 1422b, and convert the optical data back to electrical data for delivery to the DFP 1412.

[0037] Cable 1432 is configured to deliver power VBUS and GND (power rail and ground rail). These power rails are sometimes referred to as power delivery (PD) buses and can be optimized for high-power applications (e.g., requiring up to 100 watts or more). Cable 1432 is configured to deliver high-speed optical data (by converting data into optical signals and using optical fibers to deliver optical signals, as described above) via SS TX and SS RX internal databases. Cable 1432 can optionally be configured to deliver low-speed data via an internal low-speed data bus (e.g., USB2.0 data bus). In addition, cable 1432 can be configured to deliver diagnostic data via sideband buses SBU1 and SBU2 and communicate with DFP 1412 and UPF 1452.

[0038] Electronic components (e.g., DDMI 1420 and transceiver engine 1422) in transceiver modules 1416 and 1456 are powered via the internal connector power bus VCONN. In some embodiments, DFP 1412 can use the internal connector power bus VCONN to power the internal electronics at both ends of the cable. In this case, since the host powers both ends of the cable, cable 1432 does not need to wait for peripheral devices to provide power. In some embodiments, VCONN can use 5V to power the internal electronics of cable 1432 (alternative embodiments may require more or less voltage).

[0039] The cable 1432 includes a communication channel CC for initially establishing a link between the DFP 1412 and the UFP 1452. When the cable 1432 is plugged into the devices DFP 1412 and UFP 1452, the devices establish an end-to-end link over the cable using the communication channel CC.

[0040] The cable 1432 can be configured to determine the cable direction (e.g., which end is plugged into the DFP and which end is plugged into the UFP) by sensing the voltage on the resistor divider circuit on the CC and VCONN lines. Specifically, the host device (e.g., DFP 1412) can include a pull-up resistor Rp on the CC and VCONN lines, and the peripheral device (e.g., UFP 1452) can include a pull-down resistor Rd on the CC and VCONN lines. Therefore, if the transceiver module senses that the voltage at the connector (e.g., 1414) is higher than a threshold, the transceiver module can determine that it is connected to the host (e.g., DFP 1412). On the other hand, if the transceiver module senses that the voltage at the connector (e.g., 1454) is lower than a threshold, the transceiver module can determine that it is connected to the peripheral device (e.g., UFP 1452).

[0041] The cable 1432 can be configured to determine the connector orientation (e.g., which end of the connector is aligned with which end of the port socket of the host or peripheral device) by comparing the voltages on the resistor divider circuits on the CC and VCONN lines. Specifically, the cable 1432 can include an internal pull-down resistor Ra on the VCONN line. Since resistors Ra and Rd provide a ground resistance that is only slightly greater than resistor Rd, the VCONN voltage at the connector will be slightly higher than the CC voltage at the connector. Therefore, by determining which voltage is higher, the transceiver module (e.g., 1416) can determine the direction in which the connector (e.g., 1414) is inserted into the device (e.g., DFP 1412).

[0042] Figure 2A-2B is a block diagram of example pinouts for a receptacle and an AOC plug configured to carry DDMI data in accordance with some implementations.

[0043] Socket pinout 1502 may represent the pinout of a host DFP 1412 socket or a device UFP 1452 socket. These pinouts correspond to the USB-C standard. Although USB-C is provided as an example to describe relevant aspects of the present disclosure, other pinout standards may also be implemented, as the concepts described herein may be equally applicable to any standard that supports active optical communication.

[0044] Referring to the socket pinout 1502, the power rails VBUS and GND are provided at pins A1, A4, A9, A12, B1, B4, B9, and B12. The high-speed data pins are provided at pins A2, A3, A10, A11 and B2, B3, B10, and B11. The low-speed data pins are provided at pins A6, A7, B6, and B7, and the configuration channel is provided at pins A5 and B5. Finally, the sideband channel (which may be customizable depending on the application) is provided at pins A8 and B8. The layout of these pins supports reversibility when it comes to plugging in cables.

[0045] Referring to the plug pinout 1504, power rails VBUS and GND are provided at pins A1, A4, A9, A12, B1, B4, B9 and B12, which are connected to corresponding pins in the socket pinout 1502. However, the high-speed data pins are only provided at one end of the cable, namely at pins A2, A3, B10 and B11. This is to support cable reversibility. In other words, either end of the cable can be plugged into the host, and the host and the cable will communicate in the same manner. Therefore, pins A10, A11, B2 and B3 are empty (not connected to the electronics inside the cable). For the same reason, the low-speed data pins are only provided at pins A6 and A7, with pins B6 and B7 being empty. The sideband channel at pins A8 and B8 (which may be customizable depending on the application) can be configured for I2C communication as data (SDA) and clock (SCL) lines, see below. Figure 4B-4C Described in more detail. The configuration channels at pins A5 and B5 can be configured as configuration channel CC and internal connector power rail VCONN, respectively.

[0046] As in Figure 2A and Figure 2BAs can be seen in , it is important for the electronics in the AOC assembly to determine the orientation of the plug relative to the socket (e.g., whether pin A1 in the plug is aligned with pin A1 in the socket or with pin B1 in the socket, whether pin A2 in the plug is aligned with pin A2 in the socket or with pin B2 in the socket, etc.). For embodiments in which the cable is reversible, only half of the plug can use the internal optical fiber to transport high-speed data communications. In addition, for embodiments in which the sideband channel is used for I2C communications between the host and the cable (e.g., for DDMI data and / or clock disable signals), it is important for the electronics in the AOC assembly to determine the orientation of the plug relative to the socket so that both the host and cable electronics agree on which sideband pins (SBU1, SBU2) are assigned to the I2C data signal (SDA) and which sideband pins are assigned to the I2C clock signal (SCL). Additionally, it is important for the electronics in the AOC assembly to orient the plug relative to the receptacle so that both the host and cable electronics agree on which configuration pins (CC1, CC2) are assigned to the configuration channel (CC) and which configuration pins are assigned to the internal connector power bus (VCONN).

[0047] Figure 3 is a block diagram of an AOC diagnostic monitoring system 1600 with external DDMI according to some embodiments. System 1600 is an embodiment of AOC assembly 1400 in which diagnostic monitoring is moved outside of the cable and instead included as monitoring circuit 1610 in DFP 1412 .

[0048] In system 1600, the cable includes transceiver module A (1416) as described above, which interfaces with DFP 1412 via connector 1414 as described above. Transceiver module A (1416) includes transceiver engine 1422, which converts signals between electrical and optical forms, sends and receives optical signals via fiber, and conveys the signals (in electrical form) to DFP 1412 (e.g., via copper conductors), as described above. Figure 3 Only certain components of the transceiver engine 1422 are depicted (e.g., receive circuitry 1422b), while others (e.g., transmit circuitry 1422a) are omitted for the sake of brevity and so as not to obscure more relevant concepts. The transceiver engine 1422 includes a photocurrent output monitor 1423, which includes circuitry configured to measure optical power when the receive circuitry 1422b receives optical data. Specifically, the photocurrent output monitoring circuitry 1423 senses at the receive circuitry 1422b the transmit circuitry 1462a on the opposite side of the cable ( Figure 1The measured optical power (the power output of the transmitting circuit system at the other end of the cable) or a value corresponding to the measured optical power to monitor the current I MON is transmitted from the transceiver engine 1422 in the form of.

[0049] The transceiver module A (1416) transmits the monitoring current IMON to the DFP 1412 using a sideband channel (eg, SBU1, pin A8). The monitoring circuit 1610 receives and analyzes the monitoring current IMON. MON , in order to determine the monitoring current I MON The monitoring circuit 1610 determines whether the monitoring current I is within acceptable parameters and, by extension, whether the transceiver engine 1422 is performing properly and / or whether there are any issues generally with the ability of the AOC to transmit optical signals from one end to the other. In some embodiments, the monitoring circuit 1610 uses a resistor 1606 (or any suitable circuitry configured to convert a current into a voltage) to convert the monitoring current I MON The voltage is converted into a voltage, the voltage is converted into a digital signal in an analog-to-digital (A / D) converter 1602, and the digital signal is sent to a microcontroller 1604. The microcontroller 1604 is configured to convert the digital signal (representing the monitoring current I MON ) is compared with a predefined threshold (e.g., by settings in a register map), and a flag is output if the digital signal is below a minimum threshold and / or above a maximum threshold. In some embodiments, the flag is a monitored signal (e.g., I MON ) violates one or more thresholds corresponding to normal operation of the AOC. Other circuit systems (not shown) in DFP 1412 can communicate the flag to the user via an output device (e.g., a display) or any other device configured to communicate a message to the user. In an alternative embodiment, the monitoring current I MON can be processed by microcontroller 1604 as described above, but without first MON converting to voltage and / or not converting I MON In some embodiments, the flags transmitted by the microcontroller are used by other applications (either embedded in the AOC or externally, such as in the DFP 1412) to perform predictive maintenance analysis (e.g., as described below with reference to Figure 6 and Figure 7A-7B described).

[0050] Although system 1600 provides access to diagnostic data associated with the AOC (optical power monitoring current I MON ), but the diagnostic data needs to be further processed in an external device (e.g., DFP 1412) to obtain actionable data (e.g., markers) that can be used to effectively discover and / or diagnose quality problems of the AOC. Figure 4A-4C Embodiments of an AOC having DDMI functionality embedded in the cable itself are described, thereby providing actionable diagnostic data without the need for a Figure 3 Embedding the DDMI functionality in the cable itself provides enhanced diagnostic monitoring capabilities, but also introduces other issues such as increased EMI and complications related to cable orientation. Figure 4A-4C , solutions to these problems are described in the following disclosure.

[0051] Figure 4A 1 is a block diagram of an AOC diagnostic monitoring system 1700 with embedded DDMI, configured to deliver a DDMI flag using a single connector pin, according to some embodiments. In the system 1700, the transceiver engine 1422 of the transceiver module A (1416) receives the optical signal at the detector 1422b as described above, and the optical current output monitor circuit system 1423 outputs the optical power monitoring current I as described above. MON However, the transceiver engine 1422 does not monitor the current I MON is sent to DFP 1412 for further processing, but the monitoring current I MON Delivered to the embedded DDMI 1720 included in the transceiver module of the cable.

[0052] The embedded DDMI 1720 includes the monitoring current I MON A current-to-voltage converter (e.g., a resistor) 1706 that converts the analog voltage to a voltage and an A / D converter 1702 that converts the analog voltage to a digital signal for processing by the microcontroller 1704. The microcontroller 1704 is configured (e.g., through settings in a register map) to receive the digital signal, compare the digital signal to one or more thresholds, and output a flag if the signal violates a threshold (e.g., is below a minimum threshold or above a maximum threshold). In other words, if the optical power monitoring current I MON If the current I is high enough or low enough to indicate a quality problem with the AOC (e.g., bad fiber, faulty laser detector, etc.), the microcontroller 1704 transmits a flag to the DFP 1412. The flag may be delivered to the DFP 1412 using a sideband channel (e.g., SBU1) or any other available channel. As described above, in an alternative embodiment, the monitoring current I MON May be processed by the microcontroller 1704 without first being converted into a voltage and / or without being converted into a digital signal.

[0053] Since DDMI 1720 is embedded in the AOC, DDMI 1720 can directly access additional monitoring data. In some embodiments, DDMI 1720 includes a diagnostic monitor circuit system 1708, which is configured to receive signals corresponding to receive circuit system power (RX power), transmit circuit system power (TX power), transceiver engine bias current, local supply voltage, local temperature and / or soft control. Diagnostic monitor circuit system 1708 can also monitor current I MON To monitor incoming optical power. In some embodiments, the diagnostic monitor circuit system 1708 includes I MON The processing circuitry (e.g., A / D converter 1702 and / or current to voltage converter 1706). The diagnostic monitor circuitry 1708 delivers the received signals to the microcontroller 1704, which is configured to compare each respective signal to a corresponding threshold value and transmit a flag to the DFP 1412 if one or more threshold values ​​are violated.

[0054] Diagnostic monitor circuitry 1708 includes (or is otherwise associated with) clock circuitry 1710, which includes a digital clock circuit and / or one or more oscillators. Clock circuitry 1710 generates one or more clock signals that synchronize the data processing functions (e.g., the reception, processing, and transmission of diagnostic data) of monitor circuitry 1708. Thus, the operation of clock circuitry 1710 is essential to the operation of diagnostic monitor circuitry 1708, and by extension, to the operation of DDMI 1720.

[0055] In some embodiments, the embedded DDMI 1720 (specifically, the diagnostic monitor circuit system 1708) can be a source of EMI during operation of a device (e.g., DFP 1412 and / or UFP 1452) connected to the AOC. For example, for an imaging device connected to the AOC, the increased EMI caused by the DDMI 1720 may cause image artifacts during operation of the imaging device. Therefore, it may be advantageous to disable the embedded DDMI 1720 during certain noise-sensitive operations involving the AOC. Thus, in some embodiments, the microcontroller 1704 can be configured to transmit a clock disable signal (CLK disable) to the clock circuit system 1710 to disable one or more digital clocks and / or one or more oscillators of the clock circuit system 1710, thereby stopping the operation of the diagnostic monitor circuit system 1708. This may be in response to receiving a clock disable instruction from an external device (e.g., DFP 1412). The external device may send such an instruction when performing noise-sensitive operations.

[0056] In some embodiments, the instruction to disable the DDMI clock circuit system 1710 can be sent via a dedicated pin (not shown), or via two sideband pins using I2C (as described below with reference to Figure 4B-4C 1704). Thus, to disable the DDMI circuitry, an application in the external device may send an instruction or command (e.g., via I2C) that controls the on or off state of the clock circuitry 1710. Such an instruction or command will disable all clocks associated with the diagnostic monitoring circuitry 1708. In some embodiments, the clock circuitry 1710 may also be responsible for running the microcontroller 1704 (e.g., starting operations involving the microcontroller and synchronizing these operations), or the microcontroller 1704 may include its own clock circuitry. In such an embodiment, additional circuitry (not shown) in the DDMI 1720 may be configured to disable the clock circuitry 1710 (or the clock circuitry of the microcontroller 1704) for a predefined period of time (e.g., until a timing delay expires). Thus, an unresponsive microcontroller (due to the clock circuitry 1710 or its own clock circuitry being disabled) will not prevent the clock circuitry 1710 from being turned back on, because the additional circuitry will wake up the clock circuitry 1710 at the end of the predefined period of time. In some implementations, at the end of the predefined period, the additional circuitry can be configured to enable or re-enable clock circuitry 1710 .

[0057] Figure 4B 1 is a block diagram of an AOC diagnostic monitoring system 1713 with an embedded DDMI configured to convey DDMI data using two connector pins that implement I2C in a direction-agnostic manner, according to some embodiments. System 1713 corresponds to system 1700, with the addition of an I2C bus implemented between the embedded DDMI 1720 (specifically, the microcontroller 1704 of the DDMI 1720) and the DFP 1412 via two sideband channels SBU1 and SBU2. I2C requires two channels (sometimes referred to as lines) for communication, namely a clock channel (SCL) and a data channel (SDA). The microcontroller 1704 can communicate with the DFP 1412 by using one sideband channel for SCL and another sideband channel for SDA. In order to determine which sideband channel corresponds to SCL and which sideband channel corresponds to SDA, the DFP 1412 can sense the direction of the AOC (e.g., by sensing the presence of resistor Ra, as described above with reference to Figure 1 ) to determine which channel is the configuration channel CC and which channel is the internal connector power channel VCONN, thereby providing direction information from which the positions of the two sideband channels SBU1 and SBU2 can be determined (for example, as Figure 2B depicted in ).

[0058] By implementing the I2C bus in the AOC, the DFP 1412 can transmit embedded messages including a clock disable command (configured to cause the microcontroller 1704 to issue a clock disable (CLK disable) signal to the clock circuit system 1710, as described above) and / or embedded messages including direction sensing determination (e.g., based on resistor Ra sensing as described above).

[0059] In the system 1713, the microcontroller 1704 is configured to carry SCL and SDA on the same channel regardless of the orientation of the AOC relative to the DFP 1412 socket. Thus, depending on the determined orientation of the two sideband channels carrying SCL and SDA, the DFP 1412 will need to be configured to switch which channel is assigned as SCL and which channel is assigned as SDA. For example, a connector 1414 plugged into the AOC in one orientation relative to the DFP 1412 socket may carry SCL to pin A8 of the DFP 1412 socket and SDA to pin B8 of the DFP 1412 socket, while a connector 1414 plugged into the AOC in the opposite orientation relative to the DFP 1412 socket may carry SCL to pin B8 (instead of A8) of the DFP 1412 socket and SDA to pin A8 (instead of B8) of the DFP 1412 socket. Thus, the I2C circuitry in DFP 1412 will be required to determine the orientation of connector 1414 and then handle the sideband pins accordingly (by assigning each to SCL and SDA, or vice versa). Figure 4C An implementation is described in which the microcontroller 1704 always delivers SCL and SDA to the same pins of the DFP 1412 regardless of the orientation of the connector 1414 .

[0060] Figure 4C is a block diagram of an AOC diagnostic monitoring system 1740 with embedded DDMI configured to convey DDMI data using two connector pins that implement I2C in a specific orientation, according to some embodiments. System 1740 corresponds to system 1713 with the addition of a multiplexer 1712 configured to select which of the two I2C buses provided by microcontroller 1704 to convey to an external device via connector 1414. As a result, the AOC's plug pins (e.g., sideband pins SBU1 and SBU2 in connector 1414) always convey SCL and SDA to the same socket pins of an external device, regardless of the orientation of the plug relative to the socket. As shown in FIG. Figure 4C, the SBU1 pin in the DFP 1412 is always assigned to SDA, and the SBU2 pin in the DFP 1412 is always assigned to SCL, regardless of the orientation of the SBU1 and SBU2 pins in the connector 1414 of the AOC. Alternatively, the SBU1 pin in the DFP 1412 may always be assigned to SCL, and the SBU2 pin in the DFP 1412 may always be assigned to SDA, regardless of the orientation of the SBU1 and SBU2 pins in the connector 1414 of the AOC. In order to provide the same clock or data channel to the same pin of the socket regardless of the orientation of the plug, the microcontroller 1704 determines the orientation of the plug relative to the socket and uses a multiplexer 1712 to assign pins SBU1 and SBU2 to one of the two I2C buses, wherein the first of the two I2C buses (I2C-1) is configured to have SCL on the first line and SDA on the second line, and the second of the two I2C buses (I2C-2) is configured to have SDA on the first line and SCL on the second line (the opposite of the configuration of I2C-1). In this way, the multiplexer 1712 always presents SCL and SDA to the external device in the correct order regardless of the orientation of the plug relative to the socket of the external device. In other words, the microcontroller 1704 and the multiplexer 1712 configure the pinout of the connector 1414 based on the orientation of the connector 1414 relative to the socket into which the connector 1414 is inserted.

[0061] Figure 5A-Figure 5B is a block diagram depicting multiplexing circuitry 1712 and corresponding direction-based I2C output configuration examples in greater detail, according to some embodiments.

[0062] Figure 5A and Figure 5B The DFP 1412 receptacle in both includes two pins configured for I2C communication, where pin A8 (corresponding to one of the two sideband channels) is assigned to SDA, and pin B8 (corresponding to the other of the two sideband channels) is assigned to SCL. For embodiments in which the receptacle is a USB-C receptacle, Figure 2A Depicts more details about the physical layout of these two pins.

[0063] Figure 5A and Figure 5B The cable plug (connector) 1414 in both cases includes two pins configured for I2C communication, where pin A8 (corresponding to one of the two sideband channels) is assigned to SDA or SCL, and pin B8 (corresponding to the other of the two sideband channels) is assigned to SCL or SDA. For embodiments in which the plug is a USB-C plug, Figure 2BDepicts more details about the physical layout of these two pins.

[0064] exist Figure 5A , connector 1414 is inserted into the DFP 1412 receptacle in a first direction such that receptacle pin A8 (SDA) is aligned with plug pin A8, and receptacle pin B8 (SCL) is aligned with plug pin B8. Thus, multiplexer 1712 presents the first I2C bus (I2C-1) to connector 1414 such that the SDA line at plug pin A8 is presented to the SDA line assigned to receptacle pin A8, and the SCL line at plug pin B8 is presented to the SCL line assigned to receptacle pin B8.

[0065] exist Figure 5B , connector 1414 is inserted into the DFP 1412 receptacle in a second direction opposite to the first direction such that receptacle pin A8 (SDA) is aligned with plug pin B8, and receptacle pin B8 (SCL) is aligned with plug pin A8. In this way, multiplexer 1712 presents the second I2C bus (I2C-2) to connector 1414 such that the SDA line at plug pin B8 is presented to the SDA line assigned to receptacle pin A8, and the SCL line at plug pin A8 is presented to the SCL line assigned to receptacle pin B8.

[0066] Therefore, regardless of the orientation of the plug relative to the receptacle, the receptacle always engages the same I2C signals from the plug. Specifically, since the SDA channel is presented on plug pins A8 or B8 (depending on the plug orientation) and the SCL channel is presented on plug pins B8 or A8 (depending on the plug orientation), receptacle pin A8 always engages the SDA channel in the cable, and receptacle pin B8 always engages the SCL channel in the cable.

[0067] Because DFP 1412 accommodates the same I2C channels regardless of the plug orientation, DFP 1412 does not need to be configured with complex circuitry to internally reallocate the SDA and SCL channels, thereby allowing a plug using the direction-based I2C output configuration described herein to interface with external devices that do not have dedicated I2C channel switching circuitry.

[0068] In About Figure 5A and Figure 5B In the described example, the microcontroller 1704 first uses the direction detection module 1804 to determine the direction of the plug relative to the socket, and then controls the multiplexer 1712 to present one of the two I2C buses according to the determined direction as described above, using the multiplexer control signal MUX Ctrl to control the internal switching circuit system of the multiplexer 1712, as depicted in the figure.

[0069] The direction detection module 1804 can determine the plug direction in a variety of ways. Figure 1 As described above, the DFP 1412 (such as a host computer) exposes a pull-up termination Rp on its CC and VCONN pins. The UFP 1452 (such as a peripheral) exposes a pull-down termination Rd on its CC and VCONN pins. The purpose of the Rp and Rd terminations on the CC pins is to identify the connection of the DFP to the UFP and the CC pins to be used for communication (i.e., distinguishing between the CC pins and the VCONN pins). To this end, the DFP monitors the two CC pins (CC1 & CC2) to determine a voltage lower than its unterminated voltage.

[0070] The cable exposes a pull-down termination Ra on its VCONN pin to signal the DFP that it needs power. The DFP must be able to distinguish the presence of Rd and Ra to know if there is an attached UFP and where to apply VCONN. One problem with this detection method is that the method detects the cable orientation (e.g., which end is plugged into the DFP 1412 and which end is plugged into the UFP 1452), but the method does not detect the orientation of the plug into the receptacle because while the receptacle may be universal, the cable or plug is not (e.g., the UFP 1452 is not plugged into the DFP 1412). Figure 2B depicted in ).

[0071] Thus, in some embodiments, the direction detection module 1804 can determine the plug orientation by sensing the different pull-up resistors on the SDA and SCL lines. For example, the SCL line in the DFP 1412 can use a pull-up resistor with a first resistance (e.g., 4kOhm), and the SDA line in the DFP 1412 can use a pull-up resistor with a second resistance (e.g., 6kOhm) different from the first resistance. The microcontroller 1704 can monitor the SDA and SCL lines to sense the condition of the socket based on the different pull-up resistors and place the internal SDA and SCL signals on the correct pins of the connector 1414 as described above.

[0072] Additionally or alternatively, the direction detection module 1805 can determine the plug direction by receiving an I2C wake-up command (e.g., 0xFF) from the DFP 1412 (because the cable is an I2C slave and the DFP 1412 is an I2C master), at which point the microcontroller 1704 analyzes the wake-up command to determine which pin is SCL and which pin is SDA (e.g., by analyzing each pin to see which is more likely to be a clock signal and / or which is more likely to be a data signal). Upon determining which pins are SDA and SCL, the microcontroller 1704 places the internal SDA and SCL signals on the correct pins of the connector 1414 as described above.

[0073] Additionally or alternatively, the direction detection module 1805 can determine the plug orientation by performing VCONN Ra sensing as described above, or receiving an embedded I2C message corresponding to the VCONN Ra sensing result from the DFP 1412 as described above (e.g., describing which line is CC and which line is VCONN), and placing the internal SDA and SCL signals on the correct pins of the connector 1414 as described above.

[0074] The examples described above with reference to Figures 14-5B relate to connector (plug and receptacle) pinouts that conform to the USB-C standard. However, the reference to USB-C is intended to illustrate concepts related to EMI and direction-based solutions to various problems arising from embedding DDMI functionality in an AOC. Other types of cable and connector pinouts and standards are equally applicable, as long as there is at least one power channel, at least one high-speed data channel, and in some embodiments, at least one sideband channel.

[0075] Thus, in some embodiments, a diagnostic monitoring device includes: a diagnostic monitor circuit (1708) configured to monitor analog diagnostic monitoring information (e.g., Figure 4A-4C ), and is configured to convert analog diagnostic monitoring information into digital diagnostic monitoring information, the diagnostic monitor circuit comprising a first clock or a first oscillator (1710); a microcontroller (1704) comprising a register map, wherein the microcontroller is configured to receive the digital diagnostic monitoring information, store the digital diagnostic monitoring information in the register map, and provide a clock disable command (CLK disable) to the diagnostic monitor circuit; wherein the microcontroller further comprises a communication link for communicating with an external system external to the diagnostic monitoring device. The communication link can be a wired communication link, or it can be a wireless communication link as discussed below. In embodiments where the link is a wired communication link, it can be a bus (e.g., a two-pin bus, such as Figure 4B I2C or Figure 4C Alternatively, the wired communication link may be a single pin bus such as a UART bus.

[0076] In some embodiments, the diagnostic monitor circuit may be configured to receive a clock disable command from a microcontroller, and in response to receiving the clock disable command, the diagnostic monitor circuit is configured to disable the first clock or the first oscillator. In some embodiments, the clock disable command is a clock disable signal. In some embodiments, the diagnostic monitoring circuit is further configured to receive a clock enable command, which is configured to enable the first clock or the first oscillator. In some embodiments, the microcontroller further includes a second clock, and wherein the clock disable command is further configured to disable the second clock. In some embodiments, the clock disable command is further configured to re-enable the second clock after the timing delay expires without receiving a separate clock enable command. In some embodiments, the clock disable command is a message received from an external system via a bus. In some embodiments, the analog diagnostic monitoring information includes at least one of received power, transmitted power, BIAS current, supply voltage, temperature, entering optical power monitoring, and soft control.

[0077] In some embodiments, any or all communications described herein as occurring over a communication link may occur over a wireless communication link. Such a wireless communication link may receive or send communications in addition to or in lieu of a wired communication link such as a bus. In some embodiments, the wireless communication link may communicate via the Bluetooth protocol, or may use other short, medium or long range wireless protocols, which may include 802.11 wireless networks known as "Wi-Fi".

[0078] In some embodiments, programming or reprogramming of the microcontroller 1704 may occur over a communication link. In some embodiments, such reprogramming may include, for example, firmware updates to the microcontroller 1704 or other components of the DDMI 1720.

[0079] In some embodiments, the diagnostic monitoring device includes: a diagnostic monitor circuit (1708) configured to monitor one or more electrical characteristics of an associated device (e.g., Figure 4A-4C ), the diagnostic monitor circuit comprising a first clock or a first oscillator (1710); and a microcontroller (1704), which is configured to receive processed diagnostic monitoring information from the diagnostic monitor circuit and provide a clock disable signal to the diagnostic monitor circuit, the microcontroller comprising a second clock, wherein the diagnostic monitor circuit is configured to receive a clock disable command (CLK disable), and disable one or more of the first clock, the first oscillator, and the second clock based on the clock disable command.

[0080] In some embodiments, the transceiver module (1416) includes a diagnostic monitor circuit (1710) configured to detect a fault based on diagnostic monitoring information (e.g., Figure 4A-4C ) to monitor one or more electrical characteristics; a microcontroller (1710) comprising a register map, wherein the microcontroller is configured to receive diagnostic monitoring information, wherein the microcontroller further comprises a first internal bus (I2C-1) and a second internal bus (I2C-2), wherein the first internal bus and the second internal bus have opposite directions (e.g., one bus assigns SDA to a first line and SCL to a second line, while the other bus assigns SCL to a first line and SDA to a second line); a connector (1414, 1504) configured For coupling to an external system via a socket (1502) capable of accommodating a connector in more than one orientation, the connector having a first pin (A8) in a first row of pins and a second pin (B8) in a second row of pins, the second row of pins being opposite the first row of pins, the first pin being located a plurality of pins away from a start point of the first row (e.g., eight pins away from A1), and the second pin being located the same number of pins away from a start point of the second row (e.g., eight pins away from B1), wherein the start point of the first row (e.g., A1) and the start point of the second row (e.g., B1) are on opposite ends of the connector; an external bus coupled to the connector ( Figure 4C and Figure 5A-Figure 5B 1712); a direction detection module (1804) configured to detect whether the data information is received on the first pin or on the second pin (e.g., based on the detected orientation of the connector relative to the socket); if the data information is received on the first pin, activate the first internal bus (e.g., transmit one of I2C-1 or I2C-2 to the connector via the multiplexer 1712); if the data information is received on the second pin, activate the second internal bus (e.g., transmit the other of I2C-1 or I2C-2 to the connector via the multiplexer 1712); and operatively couple the activated first internal bus or the activated second internal bus to the external bus (via the multiplexer 1712 and the connector 1414).

[0081] In some embodiments, the connector is a USB Type-C connector. In some embodiments, the direction detection module is configured to detect whether the data information is received on the first pin or on the second pin by measuring a first resistance of the first pin signal received on the first pin (a pull-up resistor of one of the clock line or the data line in the DFP 1412) and measuring a second resistance of the second pin signal received on the second pin (a pull-up resistor of the other of the clock line or the data line in the DFP 1412), and determining whether the first resistance or the second resistance matches the data pin resistance (or whether the first resistance is greater than or less than the second resistance, or whether the first resistance meets or does not meet a threshold associated with a corresponding pull-up resistor of a particular clock line or data line). In some embodiments, the direction detection module is configured to detect whether the data information is received on the first pin or on the second pin by determining which pin in the first row of pins or the second row of pins receives a wake-up command (e.g., an I2C wake-up command).

[0082] Now turn to Figure 6 , which shows a flow chart of a process by which a cable can perform statistical analysis of cable faults and generate alarms or warnings. FIG. 4A to FIG. 4C As discussed, the diagnostic monitoring device (e.g., diagnostic monitoring system 1700, 1713, and / or 1740) can be configured to collect (1902) diagnostic monitoring information associated with the cable. In some embodiments, the diagnostic monitoring device can include one or more diagnostic monitoring sensors to collect the diagnostic monitoring information. Examples of diagnostic monitoring sensors can include current sensors, voltage sensors, inertial measurement devices, accelerometers, gyroscopes, etc. The diagnostic monitoring information can be information describing electrical characteristics of specific operating parameters of the cable. Examples of electrical characteristics can include laser current, laser voltage, incoming optical power, local transmitted and received power, local BIAS current, local supply voltage, local temperature, and also allow other soft controls.

[0083] In some embodiments, the electrical characteristic has a numerical value and can be stored with its type. For example, a temperature value can be stored with information indicating that the value is a temperature value.

[0084] In some embodiments, the cable can associate diagnostic monitoring information with alarm criteria based on the type of diagnostic information and store (1904). For example, an alarm can be generated if the life of the cable exceeds a certain value, or if the temperature of the cable exceeds a certain value or falls below a different value.

[0085] The diagnostic monitoring device can be configured to then determine (1906) whether the electrical characteristic meets the alarm criteria for the diagnostic information type when it collects electrical characteristic data of a given type. In some embodiments, in response to a determination that the electrical characteristic meets the alarm criteria, the diagnostic monitoring device can generate (1908) an alarm signal and transmit (1910) the alarm signal to one or more output pins of the cable.

[0086] The alarm criteria can be a rule-based system or a machine learning-based system. In a rule-based system, the diagnostic monitoring equipment of the cable collects data related to the health of the cable as part of the enhanced DDMI. As discussed above, the cable data can include laser current, laser voltage, Rx power, Tx power, bias current, supply voltage, temperature, and soft control. The data can also include the cable life or its derivatives, such as the date of first deployment. The data can also include the cable operation time or its derivatives, such as the cable life minus the amount of tracking time that the cable is down or not running. The rule-based system can also include rules that the system uses to perform statistical modeling and analysis. These rules can be updated from time to time based on data related to the cable itself or based on data related to similar cables, which can be stored in, for example, a cloud-based database.

[0087] Rules in rule-based systems can be applied to determine whether the collected data meets the rules that are worth issuing an alarm, for example, based on statistical analysis of data from the cable and other cables (past or present) similar to the cable on site, a cable failure is about to occur. In some embodiments, decision rules can be based on known statistical processing rules (such as Western Electric rules) or intuitive knowledge. In some embodiments, rules can also be applied to determine whether the collected data is worth issuing a warning, the failure is not imminent but the cable may be within a preferred threshold failure probability. This may help the owner or user of the cable know when to obtain a replacement cable and then when to deploy the replacement cable. In some embodiments, the cable may include an accelerometer. The data from the accelerometer can be stored on the cable and / or in a cable external database together with other cable data discussed above. Accelerometer data can be related to the physical wear and tear of the cable because it can inform the statistical analysis of the frequency and duration of the cable being compressed due to being in motion, twisting or bending.

[0088] If a rule is met that warrants a cable fault alert, an alert can be sent, for example, through the cable, via a connector of the cable, to a downstream or upstream device. If a rule is met that warrants a warning, a warning can be sent. In some embodiments, if multiple warnings exist simultaneously for the same cable, the multiple warnings themselves can trigger an impending fault alert even if no single statistic triggers a fault alert. If it is not worth issuing an alert or warning, the statistical analysis returns the result that the cable is working as designed, and in some embodiments can remain dormant until new statistics are collected or the rules are updated.

[0089] In some embodiments, it would be useful to dynamically update the statistical modeling to alert or warn the user of an impending or anticipated cable failure. In such embodiments, a machine learning system may be used. Exemplary machine learning systems and processes are described in further detail below.

[0090] Now turn to Fig. 7A , according to one aspect of the present invention, a flowchart of process 2000 for a machine learning model for statistical analysis is shown. Fig. 7A is a flowchart of the initial data analysis in the machine learning based system of statistical analysis.

[0091] When the cable is first deployed, an initial cable data set is collected (2001) via the enhanced DDMI process discussed herein. As previously noted, this data may include laser current, laser voltage, Rx power, Tx power, BIAS current, supply voltage, temperature, or soft control. As discussed, other diagnostic information may also be collected and monitored.

[0092] An initial exploratory data analysis will be performed (2002) on the initial cable data set, including structuring the data, determining data quality, filtering, and cleaning (or removing) data that indicates duplicate or erroneous data. An initial preliminary statistical report will be generated.

[0093] The training data sets may be generated (2003) based on an initial or exploratory data analysis. Each training data set may represent cable diagnostic data or one or more electrical characteristics of a cable (as described herein).

[0094] In some embodiments, a machine learning model may be created (2004) based on an initial or exploratory data analysis and a training data set. In some embodiments, the machine learning model may serve as a predictive model for each individual cable. This model may use Bayesian networks, decision tree learning, and other regression analyses to predict failures of a particular cable. Other predictive analyses may also be used in addition to or in lieu of those listed.

[0095] In some embodiments, a data mining (knowledge discovery) model may be created (2005) based on initial or exploratory data analysis. In some embodiments, the data mining model may be a general knowledge discovery model for all cables in the field. The data mining model may use cluster analysis, anomaly / outlier detection algorithms, and association and sequence pattern mining to better understand the general trends between deployed cables. Other data analysis techniques may also be used. The collected cable diagnostic data as well as other data (specific customers, applications, etc.) may be used to generate the models described herein.

[0096] Now go to Figure 7B , according to one aspect of the present invention, a flow chart for ongoing statistical analysis is shown. Fig. 7A The initial exploratory data analysis phase discussed above) and Fig. 7A After the initial machine learning model is built as in step 2004 or 2005, separate cable data may continue to be collected (2010). The cable data may be saved (2011) in a repository or database on the cable, i.e., in an on-cable database. The machine learning model may analyze (2012) the data, for example to help predict cable faults (2013) and alert a user if action is required (2015), or end (2014) the analysis if no action is required. As monitoring continues to occur over time, the on-cable database is updated, and based on the new data, the model may also be updated.

[0097] If available, the data is also sent to a common cloud-based data database (2016) to which the cable can communicate via a communication link, which can be within the cable. In some embodiments, the cloud-based data database will store information about past or present cables in the field. In some aspects, the data database can contain life-related data related to the cable, including the date the cable was first deployed, and can also contain the total operating time of the cable, which can be collected, for example, by subtracting the amount of time during which the clock signal on the cable is not operating from the life of the cable. The data can also include data from an accelerometer embedded in the cable, which can be used to measure direct wear and tear on the cable based on the amount and type of motion and force applied to the cable during its life.

[0098] Data mining models can be used to (2017) identify other common trends related to AOX cables.

[0099] The data mining model (1607) may also be automatically updated based on new cable data as needed.

[0100] From time to time, at set or variable intervals, the machine learning model for each individual cable is sent to the model database (2018). To clarify, the model database receives updates to the data mining model, which is completely different from updating the monitoring data itself.

[0101] Using regression analysis and / or alternative data mining models (2019), the model of each individual cable is compared with the models of other cables and the data mining models to determine whether the model of the individual cable is the best model for that cable, or whether it needs to be updated in response to new diagnostic monitoring information (2020). If a better model exists, the new machine learning model can be downloaded (2021) to the cable. Therefore, in some embodiments, if a cable failure is predicted, future analysis of the diagnostic monitoring data will sound an alarm based on the updated machine learning model. In addition, the data mining model can be updated (2022) accordingly. If no better model exists, the process ends without requiring action (2023).

[0102] Having described a number of embodiments above, it should be appreciated that heretofore unseen optoelectronic contacts, associated methods, and connection systems have been disclosed by the present disclosure. Such contacts may include an active optoelectronic converter including a converter length extending between opposing first and second ends to define a converter axis, the converter axis having a first end configured for removably optically engaging with an opposing contact. A housing, such as, for example, a cylindrical housing, may define an internal cavity having an elongated length extending between opposing first and second cylindrical openings to define an elongated axis, and having an optoelectronic converter captured in the internal cavity for optically engaging the opposing contact externally via the first cylindrical opening for relative movement of the converter axis along, transverse to, and oblique to the elongated axis, thereby accommodating mating tolerances in response to engaging the opposing contacts. In one embodiment, a flexible circuit board assembly includes an internal electrical connection end, an external electrical connection end, and an elongated length extending therebetween. The internal connection end is electrically engaged with the converter, and the external connection end can be fixedly positioned near the second cylindrical opening for external electrical connection to the photoelectric contact, so that the external connection end is positioned on the extension axis, the distance from the second end of the photoelectric contact is less than the extension length of the flexible circuit board, and the extension length is captured within the internal cavity of the cylindrical housing.

[0103] The foregoing description has been given for purposes of illustration and description. Therefore, this application is not intended to be exhaustive or to limit the invention to the precise form or forms disclosed, and other embodiments, modifications and variations are possible in light of the above teachings, wherein those skilled in the art will recognize certain modifications, permutations, additions and sub-combinations thereof.

Claims

1. A diagnostic monitoring device, comprising: a diagnostic monitor circuit configured to monitor analog diagnostic monitoring information and to convert the analog diagnostic monitoring information into digital diagnostic monitoring information, the diagnostic monitor circuit comprising a first clock or a first oscillator; A microcontroller comprising a register map, wherein the microcontroller is configured to: receiving the digital diagnostic monitoring information; storing the digital diagnostic monitoring information in the register map; as well as providing a clock disable command to the diagnostic monitor circuit; wherein the microcontroller further comprises a communication link for communicating with an external system external to the diagnostic monitoring device; The diagnostic monitor circuit is configured to receive a clock disable command from the microcontroller, and in response to receiving the clock disable command, the diagnostic monitor circuit is configured to disable the first clock or the first oscillator.

2. The diagnostic monitoring device according to claim 1, wherein: The clock disable command is a clock disable signal.

3. The diagnostic monitoring device according to claim 2, wherein: The diagnostic monitoring circuit is further configured to receive a clock enable command configured to enable the first clock or the first oscillator.

4. The diagnostic monitoring device according to claim 3, wherein: The microcontroller further includes a second clock, and wherein the clock disable command is further configured to disable the second clock.

5. The diagnostic monitoring device according to claim 4, wherein: According to the clock disable command, the second clock is re-enabled after a predefined timing delay in the absence of receiving a separate clock enable command.

6. The diagnostic monitoring device of claim 1, wherein: The clock disable command is a message received from the external system via the communication link.

7. The diagnostic monitoring device of claim 1, wherein: The analog diagnostic monitoring information includes at least one of receive power, transmit power, BIAS current, supply voltage, temperature, incoming optical power monitoring, and soft control.

8. A diagnostic monitoring device comprising: a diagnostic monitor circuit configured to monitor one or more electrical characteristics of an associated device based on diagnostic monitoring information received at the diagnostic monitor circuit, the diagnostic monitor circuit comprising a first clock or a first oscillator; as well as a microcontroller configured to receive processed diagnostic monitoring information from the diagnostic monitor circuit and to provide a clock disable signal to the diagnostic monitor circuit, the microcontroller comprising a second clock, Wherein the diagnostic monitor circuit is configured to receive a clock disable command and disable one or more of the first clock, the first oscillator, and the second clock based on the clock disable command.

9. A transceiver module, comprising: a diagnostic monitor circuit configured to monitor one or more electrical characteristics based on diagnostic monitoring information received at the diagnostic monitor circuit; a microcontroller comprising a register map, wherein the microcontroller is configured to receive the diagnostic monitoring information, wherein the microcontroller further comprises a first internal bus and a second internal bus, wherein the first internal bus and the second internal bus have opposite directions; a connector configured to be coupled to an external system via a receptacle capable of accommodating the connector in more than one orientation, the connector having a first pin in a first row of pins and a second pin in a second row of pins, the second row of pins being opposite the first row of pins, the first pin being located a number of pins from a start point of the first row, and the second pin being located the same number of pins from a start point of the second row, wherein the start point of the first row and the start point of the second row are on opposite ends of the connector; an external bus coupled to the connector; A direction detection module, which is configured to: Detecting whether data information is received on the first pin or on the second pin; If the data information is received on the first pin, activating the first internal bus; If the data information is received on the second pin, activating the second internal bus; and The activated first internal bus or the activated second internal bus is operatively coupled to the external bus.

10. The transceiver according to claim 9, wherein: The connector is a USB Type-C connector.

11. The transceiver according to claim 10, wherein: The direction detection module is configured to detect whether the data information is received on the first pin or the second pin by measuring a first resistance of a first pin signal received on the first pin and measuring a second resistance of a second pin signal received on the second pin, and determining whether the first resistance or the second resistance matches the data pin resistance.

12. The transceiver according to claim 10, wherein: The direction detection module is configured to detect whether the data information is received on the first pin or the second pin by determining which pin of the first row of pins or the second row of pins receives a wake-up command.

13. A cable comprising a diagnostic monitoring device, the diagnostic monitoring device being configured to: collecting diagnostic monitoring information associated with the cable, wherein: The diagnostic monitoring information includes electrical characteristics of the cable of a diagnostic information type; associating the diagnostic monitoring information with alarm criteria based on the diagnostic information type and storing the diagnostic monitoring information and the alarm criteria; as well as determining whether the electrical characteristic meets an alert criterion for the diagnostic information type; In response to a determination that the electrical characteristic satisfies the alarm criteria: generating an alarm signal; as well as The alarm signal is transmitted to one or more output pins of the cable.

14. The cable according to claim 13, wherein The diagnostic monitoring device is also configured to store a database of historical monitoring data.

15. The cable of claim 14, further comprising: a communications link communicatively coupled to a common database including historical monitoring data from equipment similar to the cable, The communication link is further configured to transmit updates to the common database and to update alert rules using information received from the common database.

16. The cable according to claim 15, wherein The communication link is also communicatively coupled to a machine learning database, and wherein the diagnostic monitoring device is configured to: collecting an initial diagnostic monitoring data set when said cable is first deployed; analyzing the initial diagnostic monitoring data set to structure the data, determine data quality, and identify data duplications and data errors; removing duplicate and erroneous data from said initial diagnostic monitoring data set; creating a machine learning model based on the initial diagnostic monitoring data set; storing the machine learning model in the machine learning database; updating the machine learning model in response to new diagnostic monitoring information; updating the machine learning model in response to a machine model update communication from the machine learning database; and The digital diagnostic monitoring information is analyzed using the machine learning model to predict failure of the cable.

17. The cable according to claim 16, wherein The machine learning database is updated based on updates to the general database using a data mining model.

18. The cable according to claim 17, wherein The machine learning model and the data mining model are updated based on regression analysis of the machine learning database.

19. The cable according to claim 13, wherein: The digital diagnostic monitoring information includes a date when the cable was first deployed.

20. The cable of claim 13, wherein: The digital diagnostic monitoring information includes a total operating time of the cable.

21. The cable of claim 13, further comprising an accelerometer, wherein: The digital diagnostic monitoring information includes information collected from the accelerometer related to physical strain on the cable from at least one of installation and use.

22. The cable according to claim 13, wherein The diagnostic monitoring device is further configured to store warning rules, and wherein the data analysis module is further configured to: determining whether the electrical characteristic satisfies the warning rule; and If the electrical characteristic satisfies the warning rule, a warning is generated.

23. The cable according to claim 22, wherein The data analysis module is further configured to determine whether more than one warning has been generated from more than one numerical value, and if so, generate an alarm and transmit the alarm to the microcontroller.

24. The cable of claim 13, wherein: The diagnostic monitoring device is further configured to: determining whether the electrical characteristic meets normal operating criteria for the type of diagnostic information; In response to a determination that the electrical characteristic satisfies the normal operating criteria: Generate normal operation signals; as well as The normal operating signal is transmitted to one or more output pins of the cable.

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