Fast power-up scheme for current mirrors

Abstract

An automatic charge / discharge circuit is provided that allows a current mirror circuit (275) having a high capacitance to quickly and automatically charge or discharge the capacitance in order to allow a power supply (300) to be quickly started. The charge / discharge circuit (370) automatically stops charging or discharging when the voltage across the capacitance approaches a desired steady state.

Description

Background Art

[0001] Power supplies are used in all areas of electronics. In many cases, a type of current mirror is employed. In a current mirror, the current in one branch of a circuit can be automatically controlled, at least in part, by the current in a different branch of the circuit. The actual circuitry necessary to create a current mirror can be very simple, and power can be supplied to a number of different circuits via this technique. Depending on the number and type of circuits powered by the current mirror, the combination of circuits can create a capacitance that slows down the startup power supplied by the current mirror. By automatically discharging the charge associated with this capacitance, startup delays can be reduced. Summary of the invention

[0002] A power circuit implementing a fast power-on scheme for a current mirror is presented herein. The power circuit includes a first current mirror circuit having a first and a second current path. The current through the first current path is used to control the current through the second current path. The power circuit further includes a second current mirror circuit having a third and a fourth current path, wherein the current through the third current path is used to control the current through the fourth current path. The second and third current paths are aligned so that a majority of the current through the second current path is the same as a majority of the current through the third current path. The power circuit further includes an automatic discharge configured to achieve a fast start of the current through the third and fourth current paths.

[0003] An additional fast power-up power circuit is further disclosed, comprising a first current mirror circuit. The first current mirror circuit comprises a first current path through a p-type field effect transistor (FET), and a second current path through a second p-type FET and a first n-type FET. The current mirror circuit is configured to control a current in the second current path based at least in part on a current through the first current path. The power circuit further comprises a second current mirror circuit, the second current mirror circuit comprising the second current path and a third current path through a second n-type FET. The second current is configured to control a third current through the third current path. The third current provides power to a feed circuit. The power circuit also comprises an automatic discharge configured to achieve fast startup of the third current.

[0004] A system is also disclosed, comprising a power supply that feeds a feed circuit. The power circuit and the feed circuit are combined to present a capacitance. The power supply includes an enable switch configured to allow the power supply to provide power to the feed circuit when the enable switch is enabled. The power supply further includes a discharge circuit configured to discharge a charge associated with the capacitance when the enable switch is enabled. When the enable switch is enabled, the discharge circuit automatically creates a connection with the discharge source, and automatically disconnects the connection with the discharge source when the charge is sufficiently discharged, so that the provision of power to the feed circuit is not limited based on the capacitance. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Embodiments of the present technology will be described and explained through the use of the accompanying drawings, in which:

[0006] Figure 1 is a block diagram of the implementation scheme;

[0007] Figure 2 is a schematic diagram of a current mirror;

[0008] Figure 3 is a schematic diagram of the implementation scheme;

[0009] Figure 4 is a schematic diagram of an implementation scheme; and

[0010] Figure 5 is a graphical depiction of a quick start in an implementation scheme.

[0011] The drawings are not necessarily drawn to scale. Similarly, for the purpose of discussing some embodiments of the present technology, some components and / or operations may be divided into different blocks or combined into a single block. In addition, although the technology allows various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and are described in detail below. However, it is not intended to limit the technology to the specific embodiments described. On the contrary, the technology is intended to cover all modifications, equivalents, and alternatives that fall within the scope of the technology defined by the appended claims. DETAILED DESCRIPTION

[0012] exist Figure 1100. A system diagram of an embodiment is shown in FIG. Circuits 125, 130, and 135 are shown. Although three circuits 125, 130, and 135 are shown, system 100 may include any number of circuits. These circuits may be independent circuits physically separated from other elements of system 100. If the circuits are physically separated, they may still be electrically connected to at least some of the remaining elements of system 100, for example, by wires. Circuits 125, 130, and 135 may alternatively be physically combined with one or more of the remaining elements of system 100. For example, circuits 125, 130, and 135 may be on the same circuit board as the remaining elements of system 100, or alternatively, circuits 125, 130, and 135 may be part of an integrated circuit identical to one or more of the remaining elements of system 100. Circuits 125, 130, and 135 are connected to current source 120 to draw power. This connection may be achieved via wires, metal traces, wirelessly, or in any other manner. The current source 120 may supply the same or similar current to each of the circuits 125, 130, and 135, or the current source 120 may be configured to supply power to one or more of the circuits 125, 130, or 135 in different ways. This difference may be manually configured, or may be automatic. For example, the current source 120 may include a current mirror device that controls the current supplied to the circuits 125, 130, and 135. The circuit 125 may require a large amount of power at the current rate provided, while the circuit 130 may require only a small amount of power at the current rate provided. By controlling the current through the current mirror device in the current source 120, the current source 120 may automatically control the power supplied to the circuits 125 and 130. The current source 120 is further attached to a power supply 105, a ground 110, and an enable switch 115. The power supply 105 may be any power source, such as a battery or a line voltage. Power supply 105 may be physically located with other elements of system 100, or may be remote from the other elements. Ground 110 may be a physical connection to earth ground, or may be a local ground within the circuit. Ground 110 may be one of several separate common grounds within the circuit, and may or may not be associated with an actual earth ground. Ground 110 may be a common ground relative to other elements of system 100. Enable switch 115 is connected to system 100, and when enabled enables power to be supplied to circuits 125, 130, and / or 135. The enable switch may be an actual switch. In an embodiment, the enable switch may be a transistor that allows current to flow when a voltage is applied to the transistor. Current source 120 may be any type of current source capable of supplying power to circuits 125, 130, and 135. For example, current source 120 may be configured as Figure 2 The current source 200 shown in Figure 3 The current source 300 or Figure 44. The current source 400 shown in FIG. Many other implementations are possible.

[0013] Figure 2 An implementation of a current source 200 is shown. The current source 200 shows a voltage supply node 205 and a voltage supply node 210. The voltage supply nodes 205 and 210 may be coupled to the same power supply, or may be coupled to different sources that provide substantially similar voltages. Each of the voltage supply nodes 205 and 210 may be coupled to a power supply, such as a battery or other voltage source. A ground node 215 is also shown. As described above, ground may refer to actual earth ground or circuit ground (common or otherwise). Various transistors are shown, such as a bias FFT 225, an output FET 235, a bias FFT 240, an enable FET 250, an output FET 280, and an output FET 285. Although these elements are shown as FETs, it should be understood that they may also be implemented with bipolar junction transistors (BJTs) or insulated gate bipolar transistors (IGBTs), or any other circuit element capable of providing similar effects. Similarly, although specific arrangements of p-type and n-type FETs are shown, one of ordinary skill in the art will recognize that different arrangements of n-type and p-type FETs or bipolar junction transistors can be used to achieve the same or similar results. The description of specific arrangements is not intended to limit the present disclosure to those arrangements disclosed. Rather, specific arrangements are described in order to appropriately convey the concepts presented herein.

[0014] A FET is a type of transistor that uses an electric field to control the flow of current in a semiconductor. An n-type FET allows electrons to flow between a source terminal and a drain terminal when the gate terminal is enabled. A p-type FET allows holes to flow between a source terminal and a drain terminal when the gate terminal is enabled. These distinctions, as well as many others, can be used by a person of ordinary skill in the art to design a well-functioning current source.

[0015] In current source 200, a first current mirror circuit is created using two n-type FETs, namely bias FFT 225 and output FET 235, shown as outline 270. Connection 230 connects the drain terminal of bias FFT 225 with the gate terminal of bias FFT 225 and the gate terminal of output FET 235. The gate terminals of bias FFT 225 and output FET 235 control the current allowed to pass through bias FFT 225 and output FET 235. Therefore, by connecting the gate terminals together, bias FFT 225 and output FET 235 are configured to allow corresponding currents to flow through corresponding circuit branches. If the construction of bias FFT 225 and output FET 235 is the same, the current allowed to pass through each branch of the circuit will be the same. In some cases, bias FFT 225 and output FET 235 may be different from each other. For example, in some cases, the width of the channel in output FET 235 may be twice the width of the channel in bias FFT 225, thereby allowing the current through output FET 235 to be controlled at twice the current through bias FFT 225. By connecting the drain terminal of bias FFT 225 to the gate terminals of bias FFT 225 and output FET 235, the current allowed through output FET 235 can be connected to the actual current through bias FFT 225. This allows the current allowed through output FET 235 to be controlled using the target current (provided by current source 220).

[0016] The current source 200 includes a second current mirror circuit, shown as outline 275. The bias FFT 240, output FET 280, and output FET 285 are electrically connected at the gate terminals including the gate node connection 255. The bias FFT 240, output FET 280, and output FET 285 are shown as p-type FETs, but those skilled in the art will understand that all of these transistors shown and discussed herein can be replaced with transistors of different types under different design considerations. As described with respect to the first current mirror, this connection allows a related amount of current to pass through each of the bias FFT 240, output FET 280, and output FET 285. Assuming that the bias FFT 240, output FET 280, and output FET 285 are the same, the current allowed through each branch of the current mirror will be the same. If the bias FFT 240, output FET 280, and output FET 285 vary in geometry, the current allowed through each branch is related and proportional based on the geometry. For example, if the geometry (e.g., gate / channel width) of bias FFT 240 and output FET 280 is the same, but the channel width in output FET 285 is twice as wide, then the current allowed through bias FFT 240 and output FET 280 will be the same, while the current allowed through output FET 285 will be twice the current of bias FFT 240 and output FET 280.

[0017] In the case of the current mirror circuit shown in profile 275, p-type FETs are shown. Those of ordinary skill in the art will appreciate that these FETs can be redesigned as n-type FETs, BJTs, IGBTs, or some other circuit element with similar behavior. The drain of bias FFT 240 is connected to the gates of bias FFT 240, output FET 280, and output FET 285. The current through bias FFT 240 is the target current of the current mirror shown in profile 275. This current passing through FETs 280 and 285 is allowed to be related to this target current. In an embodiment, the current through output FET 235 is almost the same as the current through bias FFT 240. Therefore, the target current provided by current source 220 can be used to provide a target current for output FET 235, output FET 280, and output FET 285. As discussed above, the target current for each of the output FETs can be the same or proportional to the target current provided by current source 220.

[0018] The current source 200 also includes an additional enable FET 250. The enable FET 250 acts as an enable switch, and the gate of the FET 250 is connected to the enable terminal 245. Providing a logic high signal to the enable terminal 245 has the effect of disconnecting the FET 250, thereby allowing the voltage on the gate node connection 255 to adjust and thereby normalize the current through the bias FFT 240, the output FET 280, and the output FET 285. In this way, the second current mirror shown in the outline 275 is enabled or turned on. Similarly, when a logic low signal is provided to the enable terminal 245, the FET 250 is turned on, which pulls the voltage on the gate node connection 255 high and disconnects the bias FFT 240, the output FET 280, and the output FET 285. Accordingly, the output branches 260 and 265 of the second current mirror shown in the outline 275 will not provide power to the circuit. When the enable terminal 245 is supplied with a logic high signal, the current mirror will begin to provide power to the circuits attached to the output branches 260 and 265 .

[0019] Figure 2 Two output branches 260 and 265 are shown. The number of output branches is not limited to two. Current source 200 can be arranged to provide power to any number of output branches. When many output branches are connected as part of current source 200, the capacitance on gate node connection 255 may be large. In addition, depending on the specific circuit attached to the output branches, the capacitance at gate node connection 255 may be large even with relatively few branches.

[0020] When the voltage at the enable terminal 245 rises, the capacitance at the gate node connection 255 prevents the current mirror shown in the profile 275 from starting quickly. For example, when the enable terminal 245 is supplied with a logic low signal, the voltage level at the gate node connection 255 can be at or close to the voltage level of the voltage supply node 210. In theory, when the enable terminal 245 switches to a logic high signal, current begins to flow through the output branches 260 and 265. However, depending on the capacitance at the gate node connection 255, a minimum current will flow through the enable FET 250 until the charge at the gate node connection is discharged. This discharge occurs via a current through the output FET 235 to the ground 215. In an embodiment, the output FET 235 is sized to be related to the bias FFT 225 so as to create the current mirror shown in the profile 270. The size of the output FET 235 limits the speed at which the charge at the gate connection node 255 can be discharged, thus delaying the introduction of current to the output branches 260 and 265. In an implementation, when enable terminal 245 is at a logic high, the voltage level of gate node connection 255 will eventually discharge to approximately 1 volt less than voltage supply node 210. One of ordinary skill in the art will appreciate that this voltage can be adjusted as desired using ordinary design considerations.

[0021] Steering Figure 3 , showing a current source 300 in which an automatic discharge circuit 370 has been added Figure 2 For convenience, the above Figure 2 The components discussed in Figure 3 2. The discharge FET 390 is attached at the source to the gate node connection 255 and at the drain to the ground 215. The discharge FET 390 can be used to discharge the charge on the gate node connection 255 by allowing current to flow to the ground 215. The function of the discharge FET 390 can be somewhat similar to a switch or a variable resistor, where the gate provides an input that determines whether the switch is open or closed (in the case of a switch) or what the resistance will be (in the case of a variable resistor).

[0022] In an embodiment, when the enable terminal 245 is low, the gate node connection 255 is at or near the voltage of the voltage supply node 310. When the enable terminal 245 goes high, the current through the sense FET 375 is initially very low (at least until the charge at the gate node connection 255 is discharged). Therefore, the voltage at the trigger 395, which may correspond to the gate of the reservoir FET 390, is low, thereby allowing current to flow from the gate node connection 255 to the ground node 315. The ground node 315 may be the same as the ground node 215, or may be separate. One or both of the ground node 315 and the ground node 215 may be connected to earth ground, a common ground, or another drain. The discharge FET 390 is not limited to a particular size, such as the output FET 235. Therefore, the discharge FET 390 may be selected to have a size that will allow a rapid discharge of the gate node connection 255. As the gate node connection 255 discharges, the current through the sense FET 375 is allowed to increase, thereby increasing the voltage provided to the trigger 395. Thus, the current allowed through the discharge FET 390 will gradually decrease and will be substantially blocked when the gate connection node 255 is nearly fully discharged.

[0023] The geometric structures of various FETs discussed above can be selected to accommodate various circuit requirements. In an embodiment, the geometric structures of various elements of automatic discharge 370 are selected to allow gate node connection 255 to discharge quickly and automatically when the enable terminal is powered. In addition, the geometric structure can be selected so that when the circuit is in a steady state after power-on, the voltage at trigger 395 remains at or close to the voltage of voltage supply node 210. In this way, the current flow from gate node connection 255 to ground 315 remains off. In an embodiment, this can be achieved by appropriately setting the size of reference FET 380 and sense FET 375. For example, reference FET 380 can be sized with reference to output FET 235 so that the ratio of the width of the channel of reference FET 380 to the width of the channel of output FET 235 is 1:N. Similarly, sense FET 375 can be sized so that the ratio of the width of the channel of sense FET 375 to the width of the channel of bias FFT 240 is 1:P. By keeping N greater than P, the voltage at trigger 395 will be drawn at or close to the voltage of voltage supply node 210 in the steady state after power-up.

[0024] Figure 4 Another embodiment of a current source 400 having an automatic discharge system is shown. Current source 400 shows a ground node 405 and a ground node 410. Ground 405 may be coupled to the same as ground 410, or may be coupled to a separate ground having a substantially similar voltage. One or both of ground node 405 and ground node 410 may be connected to earth ground, a common ground, or another drain. Voltage supply nodes 415 and 416 are also shown. Voltage supply nodes 415 and 416 may be coupled to the same power source, or may be coupled to different sources that provide substantially similar voltages. Each of voltage supply nodes 415 and 416 may be coupled to a power source, such as a battery or other voltage source. Various transistors are provided in Figure 4 FETs are shown in the drawings. Although these elements are shown as FETs, it should be understood that they can also be implemented with bipolar junction transistors (BJTs) or insulated gate bipolar transistors (IGBTs), or any other circuit elements capable of providing similar effects. Similarly, although specific arrangements of p-type and n-type FETs are shown, a person of ordinary skill in the art will recognize that different arrangements of n-type and p-type FETs or bipolar junction transistors can be used to achieve the same or similar results, depending on design constraints. The description of specific arrangements is not intended to limit the present disclosure to those arrangements disclosed. In fact, specific arrangements are described in order to appropriately convey the concepts proposed herein.

[0025] In current source 400, a first current mirror circuit is created using two p-type FETs, namely bias FFT 425 and output FET 435. Connection 430 connects the drain terminal of bias FFT 425 to the gate terminal of bias FFT 425 and the gate terminal of output FET 435. The gate terminals of bias FFT 425 and output FET 435 control the current allowed to pass through bias FFT 425 and output FET 435. Therefore, by connecting the gate terminals together, bias FFT 425 and output FET 435 are configured to allow corresponding currents to flow through corresponding circuit branches. If the construction of bias FFT 425 and output FET 435 is the same, the current allowed to pass through each branch of the circuit will be the same. In some cases, bias FFT 425 and output FET 435 may be different from each other. For example, the width of the channel in output FET 435 may be twice the width of the channel in bias FFT 425, thereby allowing the current through output FET 435 to be controlled at twice the current through bias FFT 425. By connecting the drain terminal of bias FFT 425 to the gate terminals of bias FFT 425 and output FET 435, the current allowed through output FET 435 may be connected to the actual current through bias FFT 425. This allows the current allowed through output FET 435 to be controlled using target current 420.

[0026] The current source 400 includes a second current mirror circuit created by a bias FFT 440, an output FET 480, and an output FET 485 electrically connected at a gate node connection 455. The bias FFT 440, the output FET 480, and the output FET 485 are shown as n-type FETs, but those skilled in the art will understand that all of these transistors shown and discussed herein can be replaced with transistors of different types under different design considerations. This connection allows a related amount of current to pass through each of the bias FFT 440, the output FET 480, and the output FET 485. Assuming that the bias FFT 440, the output FET 480, and the output FET 485 are the same, the current allowed through each branch of the current mirror will be the same. If the bias FFT 440, the output FET 480, and the output FET 485 vary in geometry, the current allowed through each branch can vary. For example, if the geometries of bias FFT 440 and output FET 480 are the same, but the channel in output FET 485 is only half as wide, then the current allowed through bias FFT 440 and output FET 480 will be the same, while the current allowed through output FET 485 will be only half that amount.

[0027] The drain of bias FFT 440 is connected to the gates of bias FFT 440, output FET 480, and output FET 485. The current through bias FFT 440 is the target current of the current mirror. This current through FETs 480 and 485 is allowed to be related to this target current. In an embodiment, the current through output FET 435 is almost the same as the current through bias FFT 440. Therefore, target current 420 can be used to provide a target current for output FET 435, output FET 480, and output FET 485. As discussed above, the target current for each of the output FETs can be the same or proportional to target current 420.

[0028] The current source 400 also includes an enable FET 450. The enable FET 450 is used as an enable switch, and the gate of the FET 450 is connected to the enable terminal 445. By providing an input to the enable terminal 445, the second current mirror is enabled or turned on, thereby providing power to the external circuit via the output FET 280 and the output FET 285. It should be understood that more output FETs not shown can also be used to provide power to many external circuits. In an embodiment, when the enable terminal 445 is disconnected, the output FET 480 and the output FET 485 will not provide power to the circuit. When the enable terminal 445 is turned on, the current mirror will begin to provide power to the circuit attached to the output FET 480 and the output FET 485. It should be understood that in an embodiment, turning on the enable terminal 445 includes reducing the voltage level of the enable terminal to a voltage level at or close to the ground 410.

[0029] Current source 400 can be arranged to provide power to any number of external circuits via output FETs. When many external circuits are connected to current source 400, the capacitance on gate node connection 455 may be large. Additionally, depending on the specific circuits attached to output FETs 480 and 485, the capacitance at gate node connection 455 may be large even with relatively few branches.

[0030] The capacitance at the gate node connection 455 prevents the current source 400 from starting to quickly provide power to the external circuit. For example, when the enable terminal 445 is provided with a logic high signal, the voltage level at the gate node connection 455 is at or close to the voltage level of the ground 410, thereby allowing current to pass through the enable FET 450. In theory, when the enable terminal 445 is switched to a logic low signal, the enable FET 450 is disconnected, thereby allowing the voltage on the gate node connection 455 to adjust and thereby normalize the current through the bias FFT 440, the output FET 480, and the output FET 485. In this way, current begins to flow through the output FET 480 and the output FET 485. However, depending on the capacitance at the gate node connection 455, a minimum current will actually flow through the sense FET 475 until the gate node connection is charged. This charging occurs through current from the voltage supply node 415 through the output FET 435. In an embodiment, the output FET 435 is sized to be related to the bias FFT 425 so as to create a current mirror. The size of output FET 435 limits the speed at which gate connection node 455 can be charged, thus delaying the introduction of current to the external circuit via output FET 480 and output FET 485. In an implementation, when enable terminal 445 is turned on, the voltage level of gate node connection 455 will eventually charge to approximately 1 volt above ground 410. One of ordinary skill in the art will appreciate that this voltage can be adjusted as desired using ordinary design considerations.

[0031] Figure 4 4. Also shown in FIG. 4 is an automatic charge 470. A charge FET 490 is attached at the source to the gate node connection 455 and at the drain to the voltage supply node 415. The charge FET 490 can charge the gate node connection 455 by allowing current to flow from the voltage supply node 415. The function of the charge FET 490 can be somewhat similar to a switch or a variable resistor, where the gate provides an input that determines whether the switch is open or closed (in the case of a switch) or what the resistance will be (in the case of a variable resistor).

[0032] In an embodiment, when the voltage at the enable terminal 445 is high, the gate node connection 455 is at or near the voltage of the ground 410. When the voltage at the enable terminal 445 goes low, the current initially through the sense FET 475 is very low (at least until the charge at the gate node connection 455 is charged). Therefore, the voltage at the trigger 495, which may correspond to the gate of the reservoir FET 490, is high, thereby allowing current to flow from the voltage supply node 416 to the gate node connection 455. The voltage supply node 416 may be coupled to the same power supply as the voltage supply node 415, or may be coupled to a separate power supply that provides a substantially similar voltage. One or both of the voltage supply node 415 and the voltage supply node 416 may be connected to a voltage supply source, a battery, a charging capacitor, or some other power source. Unlike the output FET 435, the charging FET 490 does not need to be limited to a certain size by the current mirror. Therefore, a charging FET 390 of a size that will allow fast charging of the gate node connection 455 may be selected. As gate node connection 455 charges, the current allowed through sense FET 475 increases, thereby reducing the voltage provided to trigger 495. Therefore, the current allowed through charge FET 490 will gradually decrease and be substantially blocked when gate connection node 455 approaches full charge.

[0033] and Figure 3 Same, Figure 4 The geometries of the various FETs shown in the embodiment can be selected to accommodate various circuit requirements. In an embodiment, the geometries of the various elements of the automatic charge 470 are selected to allow the gate node connection 455 to charge quickly and automatically when the enable terminal is powered. In addition, the geometry can be selected so that when the circuit is in a steady state after power-on, the voltage at the trigger 495 remains at or close to the voltage of the ground 410. In this way, the current flow from the voltage supply node 416 to the gate node connection 455 remains off. In an embodiment, this can be achieved by appropriately setting the size of the reference FET 465 and the sense FET 475. For example, the reference FET 465 can be sized with reference to the output FET 435 so that the ratio of the width of the channel of the reference FET 465 to the width of the channel of the output FET 435 is 1:P. Similarly, the sense FET 475 can be sized so that the ratio of the width of the channel of the sense FET 475 to the width of the channel of the bias FFT 440 is 1:N. By keeping P greater than N, the voltage at trigger 495 will be drawn to or close to ground 410 in the steady state after power-up.

[0034] Figure 5The reduced time of providing power to the external circuit based on the implementation scheme is shown. The curve graph 500 shows the voltage on the y-axis and the time on the x-axis. At the time corresponding to point 505, the enable terminal is turned on. Line 510 shows the delay before the voltage drops completely after the enable terminal is turned on. After a short delay, the voltage begins to drop slowly and eventually reaches a steady state. Line 510 shows a current source without an automatic charge / discharge circuit. Line 515 represents an implementation scheme of a current source with an automatic charge / discharge circuit. Again, at point 505, the enable terminal is turned on. At this time, depending on the circuit design, the charge / discharge FET will automatically turn on due to the trigger being high or low. This causes the capacitor on the gate node connection to charge or discharge quickly until the voltage change at the trigger is sufficient to substantially shut down the current through the charge / discharge FET. This point can be seen at point 520. The remaining charge / discharge will occur via the bias FFT. It is worth noting that in the implementation scheme, the voltage reaches the desired steady-state voltage significantly faster than in a circuit without automatic charge / discharge.

[0035] As will be appreciated by those skilled in the art, aspects of the present invention may be embodied as systems, circuits, or methods. Accordingly, aspects of the present invention may take the form of a complete hardware embodiment, or a combination of software and hardware embodiments, which may all be generally referred to herein as a "circuit," "module," or "system." In addition, when referring to capacitors herein, the terms charge and discharge may be used interchangeably. The use of charge or discharge is not intended to limit the description to an increase or decrease in voltage. In fact, those skilled in the art will understand how to design a circuit so that the capacitor will appropriately increase or decrease the voltage to achieve the desired steady state.

[0036] The included descriptions and drawings depict specific embodiments to teach those skilled in the art how to make and use the best mode. Some conventional aspects have been simplified or omitted for the purpose of teaching the principles of the invention. Those skilled in the art will understand variations that fall within the scope of the present disclosure from these embodiments. Those skilled in the art will also understand that the features described above can be combined in various ways to form multiple embodiments. Therefore, the present invention is not limited to the specific embodiments described above, but is limited only by the claims and their equivalents.

Claims

1. A power circuit, wherein include: a sensing transistor comprising a first source, a first gate, and a first drain; a bias transistor including a second source, a second gate, and a second drain; as well as a discharge transistor comprising a third source, a third gate and a third drain; wherein the first gate is coupled to the second gate, the second drain and the third source; The first drain is coupled to the third gate; The third drain is coupled to a ground node; and The first source and the second source are coupled to a voltage supply node.

2. The power circuit according to claim 1, further comprising: include: an enabling transistor including a fourth source and a fourth drain; wherein the fourth drain is coupled to the first gate, the second gate, the second drain and the third source; and The fourth source is coupled to the voltage supply node.

3. The power circuit according to claim 2, further comprising: include: an output transistor including a fifth source, a fifth gate, and a fifth drain; wherein the fifth source is coupled to the voltage supply node; and The fifth gate is coupled to the fourth drain, the first gate, the second gate, the second drain, and the third source. The power circuit according to claim 3 , wherein the fifth drain is connected to an external circuit.

5. The power circuit according to claim 1, further comprising: include: a second bias transistor including a sixth gate, a sixth source, and a sixth drain; a reference transistor including a seventh gate, a seventh source, and a seventh drain; a second output transistor including an eighth gate, an eighth source, and an eighth drain; wherein the sixth drain is coupled to the sixth gate, the seventh gate and the eighth gate; The seventh drain is coupled to the first drain and the third gate; and The eighth drain is coupled to the first gate, the second gate, the second drain, and the third source. 6 . The power circuit of claim 5 , further wherein the sixth source, the seventh source, and the eighth source are coupled to the ground node. 7 . The power circuit of claim 1 , wherein the sense transistor, the bias transistor, and the discharge transistor are n-type field effect transistors.

8. The power circuit of claim 1, wherein the sense transistor, the bias transistor, and the discharge transistor are discrete electronic components.

9. A power circuit, wherein include: a sensing transistor comprising a first source, a first gate, and a first drain; a bias transistor including a second source, a second gate, and a second drain; as well as a charging transistor including a third source, a third gate and a third drain; wherein the first gate is coupled to the second gate, the second drain and the third source; The first drain is coupled to the third gate; The third drain is coupled to a voltage supply node; and The first source and the second source are coupled to a ground node.

10. The power circuit according to claim 9, further comprising: include: an enabling transistor including a fourth source and a fourth drain; wherein the fourth drain is coupled to the first gate, the second gate, the second drain and the third source; and The fourth source is coupled to the ground node.

11. The power circuit according to claim 10, further comprising: include: an output transistor including a fifth source, a fifth gate, and a fifth drain; wherein the fifth source is coupled to the ground node; and The fifth gate is coupled to the fourth drain, the first gate, the second gate, the second drain, and the third source. 12 . The power circuit according to claim 11 , wherein the fifth drain is connected to an external circuit.

13. The power circuit according to claim 9, further comprising: include: a second bias transistor including a sixth gate, a sixth source, and a sixth drain; a reference transistor including a seventh gate, a seventh source, and a seventh drain; a second output transistor including an eighth gate, an eighth source, and an eighth drain; wherein the sixth drain is coupled to the sixth gate, the seventh gate and the eighth gate; The seventh drain is coupled to the first drain and the third gate; and The eighth drain is coupled to the first gate, the second gate, the second drain, and the third source. 14 . The power circuit of claim 13 , further wherein the sixth source, the seventh source, and the eighth source are coupled to the voltage supply node.

15. The power circuit of claim 9, wherein the sense transistor, the bias transistor, and the charge transistor are p-type field effect transistors.

16. The power circuit of claim 9, wherein the sense transistor, the bias transistor, and the charge transistor are discrete electronic components.

17. An integrated circuit, wherein include: a sensing transistor comprising a first source, a first gate, and a first drain; a bias transistor including a second source, a second gate, and a second drain; as well as a charge / discharge transistor including a third source, a third gate, and a third drain; an enabling transistor including a fourth source, a fourth gate, and a fourth drain; an output transistor including a fifth source, a fifth gate, and a fifth drain; wherein the first gate is coupled to the second gate, the second drain, the third source, the fourth drain and the fifth gate; The first drain is coupled to the third gate; The first source is coupled to the second source and the fourth source and the fifth source; and The fourth gate is coupled to an enable node.

18. The integrated circuit of claim 17, wherein the sense transistor, the bias transistor, the charge / discharge transistor, the enable transistor, and the output transistor are n-type field effect transistors.

19. The integrated circuit of claim 17, wherein the sense transistor, the bias transistor, the charge / discharge transistor, the enable transistor, and the output transistor are p-type field effect transistors.

20. The integrated circuit of claim 17, further comprising a second bias transistor including a sixth gate, a sixth source, and a sixth drain; a reference transistor including a seventh gate, a seventh source, and a seventh drain; a second output transistor including an eighth gate, an eighth source, and an eighth drain; wherein the sixth drain is coupled to the sixth gate, the seventh gate and the eighth gate; The seventh drain is coupled to the first drain and the third gate; The eighth drain is coupled to the first gate, the second gate, the second drain, the third source, the fourth drain, and the fifth gate; and The sixth source is coupled to the seventh source and the eighth source.

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