Rapid LCR instrument with electric leakage compensation

Abstract

The invention discloses an LCR instrument with a rapid balancing method. Balance can be achieved only through one-time necessary voltage measurement. The LCR meter is used for accelerating separation of balancing, a device under test (DUT) and other parasitic impedance (including leakage impedance) in measurement time. Leakage impedance and other parasitic impedance of the LCR meter and jig are measured during open / short calibration and saved in memory. The DUT is measured using a known parasitic impedance during the measurement. This allows the balance condition to be calculated using only one voltage measurement.

Description

Technical Field

[0001] The present invention relates to an instrument for impedance measurement over a wide frequency range. Background Art

[0002] The main parameters of an LCR meter are the accuracy and speed of the measurement. If the LCR meter is used as part of an impedance analyzer or in production, the speed of the measurement is crucial. Impedance measurement is based on measuring the voltage drop across a range resistor with known impedance and the device under test (DUT) arranged in series with it. The impedance of the DUT is calculated by knowing the current and voltage drop through the DUT.

[0003] In this case, the main cause of the error (see Figure 1) is the leakage current flowing through the leakage impedance located between the midpoint between the DUT and the span resistor to ground. This leakage current is the cause of the unequal currents through the span resistor and the DUT.

[0004] In order to reduce leakage current, different methods have been adopted.

[0005] One is a guarding method that applies a voltage to the shield through a voltage follower, thereby helping to reduce the voltage between the shield and the intermediate point in the cable from the low potential (LP) terminal of the LCR meter to the DUT. This method is used in the digital impedance meter ESI 251 model, see "A History of Impedance Measurements by Henry P. Hall", page 49.

[0006] Another method is an automatic bridge balance using a transimpedance amplifier (TIA). This method is used in digital impedance meters, type GR 1685-A, see "A History of Impedance Measurements by Henry P. Hall", page 49.

[0007] Both methods have an instant balancing effect, but they have low gain at high frequencies and therefore low common voltage suppression between the intermediate point and the shield of the cable. In addition, they may have stability problems.

[0008] LCR meters with modem-type auto-balancing bridges have good balance accuracy at high frequencies, such as in the Hewlett Packard 4271A LCR meter, see "A History of Impedance Measurements by Henry P. Hall", p. 49. However, they include slow integrators that require a settling time of several cycles of the signal frequency, thus consuming long measurement times at low and medium frequencies. Furthermore, they are expensive. Rayman et al. (2009) in U.S. Pat. No. 7,616,008 B1 proposed a digital version of a modem-type auto-balancing bridge, but it has the same drawbacks as the analog version, namely, low speed at low and medium frequencies.

[0009] There are some other digital methods, such as in U.S. Patent 10,013,015B2 by Ida et al. (2018), Chinese Patent CN110320410A by Fajie et al. (2019), and the book "A Novel Fast Balance Technique for the Digital AC Bridge" by Zhang et al. (1998). But all of them require at least two voltage measurements and at least two cycles of the signal frequency to achieve balance. Summary of the invention

[0010] The present invention uses a fast balancing method involving a small number of components to achieve high accuracy and high measurement rate.

[0011] First, it is the separation in measurement time of the DUT and other necessary fast balancing parameters. Such parameters are: leakage impedance of the LCR meter and fixture, and series impedance of the voltage source and fixture. These parameters are constant and can be measured only once during calibration and then used during DUT measurement.

[0012] Secondly, it can measure the DUT impedance under unbalanced conditions with moderate accuracy. In this case, the leakage current that causes measurement error is compensated by calculating this current value using the unbalanced voltage and the previously measured value of the leakage impedance.

[0013] Third, this moderately accurate value of the DUT and the previously measured series impedance of the voltage source and fixture allow the voltage of the voltage source to be calculated and adjusted in one step - without any iterations - to obtain a balanced condition, i.e., close to zero voltage at the midpoint between the DUT and the range resistor. This balanced condition allows the DUT impedance to be measured with high accuracy. With modern high-speed processors, the measurement time is not increased.

[0014] Technical issues

[0015] Some LCR meters use a modem type balancing method to exclude current through the leakage impedance to achieve balance. These LCR meters have the best accuracy at high frequencies, but are slow at medium and low frequencies.

[0016] Solution

[0017] The present invention solves the low speed problem using a fast balancing method. This method requires only one measurement of the voltage to achieve balancing, and its balancing speed is limited only by one full cycle of the signal frequency. This method uses the leakage impedance and other impedances of the initial measurement of the LCR meter and the fixture to calculate and set the required voltage in one step, thereby achieving fast balancing.

[0018] Advantageous Effects of the Invention

[0019] The invention has the advantages of high measurement speed and low cost in production. It does not have stability problems. The hardware structure allows the frequency range to be extended by calibrating each voltage channel relative to the other voltage channels. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 shows the main causes of inaccuracy in LCR meters.

[0021] FIG. 2 shows a method for measuring leakage impedance.

[0022] Figure 3 A simplified schematic diagram is shown of a first embodiment of the invention.

[0023] Figure 4 An example showing the voltage at the input multiplexer of an LCR meter during one signal cycle.

[0024] Figure 5 The ADC1 input voltage of this first embodiment is shown.

[0025] Figure 6 The ADC1 input voltage of this first embodiment is shown in more detail.

[0026] Figure 7 The gain and phase frequency response of a low-pass anti-aliasing filter is shown.

[0027] Figure 8Shown are the gain and phase errors of input buffers built around an operational amplifier with a unity-gain bandwidth of approximately 100 MHz and a frequency tolerance of ±20%.

[0028] Fig. 9 A block diagram of this first embodiment of the invention is shown.

[0029] Fig.10 A block diagram showing a second embodiment of the present invention is shown.

[0030] Fig.11 A block diagram showing the low-level processing of the first embodiment.

[0031] Fig.12 A flow chart showing the low-level work process of the processor.

[0032] Reference numerals list

[0033] 1002 first voltage source (VoltSrc1)

[0034] 1004 High Current (HC) Terminals

[0035] 1006 High Potential (HP) Terminal

[0036] 1008 Device Under Test (DUT)

[0037] 1010 Low potential (LP) terminal

[0038] 1012 Midway between the DUT and the range resistor

[0039] 1014 Leakage impedance (Zleak)

[0040] 1016 Low Current (LC) Terminals

[0041] 1018 range resistors, a set of reference resistors (Zrange)

[0042] Voltage on the second terminal of the 1020 range resistor (Vrr)

[0043] 1022 second voltage source (VoltSrc2)

[0044] 3002 Output impedance of the first voltage source (Zout1)

[0045] 3004 series current limiting resistor impedance (Zser_res)

[0046] 3006 Output impedance of the buffer of the first voltage source (Zbuff1)

[0047] 3008 Impedance of the cable between the high current terminal and the device under test (Zwire1)

[0048] 3010 Capacitance of the cable between the HP terminal and the DUT (Ccable1)

[0049] 3012 Impedance of the cable between the LC terminal and the device under test (Zwire2)

[0050] Parasitic capacitance (Cmux) of a 3014 range resistor multiplexer

[0051] Impedance of 3016 range resistor multiplexer (Zmux)

[0052] 3018 Output impedance of the second voltage source (Zout2)

[0053] 3020 Output impedance of the second voltage source buffer (Zbuff2)

[0054] 9004 Switch for calibrating high potential buffer

[0055] 9006 Switch for calibrating low potential buffer

[0056] 9008 Switch for calibrating low current buffers

[0057] 9010 Switch for calibrating the range resistor buffer

[0058] 9012 Switch used to provide calibration voltage to input buffer

[0059] 9016 High Potential Voltage Input Buffer

[0060] 9018 Low Voltage Input Buffer

[0061] 9020 Low Current Voltage Input Buffer

[0062] 9022 Range Resistor Voltage Input Buffer

[0063] 9024 First Voltage Source Output Buffer

[0064] 9026 Second voltage source output buffer

[0065] 9028 First low pass filter (LPF1)

[0066] 9030 Input Multiplexer

[0067] 9032 Output Multiplexer Buffer

[0068] 9033 Multiplexer Control Interface

[0069] 9034 Second low pass filter (LPF2)

[0070] 9036 first digital-to-analog converter (DAC) (DAC1)

[0071] 9038 first analog-to-digital converter (ADC) (ADC1)

[0072] 9040 Second DAC (DAC2)

[0073] 9042 sends digital signal to the first DAC

[0074] 9044 Digital signal from the first ADC

[0075] 9046 sends digital signal to the second DAC

[0076] 9048 processor

[0077] 10002 Second ADC (ADC2)

[0078] 10004 Third ADC (ADC3)

[0079] 10006 Fourth ADC (ADC4)

[0080] 11002 The first set of memory buffers

[0081] 11004 Second set of memory buffers

[0082] 11006 Direct Fourier Transform (DFT) Box

[0083] 11008 Cosine Multiplier

[0084] 11010 Sine Multiplier

[0085] 11012 Demultiplexer and Accumulator

[0086] 11014 Software Direct Digital Synthesizer (DDS)

[0087] 11016 Control and processing core

[0088] 12002 Commonly used direct memory access (DMA) flow chart

[0089] 12004 ADC data direct Fourier transform processing flow chart 12006 DMA data preparation flow chart for DAC and reference buffer DETAILED DESCRIPTION

[0090] To improve the accuracy of the measurement, the prior art only eliminates or reduces the voltage drop on the leakage impedance.

[0091] In addition, the prior art (excluding the protection method and the transimpedance automatic balancing method) requires at least two measurements to achieve balance because the measurement circuit has at least two significant unknown parameters, namely, the impedance of the device under test and the leakage impedance. However, according to mathematical science, two unknowns require at least two equations, and therefore two sets of measurement voltages are required.

[0092] The leakage impedance and other parasitic parameters of the LCR meter and the fixture used are constant and can be measured only once during calibration. This information can be automatically applied to save measurement time. In addition, if their values ​​are known, their effects can be compensated in the DUT impedance calculation results.

[0093] The present invention uses preliminary measurements of the leakage impedance and series impedance of the voltage source and fixture during the calibration process to improve accuracy and speed up measurements. Knowledge of the parasitic impedance allows for more accurate and faster measurements. The series impedance includes the leakage impedance, the output impedance of the voltage source, and the series impedance of the cable. Thus, the measurement of the device under test and the measurement of the parasitic impedance are separated in time. The series impedance is measured when calibrating the fixture used and can be saved in on-board memory. If the LCR meter is able to recognize the fixture, the associated series impedance is automatically used, or the user can manually select such data from previously stored values. The calibration of the leakage impedance and series impedance can be combined with the standard open / short calibration.

[0094] Knowledge of the leakage impedance and series impedance can reduce the DUT measurement time. First, a moderately accurate value of the DUT is calculated without balancing and used in the fast balancing method. Second, the value of the leakage impedance is used to compensate for the leakage current caused by the residual unbalanced voltage.

[0095] For medium accuracy requirements, at low and medium frequencies, the leakage impedance is relatively high; even one-step balancing takes a certain amount of time and may even miss the balance. Therefore, only medium-accuracy measurements with leakage compensation can be made. At high frequencies, the typical cable capacitance is about 100pF / m, and the capacitance of the range resistor multiplexer is as high as several hundred picofarads, so balancing is necessary.

[0096] Another cause of errors at high frequencies is the unequal gains and phase delays of the operational amplifiers used in input buffers 9016, 9018, 9020, and 9022. Figure 8Figure 1 shows the possible inequality in gain error and phase delay for op amps used as input buffers, which have unity gain and ±20% tolerance at approximately 100MHz. Even for a relatively low signal frequency of 1MHz, the gain error between the two channels can be ±0.4%, and the gain error between the DUT and the span voltage can be ±0.8%. This is unacceptable for a precision LCR meter.

[0097] More details will be explained in the description of the embodiments. The description of these embodiments is only for illustrative purposes and does not limit the present invention.

[0098] First embodiment

[0099] First embodiment (see Fig. 9 ) includes a processor 9048 that provides digital signals 9042 and 9046 to first 1002 and second 1022 voltage sources. These voltage sources include digital-to-analog converters (DACs) 9036 and 9040, low pass filters 9028 and 9034, and output buffers 9024 and 9026. The processor also receives a digital signal 9044 from an analog-to-digital converter (ADC) 9038 and controls an analog multiplexer 9030.

[0100] The output of the first voltage source 1002 is transmitted through its output impedance 3002 (see Figure 3 ), connected to the HC terminal and DUT 1008. Output impedance 3002 includes buffer 9024 (see Fig. 9 ), the output impedance 3006 of the DUT 1008, the series resistor 3004, the wire impedance 3008, and the capacitance of the cable 3010 between the DUT 1008 and the HC terminal 1004 of the LCR meter.

[0101] One side of the DUT 1008, which is connected to the HC terminal 1004, is also connected to the HP terminal 1006. The other side of the DUT 1008 is connected to the LP terminal 1010 and the LC terminal 1016.

[0102] The output of the second voltage source 1022 is connected to the second terminal of the range resistor 1018 through its output impedance 3018. The first terminal of the range resistor is connected to the DUT 1008 through the LC terminal 1016 and the cable between the LC terminal and the DUT 1008. The output impedance 3018 of the second voltage source 1022 includes (see Figure 3 )The output impedance 3020 of the buffer 9026, the impedance of the range resistor multiplexer 3016, and the capacitance of the multiplexer 3014.

[0103] HP terminal 1006 is connected to the normally closed input of switch 9004, the output of which is connected to input buffer 9016. LP terminal 1010 is connected to the normally closed input of switch 9006, the output of which is connected to input buffer 9018. LC terminal 1016 is connected to the normally closed input of switch 9008, the output of which is connected to input buffer 9020. A second terminal of range resistor 1018, which is opposite to the LC terminal, is connected to the normally closed input of switch 9010, the output of which is connected to input buffer 9022. The outputs of input buffers 9016, 9018, 9020, and 9022 are connected to the input of multiplexer 9030, the output of which is connected to ADC 9038 through buffer 9032. The normally open inputs of switches 9004, 9006, 9008, and 9010 are connected to the output of switch 9012. The normally closed input of the switch 9012 is connected to ground, and the normally open input of the switch 9012 is connected to the output of the second voltage source 1022 .

[0104] The first embodiment can also use a protection device to reduce the voltage between the intermediate point and the shielding of the cable. In this case, all equations are the same; the only difference is that the leakage impedance is higher.

[0105] Operation of the First Embodiment

[0106] In the first embodiment (see Fig. 9 ), leakage impedance measurement, series impedance measurement, and input buffer equalization are performed during open / short calibration.

[0107] Leak Calibration and Compensation

[0108] FIG2 shows a method of measuring leakage impedance.

[0109] The method includes:

[0110] Set the fixture to an open circuit by removing the DUT.

[0111] applying a predetermined voltage across a predetermined impedance of a range resistor;

[0112] Measure the voltage across the open-circuit fixture;

[0113] Eliminating the effect of the open clamp by setting the same voltage at the HP terminal as at the LP terminal and adjusting it in a predetermined number of iterations to obtain the closest values ​​of these voltages to reduce the current through the open clamp;

[0114] Measure the voltage across the leakage impedance and the span resistor;

[0115] Calculate the leakage impedance.

[0116] To set the necessary voltage at the HP terminal, the method in Equations 22 and 23 is used to calculate the value of the input signal to the first voltage source.

[0117] [Mathematical formula 1] Leakage impedance:

[0118] Zleak=Vlp*Zrange / (Vlc–Vrr)

[0119] All values ​​are plural.

[0120] While measuring the parameters of the DUT, the leakage impedance is used to calculate the leakage current and compensate for its effect by subtracting a current value from the current through the range resistor.

[0121] Calibration of series impedance

[0122] Figure 3 A method for measuring series impedance is shown, which includes the output impedance of the first voltage source 3002 and the second voltage source 3018 and the impedance of the wire between the DUT and the LC terminal 3012. The impedance of the cable line 3012 between the DUT and the LC terminal and the output impedance of the two voltage sources are necessary for setting a balanced voltage close to zero. Both the open circuit and short circuit states of the measurement circuit are necessary for measuring and calculating the series impedance. During the calibration process, all measured voltages of the two groups (open circuit and short circuit) will be saved and used to calculate the series impedance.

[0123] [Mathematical formula 2] The current change of the first voltage source is:

[0124] dI1=(Vlc_short–Vrr_short) / Zrange+Vlp_short / Zleak

[0125] [Mathematical formula 3] The current change of the second voltage source is:

[0126] dI2=(Vlc_short–Vrr_short) / Zrange–Vrr_open / (Zleak+Zrange)

[0127] [Mathematical formula 4] The output impedance of the first voltage source is:

[0128] Zout1=(Vrr_open–Vrr_short) / dI1

[0129] [Mathematical formula 5] The output impedance of the second voltage source:

[0130] Zout2=(Vrr_open–Vrr_short) / dI2

[0131] [Mathematical formula 6] The impedance of the wire between the DUT and the LC terminal:

[0132] Zwire2=(Vlp_short–Vlc_short) / dI2

[0133] All values ​​are plural.

[0134] Balanced approach

[0135] First embodiment (see Fig. 9 ) can perform equalization calibration to automatically eliminate gain and phase inequalities of the input buffers without user intervention. The structure of the first embodiment has independent measurement of voltages across the range resistor relative to ground and at the input terminals, allowing equalization calibration to be performed by providing the same predetermined voltage to all input buffers simultaneously. Fig. 9 The initial normally closed position of switches 9004, 9006, 9008, 9010, and 9012 is shown. For equalization, calibration requires setting the opposite position of these switches, thereby connecting the input buffer to a common point shared by all channel voltages. We then need to apply a predetermined voltage from a second voltage source, measure the voltage on the input buffer or voltage channel, and calculate and save the correction coefficient. One of the input channels needs to be designated as the reference, such as the LP channel.

[0136] [Mathematical Formula 7] Correction coefficient for HP input buffer 9016:

[0137] Chp=Vlp / Vhp

[0138] [Mathematical Formula 8] Correction coefficient for LP input buffer 9018:

[0139] Clp=Vlp / Vlp

[0140] [Mathematical formula 9] Correction coefficient for LC input buffer 9020:

[0141] Clc=Vlp / Vlc

[0142] [Mathematical formula 10] Correction coefficient for the range resistor input buffer 9022:

[0143] Crr=Vlp / Vrr

[0144] [Mathematical Formula 11] Then, during the measurement time, the correction voltage will be:

[0145] Vxx_corr=Vxx_raw*Cxx

[0146] Low-level processing

[0147] The first embodiment adopts a structure having one ADC and a four-channel multiplexer to switch voltage channels to achieve lower cost. Figure 4 shows the input voltage, Figure 5 The voltage at the ADC input is shown in Figure 1. Since switching the multiplexer channels generates commutation noise, the noise component in the time interval after switching needs to be excluded in the ADC signal processing. Figure 6 Noisy time intervals and normal time intervals are shown.

[0148] According to the Nyquist theorem, the sampling frequency must be more than twice the signal bandwidth. To measure the vector voltage by direct Fourier transform (DFT), at least one full cycle of the signal frequency is required. Therefore, the minimum vector voltage measurement time is limited to one cycle of the signal frequency and at least three ADC samples for each measured voltage. Therefore, all voltages must be measured simultaneously (see Figure 5 ), and there must be at least three sampling groups. Equations 12 to 16 describe the conditions for averaging low frequencies if the shortest measurement time is required.

[0149] [Mathematical formula 12] Sampling period:

[0150] Tsample=1 / Fsample

[0151] [Mathematical formula 13]Signal period:

[0152] Tsignal=1 / Fsignal

[0153] [Mathematical formula 14] Buffer time interval:

[0154] Tbuffer=Tsample*BufferSize

[0155] [Mathematical formula 15] Sampling group interval:

[0156] Tsamplegroup=Tbuffer*Nchannels

[0157] [Mathematical formula 16] Shortest measurement time:

[0158] Tmeas_min=Tsignal=M*Tsamplegroup

[0159] (M≥3)

[0160] BufferSize, number of channels (Nchannels), and M are all integers. BufferSize is the size of the direct memory access (DMA) buffer, Nchannels is the number of voltage channels, and M is the number of sampling groups.

[0161] Fig.11 The signal processing of the first embodiment is shown in more detail. The control and processing core 9048 includes low level processing of the instantaneous digital values ​​of the input and output voltages and high level processing of the digital representations of these voltages to calculate results in the control and processing core 11016.

[0162] The low level processing includes: a direct digital synthesizer 11014, a first set 11002 and a second set 11004 of memory buffers to store samples of input and output voltages, reference values, a multiplier, a demultiplexer and an accumulator 11012 for DFT 11008 and 11010 to separate input voltage samples from different voltage channels and accumulate them in the DFT process, an interface to transfer digital signals S1 and S2 to DAC 9042 and 9046 and an interface to transfer digital signals from ADC 9038 to memory 11002 and 11004. To speed up the processing, DMA is used to transfer data from memory to DAC 9036 and 9040 and from ADC 9038 to memory 11002 and 11004.

[0163] Fig.12 The flowchart in shows the data processing flow. First, the data from the ADC and the reference data that have been filled in the previous DMA cycle are processed. These data are used for DFT. Secondly, the data for the next DMA cycle is prepared. These data will be used for DAC and DFT. The reference data is filled with DAC data to save time during DFT processing. The "SetVoltageChannel()" procedure switches the multiplexer 9030 to the next channel.

[0164] This processing is described as being implemented in a processor, but can also be implemented in microcontrollers, DSPs, FPGAs, ASICs, and other hardware.

[0165] Fast balancing method

[0166] For balancing, a first embodiment uses a fast balancing method. If the leakage impedance is known from a previous calibration, the balanced condition can be calculated after only one voltage measurement. But this known leakage impedance has limited accuracy because some small changes may occur in the cable-to-fixture geometry, and therefore the capacitance of the cable will also change. In addition, the leakage impedance also depends on the ambient temperature. Therefore, the first calculation of the DUT impedance will have limited accuracy without balancing. It will be used to achieve balance and calculate the DUT impedance after balancing, and even higher accuracy can be achieved by applying leakage compensation methods. Equations 17 to 34 show how to calculate the fast balancing condition.

[0167] [Mathematical formula 17] The current passing through the range resistor is:

[0168] Irange=(Vlc–Vrr) / Zrange

[0169] [Mathematical formula 18] The current passing through the leakage impedance is:

[0170] Ileak=–Vlp / Zleak

[0171] [Mathematical formula 19] The current passing through the DUT is:

[0172] Idut=Irange+Ileak

[0173] [Mathematical formula 20] Rough impedance of DUT:

[0174] Zdut=(Vhp–Vlp) / Idut

[0175] [Mathematical formula 21] The electromotive force (EMF) of the first voltage source:

[0176] EMF1=Vhp+Idut*Zout1

[0177] [Mathematical formula 22] The electromotive force of the second voltage source:

[0178] EMF2=Vrr–Irange*Zout2

[0179] For the equilibrium condition where the first voltage source is an unregulated voltage and the second voltage source is a regulated voltage (LCR is in constant voltage mode):

[0180] [Mathematical formula 23] Balance condition:

[0181] Vlp=0

[0182] [Mathematical Formula 24] The new current passing through the DUT is:

[0183] Idut_new=EMF1 / (Zdut+Zout1)

[0184] [Mathematical Formula 25] The new current passing through the range resistor is:

[0185] Irange_new=Idut_new

[0186] [Mathematical formula 26] The new electromotive force of the second voltage source:

[0187] EMF2new=Irange_new*(Zwire2+Zrange+Zout2)

[0188] [Mathematical formula 27] Correction coefficient for the electromotive force of the second voltage source:

[0189] CorrCoeff=EMF2new / EMF2

[0190] [Mathematical Formula 28] The new value of the digital signal for the second voltage source:

[0191] S2new=CorrCoeff*S2

[0192] For the equilibrium condition where the second voltage source is an unregulated voltage and the first voltage source is a regulated voltage (LCR is in constant current mode):

[0193] [Mathematical formula 29] Balance condition:

[0194] Vlp=0

[0195] [Mathematical Formula 30] The new current passing through the range resistor is:

[0196] Irange_new=–EMF2 / (Zwire2+Zrange+Zou2)

[0197] [Mathematical Formula 31] The new current passing through the DUT is:

[0198] Idut_new=Irange_new

[0199] [Mathematical formula 32] The new electromotive force of the first voltage source:

[0200] EMF1new=Idut_new*(Zdut+Zout1)

[0201] [Mathematical formula 33] Correction coefficient for the electromotive force of the first voltage source:

[0202] CorrCoeff=EMF1new / EMF1

[0203] [Mathematical Formula 34] The new value of the digital signal for the first voltage source:

[0204] S1new=CorrCoeff*S1

[0205] All values ​​are plural.

[0206] The calculation of the correction coefficient (CorrCoeff) as the relationship between the old and new electromotive forces is an implicit replacement for the explicit calculation of the low pass filter (LPF) frequency response. Figure 7Examples of high order LPF amplitude and phase frequency responses are shown for an LCR meter with 1 MHz maximum signal frequency and 3 Msps sampling frequency. The calculation of CorrCoeff allows to eliminate the necessity of calibration of LPFs with very steep slopes at high frequencies.

[0207] After setting the balanced condition, the control and processing unit must wait for the voltage to settle and start the measurement under the balanced condition. After accurate measurement under the voltage balanced condition, the calculation of the parameters of the DUT is repeated by using equations 17 to 20.

[0208] Advantages of the First Embodiment

[0209] The time to achieve balance is reduced by at least a factor of two compared to any other method (excluding transimpedance amplifiers and protection methods). A single ADC enables low cost in production. Equalization of the channels allows the use of signals with higher frequencies at lower cost.

[0210] Disadvantages of the First Embodiment

[0211] For three-terminal capacitor measurements, more than one balancing cycle is required, or a special calibration is required, such as a leakage calibration for each three-terminal capacitor individually (see Figure 2), because they have some input capacitance to ground that is not included in the saved leakage impedance.

[0212] Second embodiment

[0213] Second embodiment (see Fig.10 ), unlike the first embodiment, includes four parallel voltage measurement channels, without multiplexing but with additional ADCs 10002, 10004, and 10006 and additional digital signals 10008, 10010, and 10012 to speed up the measurement speed at high frequencies. The second embodiment uses a fast balancing method similar to the first embodiment, and the working principle is also similar.

[0214] The advantage of the second embodiment is that the low-level processing can be simplified by eliminating direct memory access, thereby improving the signal-to-noise ratio and speeding up the measurement.

[0215] Practicality

[0216] The invention can be used in any industry that needs to measure impedance. The invention significantly reduces the cost of producing impedance measuring instruments and improves the measuring speed.

[0217] List of cited documents

[0218] The list of cited documents is as follows:

[0219] Patent Literature

[0220] US Patents

[0221] Patent No. Type Code Grant Date Patentee

[0222] 10,013,015 B2 2018-07-03 Ida et al.

[0223] 9,910,074 B2 2018-03-06 Lindell et al.

[0224] 7,616,008 B1 2009-11-10 Rayman et al.

[0225] US patent document added by examiner Robert P Olejnikov

[0226] 20210333348 A1 2021-10 Fortney; Houston

[0227] 20200135441 A1 2020-04 Jones; AnthonyMichael

[0229] 20140348502 A1 2014-11 Miura; Tomoko

[0230] 8547135 B1 2013-10 Yarlagadda; Archana

[0231] 6028309 A 2000-02 Parrish; William J.

[0232] Foreign patent documents

[0233] Foreign Document Country Code Publication Date Patent Owner

[0234] 110320410A CN 2019-10-11 Fajie et al.

[0235] Non-patent literature

[0236] Zhang et al. (A Novel Fast Balance Technique for the Digital ACBridge) (April 1998)

[0237] Henry P. Hall (A History of Impedance Measurements)

[0238] Keysight's E4980A Precision LCR Meter Data Sheet (2021)

[0239] Keysight's (Measurement Handbook 6th Ed) (2021)

Claims

1. A fast balancing method for impedance measurement with leakage impedance compensation, comprising: An LCR meter is provided, comprising: High Current (HC) Terminals, High potential (HP) terminal, Low potential (LP) terminal, Low current (LC) terminals, The fixture is used to connect to the device under test (DUT). a set of reference resistors having first and second terminals, the first terminals being connected to the LC terminals, a first voltage source comprising an output, the output of the first voltage source being connected to the HC terminal, a second voltage source comprising an output, the output of the second voltage source being connected to the second terminal of the set of reference resistors, a processor including memory, the processor capable of measuring voltages at the HP terminal, the LP terminal, the LC terminal, the second terminal of the set of reference resistors, and an output of the second voltage source; Attaching the clamp to the HC, HP, LP, and LC terminals; setting the impedance of the set of reference resistors to a first predetermined value; setting the output of the first voltage source to a first predetermined voltage; setting the output of the second voltage source to a second predetermined voltage; measuring a first measurement of the leakage impedance of the LCR meter and the fixture; saving the first measurement to the memory of the processor; setting the impedance of the set of reference resistors to a second predetermined value; performing a second measurement of the series impedance of the fixture, the first voltage source, and the second voltage source; saving the second measurement to the memory of the processor; attaching the DUT to the fixture; setting the impedance of the set of reference resistors to a third predetermined value; setting the output of the first voltage source to a third predetermined voltage; setting the output of the second voltage source to a fourth predetermined voltage; a third measurement measuring voltages at the HP terminal, the LP terminal, the LC terminal, and the second terminal of the set of reference resistors; calculating an impedance value of the DUT using the first measurement; calculating a specific voltage by using the second measurement that, when applied to the outputs of the first and second voltage sources, would produce a zero voltage at the LP terminal; setting the outputs of the first and second voltage sources to the specific voltage; a fourth measurement measuring voltages at the HP terminal, the LP terminal, the LC terminal, and the second terminal of the set of reference resistors; as well as The fourth measurement is used to calculate an impedance value of the DUT when there is the zero voltage at the LP terminal.

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