Vectorized operations for sparse kernels

Abstract

The present disclosure provides a data processing method and processor instructions that utilize scatter operations to efficiently merge vector and matrix indices (as compared to standard matrix and vector operations) and merge other arithmetic results, quantity lists, etc.

Description

Background Art

[0001] The present disclosure relates to computer systems. More particularly, the present disclosure relates to data processing.

[0002] Graph algorithms are common in many complex problem domains and are often implemented as linear algebra problems with extreme sparsity. Machine learning (ML) applications in general and artificial neural networks (ANNs) in particular, such as deep neural networks (DNNs), convolutional neural networks (CNNs), etc., are popular solutions to a variety of challenging classification, identification, and regression problems. Similarly, ML applications and ANNs are often (at least in part) implemented as linear algebra problems with extreme sparsity in weights and often during execution as well as linear algebra problems with extreme sparsity in data. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1A and Figure 1B A standard matrix multiplication according to an embodiment of the present disclosure is shown.

[0004] Figure 2A , Figure 2B and Figure 2C Matrix outer products according to embodiments of the present disclosure are shown.

[0005] Figure 3A , Figure 3B and Figure 3C Matrix outer products according to embodiments of the present disclosure are shown.

[0006] Figure 4A A standard matrix-vector multiplication is shown according to an embodiment of the present invention.

[0007] Figure 4B and Figure 4C A matrix-vector outer product according to an embodiment of the present disclosure is shown.

[0008] Figure 4D A merge operation according to an embodiment of the present disclosure is shown.

[0009] Figure 5A and Figure 5B A matrix-vector outer product according to an embodiment of the present disclosure is shown.

[0010] Figure 5C , Figure 5D and Figure 5E A matrix-vector outer product according to an embodiment of the present disclosure is shown.

[0011] Fig. 6A Two sparse vectors according to an embodiment of the present disclosure are shown.

[0012] Figure 6Band Figure 6C A merge operation of two vectors of sorted indices according to an embodiment of the present invention is shown.

[0013] Fig.6D A merge operation of two vectors of sorted index and data is shown according to an embodiment of the present disclosure.

[0014] Fig. 6E A merge operation of two vectors of sorted indices according to an embodiment of the present invention is shown.

[0015] Fig. 7A and Figure 7B A merge operation of two vectors of sorted indices according to an embodiment of the present invention is shown.

[0016] Figure 7C and Fig.7D A merge operation of two vectors of sorted indices according to an embodiment of the present invention is shown.

[0017] Figure 8 A scatter operation of two vectors of sorted index and data is shown according to an embodiment of the present disclosure.

[0018] Fig. 9 A block diagram of a system according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0019] Embodiments of the present disclosure will now be described with reference to the drawings, wherein like reference numerals refer to like parts throughout.

[0020] Embodiments of the present disclosure advantageously provide a data processing method and processor instructions that utilize scatter operations to efficiently merge vector and matrix indexes (compared to standard matrix and vector operations) and merge other arithmetic results, lists of quantities, etc. In general, a processor includes an instruction decoder to control, among other things, processing circuits to generate scatter index values ​​and perform scatter-accumulate operations on two vectors to efficiently generate a sorted merged vector. The processor may be a central processing unit (CPU), a core in a multi-core processor, a dedicated processor (such as, for example, a graphics processing unit (GPU) processor, a neural processing unit (NPU) processor, an ANN accelerator processor, etc.).

[0021] In one embodiment, the processor includes an instruction decoder configured to decode instructions, and a processing circuit configured to perform data processing in response to the instructions decoded by the instruction decoder. In response to one or more read instructions, the instruction decoder is configured to control the processing circuit to read a first vector and a second vector from a storage device, each vector including at least an index value. In response to the instruction sequence, the instruction decoder is configured to control the processing circuit to generate scatter index values ​​for the first vector and the second vector based on the index values ​​of the first vector and the second vector. And, in response to one or more scatter instructions, the instruction decoder is configured to perform a scatter operation using the scatter index values ​​of the first vector and the second vector to generate a sorted merged vector.

[0022] Figure 1A and Figure 1B A standard matrix multiplication 100 is shown in accordance with an embodiment of the present disclosure.

[0023] The matrix 110 includes 25 elements, namely, a 0 ,......,a 24 , these elements are arranged in five rows and five columns (5x5). Matrix 120 also includes 25 elements, namely, b 0 ,......,b 24 , these elements are arranged into five rows and five columns (5x5). To multiply matrix 110 by matrix 120, the dot product (or inner product) is calculated for each row of matrix 110 and each column of matrix 120 and stored as an element of matrix 130. Matrix 130 also includes 25 elements, i.e., c 0 ,......,c 24 , these elements are arranged into five rows and five columns (5x5). Standard matrix multiplication requires that the number of columns of matrix 110 (ie, 5) equal the number of rows of matrix 120 (ie, 5).

[0024] In general, the dot product of a row of matrix 110 and a column of matrix 130 is calculated by multiplying each element in the row of matrix 110 by the corresponding element in the column of matrix 120 to generate an intermediate product, and then accumulating the intermediate products to the corresponding element of matrix 130. For example, element c of matrix 130 0 is the dot product of the first row 112 of the matrix 110 and the first column 122 of the matrix 120, that is, c 0 Equal to a 0 b 0 +a 1 .b 5 +a 2 .b 10 +a 3 b 15 +a 4 .b 20Similarly, the element c of matrix 130 is calculated using the first row 112 of matrix 110 and the second column of matrix 120. 1 The dot product of 1 Equal to a 0 πb 1 +a 1 b 6 +a 2 b 11 +a 3 b 16 +a 4 b 21 . And for the remaining elements c of matrix 130 2 , ..., c 24 And so on.

[0025] The matrix outer product may also be used to multiply matrix 110 by matrix 120 to generate matrix 130 .

[0026] Figure 2A , Figure 2B and Figure 2C A matrix outer product 101 is shown according to an embodiment of the present disclosure.

[0027] The outer product of matrix 110 and matrix 120 generates matrix 130. To calculate the outer product of matrix 110 and matrix 120, the outer product is calculated for each row in matrix 110 and matrix 120 and stored as a row of matrix 130. The outer product of each row in matrix 110 and matrix 120 includes multiple scalar vector calculations, each of which produces a partial result for the elements of the corresponding row of matrix 130. The partial results are combined (or summed) to produce the final result for the elements of the corresponding row of matrix 130.

[0028] For example, the outer product of the first row 112 of the matrix 110 and the matrix 120 generates the first row 132 of the matrix 130. The first row of the matrix 110 includes elements a 0 、a 1 、a 2 、a 3 、a 4 The matrix 120 includes five rows, namely, the first row 124 (ie, element b 0 、b 1 、b 2 、b 3 、b 4 ), the second row 125 (ie, element b 5 、b 6 、b 7 、b 8 、b 9 ), the third row 126 (ie, element b 10 、b11 、b 12 、b 13 、b 14 ), the fourth row 127 (i.e., element b 15 、b 16 、b 17 、b 18 、b 19 ) and the fifth row 128 (i.e., element b 20 、b 21 、b 22 、b 23 、b 24 ). The first row 132 of the matrix 130 includes elements c 0 、c 1 、c 2 、c 3 、c 4 .

[0029] The first scalar vector calculation converts the element a 0 and each element in the first row 124 (i.e., element b 0 、b 1 、b 2 、b 3 、b 4 ) to generate the elements of the first row 132 of the matrix 130 (i.e., a 0 b 0 、a 0 b 1 、a 0 b 2 、a 0 b 3 、a 0 b 4 ) partial result 134. The second scalar vector calculation converts the element a 1 and each element in the second row 125 (i.e., element b 5 、b 6 、b 7 、b 8 、b 9 ) to generate the elements of the first row 132 of the matrix 130 (i.e., a 1 b 5 、a 1 b 6 、a 1 b 7 、a 1 b 8 、a 1 b 9 ) partial result 135. The third scalar vector calculation converts the element a 2 and each element in the third row 126 (i.e., element b10 、b 11 、b 12 、b 13 、b 14 ) to generate the elements of the first row 132 of the matrix 130 (i.e., element a 2 b 10 、a 2 b 11 、a 2 b 12 、a 2 b 13 、a 2 b 14 ) partial result 136. The fourth scalar vector calculation converts the element a 3 and each element in the fourth row 127 (i.e., element b 15 、b 16 、b 17 、b 18 、b 19 ) to generate the elements of the first row 132 of the matrix 130 (i.e., element a 3 b 15 、a 3 b 16 、a 3 b 17 、a 3 b 18 、a 3 b 19 ) partial result 137. The fifth scalar vector calculation converts the element a 4 and each element in the fifth row 128 (i.e., element b 20 、b 21 、b 22 、b 23 、b 24 ) to generate the elements of the first row 132 of the matrix 130 (i.e., element a 4 b 20 、a 4 b 21 、a 4 b 22 、a 4 b 23 、a 4 b 24 )Partial results 138.

[0030] The partial results are combined (or summed) to produce a final result of the elements of the first row 132 of the matrix 130, i.e., the elements c 0 Equal to a 0 b 0 +a 1 b 5 +a2 b 10 +a 3 b 15 +a 4 b 20 , element c 1 Equal to a 0 b 1 +a 1 b 6 +a 2 b 11 +a 3 b 16 +a 4 b 21 , element c 2 Equal to a 0 b 2 +a 1 b 7 +a 2 b 12 +a 3 b 17 +a 4 b 22 , element c 3 Equal to a 0 b 3 +a 1 b 8 +a 2 b 13 +a 3 b 18 +a 4 b 23 , and the element c 4 equal 0 b 4 +a 1 b 9 +a 2 b 14 +a 3 b 19 +a 4 b 24 .

[0031] The outer products of the remaining rows of matrix 130 are similarly calculated.

[0032] Figure 3A , Figure 3B and Figure 3C A matrix outer product 102 is shown in accordance with an embodiment of the present disclosure.

[0033] In this embodiment, matrix 110 and matrix 120 are sparse matrices in which more than half of the elements in each matrix have a value of 0. The non-zero elements of matrix 110 are elements a 0 、a 3 、a 6、a 9 、a 12 、a 16 、a 19 and a 23 , and the non-zero elements of matrix 120 are b 1 、b 3 、b 4 、b 7 、b 10 、b 16 、b 18 、b 20 and b 23 Due to the sparsity of matrices 110 and 120 , the outer product for each row of matrix 110 and matrix 120 includes a reduced number of scalar-vector computations that generate a reduced number of non-zero elements in matrix 130 .

[0034] For example, as described above, the outer product of the first row 112 of the matrix 110 and the matrix 120 generates the first row 132 of the matrix 130. Because the first row of the matrix 110 includes non-zero elements a 0 (column 1) and a 3 (column 4), so only two scalar-vector calculations are required to determine the non-zero elements of the first row 132 of the matrix 130.

[0035] The first scalar vector calculation converts the element a 0 and each element in the first row 124 of non-zero elements (i.e., element b 1 、b 3 、b 4 ) to generate the elements of the first row 132 of the matrix 130 (i.e., 0, a 0 b 1 , 0, a 0 b 3 、a 0 b 4 ) partial result 134. The second scalar vector calculation converts the element a 3 and each of the non-zero elements in the fourth row 127 (i.e., element b 16 、b 18 ) to generate the elements of the first row 132 of the matrix 130 (i.e., 0, a 3 b 16 , 0, a 3 b 18 ,0)partial results 137.

[0036] The partial results are combined (or summed) to produce a final result for the elements of the first row 132 of the matrix 130, i.e., the elements c 1 Equal to a 0 b 1 +a 3b 16 , element c 3 Equal to a 0 b 3 +a 3 b 18 , and the element c 4 Equal to a 0 b 4 .

[0037] Figure 4A A standard matrix-vector multiplication 103 is shown according to an embodiment of the present disclosure.

[0038] The matrix 110 includes 25 elements, namely, a 0 ,......,a 24 , these elements are arranged in five rows and five columns (5x5). Vector 140 includes five elements, namely, b 0 、b 1 、b 2 、b 3 、b 4 , these elements are arranged into five rows and one column (5x1). To multiply matrix 110 with vector 140, the dot product (or inner product) is calculated for each row of matrix 110 and vector 140 and stored as an element of vector 150. Vector 150 includes 5 elements, namely, c 0 、c 1 、c 2 、c 3 、c 4 , these elements are arranged in five rows and one column (5x1). Standard matrix-vector multiplication requires that the number of columns of matrix 110 (ie, 5) equal the number of rows of vector 140 (ie, 5).

[0039] In general, the dot product of a row of matrix 110 and vector 140 is calculated by multiplying each element of the row of matrix 110 by the corresponding element of vector 140 to generate an intermediate product, and then accumulating the intermediate products into the corresponding element of vector 150. For example, element c of vector 150 0 is the dot product of the first row 112 of the matrix 110 and the vector 140, that is, c 0 Equal to a 0 b 0 +a 1 b 1 +a 2 b 2 +a 3 b 3 +a 4 b 4 Similarly, the second row of matrix 110 and vector 140 are used to calculate element c for vector 150. 1 The dot product of1 Equal to a 5 b 0 +a 6 b 1 +a 7 b 2 +a 8 b 3 +a 9 b 4 For the remaining elements c of vector 150 2 、c 3 、c 4 And so on, that is, element c 2 Equal to b 0 a 10 +b 1 a 11 +b 2 a 12 +b 3 a 13 +b 4 a 14 , element c 3 Equal to b 0 a 15 +b 1 a 16 +b 2 a 17 +b 3 a 18 +b 4 a 19 , element c 4 Equal to b 0 a 20 +b 1 a 21 +b 2 a 22 +b 3 a 23 +b 4 a 24 .

[0040] The matrix outer product may also be used to multiply matrix 110 by vector 140 to generate vector 150 .

[0041] Figure 4B and Figure 4C A matrix-vector outer product 104 is shown in accordance with an embodiment of the present disclosure.

[0042] The outer product of matrix 110 and vector 140 generates vector 150. The outer product of matrix 110 and vector 140 includes multiple scalar vector calculations, each of which generates a partial result for an element of vector 150. The partial results are combined (or summed) to generate a final result for the elements of vector 150.

[0043] The matrix 110 includes five columns, namely, a first column 114 (i.e., element a 0 、a 5 、a 10 、a 15 、a 20 ), the second column 115 (ie, element a 1 、a 6 、a 11 、a 16 、a 21 ), the third row 126 (ie, element a 2 、a 7 、a 12 、a 17 、a 22 ), the fourth row 127 (i.e., element a 3 、a 8 、a 13 、a 18 、a 23 ) and the fifth row 128 (i.e., element a 4 、a 9 、a 14 、a 19 、a 24 ). Vector 140 includes five rows (ie, elements b 0 、b 1 、b 2 、b 3 、b 4 ), and the vector 150 includes five rows, i.e., elements c 0 、c 1 、c 2 、c 3 、c 4 .

[0044] The first scalar vector calculation converts the element b 0 (row 1) and each element in the first column 114 (i.e., element a 0 、a 5 、a 10 、a 15 、a 20 ) to generate a partial result vector 154 (i.e., b 0 a 0 、b 0 a 5 、b 0 a 10 、b 0 a 15 、b 0 a 20 ). The second scalar vector calculation converts the element b 1 (row 2) and each element in the second column 115 (i.e., element a1 、a 6 、a 11 、a 16 、a 21 ) to generate a partial result vector 155 (i.e., b 1 a 1 、b 1 a 6 、b 1 a 11 、b 1 a 16 、b 1 a 21 ). The third scalar vector calculation converts the element b 2 (row 3) and each element in the third column 116 (i.e., element a 2 、a 7 、a 12 、a 17 、a 22 ) to generate a partial result vector 156 (i.e., b 2 a 2 、b 2 a 7 、b 2 a 12 、b 2 a 17 、b 2 a 22 ). The fourth scalar vector calculation converts the element b 3 (row 4) and each element in the fourth column 117 (i.e., element a 3 、a 8 、a 13 、a 18 、a 23 ) to generate a partial result vector 157 (i.e., b 3 a 3 、b 3 a 8 、b 3 a 13 、b 3 a 18 、b 3 a 23 ). The fifth scalar vector calculation converts the element b 4 (row 5) and each element in the fifth column 118 (i.e., element a 4 、a 9 、a 14 、a 19 、a 24 ) to generate a partial result vector 158 (i.e., b 4 a 4 、b 4 a9 、b 4 a 14 、b 4 a 19 、b 4 a 24 ).

[0045] The partial result vectors are merged to generate the final result for vector 150, i.e., element c 0 Equal to b 0 a 0 +b 1 a 1 +b 2 a 2 +b 3 a 3 +b 4 a 4 , element c 1 Equal to b 0 a 5 +b 1 a 6 +b 2 a 7 +b 3 a 8 +b 4 a 9 , element c 2 Equal to b 0 a 10 +b 1 a 11 +b 2 a 12 +b 3 a 13 +b 4 a 14 , element c 3 Equal to b 0 a 15 +b 1 a 16 +b 2 a 17 +b 3 a 18 +b 4 a 19 , and the element c 4 Equal to b 0 a 20 +b 1 a 21 +b 2 a 22 +b 3 a 23 +b 4 a 24In some embodiments, the partial result vectors are merged in a single operation, while in other embodiments, the partial result vectors are merged in a series of partial merge operations.

[0046] Figure 4D A merge operation 105 is shown in accordance with an embodiment of the present disclosure.

[0047] In this embodiment, partial result vector 154 and partial result vector 155 are merged to generate intermediate partial result vector 160, partial result vector 156 and partial result vector 157 are merged to generate intermediate partial result vector 162, intermediate partial result vector 160 and intermediate partial result vector 162 are merged to generate intermediate partial result vector 164, and partial result vector 158 and intermediate partial result vector 164 are merged to generate the final result of vector 150.

[0048] The intermediate partial result vector 160 includes elements p 0 0 、p 0 1 、p 0 2 、p 0 3 、p 0 4 , the intermediate result vector 162 includes elements p 1 0 、p 1 1 、p 1 2 、p 1 3 、p 1 4 , the intermediate result vector 164 includes elements p 2 0 、p 2 1 、p 2 2 、p 2 3 、p 2 4 For the intermediate result vector 160, element p 0 0 Equal to b 0 a 0 +b 1 a 1 , element p 0 1 Equal to b 0 a 5 +b 1 a 6 , element p 02 Equal to b 0 a 10 +b 1 a 11 , element p 0 3 Equal to b 0 a 15 +b 1 a 16 , and the element p 0 4 Equal to b 0 a 20 +b 1 a 21 For the intermediate result vector 162, the element p 1 0 Equal to b 2 a 2 +b 3 a 3 , element p 1 1 Equal to b 2 a 7 +b 3 a 8 , element p 1 2 Equal to b 2 a 12 +b 3 a 13 , element p 1 3 Equal to b 2 a 17 +b 3 a 18 , and the element p 1 4 Equal to b 2 a 22 +b 3 a 23 For the intermediate result vector 164, element p 2 0 Equal to b 0 a 0 +b 1 a 1 +b 2 a 2 +b 3 a 3 , element p 2 1 Equal to b 0 a 5 +b 1 a 6 +b 2 a 7 +b3 a 8 , element p 2 2 Equal to b 0 a 10 +b 1 a 11 +b 2 a 12 +b 3 a 13 , element p 2 3 Equal to b 0 a 15 +b 1 a 16 +b 2 a 17 +b 3 a 18 , element p 2 4 Equal to b 0 a 20 +b 1 a 21 +b 2 a 22 +b 3 a 23 .

[0049] The final result for vector 150 is the same as for the standard matrix-vector multiplication operation described above.

[0050] Figure 5A and Figure 5B A matrix-vector outer product 106 is shown in accordance with an embodiment of the present disclosure.

[0051] In this embodiment, matrix 110 is a sparse matrix in which more than half of the elements have a value of 0, and vector 140 is a sparse vector in which more than half of the elements have a value of 0. The non-zero elements of matrix 110 are elements a 0 、a 3 、a 6 、a 9 、a 13 、a 17 、a 19 and a 21 , and the non-zero elements of vector 140 are b 2 and b 4 Due to the sparsity of matrix 110 and vector 140, the outer product includes a reduced number of scalar-vector computations that generate a reduced number of non-zero elements in vector 150, namely, element c 1 and c 3 .

[0052] The first scalar vector calculation converts the element b2 (row 3) and each of the non-zero elements in the third column 116 (i.e., element a 17 ) to generate a partial result vector 156 (i.e., 0, 0, 0, b 2 a 17 , 0). The second scalar vector calculation converts the element b 4 (row 5) and each of the non-zero elements in the fifth column 118 (i.e., element a 9 、a 19 ) to generate a partial result vector 158 (i.e., 0, b 4 a 9 , 0, b 4 a 19 , 0).

[0053] The partial results are combined (or summed) to produce the final result of vector 150, i.e., element c 1 Equal to b 4 a 9 , and the element c 3 Equal to b 2 a 17 +b 4 a 19 .

[0054] Figure 5C , Figure 5D and Figure 5E A matrix-vector outer product 106 is shown in accordance with an embodiment of the present disclosure.

[0055] This graph sequence gives the Figure 5A and Figure 5B The same matrix-vector outer product operation is shown for matrix 110 and vector 140 with the addition of an indexing technique to identify the non-zero elements of matrix 110 and vector 140 .

[0056] In general, a pair of index vectors or a single dimension array may be used to identify the non-zero elements of a matrix. In one embodiment, a first index vector includes an element for each column, and the value of each element is the number of non-zero elements in all previous columns, such as 0, 1, 3, 4, 6, etc. A second index vector includes row indices for the non-zero elements in each column, starting with an index value of 0. The second index vector typically includes a variable number of elements based on the number of non-zero elements in the matrix, so an indexing technique must be used to access the row index.

[0057] In this example, matrix 110 has a first index vector 170 having 5 elements (i.e., one element per column) and a second index vector 172 having 8 elements (i.e., one element per non-zero element). The first element of first index vector 170 has a value of 0, which is the number of non-zero elements before column 1, i.e., 0. The value of the first element of first index vector 170 is used as an index into second index vector 172. The element of second index vector 172 at index 0 has a value of 0, which is the row index of the non-zero element in column 1, i.e., a 0 The difference between the first and second elements of index vector 170 (ie, 1) indicates that there is only one non-zero element in column 1.

[0058] The second element of first index vector 170 has a value of 1, which is the number of non-zero elements before column 2, i.e., the number of non-zero elements in column 1. The value of the second element of first index vector 170 is used as an index into second index vector 172. The element of second index vector 172 at index 1 has a value of 1, which is the row index of the first non-zero element in column 2, i.e., a 6 The difference between the second and third elements of index vector 170 (i.e., 2) indicates that there is a second non-zero element in column 2. The element at index 2 of second index vector 172 has a value of 4, which is the row index of the second non-zero element in column 2, i.e., a 21 .

[0059] The third element of first index vector 170 has a value of 3, which is the number of non-zero elements before column 3, i.e., the number of non-zero elements in columns 1 and 2. The value of the third element of first index vector 170 is used as an index into second index vector 172. The element of second index vector 172 at index 3 has a value of 3, which is the row index of the non-zero element in column 3, i.e., a 17 The difference between the third and fourth elements of index vector 170 (ie, 1) indicates that there is only one non-zero element in column 3 .

[0060] The fourth element of first index vector 170 has a value of 4, which is the number of non-zero elements before column 4, i.e., the number of non-zero elements in columns 1, 2, and 3. The value of the fourth element of first index vector 170 is used as an index into second index vector 172. The element of second index vector 172 at index 4 has a value of 0, which is the row index of the first non-zero element in column 4, i.e., a 3 The difference between the fourth and fifth elements of index vector 170 (i.e., 2) indicates that there is a second non-zero element in column 4. The element at index 5 of second index vector 172 has a value of 2, which is the row index of the second non-zero element in column 4, i.e., a 13 .

[0061] The fifth element of first index vector 170 has a value of 6, which is the number of non-zero elements before column 5, i.e., the number of non-zero elements in columns 1, 2, 3, and 4. The value of the fourth element of first index vector 170 is used as an index into second index vector 172. The element of second index vector 172 at index 6 has a value of 1, which is the row index of the first non-zero element in column 5, i.e., a 9 The difference (i.e., 2) between the sixth element (i.e., 6) of index vector 170 and the magnitude (i.e., 8) of second index vector 172 indicates that there is a second non-zero element in column 5. The element at index 7 of second index vector 172 has a value of 3, which is the row index of the second non-zero element in column 5, i.e., a 19 Alternatively, first index vector 170 may include a seventh (last) element having a value of 8, and the difference between the sixth and seventh elements of index vector 170 (ie, 2) indicates that there is a second non-zero element in the fifth column.

[0062] In general, a single index vector or a single dimension array may be used to identify the non-zero elements of a vector. In this embodiment, the index vector includes a row index for each non-zero element in each column, starting with an index value of 0. The second index vector typically includes a variable number of elements based on the number of non-zero elements in the vector.

[0063] In this example, vector 140 has an index vector 174 with 2 elements, i.e., one index vector for each non-zero element. The first element of index vector 174 has a value of 2, which is the row index of the first non-zero element in vector 140, i.e., b 2 The second element of index vector 174 has a value of 4, which is the row index of the second non-zero element in vector 140, i.e., b 4 .

[0064] Using first index vector 170, second index vector 172, and index vector 174, a first scalar vector calculation converts element b 2 (identified by row index 2) and the non-zero elements of column 3 of matrix 110 (i.e., element a 17 (identified by column index 2 and row index 3)) to generate the element [c 3 ] partial result vector 156, that is, b 2 a 17 The partial result vector 156 is composed of the partial result [c 3 ] and may have a row index 176 that identifies the index of the non-zero partial result element, such as Figure 5C As shown in .

[0065] The second scalar vector calculation converts the element b4 (identified by row index 4) and the first non-zero element of column 5 of matrix 110 (i.e., element a 9 (identified by column index 4 and row index 1)) to produce the partial result [c 1 ], that is, b 4 a 9 The second scalar vector calculation also adds the element b 4 (identified by row index 4) and the second non-zero element of column 5 of matrix 110 (i.e., element a 19 (identified by column index 4 and row index 3)) to produce the partial result [c 3 ], that is, b 4 a 19 The partial result vector 158 is composed of the partial result [c 1 ](i.e., b 4 a 9 ) and [c 3 ](i.e., b 4 a 19 ) and may have a row index 178 identifying the index of the non-zero partial result element, such as Figure 5D As shown in .

[0066] The partial result vectors 156 and 158 are combined (or summed) to produce the final result of vector 150, i.e., element c 1 Equal to b 4 a 9 , and the element c 3 Equal to b 2 a 17 +b 4 a 19 ,like Figure 5E As shown in .

[0067] As described above, partial result vectors 156 and 158 are sparse vectors. In general, while any vector can be represented by an index vector or single dimension array and a compact data vector or single dimension array, this form of representation is particularly advantageous for sparse vectors.

[0068] Fig. 6A Two sparse vectors 210 and 220 are shown according to an embodiment of the present disclosure.

[0069] Vector 210 (i.e., Z_0

[25] ) has 25 elements, including 6 elements with non-zero values ​​and 19 elements with zero values. Using an indexing system starting at 0, elements Z_0[0], Z_0[2], Z_0[3], Z_0[7], Z_0

[20] , and Z_0

[24] have non-zero values, typically represented by A, B, C, D, E, and F, respectively. Index vector 212 (i.e., Z_0_idx[6]) is a 6-element sorted vector formed by these index values, and includes element Z_0_idx[0] with a value of 0, element Z_0_idx[1] with a value of 2, element Z_0_idx[2] with a value of 3, element Z_0_idx[3] with a value of 7, element Z_0_idx[4] with a value of 20, and element Z_0_idx[5] with a value of 24. Data vector 214 (i.e., Z_0_data[6]) is a 6-element vector formed by non-zero values ​​and includes element Z_0_data[0] with value A, element Z_0_data[1] with value B, element Z_0_data[2] with value C, element Z_0_data[3] with value D, element Z_0_data[4] with value E, and element Z_0_data[5] with value F.

[0070] Vector 220 (i.e., Z_1

[25] ) also has 25 elements, including 6 elements with non-zero values ​​and 19 elements with zero values. Using an indexing system starting at 0, elements Z_1[1], Z_1[3], Z_1[5], Z_1[7], Z_1[9], and Z_1

[20] have non-zero values ​​that are typically represented by H, I, J, K, L, and M, respectively. Index vector 222 (i.e., Z_1_idx[6]) is a 6-element sorted vector formed by these index values ​​and includes element Z_1_idx[0] with a value of 1, element Z_1_idx[1] with a value of 3, element Z_1_idx[2] with a value of 5, element Z_1_idx[3] with a value of 7, element Z_1_idx[4] with a value of 9, and element Z_1_idx[5] with a value of 20. Data vector 224 (i.e., Z_1_data[6]) is a 6-element vector formed by non-zero values ​​and includes an element Z_0_data[0] with a value H, an element Z_0_data[1] with a value I, an element Z_0_data[2] with a value J, an element Z_0_data[3] with a value K, an element Z_0_data[4] with a value L, and an element Z_0_data[5] with a value M.

[0071] In another embodiment, index vectors 212 and 222 may be used to access non-zero valued data within vectors 210 and 220, respectively, and data vectors 214 and 224 may not be required. For example, the following pseudo code loop accesses non-zero valued data in vector 210 and stores the data in Z_0_data[]:

[0072] For (i=0;i<6;i++){

[0073] Z_0_data[i]=Z_0[Z_0_idx[i]];

[0074] }

[0075] Vectors 210 and 220 , index vectors 212 and 222 , and data vectors 214 and 224 are typically stored in memory, vector registers, or the like for further processing, such as merge operations of indices or data.

[0076] Merging sparse vectors is very useful for sparse arithmetic problems, such as, as discussed above, multiplying two sparse matrices, multiplying a sparse matrix with a sparse vector, etc. In addition, it is also very useful to simply include a list of numbers without associated data. In other words, instead of a sparse vector, vector 210 may include an index vector 212 without associated data, and vector 220 may include an index vector 212 without associated data. For example, the structure or connectivity of an analysis graph may not require access to the weights of the edges of the graph (i.e., data). These problems follow the same matrix*matrix or matrix*vector process, using one (for non-zero values) and zero, which will be represented by a list of indexes in the result. In an example, a breadth-first search to find whether two nodes are connected by any series of edges can be implemented by iteration of a logical matrix*vector, thereby generating a list of connected nodes, checking the list to determine whether a certain node in the graph is connected to a starting node.

[0077] In another example, index vector 212 may be a sorted list of factors for a first number, index vector 222 may be a sorted list of factors for a second number, and the sorted merge vector (or list) is a sorted list of factors for the product of the first number and the second number. Importantly, embodiments of the present disclosure may be applied to data that includes or may be partitioned into densely populated vectors, or a combination of densely populated vectors and one or more sparse vectors, and the like.

[0078] Figure 6B and Figure 6C A merge operation 200 of two vectors of sorted indices is shown according to an embodiment of the present disclosure.

[0079] The index vector 212 is stored in the vector register 230 and the index vector 222 is stored in the vector register 232; other memories may also be used. The two-dimensional (2D) comparator array 240 includes a comparator array 242 that compares the value stored in the vector register 230 with the value stored in the vector register 232 to determine whether the value in the vector register 230 is equal to (i.e., "="), less than (i.e., "<"), or greater than (i.e., ">") the value stored in the vector register 232. The vector registers 230, 232 and the comparator array 240 are generally sized to support the size of the index vectors 212 and 222; in this embodiment, the comparator array 240 is a 6x6 array. In some embodiments, the comparator array 240 is a two-dimensional (2D) multiply and accumulate (MAC) array in which a comparator 242 has been added to each array element. In other embodiments, the vector registers 230, 232 and the comparator array 240 may be replaced by one or more processor instructions that perform comparison operations, as discussed below.

[0080] In general, the merge operation 200 reads vectors 210 and 220 from a storage device (e.g., a memory) and stores index vectors 212 and 222 in vector registers 230 and 232, respectively. The merge operation 200 then compares the index values ​​in the vector registers 230 and 232 using a comparator array 240, and generates several intermediate vectors for each of the vectors 210 and 220 based on the output of the comparator array 240. The intermediate vectors for the vector 210 include a GT_count vector 250, an EQ_count vector 252, and an EQ_prefix_sum vector 254, while the intermediate vectors for the vector 220 include a LT_count vector 260, an EQ_count vector 262, and an EQ_prefix_sum vector 264.

[0081] The merge operation 200 then generates a scatter index vector 256 for vector 210 and a scatter index vector 266 for vector 220 based on the corresponding intermediate vectors and the baseline index vector 270. The merge operation 200 then performs a scatter operation on the index vectors 212 and 222 (or data vectors 214 and 224), respectively, using the scatter index vectors 256 and 266 to generate a sorted merged vector of indices (or data, as discussed below) 290. The intermediate vectors, the baseline index vector 270, the scatter index vectors 256 and 266, and the sorted merged vector 290 may be stored in vector registers, a memory, or the like.

[0082] With respect to the comparison operation, the comparators 242 in the first row of the comparator array 240 compare the first element of the vector register 230 (i.e., Z_0_idx[0] having a value of 0) with all elements of the vector register 232 (i.e., Z_1_idx[0], ..., Z_1_idx[5] having values ​​of 1, 3, 5, 7, 9, and 20). In this example, all six comparators 242 in the first row output a value indicating "<".

[0083] The comparators 242 in the second row of the comparator array 240 compare the second element of the vector register 230 (i.e., Z_0_idx[1] having a value of 2) with all elements of the vector register 232 (i.e., Z_1_idx[0], ..., Z_1_idx[5]). In this example, the first comparator 242 outputs a value indicating ">", while the remaining five comparators 242 output values ​​indicating "<".

[0084] The comparators 242 in the third row of the comparator array 240 compare the third element of the vector register 230 (i.e., Z_0_idx[2] having a value of 3) with all elements of the vector register 232 (i.e., Z_1_idx[0], ..., Z_1_idx[5]). In this example, the first comparator 242 outputs a value representing ">", the second comparator outputs a value representing "=", and the remaining four comparators 242 output values ​​representing "<".

[0085] The comparator 242 in the fourth row of the comparator array 240 compares the fourth element of the vector register 230 (i.e., Z_0_idx[3] having a value of 7) with all elements of the vector register 232 (i.e., Z_1_idx[0], ..., Z_1_idx[5]). In this example, the first comparator 242, the second comparator 242, and the third comparator 242 output values ​​representing ">", the fourth comparator outputs a value representing "=", and the remaining two comparators 242 output values ​​representing "<".

[0086] The comparators 242 in the fifth row of the comparator array 240 compare the fifth element of the vector register 230 (i.e., Z_0_idx[4] having a value of 20) with all elements of the vector register 232 (i.e., Z_1_idx[0], ..., Z_1_idx[5]). In this example, the first five comparators 242 output values ​​indicating ">", and the last comparator 242 outputs a value indicating "=".

[0087] The comparator 242 in the sixth row of the comparator array 240 compares the sixth element of the vector register 230 (i.e., Z_0_idx[5] having a value of 24) with all elements of the vector register 232 (i.e., Z_1_idx[0], ..., Z_1_idx[5]). In this example, all six comparators 242 output a value indicating ">".

[0088] The output of comparator 242 is used to generate several intermediate vectors for each index vector, including GT_count vector 250 and EQ_count vector 252 for index vector 212 and LT_count vector 260 and EQ_count vector 262 for index vector 222. In addition, EQ_prefix_sum vector 254 is generated based on EQ_count vector 252, and EQ_prefix_sum vector 264 is generated based on EQ_count vector 262. Scattered index vector 256 is generated for index vector 212 based on GT_count vector 250, EQ_prefix_sum vector 254, and baseline index vector 270, while scattered index vector 266 is generated for index vector 222 based on LT_count vector 260, EQ_prefix_sum vector 264, and baseline index vector 270.

[0089] More specifically, the GT_count vector 250 is generated by counting the number of output values ​​representing ">" in each row of the comparator array 240. The 1st row has 0 output values ​​representing ">", the 2nd row has 1 output value representing ">", the 3rd row has 1 output value representing ">", the 4th row has 3 output values ​​representing ">", the 5th row has 5 output values ​​representing ">", and the 6th row has 6 output values ​​representing ">". Therefore, the GT_count vector 250 includes 6 elements with values ​​0, 1, 1, 3, 5, 6.

[0090] Similarly, the LT_count vector 260 is generated by counting the number of output values ​​representing "<" in each column of the comparator array 240. The 1st column has 1 output value representing "<", the 2nd column has 2 output values ​​representing "<", the 3rd column has 3 output values ​​representing "<", the 4th column has 3 output values ​​representing "<", the 5th column has 4 output values ​​representing "<", and the 6th column has 4 output values ​​representing "<". Therefore, the LT_count vector 260 includes 6 elements with values ​​1, 2, 3, 3, 4, 4.

[0091] The EQ_count vector 252 is generated by counting the number of output values ​​indicating "=" in each column of the comparator array 240. The 1st row has 0 output values ​​indicating "=", the 2nd row has 0 output values ​​indicating "=", the 3rd row has 1 output value indicating "=", the 4th row has 1 output value indicating "=", the 5th row has 1 output value indicating "=", and the 6th row has 0 output values ​​indicating "=". Therefore, the EQ_count vector 252 includes 6 elements with values ​​0, 0, 1, 1, 1, 0.

[0092] Similarly, the EQ_count vector 262 is generated by counting the number of output values ​​representing "=" in each column of the comparator array 240. The 1st column has 0 output values ​​representing "=", the 2nd column has 1 output value representing "=", the 3rd column has 0 output values ​​representing "=", the 4th column has 1 output value representing "=", the 5th column has 0 output values ​​representing "=", and the 6th column has 1 output value representing "=". Therefore, the EQ_count vector 262 includes 6 elements with values ​​0, 1, 0, 1, 0, 1.

[0093] The EQ_prefix_sum vector 254 is generated based on the EQ_count vector 252 as follows. The first element is equal to 0, the second element is equal to the value of the first element of the EQ_count vector 252 (i.e., 0), the third element is equal to the sum of the first element and the second element of the EQ_count vector 252 (i.e., 0=0+0), the fourth element is equal to the sum of the first, second, and third elements of the EQ_count vector 252 (i.e., 1=0+0+1), the fifth element is equal to the sum of the first, second, third, and fourth elements of the EQ_count vector 252 (i.e., 2=0+0+1+1), and the sixth element is equal to the sum of the first, second, third, fourth, and fifth elements of the EQ_count vector 252 (i.e., 3=0+0+1+1+1). Therefore, the EQ_prefix_sum vector 254 includes 6 elements with values ​​0, 0, 0, 1, 2, and 3.

[0094] The following pseudo-code loop illustrates another technique for generating the EQ_pref x_sum vector:

[0095]

[0096] The EQ_prefix_sum vector 264 is generated based on the EQ_count vector 262 as follows. The first element is equal to 0, the second element is equal to the value of the first element of the EQ_count vector 262 (i.e., 0), the third element is equal to the sum of the first element and the second element of the EQ_count vector 262 (i.e., 1=0+1), the fourth element is equal to the sum of the first, second, and third elements of the EQ_count vector 262 (i.e., 1=0+1+0), the fifth element is equal to the sum of the first, second, third, and fourth elements of the EQ_count vector 262 (i.e., 2=0+1+0+1), and the sixth element is equal to the sum of the first, second, third, fourth, and fifth elements of the EQ_count vector 262 (i.e., 2=0+1+0+1). Therefore, the EQ_prefix_sum vector 264 includes 6 elements with values ​​0, 0, 1, 1, 2, and 2.

[0097] Baseline index vector 270 includes 6 elements having values ​​equal to their corresponding row indices (i.e., 0, 1, 2, 3, 4, 5). In other embodiments, if vectors 210 and 220 have not been sorted, baseline index vector 270 may include a count that is greater than the vector relative to its own elements.

[0098] The scatter index vector 256 is generated by subtracting the EQ_prefix_sum vector 254 from the GT_count vector 250 and adding the baseline index vector 270. The first element is equal to 0, i.e., 0=0-0+0, the second element is equal to 2, i.e., 2=1-0+1, the third element is equal to 3, i.e., 3=1-0+2, the fourth element is equal to 5, i.e., 5=3-1+3, the fifth element is equal to 7, i.e., 7=5-2+4, and the sixth element is equal to 8, i.e., 8=6-3+5. Therefore, the scatter index vector 256 includes 6 elements with values ​​0, 2, 3, 5, 7, 8.

[0099] Similarly, scatter index vector 266 is generated by subtracting EQ_prefix_sum vector 264 from LT_count vector 260 and adding baseline index vector 270. The first element is equal to 1, i.e., 1=1-0+0, the second element is equal to 3, i.e., 3=2-0+1, the third element is equal to 4, i.e., 4=3-1+2, the fourth element is equal to 5, i.e., 5=3-1+3, the fifth element is equal to 6, i.e., 6=4-2+4, and the sixth element is equal to 7, i.e., 7=4-2+5. Therefore, scatter index vector 256 includes 6 elements with values ​​1, 3, 4, 5, 6, 7.

[0100] Scatter operation 280 merges index vectors 212 and 222 into sorted merged vector 290 using scatter index vectors 256 and 266, respectively. When the index values ​​from index vectors 212 and 222 are equal, they are scattered into the same element of sorted merged vector 290; the second value simply overwrites the first value in storage.

[0101] For vector 210, the first element of index vector 212 (having a value of 0) is scattered into the first element of sorted merged vector 290 (having a row index of 0) using the first element of scatter index vector 256 (having a value of 0). The second element of index vector 256 (having a value of 2) is scattered into the third element of sorted merged vector 290 (having a row index of 2) using the second element of scatter index vector 212 (having a value of 2). The third element of index vector 256 (having a value of 3) is scattered into the fourth element of sorted merged vector 290 (having a row index of 3) using the third element of scatter index vector 212 (having a value of 3). The fourth element of index vector 256 (having a value of 7) is scattered into the sixth element of sorted merged vector 290 (having a row index of 5) using the fourth element of scatter index vector 212 (having a value of 5). The fifth element of index vector 256 (having a value of 20) is scattered into the eighth element of sorted merged vector 290 (having row index 7) using the fifth element of scatter index vector 212 (having a value of 7). The sixth element of index vector 256 (having a value of 24) is scattered into the ninth element of sorted merged vector 290 (having row index 8) using the sixth element of scatter index vector 212 (having a value of 8).

[0102] For vector 220, the first element of index vector 266 (having a value of 1) is scattered into the second element of sorted merged vector 290 (having a row index of 1) using the first element of scatter index vector 222 (having a value of 1). The second element of index vector 266 (having a value of 3) is scattered into the fourth element of sorted merged vector 290 (having a row index of 3) using the second element of scatter index vector 222 (having a value of 3). The third element of index vector 266 (having a value of 5) is scattered into the fifth element of sorted merged vector 290 (having a row index of 4) using the third element of scatter index vector 222 (having a value of 4). The fourth element of index vector 266 (having a value of 7) is scattered into the sixth element of sorted merged vector 290 (having a row index of 5) using the fourth element of scatter index vector 222 (having a value of 5). The fifth element of index vector 266 (having a value of 9) is scattered into the seventh element of sorted merged vector 290 (having row index 6) using the fifth element of scatter index vector 222 (having a value of 6). The sixth element of index vector 266 (having a value of 20) is scattered into the eighth element of sorted merged vector 290 (having row index 7) using the sixth element of scatter index vector 222 (having a value of 7).

[0103] Thus, the sorted merged vector 290 includes 9 elements with values ​​0, 1, 2, 3, 5, 7, 9, 20, 24; three values ​​are overwritten, namely, 3, 5, 7.

[0104] In some embodiments, scatter operation 280 is performed sequentially on index vectors 212 and 222, while in other embodiments, scatter index vectors 256 and 266 are concatenated into a large scatter index vector, index vectors 212 and 222 are concatenated into a large scatter index vector, and scatter operation 280 is performed on the concatenated scatter index and index vector.

[0105] Generally speaking, the scatter operation 280 can be expressed in pseudo code. In some embodiments, the scatter operation can be expressed as a "scatter" instruction:

[0106] Scatter V0, V1, V2 / / where V0 is the output vector,

[0107] V1 is the input vector, and V2 is the index vector.

[0108] Fig.6D A merge operation 202 of two vectors of sorted index and data is shown in accordance with an embodiment of the present disclosure.

[0109] Merge operation 202 is substantially the same as merge operation 200 , with scatter operation 280 being replaced with scatter-add operation 282 that generates sorted merged vector 292 .

[0110] Scatter-add operation 282 merges data vectors 214 and 224 into sorted merged vector 292 using scatter index vectors 256 and 266, respectively. When the index values ​​from index vectors 212 and 222 are equal, the data value from vector 210 is stored in an element of sorted merged vector 292 and the data value from vector 220 is added or accumulated to the same element of sorted merged vector 292.

[0111] In some embodiments, scatter addition operation 282 is performed sequentially on data vectors 214 and 224, while in other embodiments, scatter index vectors 256 and 266 are concatenated into one large scatter index vector, data vectors 214 and 224 are concatenated into one large data vector, and scatter addition operation 282 is performed on the concatenated scatter index and data vectors.

[0112] For vector 210, the first element of data vector 214 (having value A) is scattered into the first element of sorted merged vector 290 (having row index 0) using the first element of scatter index vector 256 (having value 0). The second element of data vector 214 (having value B) is scattered into the third element of sorted merged vector 290 (having row index 2) using the second element of scatter index vector 256 (having value 2). The third element of data vector 214 (having value C) is scattered into the fourth element of sorted merged vector 290 (having row index 3) using the third element of scatter index vector 256 (having value 3).

[0113] The fourth element of the data vector 214 (having a value of D) is scattered into the sixth element of the sorted merged vector 290 (having a row index of 5) using the fourth element of the scatter index vector 256 (having a value of 5). The fifth element of the data vector 214 (having a value of E) is scattered into the eighth element of the sorted merged vector 290 (having a row index of 7) using the fifth element of the scatter index vector 256 (having a value of 7). The sixth element of the data vector 214 (having a value of F) is scattered into the ninth element of the sorted merged vector 290 (having a row index of 8) using the sixth element of the scatter index vector 256 (having a value of 8).

[0114] For vector 220, the first element of data vector 224 (having a value of H) is scattered into the second element of sorted merged vector 292 (having a row index of 1) using the first element of scatter index vector 266 (having a value of 1). The second element of data vector 224 (having a value of I) is scattered using the second element of scatter index vector 266 (having a value of 3) and added or accumulated into the fourth element of sorted merged vector 292 (having a row index of 3). The third element of data vector 224 (having a value of J) is scattered into the fifth element of sorted merged vector 292 (having a row index of 4) using the third element of scatter index vector 266 (having a value of 4).

[0115] The fourth element (having a value of 5) of the data vector 224 (having a value of K) is scattered using the fourth element of the scatter index vector 266 (having a value of 5) and is added or accumulated into the sixth element (having a row index of 5) of the sorted merged vector 292. The fifth element (having a value of L) of the data vector 224 is scattered using the fifth element (having a value of 6) of the scatter index vector 266 into the seventh element (having a row index of 6) of the sorted merged vector 292. The sixth element (having a value of M) of the data vector 224 is scattered using the sixth element (having a value of 7) of the scatter index vector 266 and is added or accumulated into the eighth element (having a row index of 7) of the sorted merged vector 292.

[0116] Thus, the sorted merged vector 292 includes 9 elements with values ​​A, H, B, C+I, J, D+K, L, E+M, F; the three values ​​are added together or accumulated, i.e., C+I, D+K, E+M.

[0117] The scatter-add (or scatter-accumulate) operation can be expressed in pseudocode. In some embodiments, the scatter-add operation can be expressed as a "ScatterAdd" instruction:

[0118] ScatterAdd V0, V1, V2 / / where V0 is the output vector,

[0119] V1 is the input vector, and V2 is the index vector.

[0120] In other embodiments, multiple instructions may be used to implement the scatter-add operation, such as, for example, instructions that scatter two vectors, then calculate an accumulated intersection value, then scatter these accumulated intersection values, overwriting previously written data, and so on.

[0121] Fig. 6E A merge operation 204 of two vectors of sorted indices is shown according to an embodiment of the present invention.

[0122] In this embodiment, vector registers 230, 232, and comparator array 240 have been replaced by processor instructions that perform comparison operations to generate data table 244, and perform row and column counting operations on the values of data table 244 to generate intermediate vectors GT_count vector 250, EQ_count vector 252, LT_count vector 260, and EQ_count vector 262.

[0123] In one embodiment, the comparison operation is a processor instruction that can generally be described by the following pseudocode (other implementations are also contemplated):

[0124]

[0125] Elements "lt", "gt", and "eq" can be condition codes, register bits in a 2D accumulator matrix, etc. The processor instruction compares each element of index vector 212 (i.e., Z_0_idx[i]) with index vector 222 (i.e., Z_1_idx[j]).

[0126] Index vectors 212 and 222 have a vector length of 6, so data table 244 includes 36 elements arranged in 6 rows and 6 columns. In this embodiment, each element contains a triple of 3 bits, where the first bit represents the "equal" or "=" condition or Z_0_idx[i] = Z_1_idx[j], the second bit represents the "less than" or "<" condition or Z_0_idx[i] < Z_1_idx[j], and the third bit represents the "greater than" or ">" condition or Z_0_idx[i] > Z_1_idx[j]. Only one bit is set to 1 in each triple; the remaining bits are set to 0 because the three conditions are mutually exclusive.

[0127] All elements in the first row of data table 244 have the same triple value, i.e., 0, 1, 0. The first element in the second row has a triple value of 0, 0, 1, while the remaining elements in the second row have a triple value of 0, 1, 0. The first element in the third row has a triple value of 0, 0, 1, the second element in the third row has a triple value of 1, 0, 0, and the remaining elements in the third row have a triple value of 0, 1, 0. The first, second, and third elements in the fourth row have a triple value of 0, 0, 1, the fourth element in the fourth row has a triple value of 1, 0, 0, and the fifth and sixth elements in the fourth row have a triple value of 0, 1, 0. The first five elements in the fifth row have a triple value of 0, 0, 1, and the sixth element has a triple value of 1, 0, 0. All elements in the sixth row have a triple value of 0, 0, 1.

[0128] The row-wise greater than (GT) count operation is a processor instruction that can generally be described by the following pseudocode (other implementations are also contemplated):

[0129]

[0130] The processor instruction POP_CNT.row.gt operates on the data table 244 to generate the GT_count vector 250 .

[0131] A row-wise equal (EQ) count operation is a processor instruction that may be generally described by the following pseudo-code (other implementations are also contemplated):

[0132]

[0133] Processor instruction POP_CNT.row.eq operates on data table 244 to generate EQ_count vector 252. EQ_prefix_sum vector 254 is calculated as described above, such as a simple loop, dedicated instruction, etc.

[0134] The column-wise greater-than (LT) count operation is a processor instruction that may be generally described by the following pseudo-code (other implementations are also contemplated):

[0135]

[0136] The processor instruction POP_CNT.column.lt operates on the data table 244 to generate the LT_count vector 260 .

[0137] The column-wise equal (EQ) count operation is a processor instruction that may be generally described by the following pseudo-code (other implementations are also contemplated):

[0138]

[0139] Processor instruction POP_CNT.column.eq operates on data table 244 to generate EQ_count vector 262. EQ_prefix_sum vector 264 is calculated as described above, such as a simple loop, dedicated instruction, etc.

[0140] Fig. 7A and Figure 7B A merge operation 300 of two vectors of sorted indices is shown according to an embodiment of the present disclosure.

[0141] In this embodiment, merge operation 300 uses processor instructions to perform vector comparison and count operations on index vectors 212 and 222 to generate intermediate vectors GT_count vector 250, EQ_count vector 252, GT_count vector 261, and EQ_count vector 262. In this embodiment, although GT_count vector 261 replaces LT_count vector 260 due to the order of the input data, the result is the same.

[0142] In one embodiment, the "greater than" vector comparison and count operation is a processor instruction that may be generally described by the following pseudo code (other implementations are also contemplated):

[0143]

[0144] In one embodiment, the "equal to" vector comparison and count operation is a processor instruction that may be generally described by the following pseudo code (other implementations are also contemplated):

[0145]

[0146] To generate GT_count vector 250 using processor instruction CMP_CNT.gt, index vector 212 is provided as input 0 and index vector 222 is provided as input 1. Similarly, to generate EQ_count vector 252 using processor instruction CMP_CNT.eq, index vector 212 is provided as input 0 and index vector 222 is provided as input 1. EQ_prefix_sum vector 254 is calculated as described above, e.g., a simple loop, a dedicated instruction, etc.

[0147] To generate GT_count vector 261 using processor instruction CMP_CNT.gt, index vector 222 is provided as input 0 and index vector 212 is provided as input 1. Similarly, to generate EQ_count vector 262 using processor instruction CMP_CNT.eq, index vector 222 is provided as input 0 and index vector 212 is provided as input 1. EQ_prefix_sum vector 264 is calculated as described above, e.g., a simple loop, a dedicated instruction, etc.

[0148] Merge operation 300 generates scatter index vector 256 for vector 210 and scatter index vector 266 for vector 220 based on the corresponding intermediate vectors and baseline index vector 270. Merge operation 200 then performs a scatter operation on index vectors 212 and 222 (or data vectors 214 and 224), respectively, using scatter index vectors 256 and 266 to generate sorted merged vector 290 of indices (or data, as discussed above). The intermediate vectors, baseline index vector 270, scatter index vectors 256 and 266, and sorted merged vector 290 may be stored in vector registers, memory, or the like.

[0149] Figure 7C and Fig.7D A merge operation 302 of two vectors of sorted indices is shown according to an embodiment of the present disclosure.

[0150] In this embodiment, merge operation 302 uses processor instructions to perform vector comparison and count operations on index vectors 212 and 222 to generate count vectors 258 and 268, from which intermediate vectors GT_count vector 250, EQ_count vector 252, GT_count vector 261, and EQ_count vector 262 are generated. Additional processor instructions are used to unpack count vectors 258 and 268. In this embodiment, although GT_count vector 261 replaces LT_count vector 260 due to the order of the input data, the result is the same.

[0151] The count vectors 258 and 268 store two values ​​in each element, the first value representing a “greater than” or “>” count of the comparison Z_0_idx[i]>Z_1_idx[j] (or Z_1_idx[i]>Z_0_idx[j]), and the second value representing an “equal to” or “=” count of the comparison Z_0_idx[i]=Z_1_idx[j] or (Z_1_idx[i]=Z_0_idx[j]).

[0152] In one embodiment, the "greater than" and "equal to" vector comparison and counting operations are combined into a single processor instruction, which can be generally described by the following pseudo code (other implementations are also contemplated):

[0153]

[0154] In one embodiment, the "greater than" elements of count vectors 258 and 268 are unpacked using a single processor instruction that can be generally described by the following pseudo code (other implementations are also contemplated):

[0155]

[0156] In one embodiment, the "equal" elements of count vectors 258 and 268 are unpacked using a single processor instruction that can be generally described by the following pseudo code (other implementations are also contemplated):

[0157]

[0158] To generate the count vector 258 using the processor instruction CMP_PCK.gt.eq, the index vector 212 is provided as input 0 and the index vector 222 is provided as input 1. To generate the GT_count vector 252 using the processor instruction PCK_CNT.gt, the count vector 258 is provided as input. To generate the EQ_count vector 252 using the processor instruction PCK_CNT.eq, the count vector 258 is provided as input and the EQ_prefix_sum vector 254 is calculated as described above, e.g., a simple loop, a dedicated instruction, etc.

[0159] To generate the count vector 268 using the processor instruction CMP_PCK.gt.eq, the index vector 222 is provided as input 0 and the index vector 212 is provided as input 1. To generate the GT_count vector 261 using the processor instruction PCK_CNT.gt, the count vector 268 is provided as input. To generate the EQ_count vector 262 using the processor instruction PCK_CNT.eq, the count vector 268 is provided as input and the EQ_prefix_sum vector 264 is calculated as described above, e.g., a simple loop, a dedicated instruction, etc.

[0160] Merge operation 302 generates scatter index vector 256 for vector 210 and scatter index vector 266 for vector 220 based on the corresponding intermediate vectors and baseline index vector 270. Merge operation 200 then performs scatter operations on index vectors 212 and 222 (or data vectors 214 and 224), respectively, using scatter index vectors 256 and 266 to generate sorted merged vector 290 of indices (or data, as discussed above). The intermediate vectors, baseline index vector 270, scatter index vectors 256 and 266, and sorted merged vector 290 may be stored in vector registers, memory, or the like.

[0161] In another embodiment, the merge operation uses a processor instruction to perform vector comparison and count operations on index vectors 212 and 222 to generate count vectors 258 and 268, from which intermediate vectors GT_count vector 250, EQ_count vector 252, GT_count vector 261, and EQ_count vector 262 are generated. In this embodiment, the "greater than", "less than", and "equal to" vector comparison and count operations are combined into a single processor instruction.

[0162] The count vectors 258 and 268 store three values in each element. The first value represents the "greater than" or ">" count for comparing Z_0_idx[i]>Z_1_idx[j] (or Z_1_idx[i]>Z_0_idx[j]), the second value represents the "equal to" or "=" count for comparing Z_0_idx[i]=Z_1_idx[j] or (Z_1_idx[i]=Z_0_idx[j]), and the third value represents the "less than" or "<" count for comparing Z_0_idx[i]<Z_1_idx[j] (or Z_1_idx[i]<Z_0_idx[j]).

[0163] Additional processor instructions are used to unpack the count vectors 258 and 268 to recover the "greater than", "equal to", and "less than" elements of the count vector 258. For example, these elements can be unpacked using a single processor instruction, individual processor instructions, etc., as described above. In this embodiment, although the GT_count vector 261 replaces the LT_count vector 260 due to the order of the input data, the result is the same.

[0164] Figure 8 A scatter operation 400 of two vectors of sorted indices and data according to an embodiment of the present disclosure is shown.

[0165] Generally, the scatter operation 400 performs scatter, compress, add, and scatter operations to generate a sorted and merged vector 292. The non-intersecting and intersecting elements of the scatter index vectors 256, 266 and the data vectors 214, 224 are identified, and the non-intersecting elements of the data vectors 214, 224 are scattered into the sorted and merged vector 292 using the non-intersecting elements of the scatter index vectors 256, 266. The sorted and merged vector 292 now includes partially merged data.

[0166] The intersecting elements of the scatter index vectors 256, 266 are respectively compressed into compressed scatter index vectors 257, 267. The intersecting data elements of the data vectors 214, 224 are respectively compressed into compressed data vectors 216, 226, added (or accumulated) into a partially merged vector 293, and then the partially merged vector is scattered into the sorted and merged vector 292 using the compressed scatter index vector 257.

[0167] Fig. 9 A block diagram of a system 500 according to an embodiment of the present disclosure is shown.

[0168] The computer 502 includes a bus 510 coupled to one or more processors 520, a memory 530, an I / O interface 540, a display interface 550, one or more communication interfaces 560, and one or more special purpose processors 570. In general, the I / O interface 540 is coupled to an I / O device 542 using a wired or wireless connection, the display interface 550 is coupled to a display 552, and the communication interface 560 is connected to a network 562 using a wired or wireless connection.

[0169] Bus 510 is a communication system that transmits data between processor 520, memory 530, I / O interface 540, display interface 550, communication interface 560, dedicated processor 570, and other components (not shown). Power connector 512 is coupled to bus 510 and a power source (not shown).

[0170] The processor 520 includes one or more general or special purpose microprocessors that execute instructions to perform control, computation, input / output, etc. functions of the computer 502. The processor 520 may include a single integrated circuit (such as a microprocessing device), multiple cores, multiple integrated circuit devices and / or circuit boards working in coordination, etc., to implement the functions of the processor 520. In addition, the processor 520 may execute computer programs or modules stored in the memory 530, such as the operating system 532, the software module 534, etc. For example, the software module 534 may include an ML application, an ANN application, a CNN application, etc. In general, the processor 520 includes one or more instruction decoders; in many embodiments, the processor 520 includes an instruction decoder configured to control the processing circuit system to execute a scatter-accumulate instruction.

[0171] In general, the storage device or memory 530 stores instructions for execution by the processor 520 and data. The memory 530 may include a variety of non-transitory computer-readable media that can be accessed by the processor 520. In various embodiments, the memory 530 may include volatile and non-volatile media, non-removable media, and / or removable media. For example, the memory 530 may include any combination of random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), read-only memory (ROM), flash memory, cache memory, and / or any other type of non-transitory computer-readable media.

[0172] Memory 530 contains various components for retrieving, presenting, modifying, and storing data. For example, memory 530 stores software modules that provide functionality when executed by processor 520. Software modules include an operating system 532 that provides operating system functionality for computer 502. Software module 534 provides various functions, such as image classification using convolutional neural networks, etc. Data 536 may include data associated with operating system 532, software module 534, etc.

[0173] The I / O interface 540 is configured to send and / or receive data from the I / O device 542. The I / O interface 540 implements the connection between the processor 520 and the I / O device 542 by encoding data to be sent from the processor 520 to the I / O device 542 and decoding data received from the I / O device 542 for the processor 520. In general, data can be sent via a wired and / or wireless connection. For example, the I / O interface 540 may include one or more wired communication interfaces (such as USB, Ethernet, etc.) and / or one or more wireless communication interfaces (such as WiFi, Bluetooth, cellular, etc.) coupled to one or more antennas.

[0174] In general, I / O devices 542 provide input to and / or output from computer 502. As discussed above, I / O devices 542 are operatively connected to computer 502 using wired and / or wireless connections. I / O devices 542 may include a local processor coupled to a communication interface that is configured to communicate with computer 502 using wired and / or wireless connections. For example, I / O devices 542 may include a keyboard, a mouse, a touch pad, a joystick, etc.

[0175] Display interface 550 is configured to send image data from computer 502 to a monitor or display 552 .

[0176] The communication interface 560 is configured to send data to and from a network 562 using one or more wired and / or wireless connections. The network 562 may include one or more local area networks, wide area networks, the Internet, etc., which may execute various network protocols (such as, for example, wired and / or wireless Ethernet, Bluetooth, etc.). The network 562 may also include various combinations of wired and / or wireless physical layers, such as, for example, copper or coaxial cable networks, fiber optic networks, Bluetooth wireless networks, WiFi wireless networks, CDMA, FDMA and TDMA cellular wireless networks, etc.

[0177] Special purpose processor 570 is configured to perform scatter-add operations and support the various applications implemented by software modules 534 .

[0178] The embodiments described herein are combinable.

[0179] In one embodiment, the processor includes an instruction decoder configured to decode instructions, and a processing circuit configured to perform data processing in response to the instructions decoded by the instruction decoder. In response to one or more read instructions, the instruction decoder is configured to control the processing circuit to read a first vector and a second vector from a storage device, each vector including at least an index value. In response to the instruction sequence, the instruction decoder is configured to control the processing circuit to generate scatter index values ​​for the first vector and the second vector based on the index values ​​of the first vector and the second vector. And, in response to one or more scatter instructions, the instruction decoder is configured to perform a scatter operation using the scatter index values ​​of the first vector and the second vector to generate a sorted merged vector.

[0180] In another embodiment of the processor, the sorted merged vector comprises merged index values.

[0181] In another embodiment of the processor, each vector includes a data value; each index value is associated with a data value; each scatter index value is associated with a data value; the scatter operation is a scatter addition operation, the scatter addition operation uses the scatter index values ​​and data values ​​of the first vector and the second vector to generate a sorted merged vector; and the sorted merged vector includes the merged data value.

[0182] In another embodiment of the processor, generating the scattering index value includes generating a baseline index value; for a first vector, in response to one or more compare count instructions, generating greater than count values ​​for the first vector, each greater than count value is associated with the index value of the first vector, and generating equal to count values ​​for the first vector, each equal to count value is associated with the index value of the first vector; and, for a second vector, in response to one or more compare count instructions, generating greater than count values ​​for the second vector, each greater than count value is associated with the index value of the second vector, and generating equal to count values ​​for the second vector, each equal to count value is associated with the index value of the second vector.

[0183] In another embodiment of the processor, the generating of the greater-than-count value for the first vector includes, for each index value of the first vector, determining the number of index values ​​of the first vector that are less than the index value of the second vector, and generating a greater-than-count value equal to the number; the generating of the equal-to-count value for the first vector includes, for each index value of the first vector, determining the number of index values ​​of the first vector that are equal to the index value of the second vector, and generating an equal-to-count value equal to the number; the generating of the greater-than-count value for the second vector includes, for each index value of the second vector, determining the number of index values ​​of the first vector that are less than the index value of the second vector, and generating a greater-than-count value equal to the number; and the generating of the equal-to-count value for the second vector includes, for each index value of the second vector, determining the number of index values ​​of the first vector that are equal to the index value of the second vector, and generating an equal-to-count value equal to the number.

[0184] In another embodiment of the processor, generating scatter index values ​​includes, for a first vector, generating equal prefix sum values ​​for the first vector based on an equal count value for the first vector, each equal prefix sum value being associated with an index value of the first vector, subtracting the equal prefix sum values ​​from greater than count values ​​to generate difference values, and adding a baseline index value to the difference values ​​to generate a scatter index value for the first vector; and, for a second vector, generating equal prefix sum values ​​for the second vector based on an equal count value for the second vector, each equal prefix sum value being associated with an index value of the second vector, subtracting the equal prefix sum values ​​from greater than count values ​​to generate difference values, each scatter index value being associated with an index value of the second vector, and adding the baseline index value to the difference values ​​to generate a scatter index value for the second vector, each scatter index value being associated with an index value of the second vector.

[0185] In another embodiment of the processor, generating an equal prefix sum value for a first vector includes, for a first index value of the first vector, generating an equal prefix sum value equal to 0; for each index value of the first vector after the first index value of the first vector, determining a partial sum of equal count values ​​from previous index values; and generating an equal prefix sum value equal to the partial sum; generating an equal prefix sum value for a second vector includes, for a first index value of the second vector, generating an equal prefix sum value equal to 0; for each index value of the second vector after the first index value of the second vector, determining a partial sum of equal count values ​​from previous index values; and generating an equal prefix sum value equal to the partial sum.

[0186] In another embodiment, a processor-based method includes reading a first vector and a second vector from a storage device, each vector including at least an index value, generating scatter index values ​​for the first vector and the second vector based on the index values ​​of the first vector and the second vector; and performing a scatter operation using the scatter index values ​​of the first vector and the second vector to generate a sorted merged vector.

[0187] In another embodiment of the processor-based method, the sorted merged vector includes merged index values.

[0188] In another embodiment of the processor-based method, each vector includes a data value; each index value is associated with a data value; each scatter index value is associated with a data value; the scatter operation is a scatter addition operation, the scatter addition operation uses the scatter index values ​​and data values ​​of the first vector and the second vector to generate a sorted merged vector; and the sorted merged vector includes the merged data value.

[0189] In another embodiment of the processor-based method, generating a scatter index value includes generating a baseline index value; and, for a first vector, generating greater-than-count values ​​for the first vector, each greater-than-count value being associated with an index value of the first vector; generating equal prefix sum values ​​for the first vector, each equal prefix sum value being associated with an index value of the first vector; subtracting the equal prefix sum values ​​from the greater-than-count values ​​to generate a difference value; and adding the baseline index value to the difference value to generate a scatter index value for the first vector, wherein each scatter index value is associated with a data value of the first vector.

[0190] In another embodiment of the processor-based method, generating a greater-than-count value for the first vector includes, for each index value of the first vector, determining a number of index values ​​of the first vector that are less than an index value of the second vector; and generating a greater-than-count value equal to the number.

[0191] In another embodiment of the processor-based method, generating equal prefix sum values ​​for a first vector includes, for each index value of the first vector, determining the number of index values ​​of the second vector that are equal to the index value of the first vector; generating an equal count value equal to the number; for a first index value of the first vector: generating an equal prefix sum value equal to 0; for each index value of the first vector after the first index value of the first vector, determining a partial sum of the equal count values ​​from previous index values; and generating an equal prefix sum value equal to the partial sum.

[0192] In another embodiment of the processor-based method, generating scatter index values ​​includes, for a second vector, generating greater-than-count values ​​for the second vector, each greater-than-count value being associated with an index value of the second vector; generating equal prefix sum values ​​for the second vector, each equal prefix sum value being associated with an index value of the second vector; subtracting the equal prefix sum values ​​from the greater-than-count values ​​to generate difference values; and adding the baseline index value to the difference values ​​to generate scatter index values ​​for the second vector, wherein each scatter index value is associated with a data value of the second vector.

[0193] In another embodiment of the processor-based method, generating a less-than-count value for the second vector includes, for each index value of the second vector, determining a number of index values ​​of the second vector that are less than an index value of the first vector; and generating a less-than-count value equal to the number.

[0194] In another embodiment of the processor-based method, generating an equal prefix sum value for a second vector includes, for each index value of the second vector, determining the number of index values ​​of the first vector that are equal to the index value of the second vector; generating an equal count value equal to the number; for the first index value of the second vector, generating an equal prefix sum value equal to 0; for each index value of the second vector after the first index value of the second vector, determining a partial sum of the equal count values ​​from previous index values; and generating an equal prefix sum value equal to the partial sum.

[0195] In another embodiment, the processor is configured to read a first vector and a second vector from a storage device, each vector including at least an index value; generate scatter index values ​​for the first vector and the second vector based on the index values ​​of the first vector and the second vector; and perform a scatter operation using the scatter index values ​​of the first vector and the second vector to generate a sorted merged vector.

[0196] In another embodiment of the processor, the sorted merged vector comprises merged index values.

[0197] In another embodiment of the processor, each vector includes a data value; each index value is associated with a data value; each scatter index value is associated with a data value; the scatter operation is a scatter addition operation, the scatter addition operation uses the scatter index values ​​and data values ​​of the first vector and the second vector to generate a sorted merged vector; and the sorted merged vector includes the merged data value.

[0198] In another embodiment of the processor, generating a scatter index value includes generating a baseline index value; for a first vector, generating greater than count values ​​for the first vector, each greater than count value is associated with the index value of the first vector, and generating equal to count values ​​for the first vector, each equal to count value is associated with the index value of the first vector; for a second vector, generating greater than count values ​​for the second vector, each greater than count value is associated with the index value of the second vector, and generating equal to count values ​​for the second vector, each equal to count value is associated with the index value of the second vector; and generating scatter index values ​​for the first vector and the second vector based on the baseline index value, the greater than count values ​​for the first vector and the second vector, and the equal to count values ​​for the first vector and the second vector.

[0199] Although the specific implementation of the present disclosure can have many different forms of embodiments, specific embodiments are shown in the drawings and will be described in detail herein, it should be understood that the present disclosure should be regarded as an example of the principles of the present disclosure, and is not intended to limit the present disclosure to the specific embodiments shown and described. In the above description, similar reference numerals may be used to describe the same, similar or corresponding parts in the several views of the drawings.

[0200] In this document, relational terms, such as first and second, top and bottom, etc., may be used only to distinguish one entity or action from another entity or action, without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms "comprises," "comprising," "containing," "having," or any other variation thereof, are intended to cover non-exclusive inclusions, such that a process, method, article, or device that includes a series of elements includes not only those elements, but may include other elements not expressly listed or inherent to such process, method, article, or device. An element preceded by "comprises ... one" does not, without more limitations, exclude the presence of additional identical elements in the process, method, article, or device that includes the element.

[0201] Reference throughout this document to "one embodiment," "certain embodiments," "an embodiment," "implementations," "aspects," or similar terms means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of such phrases in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments without limitation.

[0202] As used herein, the term "or" will be interpreted as inclusive or meaning any one or any combination. Thus, "A, B, or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B, and C." An exception to this definition will only occur if the combination of elements, functions, steps, or actions is inherently mutually exclusive in some way. In addition, grammatical conjunctions are intended to express any and all separate and connected combinations of the connected items, sentences, words, etc., unless otherwise specified or clear from the context. Thus, the term "or" should generally be understood to mean "and / or," etc. References to items in the singular should be understood to include the items in the plural, and vice versa, unless otherwise expressly stated or clear from the text.

[0203] Unless otherwise indicated, the description of the range of values ​​herein is not intended to be limiting, but refers individually to any and all values ​​falling within the range, and each individual value in such a range is incorporated into this specification as if individually stated herein. When accompanied by numerical values, the words "about", "approximately", etc. should be understood to indicate deviations, which, as will be understood by those of ordinary skill in the art, operate satisfactorily for the intended purpose. The range of values ​​and / or numerical values ​​is provided herein only as an example, and does not constitute a limitation on the scope of the embodiments. The use of any and all examples or exemplary language ("for example", "such as", etc.) provided herein is only intended to better illustrate the embodiments, rather than to limit the scope of the embodiments. Any language in this specification should not be understood to represent that any unclaimed element is essential for the practice of the embodiments.

[0204] For simplicity and clarity of description, reference numerals may be repeated in the accompanying drawings to indicate corresponding or similar elements. Many details are set forth to provide an understanding of the embodiments described herein. The embodiments may be practiced without these details. In other cases, well-known methods, procedures, and components are not described in detail to avoid obscuring the embodiments. This specification should not be considered to be limited to the scope of the embodiments described herein.

[0205] In the following description, it should be understood that terms such as "first", "second", "top", "bottom", "up", "down", "above", "below", etc. are for convenience and should not be understood as limiting terms. Moreover, the terms "device", "equipment", "system", etc. are used interchangeably herein.

[0206] Many features and advantages of the present disclosure are apparent from the detailed description, and therefore, the appended claims are intended to cover all such features and advantages of the present disclosure that fall within the scope of the present disclosure. In addition, since many modifications and variations will readily occur to those skilled in the art, it is not desired to limit the present disclosure to the exact construction and operation shown and described, and therefore, all suitable modifications and equivalents that fall within the scope of the present disclosure may be resorted to.

Claims

1. A processor, comprising: an instruction decoder configured to decode an instruction; and processing circuitry configured to perform data processing in response to instructions decoded by the instruction decoder, In response to one or more read instructions, the instruction decoder is configured to control the processing circuit to read a first vector and a second vector from a storage device, each vector including at least an index value, wherein, in response to the instruction sequence, the instruction decoder is configured to control the processing circuit to generate scatter index values ​​for the first vector and the second vector based on the index values ​​of the first vector and the second vector, and Wherein, in response to one or more scatter instructions, the instruction decoder is configured to perform a scatter operation using the scatter index values ​​of the first vector and the second vector to generate a sorted merged vector. 2 . The processor of claim 1 , wherein the sorted merged vector comprises merged index values.

3. The processor of claim 1 , wherein: Each vector includes data values; Each index value is associated with a data value; Each scatter index value is associated with a data value; The scatter operation is a scatter-add operation that uses the scatter index values ​​and the data values ​​of the first vector and the second vector to generate the sorted merged vector; and The sorted merged vector includes merged data values.

4. The processor of claim 1 , wherein said generating a scatter index value comprises: Generate baseline index values; For the first vector, in response to one or more compare count instructions: generating greater-than count values ​​for the first vector, each greater-than count value being associated with an index value of the first vector, and generating equal count values ​​for the first vector, each equal count value being associated with an index value of the first vector; and For the second vector, in response to one or more compare count instructions: generating greater-than count values ​​for the second vector, each greater-than count value being associated with an index value of the second vector, and Equal count values ​​are generated for the second vector, each equal count value being associated with an index value of the second vector.

5. The processor of claim 4, wherein: The generating a greater than count value for the first vector comprises: For each index value of the first vector: determining the number of index values ​​of the second vector that are less than the index value of the first vector, and generating a greater-than-count value equal to the number; The generating a count value equal to the first vector comprises: For each index value of the first vector: determining the number of index values ​​of the first vector that is equal to the index value of the second vector, and generating a count value equal to said quantity; The generating a greater than count value for the second vector comprises: For each index value of the second vector: determining the number of index values ​​of the first vector that are less than the index value of the second vector, and generating a greater-than-count value equal to the number; and The generating a count value equal to the count value for the second vector comprises: For each index value of the second vector: determining the number of index values ​​of the second vector that is equal to the index values ​​of the first vector, and A count value equal to the number is generated.

6. The processor of claim 5, wherein said generating a scatter index value comprises: For the first vector: generating equal prefix sum values ​​for the first vector based on the equal count value for the first vector, each equal prefix sum value being associated with an index value of the first vector, subtracting the equality prefix sum value from the greater-than count value to generate a difference value, and adding the baseline index value and the difference value to generate the scatter index value for the first vector; and for the second vector: generating equal prefix sum values ​​for the second vector based on the equal count value for the second vector, each equal prefix sum value being associated with an index value of the second vector, subtracting the equal prefix sum value from the greater than count value to generate a difference value, each scatter index value being associated with an index value of the second vector, and The baseline index value and the difference value are added to generate the scatter index values ​​for the second vector, each scatter index value being associated with an index value of the second vector.

7. The processor of claim 6, wherein: The generating an equal prefix sum value for the first vector comprises: The first index value for the first vector is: Generates equal prefix sum values ​​equal to 0; For each index value of the first vector after the first index value of the first vector: determining a partial sum of said equal count values ​​from previous index values; and generating an equal prefix sum value equal to the partial sum; The generating an equal prefix sum value for the second vector comprises: The first index value for the second vector is: Generates equal prefix sum values ​​equal to 0; For each index value of the second vector after the first index value of the second vector: determining a partial sum of said equal count values ​​from previous index values; and Generates an equal prefix sum value that is equal to the partial sum.

8. A processor-based method comprising: Reading a first vector and a second vector from a storage device, each vector including at least an index value; generating scatter index values ​​for the first vector and the second vector based on the index values ​​of the first vector and the second vector; as well as A scatter operation is performed using the scatter index values ​​of the first vector and the second vector to generate a sorted merged vector.

9. The processor-based method of claim 8, wherein the sorted merged vector comprises merged index values.

10. The processor-based method of claim 8, wherein: Each vector includes data values; Each index value is associated with a data value; Each scatter index value is associated with a data value; The scatter operation is a scatter-add operation that uses the scatter index values ​​and data values ​​of the first vector and the second vector to generate the sorted merged vector; and The sorted merged vector includes merged data values.

11. The processor-based method of claim 8, wherein said generating a scatter index value comprises: Generate baseline index values; as well as For the first vector: generating greater-than count values ​​for the first vector, each greater-than count value being associated with an index value of the first vector, generating equal prefix sum values ​​for the first vector, each equal prefix sum value being associated with an index value of the first vector, subtracting the equality prefix sum value from the greater-than count value to generate a difference value, and adding the baseline index value and the difference value to generate the scatter index value for the first vector, Each scatter index value is associated with a data value of the first vector.

12. The processor-based method of claim 11 , wherein said generating a greater-than-count value for said first vector comprises: For each index value of the first vector: determining a number of index values ​​of the second vector that are less than the index values ​​of the first vector; as well as A greater-than-count value equal to the number is generated.

13. The processor-based method of claim 12, wherein said generating an equal prefix sum value for said first vector comprises: For each index value of the first vector: determining a number of index values ​​of the second vector that is equal to the index values ​​of the first vector; generating an equal count value equal to said quantity; The first index value for the first vector is: Generates equal prefix sum values ​​equal to 0; For each index value of the first vector after the first index value of the first vector: determining a partial sum of said equal count values ​​from previous index values; and Generates an equal prefix sum value that is equal to the partial sum.

14. The processor-based method of claim 13, wherein said generating a scatter index value comprises: For the second vector: generating greater-than count values ​​for the second vector, each greater-than count value being associated with an index value of the second vector; generating equal prefix sum values ​​for the second vector, each equal prefix sum value being associated with an index value of the second vector; subtracting the equal prefix sum value from the greater-than count value to generate a difference value; as well as adding the baseline index value and the difference value to generate the scatter index value for the second vector, Each scatter index value is associated with a data value of the second vector.

15. The processor-based method of claim 14, wherein said generating a less-than count value for said second vector comprises: For each index value of the second vector: determining a number of index values ​​of the first vector that are less than the index value of the second vector; as well as A less-than count value equal to the number is generated.

16. The processor-based method of claim 15, wherein said generating an equal prefix sum value for said second vector comprises: For each index value of the second vector: determining a number of index values ​​of the first vector that is equal to the index value of the second vector; generating an equal count value equal to said quantity; The first index value for the second vector is: Generates equal prefix sum values ​​equal to 0; For each index value of the second vector after the first index value of the second vector: determining a partial sum of said equal count values ​​from previous index values; and Generates an equal prefix sum value that is equal to the partial sum.

17. A processor configured to: Reading a first vector and a second vector from a storage device, each vector including at least an index value; generating scatter index values ​​for the first vector and the second vector based on the index values ​​of the first vector and the second vector; and A scatter operation is performed using the scatter index values ​​of the first vector and the second vector to generate a sorted merged vector.

18. The processor of claim 17, wherein the sorted merged vector comprises merged index values.

19. The processor of claim 17, wherein: Each vector includes data values; Each index value is associated with a data value; Each scatter index value is associated with a data value; the scatter operation being a scatter-add operation that uses the scatter index values ​​and the data values ​​of the first vector and the second vector to generate the sorted merged vector; as well as The sorted merged vector includes merged data values.

20. The processor of claim 17, wherein said generating a scatter index value comprises: Generate baseline index values; For the first vector: generating greater-than count values ​​for the first vector, each greater-than count value being associated with an index value of the first vector, and generating equal count values ​​for the first vector, each equal count value being associated with an index value of the first vector; For the second vector: generating greater-than count values ​​for the second vector, each greater-than count value being associated with an index value of the second vector, and generating equal count values ​​for the second vector, each equal count value being associated with an index value of the second vector; as well as The scatter index values ​​for the first vector and the second vector are generated based on the baseline index value, the greater than count values ​​for the first vector and the second vector, and the equal to count values ​​for the first vector and the second vector.

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