Method for patterning substrate to adjust voltage properties

Abstract

A method of adjusting a threshold voltage in a field effect transistor (FET) device includes performing a deposition process to deposit a diffusion barrier layer over a gate dielectric layer in a first region, a second region, and a third region of a semiconductor structure, performing a first patterning process to remove a portion of the deposited diffusion barrier layer in the first region, and performing a second patterning process to remove a portion of the deposited diffusion barrier layer in the second region. Performing a second patterning process to partially remove a portion of the deposited diffusion barrier layer in the second region, and performing a dipole layer deposition process to deposit a dipole layer over the gate dielectric layer in the first region and over the diffusion barrier layer in the second region and the third region, and performing an annealing process to drive the dipole dopant from the dipole layer into the gate dielectric layer.

Description

background Technical Field

[0002] Embodiments of the present disclosure relate to methods of processing substrates, and more particularly, to adjusting a threshold voltage of a portion of a field-effect-transistor (FET) device by forming an electrostatic dipole layer and adjusting a thickness of a diffusion barrier layer between the dipole layer and a gate dielectric layer. Background Art

[0003] Semiconductor devices such as integrated circuits (ICs) generally have electronic circuit elements, such as transistors, diodes, and resistors, fabricated integrally on a single body of semiconductor material. The various circuit elements are connected by conductive connectors to form a complete circuit, which may contain millions of individual circuit elements. Advances in semiconductor materials and processing techniques have resulted in a reduction in the overall size of the IC while increasing the number of circuit elements. Additional miniaturization is highly desirable in order to improve IC performance and reduce costs. Control of the threshold voltage Vt of the transistor is very important for use in various devices including gate modules and can be a challenge as gate lengths decrease.

[0004] Therefore, there is a need for a method of forming structures in a FET device and modulating the threshold voltage in different regions of the FET device. Summary of the invention

[0005] Embodiments of the present disclosure provide a method for adjusting a threshold voltage in a field effect transistor (FET) device. The method includes performing a deposition process to deposit a diffusion barrier layer over a gate dielectric layer in a first region, a second region, and a third region of a semiconductor structure, performing a first patterning process to remove a portion of the deposited diffusion barrier layer in the first region, performing a second patterning process to partially remove a portion of the deposited diffusion barrier layer in the second region, performing a dipole layer deposition process to deposit a dipole layer over the gate dielectric layer in the first region and the diffusion barrier layer in the second region and the third region, and performing an annealing process to drive a dipole dopant from the dipole layer into the gate dielectric layer.

[0006] Embodiments of the present disclosure provide a method for adjusting a threshold voltage in a field effect transistor (FET) device, the method comprising forming a diffusion barrier layer on a gate dielectric layer, the diffusion barrier layer having a varying thickness in a first region, a second region, and a third region of a semiconductor structure, and performing a precision material engineering (PME) process on an exposed surface of the semiconductor structure.

[0007] Embodiments of the present disclosure provide a method of forming a p-type field effect transistor (PFET) device and an n-type field effect transistor (NFET) device. The method includes forming a first n-type dipole layer on a first gate dielectric layer formed on a silicon germanium-containing layer, the first n-type dipole layer having a varying thickness in a first region, a second region, and a third region of the PFET device, forming a second n-type dipole layer on a second gate dielectric layer, the second n-type dipole layer having a varying thickness in the first region, the second region, and the third region of the NFET device, and performing an annealing process to drive a dipole dopant from the first n-type dipole layer into the first gate dielectric layer, and from the second n-type dipole layer into the second gate dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Thus, the manner in which the above-described features of the present disclosure may be understood in detail, a more particular description of the present disclosure, briefly summarized above, may be obtained by reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only exemplary embodiments of the present disclosure and are therefore not to be considered limiting of the scope of the present disclosure, as the disclosure may admit to other equally effective embodiments.

[0009] Figure 1A , Figure 1B and Figure 1C Depicted is a perspective view of a substrate and a cross-sectional view of a transistor disposed on the substrate according to some embodiments.

[0010] Figure 2 Illustrated is a processing system that may be used to perform one or more of the processes described herein.

[0011] Figure 3 A process flow diagram depicts a method for processing a substrate according to some embodiments.

[0012] Figure 4 Depicted is a substrate having multiple regions according to some embodiments.

[0013] Figure 5 A process flow diagram depicts a method for processing a substrate according to some embodiments.

[0014] Figure 6 A p-type field effect transistor (PFET) device is depicted according to some embodiments.

[0015] Figure 7 An n-type field effect transistor (NFET) device is depicted according to some embodiments.

[0016] Figure 8 A PFET device according to some embodiments is depicted.

[0017] Fig. 9 A PFET device according to some embodiments is depicted.

[0018] Fig.10 An NFET device according to some embodiments is depicted.

[0019] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation. DETAILED DESCRIPTION

[0020] Embodiments of the present disclosure provided herein include processes for forming structures in field effect transistor (FET) devices and tuning the threshold voltage of these structures for various uses. Threshold voltage tuning is achieved by depositing a layer containing a dipole dopant over a gate dielectric layer and driving the dipole dopant into the underlying gate dielectric layer by annealing. The process also includes providing a protective layer, a hard mask, and a compatible etching chemistry to protect areas of the FET device where the threshold voltage is not being modified. The process used herein is suitable for structures having thin individual layers, such as about or smaller, such as about to about layer.

[0021] Figure 1A , Figure 1B and Figure 1C Depicted are a perspective view of a substrate S according to some embodiments and a cross-sectional view of a transistor disposed on the substrate S. The substrate S includes a die D1. The die D1 includes a first region R1 and a second region R2. Figure 1B A first cross-sectional view SV1 of the first region R1 is shown in FIG. Figure 1CA second cross-sectional view SV2 of the second region R2 is shown. In some embodiments, the first region R1 is a p-type metal-oxide-semiconductor field-effect transistor (PMOS) device having a gate region GR1, and the second region R2 is an n-type metal-oxide-semiconductor field-effect transistor (NMOS) device having a gate region GR2. The first region R1 may include a transistor including a p-type well region 002A having an active region defined by an isolation region 004. The second region R2 is a transistor including an n-type well region 002B having an active region defined by the isolation region 004. Each of the first region R1 and the second region R2 may also include a source / drain region disposed in the active region. The source / drain region may include a doped n-type region (e.g., an n-type region), including a lateral portion 006 and a first inter-layer dielectric (ILD) layer 018. As shown, the lateral portion 006 of the source / drain region may be laterally adjacent to the semiconductor channel 036 in the well regions 002A, 002B. The first ILD layer 018 may be any suitable dielectric material, such as silicon oxide (SiO2), borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), or the like. The first ILD layer 018 may be deposited by chemical vapor deposition (CVD), furnace chemical vapor deposition (FCVD), or another suitable deposition process.

[0022] The first region R1 includes a gate structure 030, and the gate structure 030 may include a gate region GR1. Similarly, the second region R2 includes a gate structure 030, and the gate structure 030 included in the second region R2 may include a gate region GR2. Each of the gate structures 030 may include a gate oxide layer 010, a first gate metal layer 012, and an optional second gate metal layer 020. In some embodiments, the gate structure 030 includes a spacer 022.

[0023] The first region R1 and the second region R2 may include a metal interconnect structure 034. The second ILD layer 028, which may be a material similar to the first ILD layer 018, may be deposited over the first ILD layer 018 in the same or similar manner. The layers used to form the metal interconnect structure 034 may be deposited in recesses formed in the first ILD layer 018 and the second ILD layer 028, such as by using CVD, ALD, or physical vapor deposition (PVD). The metal interconnect structure 034 may include a conformal barrier layer 024, such as titanium nitride (TiN), tantalum nitride (TaN), or the like, and a metal fill 026 on the barrier layer 024, such as tungsten (W), aluminum (Al), copper (Cu), or the like.

[0024] Although Figure 1A , Figure 1B and Figure 1C The configuration of a commonly configured metal-oxide-semiconductor field-effect transistor (MOSFET) device formed within a substrate S is illustrated, but this configuration is not intended to limit the scope of the present disclosure provided herein, as other types of formed device structures may benefit from one or more aspects of the present disclosure provided herein. The more conventional types of device structures illustrated herein are presented merely to simplify the discussion of the processes performed herein. However, it is believed that the processes described herein will provide significant advantages for configurations in which the devices to be formed are more structurally complex (such as multi-gate devices, which may include gate-all-around (GAA) FET devices and / or FinFET type devices), and for configurations in which conventional processing techniques (e.g., implantation) of various gate dielectric materials cannot reach due to the gate regions of these multi-gate devices being buried within many different layers of the device.

[0025] Figure 2 A processing system 202 is shown that can be used to perform one or more processes described herein. The processing system 202 disclosed herein may include a processor available from Applied Materials, Inc. of Santa Clara, California. II host or III host. The processing system 202 includes a first transfer module 204a, a second transfer module 204b, and a pass-through module 206, and the pass-through module 206 connects the first transfer chamber 208a of the first transfer module 204a to the second transfer chamber 208b of the second transfer module 204b. The first transfer module 204a includes a first process chamber 210a, a second process chamber 210b, a third process chamber 210c, an auxiliary process chamber 212, and a load lock chamber 213. The second transfer module 204b includes a fourth process chamber 210d, a fifth process chamber 210e, a sixth process chamber 210f, a seventh process chamber 210g, and an eighth process chamber 210h.

[0026] Each of the first transfer module 204a and the second transfer module 204b includes a substrate handling robot (not shown) in the first transfer chamber 208a and the second transfer chamber 208b. The substrate handling robot of the first transfer module 204a is operable to transfer substrates between the load lock chamber 213, the first transfer chamber 208a, the process chambers 210a-210c, the auxiliary process chamber 212, and the pass-through module 206. The substrate handling robot of the second transfer module 204b is operable to transfer substrates between the pass-through module 206, the second transfer chamber 208b, and the process chambers 210d-210h. The processing system 202 includes a load lock chamber 213 coupled to a factory interface 215. The factory interface 215 provides substrates to the processing system 202 separately via one or more factory interface (FI) robots (not shown) and a front opening unified pod (FOUP) 217.

[0027] The valve 207 is disposed at the interface between the process chambers 210a, 210b, 210c, the auxiliary process chamber 212 and the load lock chamber 213 and the first transfer chamber 208a of the first transfer module 204a. The valve 207 is also disposed at the interface between the process chambers 210d, 210e, 210f, 210g, 210h and the second transfer chamber 208b of the second transfer module 204b. In one embodiment that can be combined with other embodiments described herein, the valve 207 is a slit valve and / or a gate valve. Therefore, the process chambers 210a to 210h can be individually isolated from the first transfer chamber 208a and the second transfer chamber 208b. A vacuum pump 219 such as a cryopump, a turbo pump or the like can be coupled to the first transfer chamber 208a and the second transfer chamber 208b. The vacuum pump 219 is operable to maintain the vacuum level of the first transfer chamber 208a and the second transfer chamber 208b. When one or more substrates are transferred between the first transfer chamber 208a and the second transfer chamber 208b, the vacuum level in each of the first transfer chamber 208a and the second transfer chamber 208b may be increased or decreased.

[0028] In this configuration, the transfer of substrates within the processing system 202 can be performed while the substrates are placed in a high vacuum environment (e.g., 10 -7 -10 -9 The vacuum level in the second transfer chamber 208b is maintained at a higher base pressure than the vacuum level maintained in the first transfer chamber 208a. -3 to the second transfer chamber 208b (eg, 10 -7 ~10 -8 support) and process chambers 210d-210g (eg, 10 -8 ~10 -9 As the evaporator moves in the direction of the first transfer module 204a to the second transfer module 204b within the processing system 202, the base pressure or vacuum level increases (ie, the pressure decreases).

[0029] The process chambers 210a-210h may be any type of process chamber, such as a deposition chamber, for example, a physical vapor deposition (PVD) chamber, a chemical vapor deposition (CVD) chamber, a plasma enhanced chemical vapor deposition (PECVD) chamber, an atomic layer deposition (ALD) chamber, a plasma enhanced atomic layer deposition (PEALD), an etching chamber, a degassing chamber, and / or any other type of process chamber. The types of the process chambers 210a-210h are interchangeable in the processing system 202.

[0030] In one embodiment, process chambers 210d, 210e, 210f, 210g, 210h are ALD chambers configured to deposit a dipole layer, such as a p-type dipole layer. In this configuration, process chambers 210b and 210c may include a rapid thermal processing (RTP) chamber configured to heat the substrate to drive the dipole layer with the high-k dielectric layer. One or more of process chambers 210a and 212 may be a pre-clean chamber, such as an Aktiv ® chamber available from Applied Materials, Inc., Santa Clara, California. TM Pre-clean ("APC") Chamber In another embodiment, one or more of the process chambers 210d, 210e, 210f, 210g, 210h are configured to deposit a diffusion barrier layer by an ALD process.

[0031] The processing system 202 includes a system controller 203 that receives data corresponding to the throughput of each of the process chambers 210a-210h. The system controller 203 is operable to apply predictive modeling to the data to provide instructions corresponding to process commands for processing and transferring one or more substrates in and from the process chambers 210a-210h of the processing system 202. The system controller 203 may also provide outputs corresponding to an optimal combination of PVD chambers, CVD chambers, PECVD chambers, ALD chambers, PEALD chambers, etch chambers, degas chambers, or any other type of process chambers for the process chambers 210a-210h of the processing system 202.

[0032] Figure 3 According to some embodiments, the change in Figure 4 4. In some embodiments, each layer deposited during the activities performed in method 300 is deposited using an atomic layer deposition (ALD) process.

[0033] like Figure 4 As shown in , the semiconductor structure 400 may include a first region 400A, a second region 400B, a third region 400C, and a fourth region 400D. Each of the regions 400A, 400B, 400C, and 400D includes a substrate 402, an interface layer 404 formed on the substrate 402, and a gate dielectric layer 406 formed on the interface layer 404. The substrate 402 may be a silicon-containing substrate (e.g., an n-type Si substrate, a p-type Si substrate). The interface layer 404 may be formed of silicon oxide (SiO2).

[0034] The gate dielectric layer 406 may be formed of a high-k dielectric material. As used herein, a high-k dielectric material is a material having a dielectric constant greater than the dielectric constant of silicon oxide (SiO2) (e.g., about 3.9). In some embodiments, the gate dielectric layer 406 is formed of a metal oxide. In some embodiments, the high-k dielectric material is a hafnium-containing material, a silicon-containing material, a zirconium-containing material, a titanium-containing material, or a combination of the foregoing. In some embodiments, the high-k dielectric material is a hafnium oxide-containing material (e.g., HfO2) or other suitable material. The gate dielectric layer 406 is formed of about or less, such as about To date The gate dielectric layer 406 is connected to the interface layer 404. In one example, the gate dielectric layer 406 is formed on a channel region of a metal gate field effect transistor (FET) device, and the gate dielectric layer 406 includes an interface layer formed of silicon oxide (SiO2) and a dielectric layer of hafnium oxide (HfO2) formed on the interface layer.

[0035] The method 300 begins with activity 302, where a first deposition process is performed to deposit a first diffusion barrier layer 408A over the gate dielectric layer 406 in the first region 400A, the second region 400B, the third region 400C, and the fourth region 400D. The deposited first diffusion barrier layer 408A has a thickness of about to about Such as to about Such as to about The diffusion barrier layer 408A may be formed of a metal nitride material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (W2N, WN, WN2), or a combination thereof.

[0036] In activity 304, a first patterning process is performed to substantially remove a portion of the deposited first diffusion barrier layer 408A in the first region 400A. The first patterning process includes a number of processing steps, such as one or more deposition steps, one or more lithography steps, one or more development steps, and one or more etching steps. After performing the first patterning process, the portion of the deposited first diffusion barrier layer 408A in the first region 400A is substantially removed. The second region 400B, the third region 400C, and the fourth region 400D each include a portion of the deposited first diffusion barrier layer 408A.

[0037] In activity 306, a second deposition process is performed to deposit a second diffusion barrier layer 408B over the exposed surface of the semiconductor structure 400 (the gate dielectric layer 406 in the first region 400A and the first diffusion barrier layer 408A in the second region 400B, the third region 400C, and the fourth region 400D). The deposited second diffusion barrier layer 408B has a thickness of about to about Such as to about Such as to about In one example, the second diffusion barrier layer 408B is formed of the same material as the first diffusion barrier layer 408A. The second deposition process in activity 306 can be the same deposition process as the first deposition process in activity 302.

[0038] In activity 308, a second patterning process is performed to substantially remove portions of the second diffusion barrier layer 408B deposited in the first region 400A and the second region 400B. The second patterning process includes a number of processing steps, such as one or more deposition steps, one or more lithography steps, one or more development steps, and one or more etching steps. After performing the second patterning process, portions of the second diffusion barrier layer 408B deposited in the first region 400A and the second region 400B are substantially removed. The second region 400B includes a portion of the deposited first diffusion barrier layer 408A. The third region 400C and the fourth region 400D each include a portion of the first diffusion barrier layer 408A and a portion of the second diffusion barrier layer 408B.

[0039] The additional region, such as the fourth region 400D, may further include a portion of an additional diffusion barrier layer, such as a third diffusion barrier layer 408C having a thickness of about 100 nm. To date Such as To date Such as To date The third diffusion barrier thickness may be formed by deposition and etching back (e.g., similar to activities 302 and 304) until the semiconductor structure 400 includes different regions of the diffusion barrier layer 408 having different diffusion barrier thicknesses. For example, the combined diffusion barrier layer 408 in the second region 400B is the first diffusion barrier layer 408A and thus has a thickness equal to the first diffusion barrier layer thickness. The combined diffusion barrier layer 408 in the third region 400C is a combination of the first diffusion barrier layer 408A and the second diffusion barrier layer 408B and thus has a thickness equal to the combined thickness of the first diffusion barrier layer thickness and the second diffusion barrier layer thickness. The combined diffusion barrier layer 408 in the fourth region 400D is a combination of the first diffusion barrier layer 408A, the second diffusion barrier layer 408B, and the third diffusion barrier layer 408C and thus has a thickness equal to the combined thickness of the first diffusion barrier layer thickness, the second diffusion barrier layer thickness, and the third diffusion barrier layer thickness. In one example, the third diffusion barrier layer 408C is formed of the same material as the first diffusion barrier layer 408A and / or the second diffusion barrier layer 408B.

[0040] In some alternative embodiments, forming the diffusion barrier layer 408 having varying thicknesses in different regions of the semiconductor structure 400 includes depositing a hard mask over the diffusion barrier layer 408, patterning the hard mask, and etching portions of the diffusion barrier layer 408 through openings in the patterned hard mask. For example, after depositing the hard mask over the diffusion barrier layer 408, an opening in the hard mask is formed in the first region 400A, and then the diffusion barrier layer 408 in the first region 400A is etched. Subsequently, an opening in the hard mask is formed in the second region 400B, and then the diffusion barrier layer 408 in the second region 400B is partially etched to the thickness of the first diffusion barrier layer 408A. Another opening in the hard mask is formed in the third region 400C, and then the diffusion barrier layer 408 in the third region 400C is partially etched to the thickness of the combination of the first diffusion barrier layer 408A and the second diffusion barrier layer 408B. In some embodiments, the hard mask is formed of a refractory metal nitride or carbide. The hard mask may be deposited over a protective layer that is disposed over the diffusion barrier layer 408. The hard mask is deposited to about to about Other processes and methods of depositing a diffusion barrier layer having a varying thickness across various regions of the semiconductor structure 400 are also contemplated.

[0041] In activity 310, a dipole layer deposition process is performed to deposit a dipole layer 410 over the gate dielectric layer 406 in the first region 400A and the combined diffusion barrier layer 408 in the second region 400B, the third region 400C, and the fourth region 400D. The dipole layer 410 includes a dipole dopant. In general, a dipole dopant includes an element that forms an electrostatic dipole and is different from a fixed charge type dopant, which includes an element that forms a positive or negative charge due to the loss or gain of electrons when doped in a dielectric material. Although not intended to be bound by theory, the presence of the dipole dopant in the dielectric film is believed to bring about a surface potential at the interface of the gate dielectric layer 406, which brings about a dielectric polarization in the dielectric film. The dielectric polarization caused by the presence of a desired amount of the dipole dopant in the gate dielectric layer 406 can then be used to adjust the threshold voltage Vt of the FET device. The threshold voltage is the minimum gate-to-source voltage required to create a conductive path between the source terminal and the drain terminal. In some embodiments, it is desirable to dope different regions of the gate dielectric layer (e.g., the metal gate interface surface, the interface surface between the high-k layer and the interface dielectric layer, or the channel interface surface) to further adjust the threshold voltage Vt of the FET. The dipole dopant in the dipole layer 410 can be a metal dopant, such as aluminum (Al) or lanthanum (La). The dipole layer provides a dipole dopant that will diffuse into the gate dielectric layer 406 by subsequent annealing.

[0042] The dipole layer 410 has a to about Such as to about In some embodiments, the dipole layer 410 is formed of a metal nitride, such as titanium nitride that further includes a dipole dopant.

[0043] In some embodiments, the dipole layer 410 has a uniform concentration of the dipole dopant of about 1% to about 20%, such as about 5% to about 15%, such as about 8% to about 12%, throughout the thickness of the dipole layer 410. The concentration of the dipole dopant in the dipole layer 410 is selected based on a predetermined final concentration of the dipole dopant to be diffused into the gate dielectric layer 406. The predetermined concentration of the dipole dopant to be diffused into the gate dielectric layer 406 is determined based on a predetermined threshold voltage Vt of at least one of the regions (e.g., 400A, 400B, 400C, 400D) or a predetermined threshold voltage Vt difference of a FET device formed in one of the regions (e.g., 400A, 400B, 400C, 400D) relative to a FET device formed in another of the regions (e.g., 400A, 400B, 400C, 400D). In some embodiments, the dipole layer 410 has a substantially uniform concentration of the dipole dopant within the dipole layer.

[0044] In some other embodiments, the dipole layer 410 has a gradient concentration of the dipole dopant that varies along the thickness of the dipole layer 410, for example, a higher concentration at a surface of the dipole layer 410 near the gate dielectric layer 406 and a lower concentration at an opposite surface of the dipole layer 410. In some embodiments, the dipole dopant is formed by an atomic layer deposition (ALD) process. In some embodiments, the gradient concentration of the dipole dopant within the dipole layer 410 is formed by delivering an ALD pulse containing a precursor containing the dipole dopant, the precursor having a concentration that increases in each successive layer (i.e., a positive gradient) or decreases in each successive layer (i.e., a negative gradient) during the ALD process. In one example, about 70 atomic % or more, such as about 80 atomic % or more, such as about 90 atomic % or more of the dipole dopant is disposed in a portion of the dipole layer 410 that forms the surface of the dipole layer 410 closer to the gate dielectric layer 406, and less than 50 atomic %, such as less than 20 atomic %, is disposed in the remainder of the dipole layer 410 (i.e., a negative gradient). In some embodiments, forming the gradient concentration of the dipole dopant includes increasing the exposure time (e.g., pulse time) of the dipole dopant relative to the exposure time of other gases during the ALD process.

[0045] Without being bound by theory, it is believed that varying the thickness of the diffusion barrier layer 408 can control the dipole density at various regions of the semiconductor structure 400. In some embodiments, the diffusion barrier layer ( Figure 4 The diffusion barrier layer 408 of the second region 400B is about 0.3 nm to about 0.6 nm, and the threshold voltage Vt is "low" and greater than the threshold voltage Vt of the first region 400A. The diffusion barrier layer 408 of the third region 400C is about 0.6 nm to about 1 nm, and the threshold voltage Vt is "standard" and greater than the threshold voltage Vt of the second region 400B. The diffusion barrier layer 408 of the fourth region 400D is about 1 nm or greater (thickest), and the threshold voltage Vt is "high" and greater than the threshold voltage Vt of the third region 400C.

[0046] In activity 312, an annealing process is performed to drive the dipole dopant from the dipole layer 410 into the gate dielectric layer 406. In some embodiments, the annealing process is performed at a temperature of about 600°C to about 1100°C, such as about 800°C to about 1000°C, or about 700°C to about 950°C. In some embodiments, the annealing process is performed for a duration of about 0.5 seconds to about 15 seconds, such as about 1 second to about 10 seconds. Annealing of the semiconductor structure 400 enables the dipole dopant from the dipole layer 410 to diffuse into the gate dielectric layer 406. Without being bound by theory, in one configuration, the dipole dopant diffused into the gate dielectric layer 406 produces a threshold voltage Vt shift in the gate dielectric layer 406 at an interface with an underlying interfacial layer 404 (e.g., silicon dioxide (SiO2)) formed on the substrate 402. It has been discovered that the type and concentration of the dopant are selected so that the threshold voltage Vt can be modulated positively or negatively compared to the threshold voltage Vt of the undoped dielectric layer, depending on the desired application. In some embodiments, the dipole dopant is a p-type dopant that diffuses into the gate dielectric layer 406 to induce negative polarization and a lower threshold voltage Vt. In some embodiments, other dopants are contemplated to increase the threshold voltage Vt. It is also believed that the dipole dopant diffuses from the dipole layer 410 into the lower portion of the gate dielectric layer 406 (e.g., the interface of the gate dielectric layer and the interfacial layer 404) and interferes with the oxygen density in the lower portion of the gate dielectric layer 406 (e.g., HfO2) relative to the underlying interfacial layer 404 (e.g., silicon dioxide (SiO2)).

[0047] After performing the activities of method 300, additional steps may be performed to form FET devices having different and desired threshold voltage Vt characteristics. In some embodiments, a first FET having a first threshold voltage Vt value is formed. The first FET includes at least a portion of a dielectric layer found in a first region (e.g., gate region GR1) after the semiconductor structure 400 is exposed to an annealing process. In some embodiments, a second FET having a second threshold voltage Vt value is formed. The second FET includes at least a portion of a dielectric layer found in a second region (e.g., gate region GR2) after the semiconductor structure 400 is exposed to an annealing process. The first threshold voltage Vt value is different from the second threshold voltage Vt value. Therefore, by adjusting the amount of dipole dopant driven into the gate dielectric layer 406 during activity 312, the threshold voltage Vt value can be adjusted due to the presence of a varying thickness of the diffusion barrier layer 408. Where the first, second, third and fourth regions form part of a PMOS device, the first region 400A typically has an ultra-low threshold voltage Vt, the second region 400B has a low threshold voltage Vt, the third region 400C has a standard threshold voltage Vt, and the fourth region 400D has a high threshold voltage Vt.

[0048] Figure 5 Describes how, according to some embodiments, changes in Figure 6 The PFET device 600 shown in FIG. Figure 7 0048. The process flow diagram of method 500 for determining the characteristics of a gate dielectric layer used in an NFET device 700 is shown in FIG. Method 500 may be used to change a threshold voltage Vt in a device including a dipole layer between an interface layer and a dielectric layer without forming an additional dipole layer.

[0049] like Figure 6 As shown, the PFET device 600 includes a substrate 602, an interface layer 604 on the substrate 602, a p-type dipole layer 606 on the interface layer 604, and a gate dielectric layer 608 on the p-type dipole layer 606. Figure 7 As shown in FIG. 7 , NFET device 700 includes substrate 702, interface layer 704 on substrate 702, n-type dipole layer 706 on interface layer 704, and gate dielectric layer 708 on n-type dipole layer 706. Interface layer 604 and interface layer 704 may be formed of silicon oxide (SiO2). P-type dipole layer 606 may include p-type dipole dopant and have a gate dielectric layer of about to about The thickness, such as about to about The n-type dipole layer 706 may include an n-type dipole dopant and has a to about The thickness, such as about to about The gate dielectric layer 608 and the gate dielectric layer 708 may be formed of a high-k dielectric material and have a dielectric thickness of about to about Thickness.

[0050] The first region 600A of the PFET device 600 and the first region 700A of the NFET device 700 do not include a diffusion barrier layer. The second region 600B of the PFET device 600 and the second region 700B of the NFET device 700 each include a diffusion barrier layer 610 and a diffusion barrier layer 710. The third region 600C of the PFET device 600 and the third region 700C of the NFET device 700 each include a diffusion barrier layer 610 that is thicker relative to the second region 600B and a diffusion barrier layer 710 that is thicker relative to the second region 700B. The fourth region 600D of the PFET device 600 and the fourth region 700D of the NFET device 700 each include a diffusion barrier layer 610 that is thicker relative to the third region 600C and a diffusion barrier layer 710 that is thicker relative to the third region 700C. The diffusion barriers 610 and 710 having varying thicknesses can be obtained by comparing with the above description of the diffusion barrier layers 610 and 710. Figure 3 and Figure 4The method 300 is formed by a similar process as described.

[0051] The method 500 begins with activity 502, where a precision materials engineering (PME) process is performed on exposed surfaces of the PFET device 600 (gate dielectric layer 608 in the first region 600A and diffusion barrier layer 610 in the second region 600B, the third region 600C, and the fourth region 600D) and exposed surfaces of the NFET device 700 (gate dielectric layer 708 in the first region 700A and diffusion barrier layer 710 in the second region 700B, the third region 700C, and the fourth region 700D). The PME process includes exposing the exposed surfaces of the PFET device 600 and the exposed surfaces of the NFET device 700 to nitrogen-containing species, such as nitrogen radicals. In some embodiments, the PME process is performed using a decoupled plasma nitridation (DPN) process available from Applied Materials, Inc.

[0052] In activity 504 , after the PME process, diffusion barrier layer 610 and diffusion barrier layer 710 are removed.

[0053] Without being bound by theory, for a PFET device having a p-type dipole layer, such as the p-type dipole layer 606, the greater the thickness of the diffusion barrier layer 610, the lower the threshold voltage Vt of the region. Specifically, the threshold voltage Vt of the first region 600A is higher than the threshold voltage Vt of the second region 600B, the threshold voltage Vt of the second region 600B is higher than the threshold voltage Vt of the third region 600C, and the threshold voltage Vt of the third region 600C is higher than the threshold voltage Vt of the fourth region 600D.

[0054] Without being bound by theory, for an NFET device having an n-type dipole layer, such as the n-type dipole layer 706, the greater the thickness of the diffusion barrier layer 710, the higher the threshold voltage Vt of the region. Specifically, the threshold voltage Vt of the first region 600A is lower than the threshold voltage Vt of the second region 600B, the threshold voltage Vt of the second region 600B is lower than the threshold voltage Vt of the third region 600C, and the threshold voltage Vt of the third region 600C is lower than the threshold voltage Vt of the fourth region 600D.

[0055] In some embodiments, the PME process of method 500 may be used to change the characteristics of a gate dielectric layer in a PFET device 800 without a dipole layer.

[0056] like Figure 8As shown in FIG. 8 , a PFET device 800 includes a substrate 802, a silicon-germanium-containing layer 804 on the substrate 802, an interface layer 806 on the silicon-germanium-containing layer 804, a gate dielectric layer 808 on the interface layer 806, and a diffusion barrier layer 810 on the gate dielectric layer 808. A first region 800A of the PFET device 800 does not include a diffusion barrier layer. A second region 800B of the PFET device 800 includes a diffusion barrier layer 810. A third region 800C of the PFET device 800 has a thicker diffusion barrier layer 810 relative to the second region 800B. A fourth region 800D of the PFET device 810 has the thickest diffusion barrier layer 810. The interface layer 806 has a thickness of about 1000 W. to about The silicon germanium containing layer 804 has a thickness of about to about After performing a PME process (e.g., a nitridation process) on the exposed surface of the PFET device 800 (the gate dielectric layer 808 in the first region 800A and the diffusion barrier layer 810 in the second region 800B, the third region 800C, and the fourth region 800D), the threshold voltage Vt value decreases from the first region 800A to the fourth region 800D.

[0057] In some embodiments, forming an n-type dipole layer with a varying thickness as in method 300 may be used to vary the Fig. 9 The PFET device 900 shown in FIG. Fig.10 . The PFET device 900 includes a substrate 902, a silicon germanium containing layer 904, an interface layer 906, a gate dielectric layer 908, and an n-type dipole layer 910. The NFET device 1000 includes a substrate 1002, an interface layer 1004, a gate dielectric layer 1006, and an n-type dipole layer 1008. The n-type dipole layer 910 and the n-type dipole layer 1008 may be formed of lanthanum oxide. For the PFET device 900, after performing an annealing process (e.g., an RTP process) to drive dipole dopants from the n-type dipole layer 910 into the gate dielectric layer 908 and from the n-type dipole layer 1008 into the gate dielectric layer 1006, the thicker the formed n-type dipole layer 910, the higher the threshold voltage Vt achieved by different regions. For the NFET device 1000, the thicker the n-type dipole layer 1008 is, the lower the threshold voltage Vt to be achieved by different regions after a drive-in process is performed. The different thicknesses formed on each of the regions (including PMOS and NMOS) can be formed together during the process of forming each thickness on the n-type dipole layer 910 on the substrate.

[0058] While the foregoing is directed to implementations of the present disclosure, other and further implementations of the disclosure may be devised without departing from the basic scope thereof, and the scope of the disclosure is determined by the claims that follow.

Claims

1. A method for adjusting a threshold voltage in a field effect transistor (FET) device, comprising the steps of: performing a deposition process to deposit a diffusion barrier layer over the gate dielectric layer in the first region, the second region, and the third region of the semiconductor structure; performing a first patterning process to remove a portion of the deposited diffusion layer in the first region; performing a second patterning process to partially remove a portion of the deposited diffusion barrier layer in the second region; performing a dipole layer deposition process to deposit a dipole layer on the gate dielectric layer in the first region and on the diffusion barrier layer in the second region and in the third region; and An annealing process is performed to drive the dipole dopant from the dipole layer into the gate dielectric layer.

2. The method of claim 1, wherein the diffusion barrier layer comprises titanium nitride, tantalum nitride or tungsten nitride and has and The thickness between.

3. The method of claim 1, wherein the gate dielectric layer comprises a high-k dielectric material and has a and The thickness between.

4. The method of claim 1, wherein the dipole layer comprises a dipole dopant and has and The thickness between.

5. The method of claim 4, wherein the dipole layer has a uniform concentration of the dipole dopant between 1% and 20% throughout the thickness of the dipole layer. 6 . The method of claim 4 , wherein the dipole layer has a gradient concentration of the dipole dopant, the gradient concentration decreasing along the thickness of the dipole layer from a surface of the dipole layer closer to the gate dielectric layer to an opposite surface of the dipole layer.

7. The method of claim 1, wherein the deposition process comprises an atomic layer deposition (ALD) process.

8. The method of claim 1, wherein the annealing process is performed at a temperature between 600°C and 1100°C for a duration between 0.5 seconds and 15 seconds.

9. The method of claim 1, wherein The dipole layer is thinnest in the first region and thickest in the third region, and a threshold voltage shift compared to an undoped dielectric layer is lowest in the first region and highest in the third region.

10. A method of adjusting a threshold voltage in a field effect transistor (FET) device, comprising the steps of: forming a diffusion barrier layer on the gate dielectric layer, the diffusion barrier layer having varying thicknesses in the first region, the second region, and the third region of the semiconductor structure; and A precision materials engineering (PME) process is performed on the exposed surface of the semiconductor structure.

11. The method according to claim 10, wherein the gate dielectric layer is formed on the dipole layer, and the coupling layer has and The thickness between.

12. The method according to claim 10, wherein the gate dielectric layer is formed on the silicon germanium containing layer, and the silicon germanium containing layer has and The thickness between.

13. The method of claim 10, wherein the diffusion barrier layer comprises titanium nitride, tantalum nitride or tungsten nitride and has a thickness between and The thickness between.

14. The method of claim 10, wherein the gate dielectric layer comprises a high-k dielectric material and has a and The thickness between.

15. The method of claim 10, wherein the diffusion barrier layer is thinnest in the first region and thickest in the third region.

16. A method of forming a p-type field effect transistor (PFET) device and an n-type field effect transistor (NFET) device, the method comprising the steps of: forming a first n-type dipole layer on a first gate dielectric layer formed on the silicon germanium containing layer, the first n-type dipole layer having a varying thickness in a first region, a second region, and a third region of the PFET device; forming a second n-type dipole layer on the second gate dielectric layer, the second n-type dipole layer having varying thicknesses in the first region, the second region, and the third region of the NFET device; and An annealing process is performed to drive the dipole dopant from the first n-type dipole layer into the first gate dielectric layer and from the second n-type dipole layer into the second gate dielectric layer. middle.

17. The method of claim 16, wherein the first n-type dipole layer and the second n-type dipole layer each comprise lanthanum oxide.

18. The method of claim 16, wherein the first gate dielectric layer and the second gate dielectric layer each comprise a high-k dielectric material and have and The thickness between.

19. The method of claim 16, wherein the silicon germanium containing layer has and The thickness between.

20. The method of claim 16, wherein the annealing process comprises a rapid thermal processing (RTP) process.

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