Laser scanning control and fluorescence signal processing device and method based on FPGA

Abstract

The invention provides a laser scanning control and fluorescence signal processing device and method based on an FPGA, and the method comprises the steps: an upper computer sends scanning parameters to an FPGA control module, the FPGA control module controls a stepping motor to move based on the scanning parameters, and drives an optical module to achieve a two-dimensional scanning function, an AD module collects the scanning information of the optical module, and the scanning information is transmitted to the FPGA control module. And the FPGA control module transmits the acquired scanning information to an upper computer through a UDP (User Datagram Protocol). Laser control, signal acquisition, data processing and transmission are integrated on the same FPGA platform, so that the scanning precision, stability and response speed of the system are remarkably improved, the problems of mechanical control errors, low transmission speed and the like in the prior art are solved, meanwhile, the size and cost of equipment are reduced by adopting integrated design, and the system is suitable for large-scale popularization and application. And the application flexibility and reliability are enhanced.

Description

Technical Field

[0001] The present invention relates to the field of laser scanning technology, and in particular to a laser scanning control and fluorescence signal processing device and method based on FPGA. Background Art

[0002] With the increasing demand for disease diagnosis and cell biology research, laser scanning imagers are widely used in the fields of medicine and scientific research, especially in disease diagnosis, pharmaceutical research and cell interaction research. Traditional laser scanning imagers can no longer meet the requirements of scientific research and clinical practice in terms of scanning accuracy, signal acquisition efficiency and data processing capabilities.

[0003] In the prior art, the system usually uses a PC or dedicated hardware for control and processing. The traditional mechanical scanning system usually uses a mechanical device to scan and position the X-axis and Y-axis, which has problems such as insufficient precision. In addition, the mechanical system is limited by processing accuracy and assembly errors, resulting in poor repeatability and stability of scanning, which makes it difficult to meet the needs of high-precision imaging. This system is easily affected by factors such as mechanical wear and temperature changes, resulting in inaccurate positioning and poor repeatability. There is also a problem of poor real-time performance. The response speed of the mechanical control system is relatively slow, and fast scanning cannot be achieved, which brings challenges to real-time imaging and data processing. Traditional systems usually design the control module and the acquisition module separately, and often require multiple independent modules to realize laser control, signal acquisition and data processing, resulting in a large device size, high cost, poor system integration and poor stability. The prior art has some limitations in scanning accuracy, imaging speed and signal processing, which are mainly manifested in slow scanning speed, limited imaging resolution, low signal acquisition efficiency and poor data transmission stability. Therefore, it is very necessary to design a laser scanning control and fluorescence signal processing device and method based on FPGA. Summary of the invention

[0004] In order to overcome the deficiencies of the prior art, the object of the present invention is to provide a laser scanning control and fluorescence signal processing device and method based on FPGA.

[0005] To achieve the above object, the present invention provides the following solutions:

[0006] The present invention provides a laser scanning control and fluorescence signal processing device based on FPGA, comprising: an FPGA control module, an AD module, a stepper motor, an optical module, and a host computer. The optical module is arranged on the stepper motor through a mechanical structure to drive the optical module to achieve precise positioning. The stepper motor, the AD module and the host computer are connected to the FPGA control module, and the AD module is connected to the optical module to collect scanning information received by the optical module.

[0007] Preferably, the host computer is connected to the FPGA control module via a gigabit network cable and communicates with the FPGA control module via an Ethernet UDP protocol.

[0008] Preferably, pin 1 of the J10 expansion port of the FPGA control module is connected to the ground wire of the stepper motor and the photoelectric switch, pins 3 and 5 are respectively connected to the X-direction and Y-direction stepper motor pulse input signals, pins 7 and 9 are respectively connected to the X-direction and Y-direction stepper motor direction control input signals, pin 11 is connected to the photoelectric switch, and the positive pole of the stepper motor photoelectric switch is connected to the power supply.

[0009] Preferably, the AD module is inserted into the J9 expansion port of the FPGA control module, and the AD module is connected to the optical module via an SMA cable.

[0010] The present invention also provides a laser scanning control and fluorescence signal processing method based on FPGA, comprising:

[0011] The host computer sends scanning parameters to the FPGA control module, and the FPGA control module controls the movement of the stepper motor based on the scanning parameters, driving the optical module to achieve a two-dimensional scanning function;

[0012] The AD module collects the scanning information of the optical module and transmits it to the FPGA control module;

[0013] The FPGA control module transmits the acquired scanning information to the host computer through the UDP protocol.

[0014] Preferably, the host computer sends scanning parameters to the FPGA control module, and the FPGA control module controls the movement of the stepper motor based on the scanning parameters, driving the optical module to realize the two-dimensional scanning function, specifically:

[0015] Define the input signal, including:

[0016] sys_clk, clock signal, used to synchronously control the movement of the motor;

[0017] rst, reset signal, used to initialize the system state;

[0018] scan_start, start instruction, controlled by the host computer, instructs the system when to start scanning;

[0019] scan_init, initialization instruction, controlled by the host computer, indicates when the system starts initialization;

[0020] Init_flag, initialization flag, marks whether the system has completed initialization. When the motor is initialized and returns to the zero point of the coordinate system, the photoelectric switch is triggered and the flag is high.

[0021] x_scan_range, y_scan_range, the scanning range in the X and Y directions, controlled and changed by the host computer;

[0022] x_start_pos, y_start_pos, the scanning start position in the X and Y directions, controlled and changed by the host computer;

[0023] scan_speed, the scanning speed of the stepper motor, is controlled and changed by the host computer;

[0024] Define output signals, including:

[0025] StepDrive_1 and StepDrive_2, pulse signals of X-axis stepper motor and Y-axis stepper motor;

[0026] state_1, state_2, the states of the X-axis stepper motor and the Y-axis stepper motor, respectively, forward rotation is 0, low level, reverse rotation is 1, high level;

[0027] Dir_flag, direction flag, indicates the current scanning direction;

[0028] Define the states of the scan state machine, including:

[0029] Idle: Initialization state, the system is in reset or standby state;

[0030] Start: Starting state, the motor starts to move to the scanning starting point;

[0031] X_Forward: X-axis forward movement state, the motor moves forward along the X-axis;

[0032] Y_Forward: Y-axis forward movement state, the motor moves forward along the Y-axis;

[0033] X_Reverse: X-axis reverse movement state, the motor moves in the opposite direction along the X-axis;

[0034] Stop: Stop state, the motor stops moving;

[0035] The state transition conditions are defined as follows: after power-on, the Idle state is entered, and the Start state is entered after the host computer sends an instruction to set the Start_flag signal high. The stepper motor starts to move to the scanning starting point. In the Start state, check whether the stepper motor has moved to the scanning starting point, and then enter the X_Forward state. In the X_Forward state, the stepper motor will move in the positive direction along the X axis until it reaches the preset X-direction positive scanning boundary x_scan_range, and then enter the Y_Forward state. In the Y_Forward state, the stepper motor will move in the positive direction along the Y axis for a certain distance, and then decide whether to move in the positive direction along the X axis or in the reverse direction along the X axis. If the current X-direction coordinate X_pos is in the X-axis positive scanning boundary x_scan_range, the next step is to move in the reverse direction along the X axis. If it is in the X-axis reverse scanning boundary x_start_pos, the next step is to move in the positive direction along the X axis. Repeat the two-dimensional scanning cycle. When the Y-axis scan reaches the preset Y-direction scanning boundary y_scan_range, it enters the Stop state, stops all movements, and realizes accurate two-dimensional scanning.

[0036] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0037] The present invention provides a laser scanning control and fluorescence signal processing device and method based on FPGA. The device comprises an FPGA control module, an AD module, a stepper motor, an optical module and a host computer. The method comprises the following steps: the host computer sends scanning parameters to the FPGA control module via Ethernet, the FPGA control module controls the movement of the stepper motor based on the scanning parameters to drive the optical module to realize a two-dimensional scanning function, the AD module collects scanning information of the optical module and transmits it to the FPGA control module, and the FPGA control module transmits the acquired scanning information to the host computer via a UDP protocol. The present invention utilizes the high-speed parallel processing capability of FPGA, and through control program design, accurately controls the stepper motor, realizes high-precision positioning and scanning of the laser beam on the X-axis and Y-axis, significantly improves the scanning accuracy and system stability, overcomes the influence brought by mechanical control errors, adopts the application of AD7606 chip and the design of AD acquisition program to ensure the high-precision acquisition of fluorescence signals, combines the use of Ethernet high-speed interface and UDP protocol to ensure real-time high-speed transmission and processing of data, integrates laser control, signal acquisition, data processing and transmission on the same FPGA platform, simplifies system design, reduces the size and cost of equipment, and improves the overall work efficiency and reliability, provides an intuitive operation interface, can flexibly set and modify the scanning speed and scanning range of the stepper motor in the X and Y directions, control the start and end of scanning and acquisition, and adapt to different experimental requirements, and at the same time, the image display system performs image processing and display through the host computer software, and provides efficient and real-time image information display. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0039] Figure 1 A schematic diagram of a program flow of a laser scanning control and fluorescence signal processing device based on FPGA provided in an embodiment of the present invention;

[0040] Figure 2 A schematic flow chart of a laser scanning control and fluorescence signal processing method based on FPGA provided in an embodiment of the present invention;

[0041] Figure 3 Schematic diagram of controlling laser scanning. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0044] Figure 1 A schematic diagram of the structure of a laser scanning control and fluorescence signal processing device based on FPGA provided in an embodiment of the present invention is shown in FIG. Figure 1 As shown, the present invention provides a laser scanning control and fluorescence signal processing device based on FPGA.

[0045] FPGA control module, AD module, stepper motor, optical module, host computer, the optical module is arranged on the stepper motor through a mechanical structure to drive the optical module to achieve precise positioning, the stepper motor, AD module and host computer are connected to the FPGA control module, and the AD module is connected to the optical module to collect scanning information received by the optical module.

[0046] The host computer is connected to the FPGA control module via a gigabit network cable and communicates with the FPGA control module via the Ethernet UDP protocol. An image display system is provided on the host computer. The host computer receives digital signals via the Ethernet port and uses the designed host computer software to process and display image information, thereby achieving efficient image processing and display.

[0047] The FPGA control module ensures that the network card of the host computer (PC) supports Gigabit Ethernet, checks that the connection speed is 1.0Gbps full-duplex, and uses a Category 6 Gigabit Ethernet cable to connect the FPGA and the host computer (PC). The FPGA is responsible for parsing the UDP data packet sent from the host computer via Ethernet, and controls the stepper motor according to the parsed scanning parameters. The stepper motor and the positive pole of the photoelectric switch are connected to the power supply, the 1st pin of the J10 expansion port of the FPGA is connected to the ground wire of the stepper motor and the photoelectric switch, the 3rd and 5th pins are respectively connected to the X and Y direction stepper motor pulse input signals, the 7th and 9th pins are respectively connected to the X and Y direction stepper motor direction control input signals, and the 11th pin is connected to the photoelectric switch. The FPGA is used to accurately control the stepper motor and drive the laser beam to achieve precise positioning and two-dimensional scanning on the X and Y axes of the sample surface, thereby improving the scanning accuracy and stability.

[0048] The AD module uses the AD7606 chip to collect fluorescence signals, which has a maximum sampling rate of 200kHz and 32-bit accuracy. The AD module is inserted into the J9 expansion port of the FPGA control module, and an SMA line is used to connect the input of the AD module to the output of the photodetector. The fluorescence signal is collected, amplified and converted into an electrical signal by the light spot detector, and the AD module performs high-precision analog-to-digital conversion. The signal data is collected by the FPGA control module and transmitted to the host computer via the Ethernet UDP protocol to ensure the speed and stability of data transmission.

[0049] like Figure 2 As shown, the present invention also provides a laser scanning control and fluorescence signal processing method based on FPGA, which is characterized by comprising:

[0050] Step 100: The host computer sends scanning parameters to the FPGA control module;

[0051] Step 200: The FPGA control module controls the movement of the stepper motor based on the scanning parameters, driving the optical module to achieve a two-dimensional scanning function;

[0052] Step 300: The AD module collects the scanning information of the optical module and transmits it to the FPGA control module;

[0053] Step 400: The FPGA control module transmits the acquired scanning information to the host computer via the UDP protocol.

[0054] In step 100 and step 200, the host computer sends scanning parameters to the FPGA control module, and the FPGA control module controls the movement of the stepper motor based on the scanning parameters to drive the optical module to realize the two-dimensional scanning function, specifically:

[0055] The FPGA control module is the control core. It controls the stepper motor to drive the laser beam to perform precise two-dimensional scanning on the X-axis and Y-axis of the sample. At the same time, the FPGA control module can receive the scanning parameters sent by the host computer through Ethernet and modify the scanning parameters. This process is described in detail:

[0056] First, design the stepper motor control module (Stepmotor module) to realize the scanning control of the stepper motor:

[0057] Define the input signal, including:

[0058] sys_clk, clock signal, used to synchronously control the movement of the motor;

[0059] rst, reset signal, used to initialize the system state;

[0060] scan_start, start instruction, controlled by the host computer, instructs the system when to start scanning;

[0061] scan_init, initialization instruction, controlled by the host computer, indicates when the system starts initialization;

[0062] Init_flag, initialization flag, marks whether the system has completed initialization. When the motor is initialized and returns to the zero point of the coordinate system, the photoelectric switch is triggered and the flag is high.

[0063] x_scan_range, y_scan_range, the scanning range in the X and Y directions, controlled and changed by the host computer;

[0064] x_start_pos, y_start_pos, the scanning start position in the X and Y directions, controlled and changed by the host computer;

[0065] scan_speed, the scanning speed of the stepper motor, is controlled and changed by the host computer;

[0066] Define output signals, including:

[0067] StepDrive_1 and StepDrive_2, pulse signals of X-axis stepper motor and Y-axis stepper motor;

[0068] state_1, state_2, the states of the X-axis stepper motor and the Y-axis stepper motor, respectively, forward rotation is 0, low level, reverse rotation is 1, high level;

[0069] Dir_flag, direction flag, indicates the current scanning direction;

[0070] Define the states of the scan state machine, including:

[0071] Idle: Initialization state, the system is in reset or standby state;

[0072] Start: Starting state, the motor starts to move to the scanning starting point;

[0073] X_Forward: X-axis forward movement state, the motor moves forward along the X-axis;

[0074] Y_Forward: Y-axis forward movement state, the motor moves forward along the Y-axis;

[0075] X_Reverse: X-axis reverse movement state, the motor moves in the opposite direction along the X-axis;

[0076] Stop: Stop state, the motor stops moving;

[0077] The state transition conditions are defined as follows: enter the Idle state after power-on, wait for the host computer to send an instruction to set the Start_flag signal high, and then enter the Start state. The stepper motor starts to move to the scanning starting point. In the Start state, check whether the stepper motor has moved to the scanning starting point, and then enter the X_Forward state. In the X_Forward state, the stepper motor will move in the positive direction of the X axis until it reaches the preset X-direction positive scanning boundary x_scan_range, and then enter the Y_Forward state. In the Y_Forward state, the stepper motor will move in the positive direction of the Y axis for a certain distance, and then decide whether to move in the positive direction of the X axis or in the reverse direction of the X axis. If the current X-direction coordinate X_pos is in the X-axis positive scanning boundary x_scan_range, the next step is to move in the reverse direction of the X axis. If it is in the X-axis reverse scanning boundary x_start_pos, the next step is to move in the positive direction of the X axis. Repeat the two-dimensional scanning cycle. When the Y-axis scan reaches the preset Y-direction scanning boundary y_scan_range, enter the Stop state, stop all movements, and achieve accurate two-dimensional scanning.

[0078] Among them, the pulse signal generation generates the stepper motor drive pulse by defining a 32-bit counter StepCounter. The pulse period and duty cycle are controlled by the constants StepCounter_max and StepLockOut. The host computer can control the scanning speed of the stepper motor by adjusting the pulse period. Each cycle of the counter will generate a high-level pulse to drive the stepper motor to step.

[0079] The motor position control uses two 32-bit registers X_pos and Y_pos to record the current position coordinates of the laser on the X-axis and Y-axis. As the motor moves, the values ​​of these two registers will increase or decrease in different states of the state machine;

[0080] In general, the code controls the movement of the stepper motor through the state machine to realize the two-dimensional scanning function of the optical module. The state machine not only controls the movement direction of the motor, but also accurately generates pulse signals to drive the motor, so that the laser beam can move along the preset trajectory. Under the boundary conditions of the X-axis and Y-axis, the state machine will automatically switch direction or stop to ensure the accuracy and reliability of the scanning process. This design provides an efficient motor control solution for the implementation of the optical module, which can meet the requirements of high-precision scanning.

[0081] Secondly, the process of the FPGA control module receiving the scanning parameters sent by the host computer is introduced as follows:

[0082] The user can adjust the scanning parameters (such as scanning range, starting position and scanning speed) through the commands sent by the host computer through Ethernet. These commands are transmitted to the FPGA control module through Ethernet for processing. First, the FPGA control module controls the stepper motor to perform two-dimensional scanning in the x and y directions. The host computer can send commands through Ethernet to change the scanning range and scanning speed in the x and y directions. The logic block based on the GMII receiving clock (gmii_rx_clk) in the FPGA control module is used to parse and receive the UDP data packet sent by the host computer through Ethernet and extract the corresponding scanning parameters. Whenever the rising edge of the GMII receiving clock arrives, the FPGA control module obtains the data (udp_rec_ram_rdata) from the received UDP data packet and stores it in the corresponding position in the data_buffer array. Define a counter. Every time a byte is received, the byte_count counter is increased by 1 to track the number of data bytes currently stored. Whenever the byte_count counter reaches 20 (indicating that 20 bytes of data have been received), start parsing the received data packet:

[0083] The x_scan_range consists of data_buffer[0] to data_buffer[3], a total of 4 bytes, forming a 32-bit X scan range.

[0084] The y_scan_range consists of data_buffer[4] to data_buffer[7], a total of 4 bytes, forming a 32-bit Y scan range.

[0085] x_start_pos consists of data_buffer[8] to data_buffer

[11] , a total of 4 bytes, which constitute the 32-bit X scan start position.

[0086] y_start_pos consists of data_buffer

[12] to data_buffer

[15] , a total of 4 bytes, which constitute the 32-bit Y scan starting position.

[0087] scan_speed consists of data_buffer

[16] to data_buffer

[19] , a total of 4 bytes, indicating the scanning speed.

[0088] scan_start is taken from data_buffer

[20] [0], which indicates the start flag of the scan (the least significant bit of the 20th byte).

[0089] scan_init is taken from data_buffer

[20] [1], which indicates the scan initialization flag (the second least significant bit of the 20th byte)

[0090] After the data parsing is completed, byte_count <= 5'b0; reset the counter to 0 to prepare for the next data reception and parsing.

[0091] The code receives and parses 20 bytes of information from the UDP data packet, including the X, Y scanning range, starting position, scanning speed, and the start and initialization flags of the scan. The counter byte_count tracks the number of bytes received and parses it after receiving the complete data packet.

[0092] In step 300, the AD module collects the scanning information of the optical module and transmits it to the FPGA control module, specifically:

[0093] First, the optical module is introduced, including laser, lens group and photoelectric detector. When in use, the laser emits laser light and focuses it on the biological sample to stimulate the fluorescence signal. The fluorescence is then focused on the photoelectric detector through the lens group, and the fluorescence signal is collected by the photoelectric detector. The photoelectric detector converts the fluorescence signal into an electrical signal, and then the AD module performs high-precision data acquisition with a sampling rate of up to 200kHz and a resolution of 32 bits.

[0094] The AD module is an integrated 8-channel synchronous sampling data acquisition system, which uses the AD7606 chip, which integrates input amplifier, overvoltage protection circuit, second-order analog anti-aliasing filter, analog multiplexer, 16-bit 200kSPSSARADC and a digital filter, 2.5V reference voltage source, reference voltage buffer and high-speed serial and parallel interface.

[0095] In the AD module hardware circuit design, the working mode of AD7606 is set by adding pull-up or pull-down resistors to the three configuration pins of AD7606.

[0096] The AD7606 chip supports external reference voltage input or internal reference voltage. If an external reference voltage is used, the chip's REFIN / REFOUT needs to be connected to an external 2.5V reference source. If the internal reference voltage is used, the REFIN / REFOUT pin is a 2.5V internal reference voltage output, and the REF SELECT pin is used to select the internal reference voltage or the external reference voltage. Considering that the accuracy of the internal reference voltage of the AD7606 is also very high (2.49V~2.505V), the circuit design chooses to use the internal reference voltage.

[0097] The AD conversion data acquisition of AD7606 can be done in parallel mode or serial mode. The communication mode is set by setting the PAR / SER / BYTE SEL pin level. When designing, select the parallel mode to read the AD data of AD7606.

[0098] The input range of the AD7606 AD analog signal can be set to ±5V or ±10V. When the ±5V input range is set, 1LSB = 152.58uV; when the ±10V input range is set, 1LSB = 305.175uV. The analog input voltage range is set by setting the RANGE pin level. When designing, select the ±5V analog voltage input range.

[0099] The AD data collection program is designed as follows:

[0100] The ad7606_if module is the interface module of the AD module. It completes the data acquisition of the AD input of the AD module, generates the AD conversion signal ad_convstab according to the timing of the AD7606 chip, waits for the ADC busy signal to be invalid, generates a chip select signal, reads the AD data in sequence, and converts the analog signal of the AD module input port into a digital signal.

[0101] The ad7606_sample module mainly completes the single-channel data conversion of ad7606. First, the input data needs to be converted into an unsigned number. The final data only takes the high 8 bits of data, and the data width is converted to 8 bits (in order to be compatible with other 8-bit AD module programs). In addition, 1024 data are collected each time, and then the next 1024 data are collected after a period of time. This module will generate the ad_sample_req signal to start sampling, and output the sampling length sample_len at the same time.

[0102] The data cache and read and write program design is as follows:

[0103] FPGA processes the data collected by AD and temporarily stores it in DDR3 memory, which then transmits the data to the host computer via Ethernet, ensuring the integrity and real-time nature of the data.

[0104] The frame_read_write module is a data cache module, used as a data buffer, to coordinate the AD data acquisition rate and the DDR3 write speed, as well as the DDR3 read speed and Ethernet transmission speed. It contains a write FIFO and a read FIFO. The collected 32-bit data is first written to the write FIFO and then read from the read FIFO. Burst read and write operations ensure batch processing of data, reduce the waiting time for data transmission, and improve data throughput.

[0105] MIG IP module: MIG (Memory Interface Generator) IP core is responsible for data exchange with DDR3 memory and for managing the interface between FPGA and external memory (such as DDR3). The 32-bit data collected by AD will first be cached in DDR3. MIG IP supports Axi interface for data exchange with aq_axi_master module.

[0106] The DDR3 module is an external memory used to store data collected by AD.

[0107] In step 400, the FPGA control module transmits the acquired scanning information to the host computer via the UDP protocol, specifically:

[0108] FPGA transmits the processed data to the host computer through the UDP protocol. The use of UDP protocol ensures the real-time and efficiency of data transmission. The host computer receives and processes the data through the host computer software to generate images and conduct subsequent analysis.

[0109] First, based on UDP transmission, the following communication protocol (the composition design of the communication UDP packet) was formulated:

[0110] The first step is for the host computer to obtain the board information: First, the host computer sends a query command to the FPGA board through Ethernet (a total of 5 bytes: the first byte is the Header, and the next 4 bytes are 32'h00000000 or 32'h00010001)

[0111] After that, the development board sends a response command to the host computer through Ethernet (a total of 27 bytes: the first byte is Header|8'h01, the next 4 bytes are 32'h00010001, the next 6 bytes are the board MAC address, the next 4 bytes are the board IP address, the next 1 byte is the sign bit 8'h00: unsigned number 8'h01 signed number (the setting is invalid, the host computer requires a signed number), the next 1 byte is the ADC effective data length, for example, AD7606 is 16 bits, that is, 8'd16, the next 1 byte is the number of bytes collected once ADC (the setting is invalid, the host computer requires the ADC data bit width to be two bytes), the next 1 byte is the sampling channel (this function is not implemented in the host computer), the next 4 bytes are the sampling rate, that is, the sampling frequency, which is set to 200K in the program, and the next 4 bytes are the cached ADC data length in bytes)

[0112] The second step is for the host computer to obtain data: First, the host computer sends a control command to the board (the host computer sends a data request) (a total of 19 bytes: the first byte is the Header, the next 4 bytes are 32'h00010002, the next 6 bytes are the board MAC address, confirming that it is a local MAC address, the next 4 bytes are the sampling channel (this function is not implemented), and the next 4 bytes are the sampling times (the collected data is 16 bits, and the sampling times are half of the cache data length))

[0113] Then the development board sends a response command (a total of 1029 bytes: the first byte is Header|8'h01, the next 4 bytes are 32'h00010002, and the next 1024 bytes are ADC data)

[0114] Each of the above UDP packets contains a Header, and its format is as follows: bit 0: when the value is 0, it is a query or control, when the value is 1, it is a response, and when the bit is bit 1 to bit 7, the value is random data

[0115] The Ethernet transmission part of the program design is:

[0116] Module Definition

[0117] The PLL (Phase-Locked Loop) module provides the clock signal required by the system and provides a 200MHz c1k_200M clock source.

[0118] The eth_top module is the top-level module of Ethernet transmission, responsible for the entire Ethernet data packet processing, including the MAC layer and command control.

[0119] The mac_top module is the Ethernet MAC layer, which handles data packaging, unpacking, basic Ethernet protocol operations, and frame sending and receiving.

[0120] The eth_cmd module is a control module used to send and receive data commands.

[0121] The mac_ctrl module is a control and status monitoring module, including some status registers or configuration registers.

[0122] The util_gmii_to_rgmii module is a GMII to RGMII conversion module that converts data into a format that complies with the RGMII (Reduced GigabitMedia Independent Interface) standard so that it can be sent out through the physical layer (GPHY) interface.

[0123] The GPHY (Gigabit PHY) module is a physical layer interface module that provides the functions of the Gigabit Ethernet physical layer. It encodes and serializes the received RGMII digital signal, converts it into a signal suitable for transmission through the physical network, and communicates with the host computer (PC) through the network cable.

[0124] To sum up, the overall procedure steps are as follows:

[0125] First, the host computer software sets the scanning parameters and sends the corresponding UDP data packet to FPGA through Ethernet. FPGA extracts the corresponding scanning parameters from the UDP data packet (udp_rec_ram_rdata) and stores it in the data_buffer array as the input of the stepper motor control module (Stepmotor module). The stepper motor scanning parameters are set, and then the stepper motor enters the initialization state and further waits for the host computer to send a start command (scan_start) to start scanning;

[0126] Furthermore, when the host computer sends the start command (scan_start), it also sends the query command and the control command;

[0127] Then the received data information (the 2nd to 5th bytes of UDP received data) is judged in the eth_cmd module. If it is an inquiry command, the command response request signal cmd_reply_req and response data are generated; if it is a control command, the signal ad_data_req requesting AD request data is generated. The 32-bit data collected by AD is first stored in DDR3, and then the data collected by AD is read and sent to the computer through the Ethernet interface;

[0128] The mac_ctrl file implements Ethernet transmission control. It waits for a certain period of time in the IDLE state, enters the CMD_WAIT state, determines whether there is a command request cmd_reply_req or a data request ad_data_req, and then enters the CHECK_ARP state to check whether the corresponding IP address is in the cache list. If not, it will send an ARP request and wait for a response. Then, according to the command request or data request, it enters the corresponding data sending state, CMD_SEND or AD_SEND state. The sent AD data packet is 1024 bytes per packet, and the IP sequence number of each packet is increased by 1;

[0129] The cache space set by the host computer is 1M bytes, and the request data interval is 100ms. Therefore, these two points should be taken into account when setting the sampling depth. It is set to 32'h00008000 in the eth_top program, that is, 32K bytes, which is the amount of AD data uploaded by the FPGA when the host computer sends an AD data request. The AD sampling frequency is 200KHz, and the ADC sampling end data is two bytes long. Therefore, the sampling length is the sampling byte divided by 2, that is, 32'h00004000. The calculation shows that the acquisition is completed in 82ms. The inspection of UDP sending data has been removed.

[0130] The present invention provides a schematic diagram of controlling laser scanning as shown in Figure 3 shown.

[0131] It should be noted that the present application provides an embodiment as follows:

[0132] 1. Different ADC chips can be used: Using ADC chips with higher resolution or higher sampling rate can further improve the accuracy of signal acquisition, but it may lead to increased costs and power consumption.

[0133] 2. Use other communication protocols: such as TCP protocol. Although it can improve the reliability of transmission, it may affect the real-time performance of data transmission, especially in large-scale data transmission.

[0134] 3. Use a higher-performance DSP or processor: In some application scenarios, DSP or a higher-performance processor can be used instead of FPGA, which may increase data processing speed, but will also increase system complexity and cost and reduce the degree of system integration.

[0135] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0136] The present invention uses specific examples to illustrate the principles and implementation methods of the present invention. The above examples are only used to help understand the method and core ideas of the present invention. At the same time, for those skilled in the art, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A laser scanning control and fluorescence signal processing device based on FPGA, characterized in that: include: FPGA control module, AD module, stepper motor, optical module, host computer, the optical module is arranged on the stepper motor through a mechanical structure to drive the optical module to achieve precise positioning, the stepper motor, AD module and host computer are connected to the FPGA control module, and the AD module is connected to the optical module to collect scanning information received by the optical module.

2. The device according to claim 1, characterized in that The host computer is connected to the FPGA control module via a gigabit network cable and communicates with the FPGA control module via the Ethernet UDP protocol.

3. The device according to claim 1, characterized in that Pin 1 of the J10 expansion port of the FPGA control module is connected to the ground wire of the stepper motor and the photoelectric switch, pins 3 and 5 are respectively connected to the X-direction and Y-direction stepper motor pulse input signals, pins 7 and 9 are respectively connected to the X-direction and Y-direction stepper motor direction control input signals, pin 11 is connected to the photoelectric switch, and the positive pole of the stepper motor photoelectric switch is connected to the power supply.

4. The device according to claim 1, characterized in that The AD module is inserted into the J9 expansion port of the FPGA control module, and the AD module is connected to the optical module via an SMA line.

5. A laser scanning control and fluorescence signal processing method based on FPGA, characterized in that: include: The host computer sends scanning parameters to the FPGA control module; The FPGA control module controls the stepper motor movement based on the scanning parameters, driving the optical module to achieve a two-dimensional scanning function; The AD module collects the scanning information of the optical module and transmits it to the FPGA control module; The FPGA control module transmits the acquired scanning information to the host computer through the UDP protocol.

6. The method according to claim 5, characterized in that The host computer sends scanning parameters to the FPGA control module. The FPGA control module controls the stepper motor movement based on the scanning parameters, driving the optical module to achieve a two-dimensional scanning function, specifically: Define the input signal, including: sys_clk, clock signal, used to synchronously control the movement of the motor; rst, reset signal, used to initialize the system state; scan_start, start instruction, controlled by the host computer, instructs the system when to start scanning; scan_init, initialization instruction, controlled by the host computer, indicates when the system starts initialization; Init_flag, initialization flag, marks whether the system has completed initialization. When the motor is initialized and returns to the zero point of the coordinate system, the photoelectric switch is triggered and the flag is high. x_scan_range, y_scan_range, the scanning range in the X and Y directions, controlled and changed by the host computer; x_start_pos, y_start_pos, the scanning start position in the X and Y directions, controlled and changed by the host computer; scan_speed, the scanning speed of the stepper motor, is controlled and changed by the host computer; Define output signals, including: StepDrive_1 and StepDrive_2, pulse signals of X-axis stepper motor and Y-axis stepper motor; state_1, state_2, the states of the X-axis stepper motor and the Y-axis stepper motor, respectively, forward rotation is 0, low level, reverse rotation is 1, high level; Dir_flag, direction flag, indicates the current scanning direction; Define the states of the scan state machine, including: Idle: Initialization state, the system is in reset or standby state; Start: Starting state, the motor starts to move to the scanning starting point; X_Forward: X-axis forward movement state, the motor moves forward along the X-axis; Y_Forward: Y-axis forward moving state, the motor moves forward along the Y-axis; X_Reverse: X-axis reverse movement state, the motor moves in the opposite direction along the X-axis; Stop: Stop state, the motor stops moving; The state transition conditions are defined as follows: after power-on, the Idle state is entered, and the Start state is entered after the host computer sends an instruction to set the Start_flag signal high. The stepper motor starts to move to the scanning starting point. In the Start state, check whether the stepper motor has moved to the scanning starting point, and then enter the X_Forward state. In the X_Forward state, the stepper motor will move in the positive direction along the X axis until it reaches the preset X-direction positive scanning boundary x_scan_range, and then enter the Y_Forward state. In the Y_Forward state, the stepper motor will move in the positive direction along the Y axis for a certain distance, and then decide whether to move in the positive direction along the X axis or in the reverse direction along the X axis. If the current X-direction coordinate X_pos is in the X-axis positive scanning boundary x_scan_range, the next step is to move in the reverse direction along the X axis. If it is in the X-axis reverse scanning boundary x_start_pos, the next step is to move in the positive direction along the X axis. Repeat the two-dimensional scanning cycle. When the Y-axis scan reaches the preset Y-direction scanning boundary y_scan_range, it enters the Stop state, stops all movements, and realizes accurate two-dimensional scanning.

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