Memory system, memory controller and operating method thereof

Abstract

A memory system, a memory controller and an operating method thereof are provided. An example memory system includes a memory device and a memory controller. The memory device is configured to read hard decision data from a memory cell array based on a hard read voltage, read first soft decision data from the memory cell array based on a first soft read voltage, the first soft read voltage being obtained based on the hard read voltage and a first voltage offset, a first compressed sub-segment is generated based on encoding a position of a bit having a first value as a position value for each first soft-decision sub-segment in the first soft-decision data, and first compressed data including the first compressed sub-segment is output. The memory controller is configured to receive the first compressed data, count a number of location values for each of the first compressed sub-segments, and provide a command to the memory device requesting a change in voltage offset and a recompression operation based on the counted number.

Description

Technical Field

[0001] The present disclosure relates to a memory system, a memory controller and an operating method thereof. Background Art

[0002] The nonvolatile memory device reads hard decision data based on a hard decision voltage, and generates soft decision data by using read values ​​read based on a plurality of soft read voltages.

[0003] The soft decision data is information indicating the reliability of the hard decision data. The memory controller performs an error correction operation based on the hard decision data and the soft decision data. Summary of the invention

[0004] The present disclosure relates to a memory system configured to correct errors based on soft decision data, a memory controller configured to determine compression quality of the soft decision data, and a method of operating a memory controller.

[0005] In general, according to some aspects, a memory system includes a memory device and a memory controller, wherein the memory system is configured to read hard decision data from a memory cell array by using a hard read voltage, read first soft decision data from the memory cell array by using two or more first soft read voltages, the two or more first soft read voltages being obtained based on the hard read voltage and a first voltage offset, generate a first compressed subsegment by encoding the position of a bit having a first value as a position value for each first soft decision subsegment in a plurality of first soft decision subsegments included in the first soft decision data, and output first compressed data including a plurality of first compressed subsegments; the memory controller is configured to receive the first compressed data, count the number of position values ​​in each first compressed subsegment in the plurality of first compressed subsegments, and provide a command to the memory device based on the count number, the command requesting a change in voltage offset and recompression operation.

[0006] In general, according to some aspects, a method of operating a memory controller includes: providing a read command to a memory device; receiving hard decision data read based on a hard read voltage from the memory device; receiving first compressed data, the first compressed data including a plurality of first compressed sub-segments respectively corresponding to a plurality of first soft decision sub-segments, the plurality of first soft decision sub-segments being included in first soft decision data read based on a first soft read voltage, the first soft read voltage being obtained by the hard read voltage and a voltage offset; providing a command requesting a change in the voltage offset to the memory device based on the number of position values ​​of bits having a first value in each of the plurality of first soft decision sub-segments, the position value being included in each of the plurality of first compressed sub-segments; receiving second compressed data of second soft decision data read based on a second soft read voltage from the memory device, the second soft read voltage being obtained by the hard read voltage and the changed voltage offset; obtaining the second soft decision data by performing a decompression operation on the second compressed data; and performing error correction on the hard decision data based on the second soft decision data.

[0007] In general, according to some aspects, a memory controller includes a memory interface and an error correction circuit, wherein the memory interface is configured to receive hard decision data and first compressed data from a memory device, the hard decision data being read based on a hard read voltage, the first compressed data including a plurality of first compressed sub-segments corresponding to a plurality of first soft decision sub-segments of first soft decision data, respectively, the first soft decision data being read based on a first soft read voltage obtained by the hard read voltage and a voltage offset, and the error correction circuit being configured to output a signal requesting a change in the voltage offset based on the number of position values ​​of bits having a first value in each of the plurality of first soft decision sub-segments, the position value being included in each of the plurality of first compressed sub-segments. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0009] Figure 1 is a block diagram of an example of a memory system.

[0010] Figure 2 is a block diagram of an example of a nonvolatile memory device.

[0011] Figure 3 is a block diagram of an example of a host-memory system.

[0012] Figure 4is a diagram showing an example of threshold voltage distribution of an ideal triple-level cell (TLC).

[0013] Figure 5 is an example diagram showing that the threshold voltage distribution of TLC has deteriorated.

[0014] Fig. 6A and Figure 6B are diagrams each illustrating an example of a soft-decision read operation.

[0015] Figure 7 is a block diagram of an example of a memory system.

[0016] Fig. 8A and Figure 8B is a diagram showing an example of a read operation.

[0017] 9A to 9C is a diagram showing an example of a read operation.

[0018] Fig. 10A and Fig. 10B is a diagram showing an example of a read operation.

[0019] Fig.11 is a flowchart illustrating an example of a method of operating a memory device.

[0020] Fig.12 is a flow chart illustrating an example of a method of operating a memory controller.

[0021] Fig.13 is a diagram showing an example of a compression method of soft decision data.

[0022] FIG. 14A to FIG. 14C is a diagram showing an example of a compression method of a soft decision sub-segment.

[0023] Fig.15 is a diagram showing an example of a location mapping table.

[0024] FIG. 16A to FIG. 16C is a diagram showing an example of a compression method of a soft decision segment.

[0025] Fig.17 is a diagram illustrating an example of a method of operating a memory system.

[0026] Fig.18 is a block diagram of an example of a memory controller.

[0027] Fig.19 is a diagram illustrating an example of a method of operating a compression quality estimator.

[0028] Fig. 20 is a diagram showing an example of a decompression method.

[0029] Fig.21A and Fig. 21B is an example graph showing log-likelihood ratio (LLR) adjustment.

[0030] Fig. 22 is a diagram illustrating an example of a memory device. DETAILED DESCRIPTION

[0031] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0032] Figure 1 is a block diagram of an example of the memory system 1 .

[0033] refer to Figure 1 , the memory system 1 may include a memory device 100 and a memory controller 200. The memory system 1 may support a plurality of channels CH1 to CHm, and the memory device 100 may be connected to the memory controller 200 through the plurality of channels CH1 to CHn. For example, the memory system 1 may be implemented as a storage device such as an SSD.

[0034] The memory device 100 may include a plurality of NVM devices NVM11 to NVMmn. Each of the NVM devices NVM11 to NVMmn may be connected to one of the plurality of channels CH1 to CHm through a path corresponding thereto. For example, the NVM devices NVM11 to NVM1n may be connected to the first channel CH1 through paths W11 to W1n, and the NVM devices NVM21 to NVM2n may be connected to the second channel CH2 through paths W21 to W2n. In some embodiments, each of the NVM devices NVM11 to NVMmn may be implemented as any memory unit that may be operated according to a separate command from the memory controller 200. For example, each of the NVM devices NVM11 to NVMmn may be implemented as a chip or a die, but the present disclosure is not limited thereto.

[0035] The memory controller 200 may transmit and receive signals to and from the memory device 100 through the plurality of channels CH1 to CHm. For example, the memory controller 200 may transmit commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the memory device 100 through the channels CH1 to CHm, or may receive data DATAa to DATAm from the memory device 100.

[0036] The memory controller 200 may select one of the NVM devices NVM11 to NVMmn connected to each of the channels CH1 to CHm by using the corresponding channels among the channels CH1 to CHm, and transmit and receive signals to and from the selected NVM device. For example, the memory controller 200 may select the NVM device NVM11 from the NVM devices NVM11 to NVM1n connected to the first channel CH1. The memory controller 200 may transmit a command CMDa, an address ADDRa, and data DATAa to the selected NVM device NVM11 through the first channel CH1, or receive data DATAa from the selected NVM device NVM11.

[0037] The memory controller 200 may send and receive signals to and from the memory device 100 in parallel through different channels. For example, the memory controller 200 may send a command CMDb to the memory device 100 through the second channel CH2 while sending a command CMDa to the memory device 100 through the first channel CH1. For example, the memory controller 200 may receive data DATAb from the memory device 100 through the second channel CH2 while receiving data DATAa from the memory device 100 through the first channel CH1.

[0038] The memory controller 200 may control all operations of the memory device 100. The memory controller 200 may send signals to the channels CH1 to CHm and control each of the NVM devices NVM11 to NVMmn connected to the channels CH1 to CHm. For example, the memory controller 200 may send a command CMDa and an address ADDRa to the first channel CH1 and control one NVM device selected from the NVM devices NVM11 to NVM1n.

[0039] Each of the NVM devices NVM11 to NVMmn may be operated via the control of the memory controller 200. For example, the NVM device NVM11 may program data DATAa based on the command CMDa, the address ADDRa, and the data DATAa provided to the first channel CH1. For example, the NVM device NVM21 may read data DATAb based on the command CMDb and the address ADDb provided to the second channel CH2, and transmit the read data DATAb to the memory controller 200.

[0040] although Figure 1 An example is shown in which the memory device 100 communicates with the memory controller 200 through m channels and includes n NVM devices corresponding to each channel, but the number of channels and the number of NVM devices connected to one channel may be variously changed.

[0041] An error correction code (ECC) circuit 210 for correcting errors of data read from the memory device 100 may be disposed in the memory controller 200. An error correction method of the ECC circuit 210 may include a hard decision method and a soft decision method.

[0042] The hard decision method may be a method of correcting data errors by using ECC and data (hereinafter referred to as hard decision data) read according to the on / off characteristics of a memory cell when a specific reference voltage (hereinafter referred to as a hard read voltage) is applied to the memory cell. For example, errors in the hard decision data may be corrected based on a parity check matrix and the hard decision data.

[0043] The soft decision method may be a method of correcting a data error by additionally using additional information about the reliability of hard decision data (hereinafter referred to as soft decision data) separately from hard decision data and ECC. The soft decision data may refer to data read according to the on / off characteristics of a memory cell when a voltage obtained by adding or subtracting a specific voltage offset to or from a hard read voltage (hereinafter referred to as a soft read voltage) is applied to a memory cell.

[0044] The memory controller 200 may provide a read command of hard decision data and soft decision data to the memory device 100. The memory device 100 may provide the memory controller 200 with hard decision data obtained from an NVM device selected from the NVM devices NVM11 to NVMmn. Each of the NVM devices NVM11 to NVMmn may include a compression circuit (e.g., Figure 2 The compression circuit 107 may compress the soft decision data. The compression circuit 107 may compress the soft decision data obtained from the selected NVM device and provide the compressed data to the memory controller 200.

[0045] The ECC circuit 210 can generate soft decision data by decompressing the compressed data, and can correct errors in the hard decision data based on the hard decision data and the soft decision data. For example, the ECC circuit 210 can correct the hard decision data by calculating a log likelihood ratio (LLR) based on the soft decision data, but the embodiments of the present disclosure are not limited thereto.

[0046] In some embodiments, the soft decision data may indicate an overlapping region between adjacent threshold voltage distributions with "1", and indicate another region with "0". The overlapping region between the threshold voltage distributions may be a region where the reliability of the hard decision data is relatively low. The other region may be a region where the reliability of the hard decision data is relatively high. Because the overlapping region between adjacent threshold voltage distributions is smaller than other regions, the number of "1"s in the soft decision data may be smaller than the number of "0"s in the soft decision data. For ease of description, it is described that "1" in the soft decision data indicates an overlapping region between the threshold voltage distributions and "0" in the soft decision data indicates other regions, but the embodiments of the present disclosure are not limited thereto. For example, the soft decision data may indicate an overlapping region between the threshold voltage distributions with "0", and indicate other regions with "1".

[0047] The compression circuit 107 included in each of the NVM devices NVM11 to NVMmn may generate compressed data by encoding “1” in the soft decision data into a position value of “1”.

[0048] The NVM devices sharing the same channel may perform the output of the hard decision data and the compression of the soft decision data in parallel. For example, when some of the NVM devices NVM11 to NVM1n sharing the first channel CH1 provide the hard decision data to the memory controller 200 through the first channel CH1, some other NVM devices may compress the soft decision data. When the output of the hard decision data is completed, some other NVM devices may provide the compressed data to the memory controller 200 through the first channel CH1. Because the compression of the soft decision data and the output of the hard decision data are performed in parallel, and the compressed data is output when the output of the hard decision data is completed, the boot time for providing the hard decision data and the soft decision data to the memory controller 200 can be reduced.

[0049] The compression circuit 107 may generate compressed data including position values ​​of "1" by encoding position values ​​of "1" included in the soft decision data. The compression circuit 107 may generate compressed data having a fixed size regardless of the number of "1" in the soft decision data.

[0050] The compression circuit 107 can compress the soft decision data by unit size (e.g., 128 bits). The soft decision data of the unit size can be referred to as a soft decision sub-segment. The compression circuit 107 can compress the soft decision sub-segment and thus generate a compressed sub-segment. The compressed sub-segment may include the position value of the "1" contained in the soft decision sub-segment. The position value of each "1" can be represented by 8 bits.

[0051] The compression circuit 107 may generate a compressed sub-segment having a fixed size (e.g., 32 bits) regardless of the number of "1"s in the soft decision sub-segment. For example, when the number of "1"s in the soft decision sub-segment is less than a reference number (e.g., 4), the compression circuit 107 may generate a compressed sub-segment having a fixed size by including a dummy value in the compressed sub-segment. When the number of "1"s in the soft decision sub-segment is greater than a reference number (e.g., 4), the compression circuit 107 may generate a compressed sub-segment having a fixed size by excluding position values ​​of an excessive number of "1"s exceeding the reference number from the compressed sub-segment. Therefore, the position values ​​of "1"s may be lost.

[0052] In some embodiments, the compression circuit 107 may generate compressed sub-segments having different sizes according to the number of "1"s in the soft decision sub-segment. For example, when the soft decision sub-segment includes N "1"s (where N is a natural number), the compression circuit 107 may generate a compressed sub-segment including N position values ​​by representing each position value of "1" with 8 bits. That is, the compression circuit 107 may generate compressed data by losslessly encoding the position value of "1" included in the soft decision data. The memory controller 200 may receive the compressed data, and may obtain the soft decision data without losing the number of "1"s by decoding the compressed data.

[0053] In each soft decision sub-segment, an excessive number of "1"s exceeding a reference number may be lost. Therefore, when the compressed data is decompressed, the ECC circuit 210 obtains soft decision data in which some "1"s are lost. However, due to the nature of the error correction method, although some bits are lost in the soft decision data, the ECC circuit 210 can still perform error correction on the hard decision data by using the soft decision data. For example, the ECC circuit 210 can calculate LLRs by using the soft decision data, and can perform error correction on the hard decision data using a low-density parity check (LDPC) method based on the LLRs.

[0054] In some embodiments, the compression quality estimator 220 may estimate the compression quality of the compressed data. Since there are a large number of position values ​​in the compressed subsegment, there is a high probability that some position values ​​respectively representing "1" are lost in the soft decision subsegment. The compression quality estimator 220 may calculate the number of compressed subsegments from a plurality of compressed subsegments, each of which includes a number of position values ​​greater than a first reference number. For example, the compression quality estimator 220 may count the number of compressed subsegments each including 4 position values. When the count number is a second reference value or greater, the compression quality estimator 220 may determine that the compression quality is poor. When the compression quality is poor, the memory controller 200 may request the memory device 100 to change the voltage offset for reading the soft decision data, use the changed voltage offset and provide the compressed data again. When the count number is less than the second reference value, the compression quality estimator 220 may determine that the compression quality is good. When the compression quality is good, the ECC circuit 210 may decompress the compressed data, and may perform an ECC operation on the hard decision data based on the decompressed soft decision data.

[0055] Figure 2 is a block diagram of an example of a nonvolatile memory device 10 . Figure 2 The memory device may correspond to at least one of the plurality of NVM devices NVM11 to NVMmn. Figure 2 , the nonvolatile memory device 10 may include a control logic circuit 101, a memory cell array 102, a page buffer circuit 103, a voltage generator 104, a row decoder 105, a memory interface circuit 106, and a compression circuit 107. Figure 2 Although not shown, the nonvolatile memory device 10 may further include a column logic, a pre-decoder, a temperature sensor, a command decoder, and / or an address decoder.

[0056] The control logic circuit 101 may control all various operations of the memory device 300. The control logic circuit 101 may output various control signals in response to a command CMD and / or an address ADDR from the memory interface circuit 106. For example, the control logic circuit 101 may output a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR.

[0057] The memory cell array 102 may include a plurality of memory blocks BLK1 to BLKz (where z is a positive integer), each of which may include a plurality of memory cells. The memory cell array 102 may be connected to the page buffer circuit 103 through the bit lines BL, and connected to the row decoder 105 through the word lines WL, the string selection lines SSL, and the ground selection lines GSL.

[0058] In some embodiments, the memory cell array 102 may include a 3D memory cell array including a plurality of NAND strings. Each NAND string may include memory cells vertically stacked on a substrate and connected to word lines, respectively. The disclosures of U.S. Patent Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235 and U.S. Patent Publication No. 2011 / 0233648 are incorporated herein by reference. In some embodiments, the memory cell array 102 may include a 2D memory cell array including a plurality of NAND strings arranged in row and column directions.

[0059] The page buffer circuit 103 may include a plurality of page buffers PB1 to PBn (here, n is an integer greater than or equal to 3) that may be connected to the memory cells through a plurality of bit lines BL, respectively. The page buffer circuit 103 may select at least one bit line BL in response to the column address Y-ADDR. The page buffer circuit 103 may operate as a write driver or a sense amplifier according to an operation mode. For example, during a programming operation, the page buffer circuit 103 may apply a bit line voltage corresponding to the data to be programmed to the selected bit line. During a read operation, the page buffer circuit 103 may sense a current or voltage of the selected bit line BL and sense the data stored in the memory cell.

[0060] The page buffer circuit 103 may obtain hard decision data or soft decision data from the compression circuit 107. The compression circuit 107 may sequentially generate compressed segments by compressing soft decision segments, and may store the compressed segments in the page buffer circuit 103. When compression of the entire soft decision data is completed, the compressed data may be output to the DQ pin through the memory interface circuit 106. As used herein, the term “DQ pin” may also be referred to as the term “I / O pin”.

[0061] The compression circuit 107 may generate compressed data by encoding the positions of bits each indicating a minor value among the bits included in the soft decision data. Figures 12 to 14C A specific compression method is described in detail. Herein, it is described that the minor value is "1", but the embodiments of the present disclosure are not limited thereto. The minor value may correspond to an overlapping region between adjacent threshold voltage distributions, and the major value may correspond to another region.

[0062] The voltage generator 104 may generate various voltages for programming, reading, and erasing operations based on the voltage control signal CTRL_vol. For example, the voltage generator 104 may generate a programming voltage, a reading voltage, a programming verification voltage, and an erasing voltage as the word line voltage VWL. During a read operation of hard decision data, the voltage generator 104 may generate a hard read voltage and provide the hard read voltage to the row decoder 105. During a read operation of soft decision data, the voltage generator 104 may generate a soft read voltage and provide the soft read voltage to the row decoder 105.

[0063] The row decoder 105 may select one of the plurality of word lines WL and one of the plurality of string selection lines SSL in response to the row address X-ADDR. For example, the row decoder 105 may apply a program voltage and a program verification voltage to the selected word line WL during a program operation, and apply a read voltage to the selected word line WL during a read operation.

[0064] The memory interface circuit 106 may send and receive data through the DQ pins.

[0065] The control logic circuit 101 may include an offset adjustment circuit 108. The offset adjustment circuit 108 may adjust the level of the voltage offset added to the hard read voltage or the level of the voltage offset subtracted from the hard read voltage to calculate the soft read voltage. In some embodiments, the NVM device 10 may receive a command CMD including a voltage offset level from the memory controller 200, and the offset adjustment circuit 108 may determine the level of the soft read voltage based on the voltage offset level in the command CMD, and may output a voltage control signal CTRL_vol so that the voltage generator 104 generates the soft read voltage at the determined level. In some embodiments, the NVM device 10 may receive a command CMD requesting a change in the voltage offset from the memory controller 200, and the offset adjustment circuit 108 may reduce the voltage offset by a predetermined level. The offset adjustment circuit 108 may determine the level of the soft read voltage based on the level of the reduced voltage offset, and may output a voltage control signal CTRL_vol so that the voltage generator 104 generates the soft read voltage at the determined level. Although the offset adjustment circuit 108 is shown as being included in the control logic circuit 101, embodiments of the present disclosure are not limited thereto. The offset adjustment circuit 108 may be implemented by hardware independent of the control logic circuit 101 .

[0066] Figure 3 is a block diagram of an example of a host-memory system.

[0067] The host-memory system 3 may include a host 2 and a memory system 1. In addition, the memory system 1 may include a memory controller 200 and a memory device 100. In addition, the host 2 may include a host controller 21 and a host memory 22. The host memory 22 may be used as a buffer memory for temporarily storing data to be transferred to the memory system 1 or data that has been transferred from the memory system 1.

[0068] The memory system 1 may include a storage medium for storing data according to a request from the host 2. As an example, the memory system 1 may include at least one of a solid state drive (SSD), an embedded memory, and a removable external memory. When the memory system 1 corresponds to an SSD, the memory system 1 may be a device that complies with the non-volatile memory express (NVMe) specification. When the memory system 1 corresponds to an embedded memory or an external memory, the memory system 1 may be a device that complies with the universal flash memory (UFS) specification or the embedded multimedia card (eMMC) specification. The host 2 and the memory system 1 may each generate a packet according to the adopted standard protocol and transmit the packet.

[0069] When the memory device 100 of the memory system 1 includes a flash memory, the flash memory may include a two-dimensional (2D) NAND memory array or a three-dimensional (3D) (or vertical) NAND (VNAND) memory array. As another example, the memory system 1 may include various other NVMs. Examples of the memory system 1 may include magnetic RAM (MRAM), spin transfer torque MRAM, conductive bridge RAM (CBRAM), ferroelectric RAM (FeRAM), phase change RAM (PRAM), resistive RAM, and various other memories.

[0070] In some embodiments, the host controller 21 and the host memory 22 may be implemented by separate semiconductor chips, respectively. Alternatively, in some embodiments, the host controller 21 and the host memory 22 may be integrated in the same semiconductor chip. As an example, the host controller 21 may be one of a plurality of modules arranged in an application processor, and the application processor may be implemented by a system on chip (SoC). In addition, the host memory 22 may include an embedded memory arranged in the application processor or a memory module or a non-volatile memory arranged outside the application processor.

[0071] The host controller 21 may manage an operation of storing data (eg, recording data) of the host memory 22 in the memory device 100 or an operation of storing data (eg, reading data) of the memory device 100 in the host memory 22 .

[0072] The memory controller 200 may include a host interface 250 , a memory interface 260 , a central processing unit (CPU) 240 , a buffer memory 230 , and an ECC circuit 210 .

[0073] The host interface 250 may send packets to the host 2 and receive packets from the host 2. The packets sent from the host 2 to the host interface 250 may include commands, data to be written to the memory device 100, etc., and the packets sent from the host interface 250 to the host 2 may include responses to commands, data read from the memory device 100, etc. The memory interface 260 may transfer data to be written to the memory device 100 to the memory device 100, or may receive data read from the memory device 100. Such a memory interface 260 may be implemented to comply with standard specifications, such as Toggle or Open NAND Flash Interface (ONFI).

[0074] The ECC circuit 210 may perform an error detection and correction function on read data read from the memory device 100. More specifically, the ECC circuit 210 may generate parity bits for normal data to be written to the memory device 100, and the parity bits thus generated may be stored in the memory device 100 together with the normal data. When reading data from the memory device 100, the ECC circuit 210 may correct errors in the normal data by using the parity bits read from the memory device 100 together with the normal data, and may output the error-corrected normal data.

[0075] The ECC circuit 210 may include an ECC encoder 211 and an ECC decoder 212. The ECC encoder 211 generates a codeword in which a parity bit is added to normal data input through the host interface 250. The codeword may be stored in the memory device 100. During a read operation, the codeword may be read from the memory device 100 according to a hard decision method. That is, the codeword may correspond to hard decision data.

[0076] The ECC decoder 212 may perform error correction decoding on the hard decision data received from the memory device 100. The hard decision data received from the memory device 100 may be transmitted to the ECC decoder 212, and the ECC decoder 212 may correct the error bits in the normal data by using the parity bits in the hard decision data. The ECC circuit 210 may use, for example, an LDPC code.

[0077] Although not shown, the ECC decoder 212 may include Figure 1The compression quality estimator 220 of the memory device 100 may estimate the compression quality of the compressed data received from the memory device 100. The ECC decoder 212 may output a signal for requesting a change in the voltage offset based on the compression quality. The quality of the compressed data with the changed voltage offset may be higher than the quality of the previous compressed data.

[0078] In some embodiments, the memory controller 200 may receive compressed data with improved compression quality from the memory device 100. Therefore, the reliability of the soft decision data obtained by the decompression operation may be improved. That is, the memory controller 200 may obtain high-quality soft decision data. Since the ECC decoder 212 performs error correction on the hard decision data based on the soft decision data, high-quality soft decision data may be obtained, thereby improving ECC performance.

[0079] Figure 4 is a diagram showing an example of threshold voltage distribution of an ideal triple-level memory cell (TLC).

[0080] refer to Figure 2 and Figure 4 , when the NVM device 10 corresponds to a TLC memory device capable of storing 3 bits in one memory cell in the memory cell array 102, in order to program 3 bits into one memory cell, the threshold voltage of the memory cell may be programmed to one of 8 threshold voltages. However, since there are differences in electrical characteristics between memory cells programmed to the same threshold voltage, the threshold voltages of a plurality of memory cells programmed to the same threshold voltage may be formed as follows: Figure 4 Thus, in the case of a TLC memory device, eight threshold voltage distributions (ie, E and P1 to P7) can be formed.

[0081] When the threshold voltage distribution of the memory cell array 102 is as follows Figure 4 The ideal condition is shown, which can be achieved by using Figure 4 The hard read voltages Vhread1 to Vhread7 shown are used to perform a read operation, thereby obtaining read data with fewer errors, and the possibility of successful error correction decoding is high. Herein, the read operation using the hard read voltages Vhread1 to Vhread7 may be referred to as a hard decision read operation. The hard decision read operation may refer to reading the data stored in the memory cell as 1 or 0 according to the on state or off state of the memory cell when the hard read voltages Vhread1 to Vhread7 are supplied to the word line of the memory cell.

[0082] The threshold voltage distribution may degrade with repeated operations on the memory cell array 102 .

[0083] Figure 5is an example diagram showing that the threshold voltage distribution of TLC has deteriorated.

[0084] refer to Figure 5 , the threshold voltage distribution may shift to the left or right due to the loss of charge generated by the emission of electrons stored in the memory cells in the memory cell array 102 over time. Therefore, the threshold voltage distributions in the erase state E and the seven program states P1 to P7 may overlap with each other.

[0085] In a case where the threshold voltage distributions overlap each other like this, when a read operation has been performed by using the hard read voltages Vhread1 to Vhread7 , an uncorrectable error correction code (UECC) error may be generated due to a large number of error bits.

[0086] For example, when a read operation is performed by using a hard read voltage Vhread1, although it is necessary to distinguish between the on-cell in the erase state E on the left and the off-cell in the program state P1 on the right, in the case of Figure 5 In the case where the cell distributions of the illustrated memory cells overlap each other, there may be memory cells that are read as off cells although they are actually on cells, and there may also be memory cells that are read as on cells although they are actually off cells.

[0087] Therefore, in a threshold voltage distribution such as Figure 5 In the illustrated case, when a read operation is performed by using the hard read voltages Vhread1 to Vhread7 , because the memory controller 200 receives hard decision data having a large number of errors, the possibility of error correction decoding failure may be high.

[0088] Therefore, the memory controller 200 can receive the compressed data for the soft decision data from the memory device 100, and can perform decompression on the compressed data, thereby obtaining the soft decision data. The memory controller 200 can perform error correction decoding on the hard decision data based on the soft decision data. By distinguishing the overlapping area between the threshold voltage distributions from other areas, the soft decision data can indicate the reliability of the hard decision data.

[0089] Fig. 6A and Figure 6B are diagrams each illustrating an example of a soft-decision read operation.

[0090] like Fig. 6AAs shown, the soft read voltages used in the soft decision read operation may be Vsread1 and Vsread2. The soft decision read operation may refer to an operation of forming information for increasing reliability to the hard decision data HD by applying a plurality of soft read voltages Vsread1 and Vsread2 having a specific voltage difference (i.e., voltage offset) from the hard read voltage Vhread1 as a reference to the memory cell. Fig. 6A , the voltage offset may be ofs1. The level of the soft read voltage Vsread1 may be obtained by subtracting ofs1 from the hard read voltage Vhread1. The level of the soft read voltage Vsread2 may be obtained by adding ofs1 to the hard read voltage Vhread1. When the soft read voltage Vsread1 is applied to the memory cell, the data (i.e., the first SRD) determined according to the on or off of the memory cell may be 1, 0, 0, and 0. When the soft read voltage Vsread2 is applied to the memory cell, the data (i.e., the second SRD) determined according to the on or off of the memory cell may be 1, 1, 1, and 0.

[0091] By performing an exclusive OR (XOR) operation on the read values ​​obtained by the two read operations (ie, the first SRD and the second SRD), the soft decision data SD can be formed. Fig. 6A As shown, the soft decision data SD may be 0, 1, 1, and 0. The XOR operation may be performed in the page buffer circuit 103. That is, the XOR operation may be performed on the read values ​​(i.e., the first SRD and the second SRD) obtained by the two read operations by using a plurality of latches in the page buffer circuit 103. The soft decision data SD may indicate the reliability of the hard decision data HD. When the soft decision data SD is 0, it may mean that the reliability of the hard decision data HD is high, i.e., strong (S), and when the soft decision data SD is 1, it may mean that the reliability of the hard decision data HD is low, i.e., weak (W). That is, 10, 11, 01, and 00, which are combinations of the hard decision data HD 1, 1, 0, and 0 and the soft decision data SD 0, 1, 1, and 0, respectively, may represent high reliability hard decision data HD 1, low reliability hard decision data HD 1, low reliability hard decision data HD 0, and high reliability hard decision data HD 0, respectively.

[0092] The width of the overlap region between state P1 and state P2 may be very small compared to the respective distribution widths of state P1 and state P2. Therefore, when soft decision data SD is read from a plurality of memory cells (e.g., 4KB memory cells) programmed in state P1 and state P2, the number of 1s each indicating an overlap region may be much smaller than the number of 0s each indicating another region.

[0093] Figure 1 and Figure 2The compression circuit 107 may generate compressed data by compressing the soft decision data SD, and provide the compressed data to the memory controller 200 .

[0094] exist Figure 6B The voltage offset ofs2 can be less than Fig. 6A That is, the width of the overlapped region between the soft read voltages Vsread3 and Vsread4 may be smaller than the width of the overlapped region between the soft read voltages Vsread1 and Vsread2.

[0095] Therefore, the number of "1" in the soft decision data SD read based on the voltage offset ofs2 may be smaller than the number of "1" in the soft decision data SD read based on the voltage offset ofs1. In addition, the number of position values ​​of "1" in the compressed data of the soft decision data SD read based on the voltage offset ofs2 may be smaller than the number of position values ​​of "1" in the compressed data of the soft decision data SD read based on the voltage offset ofs1.

[0096] In some embodiments, when receiving low-quality compressed data, the memory controller 200 may request the memory device 100 to read the soft decision data by using a relatively small voltage offset. When the soft decision data is read by using a relatively small voltage offset, the loss of position values ​​can be reduced because the number of "1" in the soft decision data is reduced. Therefore, the quality of the compressed data corresponding to the soft decision data read based on the small voltage offset can be improved.

[0097] although Fig. 6A and Figure 6B Each shows that there is a voltage offset, but the embodiments of the present disclosure are not limited thereto, and the soft decision data can be read by using multiple voltage offsets. For example, the first soft decision data can be read based on the first voltage offset, and the second soft decision data can be read based on the second voltage offset. The combination of the first soft decision data and the second soft decision data can represent the reliability of the hard decision data through 6 categories (i.e., very strong 1, strong 1, weak 1, weak 0, strong 0, and very strong 0). In some embodiments, the memory controller 200 can request the memory device 100 to generate soft decision data by adjusting at least one voltage offset of the multiple voltage offsets to be smaller.

[0098] Figure 7 is a block diagram of an example of a memory system 1'. Figure 7 , the memory system 1' may include a memory device 100' and a memory controller 200'. The memory device 100' may correspond to a memory device based on Figure 1One of the multiple channels CH1 to CHm of the memory controller 200' communicates with one of the NVM devices NVM11 to NVMmn. The memory controller 200' may correspond to Figure 1 A memory controller 200 is provided.

[0099] The memory device 100 ′ may include first to eighth pins P11 to P18 , a memory interface circuit 106 , a control logic circuit 101 , and a memory cell array 102 .

[0100] The memory interface circuit 106 may receive a chip enable signal nCE from the memory controller 200' through the first pin P11. The memory interface circuit 106 may send a signal to the memory controller 200' and receive a signal from the memory controller 200' through the second pin P12 to the eighth pin P18 in response to the chip enable signal nCE. For example, when the chip enable signal nCE is in an enabled state (e.g., a low level), the memory interface circuit 106 may send a signal to the memory controller 200' and receive a signal from the memory controller 200' through the second pin P12 to the eighth pin P18.

[0101] The memory interface circuit 106 can receive a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal nWE from the memory controller 200' through the second pin P12 to the fourth pin P14. The memory interface circuit 106 can receive a data signal DQ from the memory controller 200' through the seventh pin P17, or send a data signal DQ to the memory controller 200'. The command CMD, the address ADDR, and the data can be transmitted via the data signal DQ. For example, the data signal DQ can be transmitted through multiple data signal lines. In this case, the seventh pin P17 may include multiple pins corresponding to the multiple data signals DQ, respectively. For example, Fig. 9A As shown, the memory device 100 ′ may provide data DATA to the memory controller 200 ′ via eight DQ pins ( DQ0 to DQ7 ).

[0102] The memory interface circuit 106 may obtain the command CMD from the data signal DQ received in the enabled portion (e.g., high level state) of the command latch enable signal CLE based on the switching time point of the write enable signal nWE. The memory interface circuit 106 may obtain the address ADDR received in the enabled portion (e.g., high level state) of the address latch enable signal ALE from the data signal DQ based on the switching time point of the write enable signal nWE.

[0103] In some embodiments, the write enable signal nWE may be maintained at a static state (e.g., a high level or a low level) and switched between a high level and a low level. For example, in a portion of transmitting a command CMD or an address ADDR, the write enable signal nWE may switch. Therefore, the memory interface circuit 106 may obtain the command CMD or the address ADDR based on the switching time point of the write enable signal nWE.

[0104] The memory interface circuit 106 may receive a read enable signal nRE from the memory controller 200' through a fifth pin P15. The memory interface circuit 106 may receive a data strobe signal DQS from the memory controller 200' through a sixth pin P16, or send the data strobe signal DQS to the memory controller 200'.

[0105] In the data (DATA) output operation of the memory device 100', the memory interface circuit 106 may receive a read enable signal nRE switched through the fifth pin P15 before outputting the data DATA. The memory interface circuit 106 may generate a data select signal DQS switched based on the switching of the read enable signal nRE. For example, the memory interface circuit 106 may generate a data select signal DQS that starts switching after a predetermined delay (e.g., tDQSRE) based on the switching start time of the read enable signal nRE. The memory interface circuit 106 may transmit a data signal DQ including data DATA based on the switching time point of the data select signal DQS. Therefore, the data DATA may be aligned with the switching time point of the data select signal DQS and transmitted to the memory controller 200'.

[0106] In the data (DATA) input operation of the memory device 100', when the data signal DQ including the data DATA is received from the memory controller 200', the memory interface circuit 106 may receive the switched data DATA together with the data strobe signal DQS from the memory controller 200'. The memory interface circuit 106 may obtain the data DATA from the data signal DQ based on the switching time point of the data strobe signal DQS. For example, the memory interface circuit 106 may sample the data signal DQ at the rising edge and the falling edge of the data strobe signal DQS and obtain the data DATA.

[0107] The memory interface circuit 106 may send a ready / busy output signal nR / B to the memory controller 200' through the eighth pin P18. The memory interface circuit 106 may send the status information of the memory device 100' to the memory controller 200' through the ready / busy output signal nR / B. When the memory device 100' is in a busy state (i.e., when an operation is being performed in the memory device 100'), the memory interface circuit 106 may send the ready / busy output signal nR / B indicating the busy state to the memory controller 200'. When the memory device 100' is in a ready state (i.e., when an operation is not being performed or an operation is completed in the memory device 100'), the memory interface circuit 106 may send the ready / busy output signal nR / B indicating the ready state to the memory controller 200'. For example, when the memory device 100' reads data DATA from the memory cell array 102 in response to a page read command, the memory interface circuit 106 may send a ready / busy output signal nR / B indicating a busy state (e.g., a low level) to the memory controller 200'. For example, when the memory device 100' is programming data DATA to the memory cell array 102 in response to a program command, the memory interface circuit 106 may send a ready / busy output signal nR / B indicating a busy state to the memory controller 200'.

[0108] The control logic circuit 101 may control all operations of the memory device 100'. The control logic circuit 101 may receive a command CMD / address ADDR obtained from the memory interface circuit 106. The control logic circuit 101 may generate a control signal for controlling other components of the memory device 100' in response to the received command CMD / address ADDR. For example, the control logic circuit 101 may generate various control signals for programming data DATA into the memory cell array 102 or reading data DATA from the memory cell array 102.

[0109] The memory cell array 102 may store the data DATA obtained from the memory interface circuit 106 via the control of the control logic circuit 101. The memory cell array 102 may output the stored data DATA to the memory interface circuit 106 via the control of the control logic circuit 101.

[0110] The memory cell array 102 may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. However, the present disclosure is not limited thereto, and the memory cells may be RRAM cells, FRAM cells, PRAM cells, thyristor RAM (TRAM) cells, or MRAM cells. Hereinafter, an embodiment in which the memory cells are NAND flash memory cells will be mainly described.

[0111] The memory controller 200' may include first to eighth pins P21 to P28 and a controller interface circuit 206. The first to eighth pins P21 to P28 may correspond to first to eighth pins P11 to P18 of the memory device 100', respectively.

[0112] The controller interface circuit 206 may send a chip enable signal nCE to the memory device 100' through the first pin P21. The controller interface circuit 206 may send and receive a signal selected by the chip enable signal nCE to the memory device 100' through the second pin P22 to the eighth pin P28.

[0113] The controller interface circuit 206 can send a command latch enable signal CLE, an address latch enable signal ALE and a write enable signal nWE to the memory device 100' through the second to fourth pins P22 to P24. The controller interface circuit 206 can send a data signal DQ to or receive a data signal DQ from the memory device 100' through the seventh pin P27.

[0114] The controller interface circuit 206 may transmit the data signal DQ including the command CMD or the address ADDR together with the switched write enable signal nWE to the memory device 100'. The controller interface circuit 206 may transmit the data signal DQ including the command CMD to the memory device 100' by transmitting the command latch enable signal CLE having an enable state. In addition, the controller interface circuit 206 may transmit the data signal DQ including the address ADDR to the memory device 100' by transmitting the address latch enable signal ALE having an enable state.

[0115] The controller interface circuit 206 may send a read enable signal nRE to the memory device 100' through the fifth pin P25. The controller interface circuit 206 may receive a data strobe signal DQS from the memory device 100' or send a data strobe signal DQS to the memory device 100' through the sixth pin P26.

[0116] In the data (DATA) output operation of the memory device 100', the controller interface circuit 206 may generate a switched read enable signal nRE and send the read enable signal nRE to the memory device 100'. For example, before outputting the data DATA, the controller interface circuit 206 may generate a read enable signal nRE that changes from a static state (e.g., a high level or a low level) to a switched state. Therefore, the memory device 100' may generate a switched data strobe signal DQS based on the read enable signal nRE. The controller interface circuit 206 may receive a data signal DQ including data DATA and a switched data strobe signal DQS from the memory device 100'. The controller interface circuit 206 may obtain data DATA from the data signal DQ based on the switching time point of the data strobe signal DQS.

[0117] In the data (DATA) input operation of the memory device 100', the controller interface circuit 206 may generate a switched data strobe signal DQS. For example, before sending the data DATA, the controller interface circuit 206 may generate a data strobe signal DQS that changes from a static state (e.g., a high level or a low level) to a switched state. The controller interface circuit 206 may send a data signal DQ including the data DATA to the memory device 100' based on the switching time point of the data strobe signal DQS.

[0118] The controller interface circuit 206 may receive the ready / busy output signal nR / B from the memory device 100' through the eighth pin P28. The controller interface circuit 206 may determine the status information of the memory device 100' based on the ready / busy output signal nR / B.

[0119] Despite Figure 7 Although not shown, the memory device 100 ′ may include a plurality of memory cell arrays, and the memory interface circuit 106 may provide hard decision data and soft decision data obtained from the plurality of memory cell arrays via a seventh pin P17 .

[0120] Fig. 8A and Figure 8B is an example diagram showing a read operation. Figure 2 right Fig. 8A and Figure 8B Give a description.

[0121] refer to Fig. 8A , the memory device 10 may receive a read command (S10). The read command may be a command requesting hard decision data and compressed data.

[0122] The memory device 10 can be read by using a hard read voltage (e.g., Fig. 6AThe hard decision data HD is read from the memory cell array 102 according to Vhread1 (S20). The read hard decision data HD may be stored in the page buffer circuit 103.

[0123] The memory device 10 can read the soft decision data SD from the memory cell array 102 and output the hard decision data HD through the memory interface circuit 106 (S30). Figure 8B After the hard decision data HD is read, the hard decision data HD may be output through the DQ pin. The time period for outputting the hard decision data HD may at least partially overlap with the time period for reading the soft decision data SD.

[0124] The memory device 10 may generate the compressed data COMP_SD by compressing the read soft decision data SD. In some embodiments, a time period for outputting the hard decision data HD may at least partially overlap with a time period for compressing the soft decision data SD.

[0125] After the output of the hard decision data HD is completed, the memory device 10 may output the compressed data COMP_SD through the DQ pin ( S50 ).

[0126] according to Fig. 8A and Figure 8B In the embodiment of the present invention, the time period for reading or compressing the soft decision data SD may partially overlap with the time period for outputting the hard decision data HD. Therefore, the time period for providing the compressed data COMP_SD and the hard decision data HD to the memory controller 200 in response to the read command may be shortened.

[0127] 9A to 9C is a diagram showing an example of a read operation.

[0128] refer to Fig. 9A , the memory device 300 may include a first memory cell array 311 and a second memory cell array 321, a first page buffer circuit 312 and a second page buffer circuit 322, a first compression circuit 313 and a second compression circuit 323, and a memory interface circuit 330. The memory device 300 may be received from a memory controller (e.g., Figure 1 200) receives a specific type of read command, can read hard decision data and soft decision data from at least one of the first memory cell array 311 and the second memory cell array 321, can compress the soft decision data, and can provide the hard decision data and the compressed soft decision data (i.e., compressed data) to the memory controller 200 (see Figure 1 ). In some implementations, a particular type of read command may be referred to as a fast read command.

[0129] Specifically, the first page buffer circuit 312 may obtain the first hard decision data HD1 and the first soft decision data SD1 from the first memory cell array 311. The first compression circuit 313 may generate the first compressed data COMP_SD1 by compressing the first soft decision data SD1. The first page buffer circuit 312 may provide the first hard decision data HD1 and the first compressed data COMP_SD1 to the memory interface circuit 330.

[0130] The second page buffer circuit 322 may obtain the second hard decision data HD2 and the second soft decision data SD2 from the second memory cell array 321. The second compression circuit 323 may generate the second compressed data COMP_SD2 by compressing the second soft decision data SD2. The second page buffer circuit 322 may provide the second hard decision data HD2 and the second compressed data COMP_SD2 to the memory interface circuit 330.

[0131] The memory interface circuit 330 may output the first and second hard decision data HD1 and HD2 and the first and second compressed data COMP_SD1 and COMP_SD2 through the first to eighth DQ pins DQ0 to DQ7 .

[0132] refer to Fig. 9B , the memory interface circuit 330 may sequentially output the first hard decision data HD1 and the second hard decision data HD2. In some embodiments, when the first hard decision data HD1 is output through the DQ pins (i.e., DQ0 to DQ7), the first compression circuit 313 may compress the first soft decision data SD1. That is, the time period for outputting the first hard decision data HD1 may at least partially overlap with the time period for compressing the first soft decision data SD1. Although not shown, in some embodiments, the time period for reading the first soft decision data SD1 from the first memory cell array 311 may at least partially overlap with the time period for outputting the first hard decision data HD1. Before being output through the DQ pins, the first compressed data COMP_SD1 may be stored in the first compression circuit 313, the first page buffer circuit 312, or a separately provided buffer.

[0133] In addition, when the second hard decision data HD2 is output through the DQ pins (i.e., DQ0 to DQ7), the second compression circuit 323 may compress the second soft decision data SD2. That is, the time period for outputting the second hard decision data HD2 may at least partially overlap with the time period for compressing the second soft decision data SD2. Although not shown, the time period for reading the second soft decision data SD2 from the second memory cell array 321 may at least partially overlap with the time period for outputting the second hard decision data HD2. Before being output through the DQ pins, the second compressed data COMP_SD2 may be stored in the second compression circuit 323, the second page buffer circuit 322, or a separately provided buffer.

[0134] After outputting the second hard decision data HD2, the memory interface circuit 330 may output the first compressed data COMP_SD1 and the second compressed data COMP_SD2 through the DQ pin. The order of outputting the first compressed data COMP_SD1 and the second compressed data COMP_SD2 is not limited thereto.

[0135] refer to Fig. 9C , when the memory interface circuit 330 outputs the second hard decision data HD2 through the DQ pins (i.e., DQ0 to DQ7), the first compression circuit 313 may compress the first soft decision data SD1. When the output of the second hard decision data HD2 is completed, the memory interface circuit 330 may output the first compressed data COMP_SD1 through the DQ pins (i.e., DQ0 to DQ7). When the output of the first compressed data COMP_SD1 is completed, the memory interface circuit 330 may output the first hard decision data HD1 through the DQ pins (i.e., DQ0 to DQ7). While the memory interface circuit 330 outputs the first hard decision data HD1 through the DQ pins (i.e., DQ0 to DQ7), the second compression circuit 323 may compress the second soft decision data SD2. When the output of the first hard decision data HD1 is completed, the memory interface circuit 330 may output the second compressed data COMP_SD2 through the DQ pins.

[0136] Since the compressed soft decision data is output through the DQ pins (ie, DQ0 to DQ7), the period of time for reading the hard decision data and the soft decision data can be shortened.

[0137] according to 9A to 9CIn the embodiment of the present invention, a time period for reading or compressing at least one of the first soft decision data SD1 and the second soft decision data SD2 may partially overlap with a time period for outputting at least one of the first hard decision data HD1 and the second hard decision data HD2. Therefore, a time period for providing the first compressed data COMP_SD1 and the second compressed data COMP_SD2 and the first hard decision data HD1 and the second hard decision data HD2 to the memory controller 200 in response to a read command may be shortened.

[0138] Fig. 10A and Fig. 10B is a diagram showing an example of a read operation.

[0139] refer to Fig. 10A Compared with the memory device 300 , the memory device 400 may further include third and fourth memory cell arrays 331 and 341 , third and fourth page buffer circuits 332 and 342 , and third and fourth compression circuits 333 and 343 .

[0140] The third page buffer circuit 332 may obtain the third hard decision data HD3 and the third soft decision data SD3 from the third memory cell array 331. The third compression circuit 333 may generate the third compressed data COMP_SD3 by compressing the third soft decision data SD3. The third page buffer circuit 332 may provide the third hard decision data HD3 and the third compressed data COMP_SD3 to the memory interface circuit 330.

[0141] The fourth page buffer circuit 342 may obtain the fourth hard decision data HD4 and the fourth soft decision data SD4 from the fourth memory cell array 341. The fourth compression circuit 343 may generate fourth compressed data COMP_SD4 by compressing the fourth soft decision data SD4. The fourth page buffer circuit 342 may provide the fourth hard decision data HD4 and the fourth compressed data COMP_SD4 to the memory interface circuit 330.

[0142] refer to Fig. 10B , while the memory interface circuit 330 outputs the third hard decision data HD3 and the fourth hard decision data HD4 through the DQ pins (ie, DQ0 to DQ7), the first compression circuit 313 and the second compression circuit 323 can compress the first soft decision data SD1 and the second soft decision data SD2, respectively.

[0143] When the output of the third hard decision data HD3 and the fourth hard decision data HD4 is completed, the memory interface circuit 330 may output the first compressed data COMP_SD1 and the second compressed data COMP_SD2 .

[0144] When the output of the first compressed data COMP_SD1 and the second compressed data COMP_SD2 is completed, the memory interface circuit 330 may output the first hard decision data HD1 and the second hard decision data HD2. While the memory interface circuit 330 outputs the first hard decision data HD1 and the second hard decision data HD2 through the DQ pins (i.e., DQ0 to DQ7), the third compression circuit 333 and the fourth compression circuit 343 may compress the third decision data SD3 and the fourth decision data SD4, respectively.

[0145] When the output of the first hard decision data HD1 and the second hard decision data HD2 is completed, the memory interface circuit 330 may output the third compressed data COMP_SD3 and the fourth compressed data COMP_SD4.

[0146] In some embodiments, a time period for reading or compressing at least one of the first to fourth soft decision data SD1 to SD4 may partially overlap with a time period for outputting at least one of the first to fourth hard decision data HD1 to HD4. Therefore, a time period for providing the first to fourth compressed data COMP_SD1 to COMP_SD4 and the first to fourth hard decision data HD1 to HD4 to the memory controller 200 in response to a read command may be shortened.

[0147] Fig.11 is a flowchart showing an example of a method of operating a memory device. Fig. 9A right Fig.11 Give a description.

[0148] refer to Fig.11 , the first page buffer circuit 312 may read the first hard decision data HD1 from the first memory cell array 311 ( S100 ).

[0149] While the memory interface circuit 330 outputs the first hard decision data HD1 through the DQ pins (i.e., DQ0 to DQ7), the second compression circuit 323 may generate the second compressed data COMP_SD2 (S200) by compressing the second soft decision data SD2 obtained from the second memory cell array 321. When compressing the second soft decision data SD2, the second compression circuit 323 may use the following reference Figures 13 to 16C Describes the compression method.

[0150] After the output of the first hard decision data HD1 is completed, the memory interface circuit 330 may output the second compressed data COMP_SD2 through the DQ pins (ie, DQ0 to DQ7 ) ( S300 ).

[0151] The second page buffer circuit 322 may read the second hard decision data HD2 from the second memory cell array 321 (S400). In some implementations, operation S400 may be performed in parallel with operation S300.

[0152] While the memory interface circuit 330 outputs the second hard decision data HD2 through the DQ pins (i.e., DQ0 to DQ7), the first compression circuit 313 may generate the first compressed data COMP_SD1 (S500) by compressing the first soft decision data SD1 obtained from the first memory cell array 311. When compressing the first soft decision data SD1, the first compression circuit 313 may use the following reference Figures 13 to 16C Describes the compression method.

[0153] After the output of the second hard decision data HD2 is completed, the memory interface circuit 330 may output the first compressed data COMP_SD1 through the DQ pins (ie, DQ0 to DQ7 ) ( S600 ).

[0154] Fig.12 is a flowchart illustrating an example of a method of operating a memory controller. Figure 1 , Figure 3 or Fig. 9A right Fig.12 Give a description.

[0155] The memory controller 200 may receive first and second hard decision data HD1 and HD2 and first and second compression data COMP_SD1 and COMP_SD2 from the memory device 3000 through the DQ pins ( S110 ).

[0156] The ECC decoder 212 of the memory controller 200 may decompress the first compressed data COMP_SD1 and the second compressed data COMP_SD2 (S120). When decompressing the first compressed data COMP_SD1 and the second compressed data COMP_SD2, the ECC decoder 212 may use the following reference Fig. 20 Describes the decompression method.

[0157] The ECC decoder 212 may perform error correction on the first hard decision data HD1 based on the first hard decision data HD1 and the first soft decision data SD1 ( S130 ).

[0158] The ECC decoder 212 may perform error correction on the second hard decision data HD2 based on the second hard decision data HD2 and the second soft decision data SD2 ( S140 ).

[0159] Fig.13 is a diagram showing an example of a method for compressing soft decision data. Figure 1 and Figure 2 right Fig.13 Give a description.

[0160] refer to Fig.13 , the size of the soft decision data SD may be M bytes, and the soft decision data SD may be divided into a plurality of soft decision segments SD_SG1 to SD_SGn. Here, M may be 16K. The size of each of the plurality of soft decision segments SD_SG1 to SD_SGn may be K bytes less than M bytes. For example, K may be a multiple of 16. The plurality of soft decision segments SD_SG1 to SD_SGn may each be divided into a plurality of soft decision sub-segments SD_SG_SUB1 to SD_SG_SUBa. The size of each of the plurality of soft decision sub-segments SD_SG_SUB1 to SD_SG_SUBa may be A bits less than K bytes. For example, A may be 128.

[0161] The size of the compressed data COMP_SD may be N bytes less than M bytes, and the compressed data COMP_SD may be divided into a plurality of compressed segments COMP_SD_SG1 to COMP_SD_SGn. The size of each of the plurality of compressed segments COMP_SD_SG1 to COMP_SD_SGn may be L bytes less than K bytes. Regardless of the degree of compression, N and L may be fixed values. Regardless of the number of bits indicating a secondary value (e.g., "1") in the soft decision data SD, N and L may be fixed values. The plurality of compressed segments COMP_SD_SG1 to COMP_SD_SGn may be divided into a plurality of compressed sub-segments COMP_SD_SG_SUB1 to COMP_SD_SG_SUBa. The plurality of soft decision sub-segments SD_SG_SUB1 to SD_SG_SUBa may be compressed into a plurality of compressed sub-segments COMP_SD_SG_SUB1 to COMP_SD_SG_SUBa, respectively. The size of each of the plurality of compressed sub-segments COMP_SD_SG_SUB1 to COMP_SD_SG_SUBa may be B bits which is less than L bytes. For example, B may be 32.

[0162] Herein, although it is described that the soft decision sub-segments (ie, SD_SG_SUB1 to SD_SG_SUBa) having 128 bits are compressed into compressed sub-segments (ie, COMP_SD_SG_SUB1 to COMP_SD_SG_SUBa) having 32 bits, embodiments of the present disclosure are not limited thereto.

[0163] The compression circuit 107 may generate a plurality of compressed segments COMP_SD_SG1 to COMP_SD_SGn by respectively compressing a plurality of soft decision segments SD_SG1 to SD_SGn. Specifically, the compression circuit 107 may read one of the plurality of soft decision segments SD_SG1 to SD_SGn, and may generate a plurality of compressed sub-segments COMP_SD_SG_SUB1 to COMP_SD_SG_SUBa by encoding the positions of bits indicating secondary values ​​in the plurality of soft decision sub-segments SD_SG_SUB1 to SD_SG_SUBa included in the read soft decision segment. FIG. 14A to FIG. 16C Describe in detail the compression method of the soft decision sub-segment.

[0164] FIG. 14A to FIG. 14C is a diagram showing an example of a compression method for soft decision sub-segments. Figure 1 , Figure 2 and Fig.13 right FIG. 14A to FIG. 14C Give a description.

[0165] refer to Fig.14A , the compression circuit 107 can compress the 128-bit soft decision sub-segment SD_SG_SUB1 into a 32-bit compressed sub-segment COMP_SD_SG_SUB1. The description of the soft decision sub-segment SD_SG_SUB1 can also be applied to the other soft decision sub-segments SD_SG_SUB2 to SD_SG_SUBa. The description of the compressed sub-segment COMP_SD_SG_SUB1 can also be applied to the other compressed sub-segments COMP_SD_SG_SUB2 to COMP_SD_SG_SUBa.

[0166] The compression circuit 107 may generate the compressed sub-segment COMP_SD_SG_SUB1 by encoding the position of “1” in the soft decision sub-segment SD_SG_SUB1.

[0167] exist Fig.14A In the soft decision sub-segment SD_SG_SUB1, the soft decision sub-segment SD_SG_SUB1 may include three "1s". The position of each "1" may be encoded using 8 bits. The encoded 8-bit position value may be included in the compressed sub-segment COMP_SD_SSG_SUB1. Fig.14A , the first to third groups of 8 bits in the compressed sub-segment COMP_SD_SG_SUB1 may respectively correspond to the position values ​​of three “1”s in the soft decision sub-segment SD_SG_SUB1.

[0168] The compression circuit 107 may fix the size of the compressed sub-segment COMP_SD_SG_SUB1 to 32 bits by including a fourth group of 8 bits having a dummy value in the compressed sub-segment COMP_SD_SG_SUB1. The dummy value may be 0xFF. Therefore, all 8 bits indicating the dummy value may be "1". However, embodiments of the present disclosure are not limited thereto, and the dummy value may have a value different from the position value of any "1" in the soft decision sub-segment SD_SG_SUB1.

[0169] That is, when the number of "1"s in the compressed subsegment COMP_SD_SG_SUB1 is less than a reference number (e.g., 4), the compression circuit 107 may perform fixed-size compression by including a number of virtual values ​​corresponding to the difference between the reference number and the number of position values ​​of "1"s in the compressed subsegment COMP_SD_SG_SUB1.

[0170] The compressed sub-segment COMP_SD_SG_SUB1 may be transmitted to the memory interface circuit 330 directly or through the page buffer circuit 103. The memory interface circuit 330 may provide the compressed sub-segment COMP_SD_SG_SUB1 to the memory controller 200 through the DQ pins (ie, DQ0 to DQ7).

[0171] exist Fig. 14B In the example, the soft decision sub-segment SD_SG_SUB1 may include four "1s". The compression circuit 107 may encode the position of each "1" by using 8 bits. The encoded 8-bit position value may be included in the compressed sub-segment COMP_SD_SG_SUB1. Fig. 14B , the first to fourth groups of 8 bits in the compressed sub-segment COMP_SD_SG_SUB1 may correspond to the four position values ​​of "1" in the soft decision sub-segment SD_SG_SUB1. That is, because the number of position values ​​of "1" in the compressed sub-segment COMP_SD_SG_SUB1 is equal to the reference number (e.g., 4), the compression circuit 107 can generate a compressed sub-segment COMP_SD_SG_SUB1 having 32 bits by representing each of the four position values ​​of "1" in the compressed sub-segment COMP_SD_SG_SUB1 with 8 bits.

[0172] exist Fig. 14CIn the compressed sub-segment COMP_SD_SG_SUB1, the soft decision sub-segment SD_SG_SUB1 may include five "1s". Only the position values ​​of four "1s" among the "1s" in the soft decision sub-segment SD_SG_SUB1 are included. That is, the position value of the "1" located at the far right may be lost. The embodiments of the present disclosure are not limited to this, and the position value of any "1" among the five "1s" may not be included in the compressed sub-segment COMP_SD_SG_SUB1. In some embodiments, the position value to be lost may be selected based on the amplitude of the position value of "1". For example, the position value with the smallest amplitude or the largest amplitude may be selected as the position value to be lost.

[0173] In some embodiments, depending on the compression method, even when the number of "1" included in the soft decision sub-segment SD_SG_SUB1 is equal to or less than the reference number, some position values ​​of "1" may not be included in the compressed sub-segment COMP_SD_SG_SUB1. That is, even when the number of "1" included in the soft decision sub-segment SD_SG_SUB1 is equal to or less than the reference number, some position values ​​may be lost.

[0174] Fig.15 is a diagram showing an example of a location mapping table. Figure 2 right Fig.15 Give a description.

[0175] The compression circuit 107 may compress the soft decision segment SD_SG into the compressed segment COM_SD_SG with reference to the position mapping table. Specifically, the compression circuit 107 may encode the "1" in the soft decision segment SD_SG into position values ​​with reference to the position mapping table.

[0176] The length of the soft decision segment SD_SG may be 128 bits. 8 bits sequentially output to the first to eighth DQ pins DQ0 to DQ7 may constitute 1 byte.

[0177] refer to Fig.15 , when the value of the last bit in the soft decision segment SD_SG is "1", the position value of the "1" can be 0x7F, that is, 0111 1111. Therefore, the position of 128 bits can be encoded by using 7 bits as an index. In some embodiments, the compression circuit 107 can use a value different from the position value listed in the position mapping table as a virtual value. For example, the compression circuit 107 can generate compressed data with a fixed size by using 0xFF (i.e., 1111 111) as a virtual value. However, the embodiments of the present disclosure are not limited to this, and any value from 0xF0 to 0xFF can be used as a virtual value.

[0178] FIG. 16A to FIG. 16C is a diagram showing an example of a compression method of a soft decision segment.

[0179] refer to Fig.16A , the soft decision sub-segment SD_SG_SUB may have 128 bits and may include three "1s". The compression circuit 107 may be based on Fig.15 The position mapping table generates the compressed sub-segment COMP_SD_SG_SUB. Because there are three position values ​​for "1" and each position value is represented by 8 bits, these three position values ​​can be represented by 24 bits.

[0180] The compression circuit 107 may generate a compressed sub-segment COMP_SD_SG_SUB having a fixed size (ie, 32 bits) by including three position values ​​and an 8-bit dummy value in the compressed sub-segment COMP_SD_SG_SUB.

[0181] refer to Fig. 16B , the soft decision sub-segment SD_SG_SUB may include four "1s". Since there are four position values ​​for "1", and each position value is represented by 8 bits, these four position values ​​can be represented by 32 bits.

[0182] Therefore, the compression circuit 107 may generate a compressed sub-segment COMP_SD_SG_SUB having a fixed size (ie, 32 bits) by including only four position values ​​in the compressed sub-segment COMP_SD_SG_SUB.

[0183] refer to Fig. 16C , the soft decision sub-segment SD_SG_SUB may include five "1s". Since there are five position values ​​for "1", and each position value is represented by 8 bits, these five position values ​​can be represented by 40 bits.

[0184] The compression circuit 107 may generate a compressed sub-segment COMP_SD_SG_SUB having a fixed size (i.e., 32 bits) by including only the position values ​​of four "1"s among the five "1"s in the compressed sub-segment COMP_SD_SG_SUB. Although the position value of the last "1" is lost by excluding the position value of the last "1" from the compressed sub-segment COMP_SD_SG_SUB, the compressed sub-segment COMP_SD_SG_SUB may be generated by the compression circuit 107. Fig. 16C The last "1" in , but the embodiments of the present disclosure are not limited thereto, and any one of the five "1"s may be lost. In some embodiments, the position value to be lost may be selected based on the size of the position value. For example, referring to Fig. 16C In the implementation method where the maximum position value is lost, the maximum position value 0x7F among the position values ​​of "1" may be lost. Alternatively, in the implementation method where the minimum position value is lost, the minimum position value 0x3F among the position values ​​of "1" may be lost.

[0185] Fig.17is a diagram illustrating an example of a method of operating a memory system.

[0186] The memory controller 200 may provide a read command to the memory device 100 (S1601). The read command may be a command requesting hard decision data HD and compressed data COMP_SD corresponding to soft decision data SD.

[0187] The memory device 100 may read hard decision data HD from the memory cell array by using a hard read voltage ( S1602 ).

[0188] The memory device 100 may read soft decision data SD from the memory cell array based on the first voltage offset OFFSET1 (S1603). Specifically, the memory device 100 may obtain the soft decision data SD by using a soft read voltage obtained by adding the first voltage offset OFFSET1 to the hard read voltage and a soft read voltage obtained by subtracting the first voltage offset OFFSET1 from the hard read voltage.

[0189] The memory device 100 may compress the soft decision data SD (S1604). The memory device 100 may use the above reference Figures 13 to 16C Describes the compression method.

[0190] The memory device 100 may provide the hard decision data HD and the compression data COMP_SD to the memory controller 200 ( S1605 ).

[0191] The memory controller 200 may estimate the compression quality of the compressed data COMP_SD ( S1606 ).

[0192] In some embodiments, the memory controller 200 may count the number of compressed sub-segments in the plurality of compressed sub-segments included in the compressed data COMP_SD, wherein the number of position values ​​is equal to or greater than a first reference number. When the counted number is equal to or greater than a second reference value, the memory controller 200 may determine that the compression quality is poor, and when the counted number is less than the second reference value, the memory controller 200 may determine that the compression quality is good.

[0193] In some embodiments, the memory controller 200 may calculate a weighted sum based on the number of position values ​​included in the plurality of compressed sub-segments and the weights. When the weighted sum is equal to or greater than a third reference value, the memory controller 200 may determine that the compression quality is poor, and when the weighted sum is less than the third reference value, the memory controller 200 may determine that the compression quality is good.

[0194] When it is determined that the compression quality is poor, the memory controller 200 may provide a command requesting a change of the voltage offset to the memory device 100 (S1607). The command may include information for requesting compressed data with the changed voltage offset.

[0195] Although not shown, when it is determined that the compression quality is good, the memory controller 200 may obtain soft decision data SD by performing decompression on the compressed data COMP_SD, and may perform error correction on the hard decision data HD based on the soft decision data SD.

[0196] The memory device 100 may change the voltage offset to a second voltage offset OFFSET2, and may read the soft decision data SD' based on the second voltage offset OFFSET2 (S1608). The second voltage offset OFFSET2 may be smaller than the first voltage offset OFFSET1. The number of "1" in the soft decision data SD' may be less than the number of "1" in the soft decision data SD.

[0197] The memory device 100 may compress the soft decision data SD' (S1609). The memory device 100 may use the above reference Figures 13 to 16C Describes the compression method.

[0198] The memory device 100 may provide the compressed data COMP_SD′ to the memory controller 200 ( S1610 ).

[0199] The memory controller 200 may estimate the compression quality of the compressed data COMP_SD' (S1610). The description regarding operation S1606 may be applied to operation S1610.

[0200] When it is determined that the compression quality is good, the memory controller 200 may obtain soft decision data SD′ by performing decompression on the compressed data COMP_SD′ ( S1611 ).

[0201] Although not shown, when it is determined that the compression quality is poor, the memory controller 200 may again provide a command requesting a change in voltage offset to the memory device 100. That is, the operation of the memory controller 200 providing a command requesting a change in voltage offset to the memory device 100 based on the quality of compressed data and receiving new compressed data from the memory device 100 may be repeated.

[0202] When the voltage offset approaches 0, the level difference between the soft read voltage and the hard read voltage may be very small. When the soft read voltage and the hard read voltage are substantially equal to each other, because the overlapping area that the soft decision data can indicate is very small, the soft decision data may be difficult to indicate the reliability of the hard decision data. Therefore, in some embodiments, when the number of changes in the voltage offset is equal to or greater than the reference number of times, the memory controller 200 can obtain the soft decision data by performing a decompression operation on the most recently received compressed data without providing a command requesting a change in the voltage offset to the memory device 100, and can perform error correction on the hard decision data based on the soft decision data.

[0203] The memory controller 200 may perform error correction on the hard decision data HD based on the soft decision data SD′ ( S1612 ).

[0204] Fig.18 is a block diagram of an example of a memory controller.

[0205] refer to Fig.18 , the memory controller 200 may include an ECC encoder 211 and an ECC decoder 212. The ECC encoder 211 may generate a codeword CW based on the normal data NM_DATA received from the host 2. Specifically, the ECC encoder 211 may generate parity bits for the normal data NM_DATA based on a parity generation matrix, and may generate a codeword CW including the normal data NM_DATA and the parity bits. The codeword CW may be programmed into a memory cell array in the memory device 100.

[0206] The memory device 100 may read the hard decision data HD and the soft decision data SD from the region where the codeword CW is stored, and may generate the compressed data COMP_SD by compressing the soft decision data SD.

[0207] The ECC decoder 212 may include a compression quality estimator 220 , a decompressor 270 , and an ECC core 280 .

[0208] The compression quality estimator 220 may estimate the compression quality of the compressed data COMP_SD. Specifically, the compression quality estimator 220 may estimate the degree of loss of position values ​​in the compressed data COMP_SD. For example, the compression quality estimator 220 may count the number of compressed sub-segments in which the number of position values ​​is equal to or greater than a first reference number among a plurality of compressed sub-segments in the compressed data COMP_SD, and may determine that the compression quality is poor when the counted number is equal to or greater than a second reference value, and may determine that the compression quality is good when the counted number is less than the second reference value.

[0209] When it is determined that the compression quality of the compressed data COMP_SD is good, the compression quality estimator 220 may provide the compressed data COMP_SD to the decompressor 270. The decompressor 270 may Fig. 20 The decompression method performs a decompression operation on the compressed data COMP_SD.

[0210] The ECC core 280 may calculate LLRs based on the soft decision data SD and may perform error correction on the hard decision data HD by using the LLRs. In some embodiments, the ECC core 280 may perform error correction on the hard decision data HD based on the parity check matrix and the hard decision data HD without using the soft decision data SD.

[0211] The ECC core 280 may generate normal data NM_DATA′ by performing error correction on the hard decision data HD. The normal data NM_DATA′ may be provided to the host 2 .

[0212] In some embodiments, when it is determined that the compression quality of the compressed data COMP_SD is poor, the compression quality estimator 220 may output a voltage offset change signal OFFSET CHANGE SIGNAL. The memory controller 200 may provide a command CMD requesting a change in voltage offset based on the voltage offset change signal OFFSET CHANGE SIGNAL. The memory device 100 may read the soft decision data again based on the changed voltage offset, and may provide compressed data of the read soft decision data to the memory controller 200.

[0213] In some embodiments, when the number of changes in the voltage offset is equal to or greater than a reference number of times, the compression quality estimator 220 may provide the compressed data COMP_SD to the decompressor 270 without providing the command CMD to the memory device 100 .

[0214] Fig.19 is a diagram illustrating an example of a method of operating a compression quality estimator.

[0215] refer to Fig.19 , the compression quality estimator 220 may count the number of compressed subsegments whose number of position values ​​(ie, locval) is equal to or greater than a first reference number (ie, ref1) among a plurality of compressed subsegments COMP_SD_SG_SUB1 to COMP_SD_SG_SUBn included in the compressed data COMP_SD.

[0216] When the count number is equal to or greater than the second reference value, the compression quality estimator 220 may determine that the compression quality is poor, and when the count number is less than the second reference value, the compression quality estimator 220 may determine that the compression quality is good.

[0217] Fig. 20 is a diagram showing an example of a decompression method.

[0218] refer to Fig. 20 , the decompressor circuit 270 may receive the compressed data COMP_SD from the compression quality estimator 220 .

[0219] The compressed data COMP_SD may include a plurality of compressed sub-segments, including a compressed sub-segment COMP_SD_SG_SUB1. The compressed sub-segment COMP_SD_SG_SUB1 may include a plurality of position values. Fig. 20 , the compressed sub-segment COMP_SD_SG_SUB1 may include a first position value Locval1 to a fourth position value Locval4. In some embodiments, the compressed sub-segment COMP_SD_SG_SUB1 may include at least one virtual value.

[0220] The decompressor circuit 270 may include a plurality of conversion circuits cLUT and an OR gate. The plurality of conversion circuits cLUT may receive a first position value Locval1 to a fourth position value Locval4, respectively. The conversion circuit cLUT may convert the bit indicated by the received position value among the bits corresponding to the size of the soft decision sub-segment (e.g., 128 bits) to "1", and convert the remaining bits to "0", thereby generating a partial soft decision sub-segment. Because the first position value Locval1 to the fourth position value Locval4 are different from each other, the plurality of conversion circuits cLUT may output a 128-bit partial soft decision sub-segment, respectively, in which the bits at different positions are respectively converted to "1".

[0221] The OR gate may receive partial soft decision sub-segments from a plurality of conversion circuits cLUT, and may generate a soft decision sub-segment SD_SG_SUB1' by performing an OR operation on the received partial soft decision sub-segments. The size of the soft decision sub-segment SD_SG_SUB1' may be 128 bits. Among the 128 bits in the soft decision sub-segment SD_SG_SUB1', the bits indicated by the first position value Locval1 to the fourth position value Locval4, respectively, may all be "1", and the remaining bits may all be "0".

[0222] In some embodiments, Fig.18 The conversion circuit cLUT and the OR gate shown in can perform decompression operations on different compressed sub-segments from the compressed sub-segment COMP_SD_SG_SUB1.

[0223] In some embodiments, although not shown, the decompressor 270 may further include a conversion circuit cLUT and an OR gate that perform a decompression operation on a compressed sub-segment different from the compressed sub-segment COMP_SD_SG_SUB1.

[0224] exist Fig. 20 , although decompression of the compressed sub-segment COMP_SD_SG_SUB1 is described for convenience of description, the decompressor 270 may obtain the decompressed soft decision data SD by performing decompression on all compressed sub-segments included in the compressed data COMP_SD.

[0225] Fig.21A and Fig. 21B is a diagram showing an example of LLR adjustment.

[0226] refer to Fig.18 and Fig.21A , the ECC core 280 may calculate the LLR value based on the LLR mapping table. Specifically, the hard decision data HD may determine the sign of the LLR value, and the soft decision data SD may determine the absolute value of the LLR value. For example, the sign of the LLR value corresponding to "1" in the hard decision data HD may be -, and the sign of the LLR value corresponding to "0" in the hard decision data HD may be +. The absolute value of the LLR value corresponding to "1" in the soft decision data SD may be 1, and the absolute value of the LLR value corresponding to "0" in the soft decision data SD may be 3. However, embodiments of the present disclosure are not limited thereto.

[0227] The ECC core 280 may calculate an LLR value, and may perform error correction on the hard decision data HD based on the calculated LLR value.

[0228] refer to Fig. 21B After the soft decision data SD is compressed into the compressed data COMP_SD, some "1"s may be lost when the compressed data COMP_SD is decompressed into the soft decision data SD'. Therefore, an error bit may be included in the soft decision data SD'. Since the ECC core 280 performs LLR mapping based on the soft decision data SD', an error may occur in the LLR mapping.

[0229] Therefore, when the compression quality is poor, the ECC core 280 may perform LLR adjustment. Specifically, the ECC core 280 may change some "0"s in the soft decision data SD' to "1", respectively, and may perform LLR mapping based on the changed bits.

[0230] exist Fig. 21B In the example of , although the LLR value is -3 when the soft decision data SD' is 0 and the hard decision data HD is 1, the ECC core 280 may change the LLR value to -1 through LLR adjustment.

[0231] Fig. 22 is a diagram showing an example of a memory device 500 .

[0232] refer to Fig. 22 , the memory device 500 may have a chip-to-chip (C2C) structure. At least one upper chip including a cell area and a lower chip including a peripheral circuit area PERI may be manufactured separately, and then, at least one upper chip and a lower chip may be connected to each other by a bonding method to realize a C2C structure. For example, a bonding method may mean a method of electrically or physically connecting a bonding metal pattern formed in the uppermost metal layer of an upper chip to a bonding metal pattern formed in the uppermost metal layer of a lower chip. For example, in the case where the bonding metal pattern is formed by copper (Cu), the bonding method may be a Cu-Cu bonding method. Alternatively, the bonding metal pattern may be formed by aluminum (al) or tungsten (W).

[0233] The memory device 500 may include at least one upper chip having a cell region. Fig. 22 As shown, the memory device 500 may include two upper chips. However, the number of upper chips is not limited thereto. In the case where the memory device 500 includes two upper chips, a first upper chip including a first cell area CELL1, a second upper chip including a second cell area CELL2, and a lower chip including a peripheral circuit area PERI may be manufactured separately, and then, the first upper chip, the second upper chip, and the lower chip may be connected to each other by a bonding method to manufacture the memory device 500. The first upper chip may be flipped over and then connected to the lower chip by a bonding method, and the second upper chip may also be flipped over and then connected to the first upper chip by a bonding method. Hereinafter, the upper and lower parts of each of the first upper chip and the second upper chip will be defined based on before each of the first upper chip and the second upper chip is flipped over. In other words, in Fig. 22 In the embodiment, the upper portion of the lower chip may refer to the upper portion defined based on the +Z axis direction, and the upper portion of each of the first upper chip and the second upper chip may refer to the upper portion defined based on the -Z axis direction. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, one of the first upper chip and the second upper chip may be flipped and then connected to the corresponding chip by a bonding method.

[0234] The peripheral circuit region PERI and the first and second cell regions CELL1 and CELL2 of the memory device 500 may each include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.

[0235] The peripheral circuit region PERI may include a first substrate 610 and a plurality of circuit elements 620a, 620b, and 620c formed on the first substrate 610. An interlayer insulating layer 615 including one or more insulating layers may be provided on the plurality of circuit elements 620a, 620b, and 620c, and a plurality of metal lines electrically connected to the plurality of circuit elements 620a, 620b, and 620c may be provided in the interlayer insulating layer 615. For example, the plurality of metal lines may include first metal lines 630a, 630b, and 630c connected to the plurality of circuit elements 620a, 620b, and 620c and second metal lines 640a, 640b, and 640c formed on the first metal lines 630a, 630b, and 630c. The plurality of metal lines may be formed of at least one of various conductive materials. For example, the first metal lines 630a, 630b, and 630c may be formed of tungsten having a relatively high resistivity, and the second metal lines 640a, 640b, and 640c may be formed of copper having a relatively low resistivity.

[0236] In the present embodiment, the first metal lines 630a, 630b and 630c and the second metal lines 640a, 640b and 640c are shown and described. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, at least one or more additional metal lines may be further formed on the second metal lines 640a, 640b and 640c. In this case, the second metal lines 640a, 640b and 640c may be formed of aluminum, and at least some of the additional metal lines formed on the second metal lines 640a, 640b and 640c may be formed of copper having a resistivity lower than the resistivity of the aluminum of the second metal lines 640a, 640b and 640c.

[0237] The interlayer insulating layer 615 may be disposed on the first substrate 610 and may include an insulating material such as silicon oxide and / or silicon nitride.

[0238] Each of the first cell region CELL1 and the second cell region CELL2 may include at least one memory block. The first cell region CELL1 may include a second substrate 710 and a common source line 720. A plurality of word lines 730 (731 to 738) may be stacked on the second substrate 710 in a direction perpendicular to the top surface of the second substrate 710 (i.e., the Z-axis direction). A string selection line and a ground selection line may be provided on and below the word line 730, and a plurality of word lines 730 may be provided between the string selection line and the ground selection line. Similarly, the second cell region CELL2 may include a third substrate 810 and a common source line 820, and a plurality of word lines 830 (831 to 838) may be stacked on the third substrate 810 in a direction perpendicular to the top surface of the third substrate 810 (i.e., the Z-axis direction). The second substrate 710 and the third substrate 810 may each be formed of at least one of various materials, and may be, for example, a silicon substrate, a silicon germanium substrate, a germanium substrate, or a substrate having a single crystal epitaxial layer grown on a single crystal silicon substrate. A plurality of channel structures CH may be formed in each of the first cell region CELL1 and the second cell region CELL2 .

[0239] In some embodiments, as shown in region "A1", the channel structure CH may be disposed in the bit line bonding region BLBA and may extend in a direction perpendicular to the top surface of the second substrate 710 to penetrate the word line 730, the string selection line, and the ground selection line. The channel structure CH may include a data storage layer, a channel layer, and a filling insulating layer. The channel layer may be electrically connected to the first metal line 750c and the second metal line 760c in the bit line bonding region BLBA. For example, the second metal line 760c may be a bit line and may be connected to the channel structure CH through the first metal line 750c. The bit line 760c may extend in a first direction (e.g., a Y-axis direction) parallel to the top surface of the second substrate 710.

[0240] In some embodiments, as shown in region "A2", the channel structure CH may include a lower channel LCH and an upper channel UCH connected to each other. For example, the channel structure CH may be formed by a process of forming the lower channel LCH and a process of forming the upper channel UCH. The lower channel LCH may extend in a direction perpendicular to the top surface of the second substrate 710 to penetrate the common source line 720 and the lower word lines 731 and 732. The lower channel LCH may include a data storage layer, a channel layer, and a filling insulating layer, and may be connected to the upper channel UCH. The upper channel UCH may penetrate the upper word lines 733 to 738. The upper channel UCH may include a data storage layer, a channel layer, and a filling insulating layer, and the channel layer of the upper channel UCH may be electrically connected to the first metal line 750c and the second metal line 760c. As the channel length increases, it may be difficult to form a channel with substantially uniform width due to the characteristics of the manufacturing process. The memory device 500 according to the present embodiment may include a channel having improved width uniformity due to a lower channel LCH and an upper channel UCH formed through sequentially performed processes.

[0241] As shown in area "A2", in the case where the channel structure CH includes a lower channel LCH and an upper channel UCH, a word line located near the boundary between the lower channel LCH and the upper channel UCH may be a dummy word line. For example, word lines 732 and 733 adjacent to the boundary between the lower channel LCH and the upper channel UCH may be dummy word lines. In this case, data may not be stored in the memory cells connected to the dummy word lines. Alternatively, the number of pages corresponding to the memory cells connected to the dummy word lines may be less than the number of pages corresponding to the memory cells connected to the universal word lines. The level of the voltage applied to the dummy word line may be different from the level of the voltage applied to the universal word line, so that the effect of the inconsistent channel width between the lower channel LCH and the upper channel UCH on the operation of the memory device can be reduced.

[0242] At the same time, in the region "A2", the number of lower word lines 731 and 732 penetrated by the lower channel LCH is less than the number of upper word lines 733 to 738 penetrated by the upper channel UCH. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, the number of lower word lines penetrated by the lower channel LCH may be equal to or greater than the number of upper word lines penetrated by the upper channel UCH. In addition, the structural features and connection relationships of the channel structure CH disposed in the second cell region CELL2 may be substantially the same as the structural features and connection relationships of the channel structure CH disposed in the first cell region CELL1.

[0243] In the bit line bonding area BLBA, the first through electrode THV1 may be disposed in the first cell area CELL1, and the second through electrode THV2 may be disposed in the second cell area CELL2. Fig. 22As shown, the first through electrode THV1 may penetrate the common source line 720 and the plurality of word lines 730. In some embodiments, the first through electrode THV1 may further penetrate the second substrate 710. The first through electrode THV1 may include a conductive material. Alternatively, the first through electrode THV1 may include a conductive material surrounded by an insulating material. The second through electrode THV2 may have the same shape and structure as the first through electrode THV1.

[0244] In some embodiments, the first through electrode THV1 and the second through electrode THV2 may be electrically connected to each other through the first through metal pattern 772d and the second through metal pattern 872d. The first through metal pattern 772d may be formed at the bottom end of the first upper chip including the first cell region CELL1, and the second through metal pattern 872d may be formed at the top end of the second upper chip including the second cell region CELL2. The first through electrode THV1 may be electrically connected to the first metal line 750c and the second metal line 760c. A lower via 771d may be formed between the first through electrode THV1 and the first through metal pattern 772d, and an upper via 871d may be formed between the second through electrode THV2 and the second through metal pattern 872d. The first through metal pattern 772d and the second through metal pattern 872d may be connected to each other by a bonding method.

[0245] In addition, in the bit line bonding area BLBA, an upper metal pattern 652 may be formed in the uppermost metal layer of the peripheral circuit area PERI, and an upper metal pattern 792 having the same shape as the upper metal pattern 652 may be formed in the uppermost metal layer of the first cell area CELL1. The upper metal pattern 792 of the first cell area CELL1 and the upper metal pattern 652 of the peripheral circuit area PERI may be electrically connected to each other by a bonding method. In the bit line bonding area BLBA, the bit line 760c may be electrically connected to a page buffer included in the peripheral circuit area PERI. For example, some circuit elements 620c of the peripheral circuit area PERI may constitute a page buffer, and the bit line 760c may be electrically connected to the circuit element 620c constituting the page buffer through the upper bonding metal pattern 770c of the first cell area CELL1 and the upper bonding metal pattern 670c of the peripheral circuit area PERI.

[0246] Continue to refer Fig. 22In the word line bonding area WLBA, the word line 730 of the first cell area CELL1 may extend in a second direction (e.g., an X-axis direction) parallel to the top surface of the second substrate 710, and may be connected to a plurality of cell contact plugs 740 (741 to 747). The first metal line 750b and the second metal line 760b may be sequentially connected to the cell contact plugs 740 connected to the word line 730. In the word line bonding area WLBA, the cell contact plugs 740 may be connected to the peripheral circuit area PERI through the upper bonding metal pattern 770b of the first cell area CELL1 and the upper bonding metal pattern 670b of the peripheral circuit area PERI.

[0247] The cell contact plug 740 may be electrically connected to a row decoder included in the peripheral circuit region PERI. For example, some circuit elements 620b of the peripheral circuit region PERI may constitute a row decoder, and the cell contact plug 740 may be electrically connected to the circuit element 620b constituting the row decoder through the upper bonding metal pattern 770b of the first cell region CELL1 and the upper bonding metal pattern 670b of the peripheral circuit region PERI. In some embodiments, the operating voltage of the circuit element 620b constituting the row decoder may be different from the operating voltage of the circuit element 620c constituting the page buffer. For example, the operating voltage of the circuit element 620c constituting the page buffer may be greater than the operating voltage of the circuit element 620b constituting the row decoder.

[0248] Likewise, in the word line bonding area WLBA, the word lines 830 of the second cell area CELL2 may extend in a second direction (e.g., X-axis direction) parallel to the top surface of the third substrate 810, and may be connected to a plurality of cell contact plugs 840 (841 to 847). The cell contact plugs 840 may be connected to the peripheral circuit area PERI through the upper metal pattern of the second cell area CELL2 and the lower and upper metal patterns of the first cell area CELL1 and the cell contact plugs 348.

[0249] In the word line bonding area WLBA, an upper bonding metal pattern 770b may be formed in the first cell area CELL1, and an upper bonding metal pattern 670b may be formed in the peripheral circuit area PERI. The upper bonding metal pattern 770b of the first cell area CELL1 and the upper bonding metal pattern 670b of the peripheral circuit area PERI may be electrically connected to each other by a bonding method. The upper bonding metal pattern 770b and the upper bonding metal pattern 670b may be formed of aluminum, copper, or tungsten.

[0250] In the external pad bonding area PA, a lower metal pattern 771e may be formed at a lower portion of the first cell area CELL1, and an upper metal pattern 872a may be formed at an upper portion of the second cell area CELL2. The lower metal pattern 771e of the first cell area CELL1 and the upper metal pattern 872a of the second cell area CELL2 may be connected to each other by a bonding method in the external pad bonding area PA. Similarly, an upper metal pattern 772a may be formed at an upper portion of the first cell area CELL1, and an upper metal pattern 672a may be formed at an upper portion of the peripheral circuit area PERI. The upper metal pattern 772a of the first cell area CELL1 and the upper metal pattern 672a of the peripheral circuit area PERI may be connected to each other by a bonding method.

[0251] Common source line contact plugs 780 and 880 may be disposed in the external pad bonding area PA. Common source line contact plugs 780 and 880 may be formed of a conductive material such as a metal, a metal compound, and / or doped polysilicon. The common source line contact plug 780 of the first cell area CELL1 may be electrically connected to the common source line 720, and the common source line contact plug 880 of the second cell area CELL2 may be electrically connected to the common source line 820. The first metal line 750a and the second metal line 760a may be sequentially stacked on the common source line contact plug 780 of the first cell area CELL1, and the first metal line 850a and the second metal line 860a may be sequentially stacked on the common source line contact plug 880 of the second cell area CELL2.

[0252] The input / output pads 605, 805, and 806 may be disposed in the external pad landing area PA. Fig. 22 , a lower insulating layer 611 may cover the bottom surface of the first substrate 610, and a first input / output pad 605 may be formed on the lower insulating layer 611. The first input / output pad 605 may be connected to at least one of a plurality of circuit elements 620a disposed in the peripheral circuit region PERI through the first input / output contact plug 603, and may be separated from the first substrate 610 by the lower insulating layer 611. In addition, a side insulating layer may be disposed between the first input / output contact plug 603 and the first substrate 610 to electrically isolate the first input / output contact plug 603 from the first substrate 610.

[0253] An upper insulating layer 801 covering the top surface of the third substrate 810 may be formed on the third substrate 810. Second input / output pads 805 and / or third input / output pads 806 may be disposed on the upper insulating layer 801. The second input / output pads 805 may be connected to at least one of the plurality of circuit elements 620a disposed in the peripheral circuit region PERI through second input / output contact plugs 803 and 703, and the third input / output pads 806 may be connected to at least one of the plurality of circuit elements 620a disposed in the peripheral circuit region PERI through third input / output contact plugs 804 and 704.

[0254] In some embodiments, the third substrate 810 may not be disposed in a region in which the input / output contact plug is disposed. For example, as shown in region "B", the third input / output contact plug 804 may be separated from the third substrate 810 in a direction parallel to the top surface of the third substrate 810, and may penetrate the interlayer insulating layer 815 of the second cell region CELL2 to be connected to the third input / output pad 806. In this case, the third input / output contact plug 804 may be formed by at least one of various processes.

[0255] In some embodiments, as shown in region "B1", the third input / output contact plug 804 may extend in a third direction (e.g., Z-axis direction), and the diameter of the third input / output contact plug 804 may gradually increase toward the upper insulating layer 801. In other words, the diameter of the channel structure CH described in region "A1" may gradually decrease toward the upper insulating layer 801, but the diameter of the third input / output contact plug 804 may gradually increase toward the upper insulating layer 801. For example, after the second cell region CELL2 and the first cell region CELL1 are bonded to each other by a bonding method, the third input / output contact plug 804 may be formed.

[0256] In some embodiments, as shown in region "B2", the third input / output contact plug 804 may extend in a third direction (e.g., Z-axis direction), and the diameter of the third input / output contact plug 804 may gradually decrease toward the upper insulating layer 801. In other words, like the channel structure CH, the diameter of the third input / output contact plug 804 may gradually decrease toward the upper insulating layer 801. For example, the third input / output contact plug 804 may be formed together with the cell contact plug 840 before the second cell region CELL2 and the first cell region CELL1 are bonded to each other.

[0257] In some embodiments, the input / output contact plug may overlap the third substrate 810. For example, as shown in region "C", the second input / output contact plug 803 may penetrate the interlayer insulating layer 815 of the second cell region CELL2 in a third direction (e.g., Z-axis direction), and may be electrically connected to the second input / output pad 805 through the third substrate 810. In this case, the connection structure of the second input / output contact plug 803 and the second input / output pad 805 may be implemented by various methods.

[0258] In some embodiments, as shown in region "C1", an opening 808 may be formed to penetrate the third substrate 810, and the second input / output contact plug 803 may be directly connected to the second input / output pad 805 through the opening 808 formed in the third substrate 810. In this case, as shown in region "C1", the diameter of the second input / output contact plug 803 may gradually increase toward the second input / output pad 805. However, the embodiments of the present disclosure are not limited thereto, and in some embodiments, the diameter of the second input / output contact plug 803 may gradually decrease toward the second input / output pad 805.

[0259] In some embodiments, as shown in region “C2”, an opening 808 penetrating the third substrate 810 may be formed, and a contact 807 may be formed in the opening 808. One end of the contact 807 may be connected to the second input / output pad 805, and the other end of the contact 807 may be connected to the second input / output contact plug 803. Therefore, the second input / output contact plug 803 may be electrically connected to the second input / output pad 805 through the contact 807 in the opening 808. In this case, as shown in region “C2”, the diameter of the contact 807 may gradually increase toward the second input / output pad 805, and the diameter of the second input / output contact plug 803 may gradually decrease toward the second input / output pad 805. For example, the second input / output contact plug 803 may be formed together with the cell contact plug 840 before the second cell region CELL2 and the first cell region CELL1 are bonded to each other, and the contact 807 may be formed after the second cell region CELL2 and the first cell region CELL1 are bonded to each other.

[0260] Compared to the embodiments of region "C2", in some embodiments shown in region "C3", a stopper 809 may be further formed on the bottom end of the opening 808 of the third substrate 810. The stopper 809 may be a metal line formed in the same layer as the common source line 820. Alternatively, the stopper 809 may be a metal line formed in the same layer as the at least one word line 830. The second input / output contact plug 803 may be electrically connected to the second input / output pad 805 through the contact 807 and the stopper 809.

[0261] Similar to the second input / output contact plug 803 and the third input / output contact plug 804 of the second cell area CELL2, the diameters of the second input / output contact plug 703 and the third input / output contact plug 704 of the first cell area CELL1 can gradually decrease or gradually increase toward the lower metal pattern 771e.

[0262] Meanwhile, in some embodiments, the slit 811 may be formed in the third substrate 810. For example, the slit 811 may be formed at a specific position of the external pad bonding area PA. For example, as shown in area "D", when viewed from a top view, the slit 811 may be located between the second input / output pad 805 and the cell contact plug 840. Alternatively, when viewed in a top view, the second input / output pad 805 may be located between the slit 811 and the cell contact plug 840.

[0263] In some embodiments, as shown in region "D1", a slit 811 may be formed to penetrate the third substrate 810. For example, the slit 811 may be used to prevent the third substrate 810 from being finely cracked when the opening 808 is formed. However, the embodiments of the present disclosure are not limited thereto, and in some embodiments, the slit 811 may be formed to have a depth of about 60% to about 70% of the thickness of the third substrate 810.

[0264] In some embodiments, as shown in region "D2", a conductive material 812 may be formed in the slit 811. For example, the conductive material 812 may be used to discharge leakage current occurring when driving circuit elements in the external pad bonding region PA to the outside. In this case, the conductive material 812 may be connected to an external ground line.

[0265] In some embodiments, as shown in region "D3", an insulating material 813 may be formed in the slit 811. For example, the insulating material 813 may be used to electrically isolate the second input / output pad 805 and the second input / output contact plug 803 disposed in the external pad bonding region PA from the word line bonding region WLBA. Because the insulating material 813 is formed in the slit 811, a voltage provided through the second input / output pad 805 may be prevented from affecting a metal layer on the third substrate 810 disposed in the word line bonding region WLBA.

[0266] Meanwhile, in some embodiments, the first to third input / output pads 605, 805, and 806 may be selectively formed. For example, the memory device 500 may be implemented to include only the first input / output pad 605 disposed on the first substrate 610, only the second input / output pad 805 disposed on the third substrate 810, or only the third input / output pad 806 disposed on the upper insulating layer 801.

[0267] In some embodiments, at least one of the second substrate 710 of the first cell region CELL1 or the third substrate 810 of the second cell region CELL2 may be used as a sacrificial substrate and may be completely or partially removed before or after the bonding process. After removing the substrate, additional layers may be stacked. For example, the second substrate 710 of the first cell region CELL1 may be removed before or after the bonding process of the peripheral circuit region PERI and the first cell region CELL1, and then an insulating layer covering the top surface of the common source line 720 or a conductive layer for connection may be formed. Similarly, the third substrate 810 of the second cell region CELL2 may be removed before or after the bonding process of the first cell region CELL1 and the second cell region CELL2, and then an upper insulating layer 801 covering the top surface of the common source line 820 or a conductive layer for connection may be formed.

[0268] Figure 2 The memory cell array 102 may be included in the first cell region CELL1 or the second cell region CELL2 , and other circuits included in the nonvolatile memory device 10 may be included in the peripheral circuit region PERI.

[0269] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of any invention or the scope that may be claimed, but rather as descriptions of features that are peculiar to a particular embodiment of a particular invention. Certain features described in this specification in the context of a separate embodiment may also be implemented in combination in a single embodiment. Conversely, the various features described in a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations, in some cases, one or more features from a combination may be deleted from the combination, and a combination may point to a sub-combination or a variation of a sub-combination.

[0270] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A memory system, comprising a memory device and a memory controller, The memory device is configured to: Reading hard decision data from the memory cell array based on a hard read voltage, reading first soft decision data from the memory cell array based on two or more first soft read voltages, the two or more first soft read voltages being obtained based on the hard read voltage and a first voltage offset, generating a first compressed subsegment based on encoding a position of a bit having a first value into a position value for each of a plurality of first soft decision subsegments in the first soft decision data, and outputting first compressed data including a plurality of said first compressed sub-segments; and The memory controller is configured to: receiving the first compressed data, counting the number of position values ​​in each of the plurality of first compressed subsegments, and A command is provided to the memory device based on the count number, the command requesting a change in voltage offset and a recompression operation.

2. The memory system according to claim 1, wherein: The memory device is further configured to: changing the voltage offset to a second voltage offset based on the command; reading second soft decision data from the memory cell array based on the hard read voltage and the second voltage offset; generating a second compressed sub-segment based on encoding the position of the bit having the first value into the position value of each second soft decision sub-segment in a plurality of second soft decision sub-segments in the second soft decision data, and The output comprises second compressed data of a plurality of said second compressed sub-segments.

3. The memory system according to claim 2, wherein: The second voltage offset is smaller than the first voltage offset.

4. The memory system according to claim 1, wherein: The memory controller is further configured to: counting the number of first compressed subsegments in which the number of the position values ​​in the plurality of first compressed subsegments is equal to or greater than a first reference number; and Based on the counted number of the first compressed subsegments being equal to or greater than a second reference value, the command is provided to the memory device.

5. The memory system according to claim 4, wherein: The memory controller is further configured to: generating the first soft decision data based on performing a decompression operation on the first compressed data based on the count number of the first compressed sub-segments being less than the second reference value; as well as Error correction is performed on the hard decision data based on the decompressed first soft decision data.

6. The memory system according to claim 1, wherein: The memory controller is further configured to: calculating a weighted sum based on the number of the position values ​​in each of the plurality of first compressed subsegments and a plurality of weights; and Based on the weighted sum being equal to or greater than a third reference value, the command is provided to the memory device.

7. The memory system according to claim 1, wherein: The memory controller is further configured to: receiving the hard decision data from the memory device; obtaining soft decision data based on performing decompression on compressed data received from the memory device based on the number of changes in the voltage offset; as well as Error correction is performed on the hard decision data based on the soft decision data.

8. The memory system according to claim 1, wherein: The memory controller is further configured to: counting the number of first compressed subsegments in which the number of the position values ​​in the plurality of first compressed subsegments is equal to or greater than a first reference number; Obtaining soft decision data based on performing decompression on the first compressed data based on the count number of the first compressed sub-segments being equal to or greater than a second reference value; Obtaining multiple log-likelihood ratio values ​​of the hard decision data and the soft decision data based on a log-likelihood ratio mapping table; as well as The log-likelihood ratio values ​​corresponding to the bits having the second value in the soft decision data are adjusted.

9. A method of operating a memory controller, the method comprising: providing a read command to a memory device; receiving hard decision data read based on a hard read voltage from the memory device; receiving first compressed data, the first compressed data including a plurality of first compressed sub-segments respectively corresponding to a plurality of first soft decision sub-segments, the plurality of first soft decision sub-segments being included in first soft decision data read based on a plurality of first soft read voltages, the plurality of first soft read voltages being obtained based on the hard read voltage and a voltage offset; providing a command to the memory device, the command requesting a change in the voltage offset based on a number of position values ​​of bits having a first value in each of the plurality of first soft decision subsegments, the position values ​​being included in each of the plurality of first compressed subsegments; receiving, from the memory device, second compressed data of second soft decision data read based on a plurality of second soft read voltages, the plurality of second soft read voltages being obtained based on the hard read voltage and the changed voltage offset; Obtaining the second soft decision data based on performing a decompression operation on the second compressed data; as well as Error correction is performed on the hard decision data based on the second soft decision data.

10. The method according to claim 9, wherein: Providing the command to the memory device comprises: counting the number of first compressed subsegments in which the number of the position values ​​in the plurality of first compressed subsegments is equal to or greater than a first reference number; providing the command to the memory device based on the counted number of the first compressed subsegments being equal to or greater than a second reference value; and Based on the count number of the first compressed sub-segments being less than the second reference value, the first soft decision data is obtained based on a decompression operation performed on the first compressed data, and error correction is performed on the hard decision data based on the first soft decision data.

11. The method according to claim 9, wherein: Providing the command to the memory device comprises: calculating a weighted sum based on the number of the position values ​​in each of the plurality of first compressed subsegments and a plurality of weights; providing the command to the memory device based on the weighted sum being equal to or greater than a third reference value; and Based on the weighted sum being less than the third reference value, the first soft decision data is obtained based on performing a decompression operation on the first compressed data, and error correction is performed on the hard decision data based on the first soft decision data.

12. The method according to claim 9, wherein: Performing error correction on the hard decision data based on the second soft decision data includes: Obtaining multiple log-likelihood ratio values ​​of the hard decision data and the second soft decision data based on a log-likelihood ratio mapping table; and The log-likelihood ratio values ​​corresponding to the bits having the second value in the second soft decision data are adjusted.

13. The method according to claim 9, wherein: The number of position values ​​of bits that each have the first value in the second compressed data is smaller than the number of position values ​​of bits that each have the first value in the first compressed data.

14. The method according to claim 9, wherein: Obtaining the second soft decision data based on performing the decompression operation on the second compressed data includes: for each of a plurality of second compressed subsegments in the second compressed data, generating a soft decision subsegment based on including a bit having the first value in each of a plurality of positions, the plurality of positions being respectively indicated by a plurality of position values ​​included in each of the plurality of second compressed subsegments; and The second soft decision data is generated based on the generated plurality of soft decision sub-segments.

15. The method according to claim 9, wherein: The plurality of first compressed sub-segments have the same size.

16. A memory controller, the memory controller comprising: a memory interface configured to receive hard decision data and first compressed data from a memory device, the hard decision data being read based on a hard read voltage, and the first compressed data comprising a plurality of first compressed sub-segments respectively corresponding to a plurality of first soft decision sub-segments of first soft decision data, the first soft decision data being read based on a plurality of first soft read voltages, the plurality of first soft read voltages being obtained based on the hard read voltage and a voltage offset; as well as An error correction circuit is configured to output a signal based on the number of position values ​​of bits having a first value in each of the plurality of first soft decision subsegments, the signal requesting a change in the voltage offset, the position value being included in each of the plurality of first compressed subsegments.

17. The memory controller according to claim 16, wherein: The memory interface is further configured to: providing a command to the memory device, the command requesting a change in the voltage offset; as well as receiving second compressed data of second soft decision data read based on a plurality of second soft read voltages from the memory device, the plurality of second soft read voltages being obtained based on the hard read voltage and the changed voltage offset, and Wherein, the error correction circuit is further configured as: Obtaining the second soft decision data based on performing a decompression operation on the second compressed data; and Error correction is performed on the hard decision data based on the second soft decision data.

18. The memory controller according to claim 17, wherein: The number of position values ​​of bits that each have the first value in the second compressed data is smaller than the number of position values ​​of bits that each have the first value in the first compressed data.

19. The memory controller according to claim 16, wherein: The error correction circuit is further configured to: counting the number of first compressed subsegments in which the number of the position values ​​in the plurality of first compressed subsegments is equal to or greater than a first reference number; as well as Based on the count number of the first compressed sub-segments being less than a second reference value, the first soft decision data is obtained based on a decompression operation performed on the first compressed data, and error correction is performed on the hard decision data based on the first soft decision data.

20. The memory controller according to claim 19, wherein: The memory interface is further configured to provide a command to the memory device based on the counted number of the first compression subsegments being equal to or greater than the second reference value, the command requesting a change in the voltage offset.

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