Low-power-consumption verification method, system and device for system-on-chip, and storage medium

Abstract

The invention provides a low-power-consumption verification method, system and device for a system-on-chip and a storage medium, and the method comprises the steps: simulating the power-on of the system-on-chip through a verification platform in a preset verification stage, and pre-loading a chip starting instruction and an AON register assembly instruction into the system-on-chip; the chip starting instruction is executed, and the verification platform judges whether the power management unit enters a low-power-consumption state or not; if the power management unit does not enter the low-power-consumption state, the system-on-chip is normally powered on and started, and the system-on-chip is reguided to execute the chip starting instruction; if the power management unit enters the low-power-consumption state, a central processing unit of the system-on-chip is guided to execute the AON register assembly instruction, and the verification platform judges whether the AON register assembly instruction is correctly executed or not so as to determine whether low-power-consumption verification of the system-on-chip succeeds or not. According to the method, the correctness of system-on-chip starting and software and hardware cooperative processing can be effectively verified, and whether low-power-consumption verification succeeds or not is automatically judged.

Description

Technical Field

[0001] The present invention relates to the field of electronic communication technology, and in particular to a low-power consumption verification method, system, device and storage medium for a system-level chip. Background Art

[0002] System on Chip (SOC) refers to a chip that integrates the central processing unit (CPU) with input and output peripherals, memory, and other functional peripherals. As the application scenarios of SoCs become more and more complex, the power consumption requirements for SoCs are getting higher and higher. Low-power design has become a key performance indicator of SoCs, and low-power verification of SoCs has also become an independent verification direction. A common and effective low-power design uses power domain design. In different working modes, the SoC only keeps the necessary power domains working, and all other power domains are in a power-off state, which greatly saves the power consumption of the SoC.

[0003] However, the low-power design of the system-level chip has brought new challenges to the verification of the system-level chip. The currently commonly used low-power verification method is to simulate the chip sleep and wake-up scenarios in the file format (Unified Power Format, UPF) constrained by the power domain design in the chip at the unit test UT layer or the system test ST layer, and check whether the specific signal meets the expectations through assertions (SystemVerilog Assertion, SVA) or waveforms. This method can only verify the correctness of the hardware and is difficult to achieve automatic monitoring. The processing of actual low-power scenarios is strongly related to software and hardware. In addition to verifying whether the hardware can be correctly awakened, it is also necessary to verify whether the Romcode software can be correctly started after waking up from low power. The verification of Romcode software is generally performed on a field programmable logic gate array FPGA, but the low-power shutdown power domain scenario of the chip cannot be simulated on the FPGA. Therefore, there is an urgent need for a low-power verification method for a system-level chip to solve the problem of the lack of low-power verification for actual scenarios with strong correlation between software and hardware of the system-level chip in the prior art. Summary of the invention

[0004] In view of the above-mentioned deficiencies in the prior art, the present invention provides a low-power consumption verification method, system, device and storage medium for a system-level chip, which effectively solves the problem in the prior art of lack of low-power consumption verification for actual scenarios where the software and hardware of the system-level chip are strongly related.

[0005] In a first aspect, the present invention provides a low power consumption verification method for a system-level chip, the method being applied to a verification platform constructed by electronic design automation software and a power domain constraint file format UPF constraint file, the method comprising:

[0006] In the preset verification stage, the verification platform simulates the power-on of the system-level chip, and pre-loads the chip startup instruction and the AON register assembly instruction into the system-level chip;

[0007] Executing the chip startup instruction, the verification platform determines whether the power management unit of the system-level chip enters a low power consumption state;

[0008] If the power management unit does not enter the low power consumption state, the system-on-chip is powered on and started normally, and the system-on-chip is redirected to execute the chip startup instruction;

[0009] If the power management unit enters the low power state, the central processor of the system-level chip is guided to execute the AON register assembly instruction, and the verification platform determines whether the AON register assembly instruction is executed correctly to determine whether the low power consumption verification of the system-level chip is successful.

[0010] Furthermore, the preset verification stage includes a register transfer level RTL simulation stage and a power supply PG netlist simulation stage.

[0011] Furthermore, simulating the power-on of the system-level chip through the verification platform in the preset verification stage includes:

[0012] If the preset verification stage is the register transfer level RTL simulation stage, the power supply signal is simulated by using a standard library power-on function.

[0013] If the preset verification stage is the power PG netlist simulation stage, simulated power supply is performed by pulling up the power pin.

[0014] Furthermore, the chip startup instruction includes initialization configuration parameters, startup environment parameters and startup address parameters of the system-level chip, and the AON register assembly instruction includes a serial port printing command and a fixed register operation command.

[0015] Further, the pre-loading of the chip startup instruction and the AON register assembly instruction into the system-on-chip includes:

[0016] Convert the software text files corresponding to the chip startup instruction and the AON register assembly instruction into corresponding binary files;

[0017] The corresponding binary file is written into the system-on-chip through a hardware description language.

[0018] Furthermore, the system-on-chip is powered on and started normally, and the system-on-chip is redirected to execute the chip startup instruction, including:

[0019] The system-level chip is powered on and started normally, and the verification platform triggers the power management unit to enter the low power consumption state and shut down at least one power domain except the AON register;

[0020] The verification platform triggers the power management unit to exit the low power state, restore all power domains, and reboot the system-on-chip to execute the chip startup instruction.

[0021] Further, the verification platform determines whether the AON register assembly instruction is correctly executed to determine whether the low power consumption verification of the system-level chip is successful, including:

[0022] If the verification platform determines that the AON register assembly instruction is executed correctly, it is determined that the low power consumption verification of the system-on-chip is successful;

[0023] If the verification platform determines that the AON register assembly instruction is not correctly executed, it is determined that the system-on-chip low power consumption verification has failed.

[0024] In a second aspect, the present invention provides a low-power verification system for a system-level chip, the system being applied to a verification platform constructed by electronic design automation software and a power domain constraint file format UPF constraint file, the system comprising:

[0025] A first processing module is used for simulating the power-on of the system-on-chip through the verification platform in a preset verification stage, and pre-loading the chip startup instruction and the AON register assembly instruction into the system-on-chip;

[0026] A state judgment module, used for executing the chip startup instruction, and the verification platform judges whether the power management unit of the system-level chip enters a low power consumption state;

[0027] A second processing module is used for, if the power management unit does not enter the low power consumption state, and the system-on-chip is normally powered on and started, to redirect the system-on-chip to execute the chip startup instruction;

[0028] The state verification module is used to guide the central processor of the system-level chip to execute the AON register assembly instruction if the power management unit enters the low power consumption state. The verification platform determines whether the AON register assembly instruction is executed correctly to determine whether the low power consumption verification of the system-level chip is successful.

[0029] In a third aspect, the present invention provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the low power consumption verification method for the system-level chip as described in the first aspect of the present invention.

[0030] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the low power consumption verification method for a system-on-chip as described in the first aspect of the present invention.

[0031] The present invention provides a method, system, device and storage medium for verifying the low power consumption of a system-level chip. The method uses electronic design automation software and a verification platform built with a power domain constraint file format UPF constraint file to verify the low power consumption of the system-level chip from a more systematic perspective in the register transfer level RTL simulation stage and the power PG netlist simulation stage, which is close to the actual use scenario of the system-level chip. At the same time, it can effectively verify the correctness of the system-level chip startup and the coordinated processing of software and hardware, and automatically determine whether the low power consumption verification is successful. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 It is a first schematic diagram of the low power consumption verification method process of the system-on-chip provided by an embodiment of the present invention;

[0034] Figure 2 It is a second schematic diagram of the low power consumption verification method flow of the system-on-chip provided by an embodiment of the present invention;

[0035] Figure 3 It is a schematic diagram of the structure of a low-power verification system for a system-on-chip provided by an embodiment of the present invention;

[0036] Figure 4 It is a structural schematic diagram of an electronic device in an embodiment of the present invention.

[0037] Description of main component symbols:

[0038] 300. Low power consumption verification system of system-level chip; 310. First processing module; 320. Status judgment module; 330. Second processing module; 340. Status verification module; 400. Electronic device; 410. Processor; 420. Communication interface; 430. Memory; 440. Communication bus. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be further clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. It should be noted that the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0040] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used in this specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0042] The low-power design of system-level chips has brought new challenges to the verification of system-level chips. The currently commonly used low-power verification method is to simulate the chip sleep and wake-up scenarios in the file format (Unified Power Format, UPF) constrained by the power domain design in the chip at the unit test UT layer or the system test ST layer, and check whether the specific signal meets the expectations through SVA or waveform. This method can only verify the correctness of the hardware and it is difficult to achieve automatic monitoring. The actual processing of low-power scenarios is strongly related to software and hardware. In addition to verifying whether the hardware can be woken up correctly, it is also necessary to verify whether the Romcode software can be correctly started after waking up from low power. The verification of Romcode software is generally performed on the field programmable gate array FPGA, but the low-power shutdown power domain scenario of the chip cannot be simulated on the FPGA.

[0043] Example 1

[0044] In view of the above-mentioned deficiencies in the prior art, an embodiment of the present invention provides a low-power verification method for a system-level chip, which effectively solves the problem of the lack of low-power verification for actual scenarios with strong correlation between the software and hardware of the system-level chip in the prior art. The method is applied to a verification platform built by electronic design automation (EDA) software and UPF constraint files, wherein EDA is a design tool that uses computer-aided design software to complete the functional design, synthesis, verification, physical design and other processes of ultra-large-scale integrated circuit chips; UPF constraint files are a file format that constrains the power domain design in the chip. Through the Liberty file that matches the UPF format, the UPF constraint file can be directly used by any link of the entire Galaxy physical implementation platform, and the designer's power design constraints are passed to the design tool, and the design implementation work is completed by the tool, thereby realizing the process of low-power physical implementation of the entire set of digital integrated circuits.

[0045] Figure 1 FIG. 1 is a first schematic diagram of a low power consumption verification method for a system-level chip according to an embodiment of the present invention. Figure 1 As shown, the method comprises the following steps:

[0046] S100 , in a preset verification phase, simulating the power-on of the system-on-chip through a verification platform, and pre-loading a chip startup instruction and an AON register assembly instruction into the system-on-chip.

[0047] In an embodiment of the present invention, the AON register (Always-On Register) is used to implement a continuous operation or always-on function in the system. This register is designed to ensure that certain key information or control instructions can still be saved or executed when other parts of the system or device enter a low-power mode or a shutdown state, thereby maintaining the overall availability and functionality of the system.

[0048] The preset verification stage includes a register transfer level RTL (Register-Transfer Level) simulation stage and a power supply PG (Power / Ground) netlist simulation stage. If the preset verification stage is the register transfer level RTL simulation stage, the power supply signal is simulated powered by the standard library power-on function. In the embodiment of the present invention, the supply_on function is used to simulate the power supply signal; if the preset verification stage is the power supply PG netlist simulation stage, the power supply is simulated by pulling up the power pin pg_pin.

[0049] In the embodiment of the present invention, the chip startup instruction is a Romcode instruction, which includes the initialization configuration parameters, startup environment parameters and startup address parameters of the system-level chip. It can be pre-loaded into the read-only memory (ROM) of the system-level chip to guide the system-level chip to start.

[0050] The AON register assembly instruction includes a serial port print command and a fixed register operation command. The execution of the AON register assembly instruction can determine the correctness of the entire hardware low power consumption and software startup. In an embodiment of the present invention, the AON register assembly instruction is a simple and iconic print statement, such as "fw code enter AON rom". The verification platform can determine whether the AON register assembly instruction is executed by checking whether this print occurs within the expected time.

[0051] The above-mentioned Romcode instructions and AON register assembly instructions are pre-loaded into the system-level chip, wherein the Romcode instructions are loaded into the ROM of the system-level chip, and the AON register assembly instructions are loaded into the AON RAM of the system-level chip. The specific loading method is as follows: the software text file hex file corresponding to the Romcode instruction and the AON register assembly instruction is converted into the corresponding binary file bin file, and then the binary file bin file is loaded into the hardware description language Verilog model of the system-level chip through the system function readmemh of the hardware description language Verilog.

[0052] S200, executing a chip startup instruction, and the verification platform determines whether the power management unit of the system-level chip enters a low power consumption state.

[0053] Execute the Romcode instruction to complete the initialization parameter configuration of the system-level chip, and guide the system-level chip to start from the correct address by identifying the startup environment. The verification platform determines whether the power management unit of the system-level chip has entered a low-power state. Different system-level chips have different low-power states, and the entry and exit conditions are also different. Usually, the system-level chip enters a low-power state when it is idle for a long time, or the entry and exit of the low-power state is triggered by pulling up or pulling down a pin of the system-level chip.

[0054] S300: If the power management unit does not enter the low power consumption state, the system-on-chip is powered on and started normally, and the system-on-chip is rebooted to execute the chip startup instruction.

[0055] Figure 2 FIG. 2 is a second schematic diagram of a low power consumption verification method for a system-level chip according to an embodiment of the present invention. Figure 2As shown, step S300 specifically includes the following steps:

[0056] S310: The system-level chip is powered on and started normally, and the verification platform triggers the power management unit to enter a low power consumption state, and shuts down at least one power domain except the AON register.

[0057] If the power management unit does not enter the low power state, the system-level chip is powered on and started normally. After the verification platform runs for a period of time, the verification platform triggers the power management unit to enter the low power state. At this time, one or all power domains except the AON register will be turned off.

[0058] S320, the verification platform triggers the power management unit to exit the low power state, restore all power domains, and reboot the system-level chip to execute the chip startup instruction.

[0059] In the embodiment of the present invention, if the verification platform triggers the power management unit to exit the low power consumption state, all power domains are restored, the central processor of the system-level chip is restarted, and the Romcode instruction is re-executed.

[0060] S400: If the power management unit enters a low power state, the central processor of the system-level chip is guided to execute an AON register assembly instruction, and the verification platform determines whether the AON register assembly instruction is correctly executed to determine whether the low power consumption verification of the system-level chip is successful.

[0061] After the CPU of the system-level chip is restarted and the Romcode instruction is re-executed, if the power management unit enters a low-power state, the CPU of the system-level chip executes the AON register assembly instruction, and the verification platform determines whether the AON register assembly instruction is executed correctly to determine whether the low-power verification of the system-level chip is successful. Specifically, if the verification platform determines that the AON register assembly instruction is executed correctly, it is determined that the low-power verification of the system-level chip is successful; if the verification platform determines that the AON register assembly instruction is not executed correctly, it is determined that the low-power verification of the system-level chip has failed. That is, by judging whether the AON register assembly instruction is correct, the hardware low-power state entry exit process and the Romcode software startup process are judged to be correct. If the hardware low-power state entry exit process is wrong, the Romcode software startup will not recognize the low-power startup of the system-level chip, and will not jump to execute the AON register assembly instruction.

[0062] Example 2

[0063] Based on the same technical concept as the method embodiment of the above embodiment 1, the embodiment of the present invention provides a low-power verification system for a system-level chip, which is applied to a verification platform built by electronic design automation EDA software and UPF constraint files. Figure 3FIG. 1 is a schematic diagram of a low power consumption verification system of a system-on-chip according to an embodiment of the present invention. Figure 3 As shown, the low power consumption verification system 300 of the system-level chip mainly includes:

[0064] The first processing module 310 is used for simulating the power-on of the system-on-chip through the verification platform in the preset verification stage, and pre-loading the chip startup instruction and the AON register assembly instruction into the system-on-chip;

[0065] The state judgment module 320 is used to execute the chip startup instruction, and the verification platform determines whether the power management unit of the system-level chip enters a low power consumption state;

[0066] The second processing module 330 is used to redirect the system-level chip to execute the chip startup instruction if the power management unit does not enter the low power consumption state and the system-level chip is powered on and started normally;

[0067] The state verification module 340 is used to guide the central processor of the system-level chip to execute the AON register assembly instruction if the power management unit enters the low power state. The verification platform determines whether the AON register assembly instruction is executed correctly to determine whether the low power verification of the system-level chip is successful.

[0068] Example 3

[0069] Based on the same concept, an embodiment of the present invention further provides an electronic device, Figure 4 is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention, such as Figure 4 As shown, the electronic device 400 may include: a processor 410, a communication interface 420, a memory 430 and a communication bus 440, wherein the processor 410, the communication interface 420, and the memory 430 communicate with each other through the communication bus 440. The processor 410 may call the logic instructions in the memory 430 to execute the steps of the low power consumption verification method of the system-level chip as described in the above embodiments. For example, it includes:

[0070] S100, simulating the power-on of the system-level chip through the verification platform in the preset verification stage, and pre-loading the chip startup instruction and the AON register assembly instruction into the system-level chip;

[0071] S200, executing a chip startup instruction, and the verification platform determines whether the power management unit of the system-level chip enters a low power consumption state;

[0072] S300: If the power management unit does not enter the low power consumption state, the system-level chip is powered on and started normally, and the system-level chip is rebooted to execute the chip startup instruction;

[0073] S400: If the power management unit enters a low power state, the central processor of the system-level chip is guided to execute an AON register assembly instruction, and the verification platform determines whether the AON register assembly instruction is correctly executed to determine whether the low power consumption verification of the system-level chip is successful.

[0074] The processor 410 may be a central processing unit (CPU). The processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or a combination of the above chips.

[0075] In addition, the logic instructions in the above-mentioned memory 430 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0076] The memory 430 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created by the processor, etc. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0077] Example 4

[0078] Based on the same concept, an embodiment of the present invention further provides a computer-readable storage medium, which stores a computer program, and the computer program includes at least one code segment, which can be executed by a main control device to control the main control device to implement the steps of the low power consumption verification method of the system-level chip as described in the above embodiments. For example, it includes:

[0079] S100, simulating the power-on of the system-level chip through the verification platform in the preset verification stage, and pre-loading the chip startup instruction and the AON register assembly instruction into the system-level chip;

[0080] S200, executing a chip startup instruction, and the verification platform determines whether the power management unit of the system-level chip enters a low power consumption state;

[0081] S300: If the power management unit does not enter the low power consumption state, the system-level chip is powered on and started normally, and the system-level chip is rebooted to execute the chip startup instruction;

[0082] S400: If the power management unit enters a low power state, the central processor of the system-level chip is guided to execute an AON register assembly instruction, and the verification platform determines whether the AON register assembly instruction is correctly executed to determine whether the low power consumption verification of the system-level chip is successful.

[0083] Based on the same technical concept, an embodiment of the present invention further provides a computer program, which is used to implement the above method embodiment when executed by a main control device.

[0084] The program may be stored in whole or in part on a storage medium packaged together with the processor, or may be stored in whole or in part on a memory not packaged together with the processor.

[0085] Based on the same technical concept, an embodiment of the present invention further provides a processor, which is used to implement the above method embodiment. The above processor can be a chip.

[0086] In summary, the present invention provides a method, system, device and storage medium for verifying the low power consumption of a system-level chip, which uses a verification platform built by electronic design automation EDA software and UPF constraint files to verify the low power consumption of the system-level chip from a more systematic perspective in the register transfer level RTL simulation stage and the power PG netlist simulation stage, which is close to the actual usage scenario of the system-level chip. At the same time, it can effectively verify the correctness of the system-level chip startup and the coordinated processing of software and hardware, and automatically determine whether the low power consumption verification is successful.

[0087] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0088] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

[0089] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A low power consumption verification method for a system-on-chip, characterized in that: The method is applied to a verification platform built by electronic design automation software and a power domain constraint file format UPF constraint file, and the method comprises: In the preset verification stage, the verification platform simulates the power-on of the system-level chip, and pre-loads the chip startup instruction and the AON register assembly instruction into the system-level chip; Executing the chip startup instruction, the verification platform determines whether the power management unit of the system-level chip enters a low power consumption state; If the power management unit does not enter the low power consumption state, the system-on-chip is powered on and started normally, and the system-on-chip is redirected to execute the chip startup instruction; If the power management unit enters the low power state, the central processor of the system-level chip is guided to execute the normally open register AON register assembly instruction, and the verification platform determines whether the AON register assembly instruction is executed correctly to determine whether the low power consumption verification of the system-level chip is successful.

2. The low power consumption verification method of the system-on-chip according to claim 1, characterized in that: The preset verification stage includes a register transfer level RTL simulation stage and a power supply PG netlist simulation stage.

3. The low power consumption verification method of the system-on-chip according to claim 2, characterized in that: The simulating the power-on of the system-level chip by the verification platform in the preset verification stage includes: If the preset verification stage is the register transfer level RTL simulation stage, then simulating power supply to the power signal through the standard library power-on function; If the preset verification stage is the power PG netlist simulation stage, simulated power supply is performed by pulling up the power pin.

4. The low power consumption verification method of the system-on-chip according to claim 1, characterized in that: The chip startup instruction includes initialization configuration parameters, startup environment parameters and startup address parameters of the system-level chip, and the AON register assembly instruction includes a serial port printing command and a fixed register operation command.

5. The low power consumption verification method of the system-on-chip according to claim 4, characterized in that: The step of preloading the chip startup instruction and the AON register assembly instruction into the system-on-chip comprises: Convert the software text files corresponding to the chip startup instruction and the AON register assembly instruction into corresponding binary files; The corresponding binary file is written into the system-on-chip through a hardware description language.

6. The low power consumption verification method of the system-on-chip according to claim 1, characterized in that: The system-on-chip is powered on and started normally, and the system-on-chip is redirected to execute the chip startup instruction, including: The system-level chip is powered on and started normally, and the verification platform triggers the power management unit to enter the low power consumption state and shut down at least one power domain except the AON register; The verification platform triggers the power management unit to exit the low power state, restore all power domains, and reboot the system-on-chip to execute the chip startup instruction.

7. The low power consumption verification method of the system-on-chip according to claim 1, characterized in that: The verification platform determines whether the AON register assembly instruction is correctly executed to determine whether the low power consumption verification of the system-level chip is successful, including: If the verification platform determines that the AON register assembly instruction is executed correctly, it is determined that the low power consumption verification of the system-on-chip is successful; If the verification platform determines that the AON register assembly instruction is not correctly executed, it is determined that the system-on-chip low power consumption verification has failed.

8. A low power consumption verification system for a system-on-chip, characterized in that: The system is applied to a verification platform built by electronic design automation software and a power domain constraint file format UPF constraint file, and the system includes: A first processing module is used for simulating the power-on of the system-on-chip through the verification platform in a preset verification stage, and pre-loading the chip startup instruction and the AON register assembly instruction into the system-on-chip; A state judgment module, used for executing the chip startup instruction, and the verification platform judges whether the power management unit of the system-level chip enters a low power consumption state; A second processing module is used for, if the power management unit does not enter the low power consumption state, and the system-on-chip is normally powered on and started, to redirect the system-on-chip to execute the chip startup instruction; The state verification module is used to guide the central processor of the system-level chip to execute the AON register assembly instruction if the power management unit enters the low power consumption state. The verification platform determines whether the AON register assembly instruction is executed correctly to determine whether the low power consumption verification of the system-level chip is successful.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: The processor executes the computer program to implement the low power consumption verification method for the system-on-chip according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the low power consumption verification method for a system-on-chip according to any one of claims 1 to 7 is implemented.

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