Secondary cache module verification method, device and computer equipment

Abstract

The present application relates to a verification method, device and computer equipment for a secondary cache module. The method comprises: using the memory model UVM_MEM method in the universal verification methodology to construct a storage model corresponding to the storage area of ​​the target secondary cache module; performing read and write operations on the target secondary cache module to obtain target read and write data and target read and write addresses; performing backdoor read operations on the storage model to obtain various types of storage data in all storage class models inside the target secondary cache module; wherein the read and write addresses corresponding to the read and write operations are consistent with the read and write addresses corresponding to the backdoor read operations; based on the target read and write data, the target read and write addresses and the various types of storage data, the target secondary cache module is verified to obtain the verification result of the target secondary cache module. The use of this method can improve the verification efficiency of the secondary cache module.

Description

Technical Field

[0001] The present application relates to the technical field of digital integrated circuit verification, and in particular to a verification method, apparatus, computer equipment, computer-readable storage medium and computer program product for a secondary cache module. Background Art

[0002] Currently, processors are running faster and faster. In order to balance the efficiency difference between high-speed processors and low-speed large memory, and to improve processor performance, Level 1 Cache (L1 cache), Level 2 Cache (L2 cache) and Level 3 Cache (L3 cache) have appeared one after another as temporary caches between processors and off-chip storage. Relatively speaking, their speeds are getting slower and slower, and their memory capacities are getting larger and larger. In digital integrated circuit (IC) verification, these cache modules are required for module-level verification.

[0003] The verification method of the relevant secondary cache module is to use SystemVerilog or SystemC to write a reference model for the storage logic inside the secondary cache module, and perform white-box verification on the secondary cache module based on the reference model of the storage logic.

[0004] However, the storage logic inside the L2 cache module can have two different sets of storage logic. For example, not only can the L2 cache module be used for the processor, but also when the chip is used as an application-specific integrated circuit (ASIC) chip, the storage part of the L2 cache module can be reused and converted into a static random access memory (SRAM) using different storage logic. Therefore, the verification method of the related L2 cache module needs to write a reference model containing two sets of storage logic according to the two different sets of storage logic, which is time-consuming, labor-intensive, and troublesome to debug. Therefore, the verification method of the related L2 cache module is inefficient. Summary of the invention

[0005] Based on this, it is necessary to provide a verification method, device, computer equipment, computer-readable storage medium and computer program product for a secondary cache module that can improve efficiency in response to the above technical problems.

[0006] In a first aspect, the present application provides a method for verifying a secondary cache module, comprising:

[0007] The memory model UVM_MEM method in the universal verification methodology is used to construct a storage model corresponding to the storage area of ​​the target secondary cache module;

[0008] Performing read and write operations on the target secondary cache module to obtain target read and write data and target read and write addresses;

[0009] Performing a backdoor read operation on the storage model to obtain various types of storage data in all storage class models inside the target secondary cache module; wherein the read and write addresses corresponding to the read and write operations are consistent with the read and write addresses corresponding to the backdoor read operation;

[0010] Based on the target read / write data, the target read / write address and the various types of storage data, the target secondary cache module is verified to obtain a verification result of the target secondary cache module.

[0011] In one embodiment, the verification result includes a read failure verification sub-result, the target read / write data includes a first read address and first read data provided by an agent of a bus master connected to a digital signal processor, and a second read address and second read data provided by an agent of a bus slave connected to a double data rate synchronous dynamic random access memory, the various types of storage data include original data and associated data, and the verification of the target secondary cache module based on the target read / write data, the target read / write address and the various types of storage data to obtain the verification result of the target secondary cache module includes:

[0012] Compare the first read address with part or all of the second read address to obtain a first read failure address comparison sub-result, and compare the first read data with part or all of the second read data to obtain a first read failure data comparison sub-result;

[0013] Determine a first read failure comparison result according to the first read failure address comparison sub-result and the first read failure data comparison sub-result;

[0014] Comparing the original data with the second read data to obtain a second read failure comparison result;

[0015] Based on the preset associated data read failure verification rule and the target read / write address, the associated data is verified to obtain an associated data read failure verification result;

[0016] Based on the first read invalidation comparison result, the second read invalidation comparison result and the associated data read invalidation verification result, a read invalidation verification sub-result of the target secondary cache module is determined.

[0017] In one embodiment, the verification result includes a write failure verification sub-result, the target read / write data includes a first write address and first write data provided by an agent of a bus master connected to a digital signal processor, and a second write address and second write data provided by an agent of a bus slave connected to a double data rate synchronous dynamic random access memory, the various types of storage data include original data and associated data, and the verification of the target secondary cache module based on the target read / write data, the target read / write address and the various types of storage data to obtain the verification result of the target secondary cache module includes:

[0018] Determining first expected data written into the data storage of the storage model according to the first write address, the second write address, the first write data, and the second write data;

[0019] Comparing the original data with the first expected data to obtain a write failure comparison result;

[0020] Based on the preset associated data write failure verification rule and the target read / write address, the associated data is verified to obtain an associated data write failure verification result;

[0021] Based on the write failure comparison result and the associated data write failure verification result, a write failure verification sub-result of the target secondary cache module is determined.

[0022] In one embodiment, the verification result includes a read hit verification sub-result, the target read / write data includes a third read address and third read data corresponding to the current read hit provided by an agent of a bus master connected to a digital signal processor, the various types of storage data include and associated data, and the verification of the target secondary cache module based on the target read / write data, the target read / write address and the various types of storage data to obtain the verification result of the target secondary cache module includes:

[0023] Determine a read hit comparison result according to the third read address and the third read data; in a case where the target read / write data also includes a fourth read address and fourth read data corresponding to a previous read failure provided by an agent of a bus master connected to a digital signal processor, the read hit comparison result is determined based on a read hit address comparison sub-result and a read hit data comparison sub-result, the read hit address comparison sub-result is obtained based on a comparison between the fourth read address and the third read address, and the read hit data comparison sub-result is obtained based on a comparison between the fourth read data and the third read data; in a case where the target read / write data also includes a third write address corresponding to a previous write failure provided by an agent of a bus master connected to a digital signal processor, the read hit comparison result is obtained based on a comparison between second expected data and the third read data, and the second expected data is determined based on the third write address;

[0024] Based on the preset associated data read hit verification rule and the target read / write address, verify the associated data to obtain an associated data read hit verification result;

[0025] Based on the read hit comparison result and the associated data read hit verification result, a read hit verification sub-result of the target secondary cache module is determined.

[0026] In one embodiment, the verification result includes a write hit verification sub-result, the target read / write data includes a fourth write address and fourth write data corresponding to the current write hit provided by an agent of a bus master connected to a digital signal processor, the various types of storage data include original data and associated data, and the verification of the target secondary cache module based on the target read / write data, the target read / write address and the various types of storage data to obtain the verification result of the target secondary cache module includes:

[0027] determining, according to the fourth write address and the fourth write data, third expected data corresponding to the current write hit; in a case where the target read-write data also includes a fourth read address and fourth read data corresponding to a previous read failure provided by an agent of a bus master connected to the digital signal processor, the third expected data is determined based on the fourth read address, the fourth read data, the fourth write address and the fourth write data; in a case where the target read-write data also includes a third write address and third write data corresponding to a previous write failure provided by an agent of a bus master connected to the digital signal processor, the third expected data is determined based on the second expected data, the fourth write address and the fourth write data, and the second expected data is determined based on the third write address and the third write data;

[0028] Comparing the original data with the third expected data to obtain a write hit comparison result;

[0029] Based on a preset associated data write hit verification rule and the target read / write address, verify the associated data to obtain an associated data write hit verification result;

[0030] Based on the write hit comparison result and the associated data write hit verification result, a write hit verification sub-result of the target secondary cache module is determined.

[0031] In one embodiment, the verification result includes a write-back data verification sub-result, the target read-write data includes a fifth write address and fifth write data corresponding to a first write failure provided by an agent of a bus master connected to a digital signal processor, and a sixth write address, sixth write data, write-back address and write-back data corresponding to a first write failure provided by an agent of a bus slave connected to a double data rate synchronous dynamic random access memory, and the verification result of the target secondary cache module is obtained by verifying the target secondary cache module based on the target read-write data, the target read-write address and the various types of storage data, including:

[0032] Determining fourth expected data written into the data storage of the storage model according to the fifth write address, the sixth write address, the fifth write data, and the sixth write data;

[0033] Comparing the write-back data with the fourth expected data to obtain a first write-back data comparison result;

[0034] Comparing the write-back address with the fifth write-in address and the sixth write-in address to obtain a second write-back data comparison result;

[0035] A write-back data verification sub-result is determined based on the first write-back data comparison result and the second write-back data comparison result.

[0036] In a second aspect, the present application also provides a verification device for a secondary cache module, including:

[0037] A construction module is used to construct a storage model corresponding to the storage area of ​​the target secondary cache module by using a memory model UVM_MEM device in universal verification device theory;

[0038] A read / write module, used to perform read / write operations on the target secondary cache module to obtain target read / write data and target read / write addresses;

[0039] A backdoor reading module, used to perform a backdoor reading operation on the storage model to obtain various types of storage data in all storage class models inside the target secondary cache module; wherein the read and write addresses corresponding to the read and write operations are consistent with the read and write addresses corresponding to the backdoor reading operations;

[0040] The verification module is used to verify the target secondary cache module based on the target read-write data, the target read-write address and the various types of storage data to obtain a verification result of the target secondary cache module.

[0041] In a third aspect, the present application further provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps described in the first aspect when executing the computer program.

[0042] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps described in the first aspect above.

[0043] In a fifth aspect, the present application further provides a computer program product, comprising a computer program, which implements the steps described in the first aspect when executed by a processor.

[0044] The verification method, device, computer equipment, computer-readable storage medium and computer program product of the above-mentioned secondary cache module adopt the memory model UVM_MEM method in the universal verification methodology to construct a storage model corresponding to the storage area of ​​the target secondary cache module; perform read and write operations on the target secondary cache module to obtain target read and write data and target read and write addresses; perform backdoor read operations on the storage model to obtain various types of storage data in all storage class models inside the target secondary cache module; wherein the read and write addresses corresponding to the read and write operations are consistent with the read and write addresses corresponding to the backdoor read operations; based on the target read and write data, the target read and write addresses and the various types of storage data, the target secondary cache module is verified to obtain a verification result of the target secondary cache module. In this way, for the storage area of ​​the secondary cache module, the UVM_MEM method is used to build a storage class reference model of the secondary cache module, and the reading and writing of the secondary cache module is used in combination with the UVM_MEM method to perform a backdoor read operation on the storage model to perform module-level white box verification of the secondary cache module. Since the storage areas corresponding to the two different storage logics are unchanged, even if there may be two different storage logics inside the secondary cache module, only one set of storage model needs to be written and debugged, which can shorten the verification time of the secondary cache module and improve the verification efficiency of the secondary cache module. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0046] FIG1 is a schematic diagram of a flow chart of a method for verifying a secondary cache module in one embodiment;

[0047] FIG2 is a flowchart of a verification step for performing verification on a target secondary cache module in an embodiment in which the verification result includes a read invalidation verification sub-result;

[0048] 3 is a flow chart of steps of verifying a target secondary cache module in which a verification result includes a write failure verification sub-result in one embodiment;

[0049] FIG4 is a flowchart showing steps of verifying a target secondary cache module in which a verification result includes a read hit verification sub-result in one embodiment;

[0050] FIG5 is a flowchart showing steps of verifying a target secondary cache module in which a verification result includes a write hit verification sub-result in one embodiment;

[0051] 6 is a flowchart of a verification step of performing verification on a target secondary cache module in which a verification result includes a write-back data verification sub-result in one embodiment;

[0052] FIG7 is a flowchart of performing read-write invalidation verification on a target secondary cache module in one embodiment;

[0053] FIG8 is a flowchart of performing read-write hit verification on a target secondary cache module in one embodiment;

[0054] FIG9 is a flowchart of performing write-back operation verification on a target secondary cache module in one embodiment;

[0055] FIG10 is a flowchart of performing tag data error verification on a target secondary cache module through a write invalidation operation in one embodiment;

[0056] FIG11 is a flowchart of performing 1-bit storage data error verification on a target secondary cache module through a write failure operation in one embodiment;

[0057] FIG12 is a block diagram of a verification device for a secondary cache module in one embodiment;

[0058] FIG. 13 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0059] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0060] In one embodiment, as shown in FIG1 , a verification method for a secondary cache module is provided. This embodiment uses the method applied to a terminal as an example. It is understandable that the method can also be applied to a server, and can also be applied to a system including a terminal and a server, and is implemented through the interaction between the terminal and the server. Among them, the terminal can be, but is not limited to, various personal computers, laptops, smart phones, tablet computers, Internet of Things devices and portable wearable devices. The Internet of Things devices can be smart speakers, smart TVs, smart air conditioners, smart car-mounted devices, projection devices, etc. Portable wearable devices can be smart watches, smart bracelets, head-mounted devices, etc. The head-mounted device can be a virtual reality (VR) device, an augmented reality (AR) device, smart glasses, etc. The server can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides cloud computing services. In this embodiment, the method includes the following steps:

[0061] Step 101, using the memory model UVM_MEM method in the universal verification methodology, constructing a storage model corresponding to the storage area of ​​the target secondary cache module.

[0062] In an embodiment of the present application, the target secondary cache module is a secondary cache module to be verified for a digital integrated circuit, which is a device under test (DUT). UVM_MEM is a memory model (MEM) in the Universal Verification Methodology (UVM). The storage model is a storage class reference model of the L2Cache module. The storage model may include: an original data sub-storage model (data_mem) and an associated data sub-storage model. The original data sub-storage model is used to store original data (data). The associated data sub-storage model is used to store associated data. Associated data is data associated with the original data. Associated data may include: classification tag data, valid data, dirty data, lock data, least recently used policy (lru) data, error checking and correction (ecc) data, and error checking and correction whether the state (ecc state) is effective. The associated data sub-storage model may include: a classification tag sub-storage model (tag_mem), a valid sub-storage model (valid_mem), a dirty sub-storage model (dirty_mem), a lock sub-storage model (lock_mem), a least recently used policy sub-storage model (lru_mem), an error checking and correction sub-storage model (ecc_mem), and a state sub-storage model of whether the error checking and correction is effective (ecc state_mem).

[0063] Step 102, performing read and write operations on the target secondary cache module to obtain target read and write data and target read and write addresses.

[0064] In an embodiment of the present application, a read-write operation may include at least one of a read-failure operation, a write-failure operation, a read-hit operation, a write-hit operation, and a write-back operation. The target read-write data includes the read-write data corresponding to at least one read-write operation, and the target read-write address includes the read-write address corresponding to at least one read-write operation. The read-write data includes at least one of read data, write data, and write-back data. The read-write address includes at least one of a read address, a write address, and a write-back address. The target read-write data may include the read-write data corresponding to multiple read-write operations, and the target read-write address may include the read-write addresses corresponding to multiple read-write operations, and the multiple read-write operations may be the same read-write operation or different read-write operations.

[0065] Step 103, performing a backdoor read operation on the storage model to obtain various types of storage data in all storage class models inside the target secondary cache module.

[0066] The read / write address corresponding to the read / write operation is consistent with the read / write address corresponding to the backdoor read operation.

[0067] In the embodiment of the present application, each type of storage data includes original storage data and associated storage data. The storage class model is a sub-storage model, which can be an original data sub-storage model and an associated data sub-storage model.

[0068] In an example, the terminal uses a backdoor read operation to backdoor read out various types of data stored in all storage class models inside the storage model of the target secondary cache module through the read and write addresses of the bus master's agent (dsp_mater_agt) originally connected to the digital signal processor (DSP), and obtains data stored in data_mem, data stored in tag_mem, data stored in valid_mem, data stored in dirty_mem, data stored in lock_mem, data stored in lru_mem, data stored in ecc_mem, and data stored in ecc state_mem.

[0069] In one example, for each storage class model, the terminal uses the backdoor read function according to the storage logic corresponding to the storage class model in the cache storage logic, and the backdoor reads the storage data in the storage class model inside the target secondary cache module. Specifically, for the original data sub-storage model, the terminal determines the number of ways through the lru calculation result according to the data_mem storage logic in the cache storage logic, and determines the number of rows according to the read operation address [17:7]. Then, the terminal uses the backdoor read function of UVM_MEM, and the backdoor reads the storage data in data_mem.

[0070] Data_mem storage logic: data_mem has a total of 2048 rows, divided into 4 channels, and each row of each channel stores 1024 bits of data. The bus slave agent (ddr_slave_agt) connected to the double data rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM or DDR) provides 4 read data according to the address read each time, each with 256 bits, totaling 1024 bits. DUT stores the 1024 bits of data in one of the 4 channels in the 4-way group connection according to the LRU rule, and then determines the specific storage row position according to the [17:7] bit of the read address.

[0071] Tag_mem storage logic: tag_mem has a total of 2048 rows, each row stores 76 bits of data, and each row of data contains the tag data of the same group in a 4-way group, where 1 group contains 4 ways, and each tag storage contains 1 bit of parity bit, 18 bits of high-order address, that is, the high-order address [35:18] in the read and write address, totaling 19 bits. The tag_mem row data from low to high are the 19-bit tag data of the first way, the 19-bit tag data of the second way, the 19-bit tag data of the third way, and the 19-bit tag data of the fourth way. DUT determines the specific row location of the tag storage according to the [17:7] bits of the read and write address of dsp_master_agt, and then determines the specific number of ways where the tag address of this read and write operation needs to be stored according to the lru calculation result.

[0072] Valid_mem storage logic: valid_mem has a total of 64 rows, each row stores 128 bits of data, indicating that the 4-way group simultaneously increases the valid flag of 32 rows in 32 rows each time starting from 0. Each way contains 32 rows, and a total of 128 rows of valid data are contained. DUT determines the number of ways based on the lru calculation result, determines the row position where the valid data is stored based on the dap_master_agt read and write address [17:12] bit, and then determines the specific bit position in the 32 bits based on the read and write address [11:7] bit.

[0073] Dirty_mem storage logic: dirty_mem has a total of 64 rows, each row stores 128 bits of data, indicating that the dirty flag of 32 rows in the 4-way group is incremented from 0 at the same time. Each way contains 32 rows, and a total of 128 rows. DUT determines the number of ways based on the lru calculation result, and determines the row position where the dirty data is stored based on the dap_master_agt read and write address [17:12] bit, and then determines the specific bit position in the 32 bits based on the read and write address [11:7] bit.

[0074] Lock_mem storage logic: Lock_mem has a total of 64 rows, each row stores 128-bit data, indicating that the lock flag of a certain 32 rows in the 32 rows is incremented each time starting from 0 in the 4-way group. Each way contains 32 rows, and a total of 128 rows. DUT determines the number of ways based on the lru calculation result, determines the row position where the lock data is stored based on the dsp_master_agt read and write address [17:12] bit, and then determines the specific bit position in the 32 bits based on the read and write address [11:7] bit.

[0075] Lru_mem storage logic: lru_mem has a total of 64 rows, each row stores 256 bits of data, indicating that the lru flag of a certain 32 groups in the 4-way group is incremented from 0 at a time, each group has 8 bits of data, dut determines which specific 32 groups, that is, which row, according to the dsp_master_agt read and write address [17:12] bits, and then determines which group of the 32 groups according to the read and write address [11:7] bits, and writes the 8-bit result of the lru calculation, indicating the least recently used order of a certain group of 4-way in the 4-way group, from 0 to 3. The larger the value, the less used it is and the greater the probability of being replaced.

[0076] Ecc storage logic: ecc_mem contains 32 sub-storage mems, each of which consists of 2048 rows of 9-bit data, indicating the ECC calculation result of a 128-bit data. DUT determines which of the 32 self-storage mems it is based on the read-write address [19:15], and determines the specific number of rows based on the read-write address [14:4], and then stores it.

[0077] Ecc_state_mem storage logic: ecc_state_mem contains 32 sub-storage mems, each sub-storage mem consists of 16 rows of 128-bit data, 1 bit represents the state of ECC data in a row in ecc_mem, dut determines a sub-storage mem according to the [19:15] bit of the read-write address, and then determines the number of rows according to the read-write address [14:11], and determines a bit in the 128 bits according to the read-write address [10:4] bit, and then stores it.

[0078] The specific process of the backdoor read operation can be as follows: the terminal uses uvm_component to declare an intermediate state environment (env) component in the virtual sequencer (v_seq), and uses the current bus environment (amba_env) to declare a final state environment (env) component. Then, the terminal assigns the handle of the environment (env) obtained through the p_sequencer.get_parent() function to the intermediate state environment (env). Then, the terminal dynamically converts the final state env through the $cast (final state env, intermediate state env) function so that the final state env obtains the actual object. Since mem_model is declared and instantiated under the final state env, the handles of all sub-models under mem_model can be obtained through the tree structure of the component component. With the help of the peek (status, offset_addr, value) function that comes with UVM_MEM, the storage data stored under a certain offset address offset_addr can be obtained without affecting the storage result and storage logic.

[0079] Step 104 , based on the target read / write data, the target read / write address and various types of storage data, the target secondary cache module is verified to obtain a verification result of the target secondary cache module.

[0080] In an embodiment of the present application, verification may include: at least one of normal function verification and abnormal test verification. Normal function verification may include: read-write failure verification, read-write hit verification, write-back operation verification, lru function verification, block failure verification, block failure and write-back verification, global failure verification, and global failure and write-back verification. Read-write failure verification includes at least one of read failure verification and write failure verification. Read-write hit verification includes at least one of read hit verification and write hit verification. Abnormal test verification may include: at least one of tag data bit error verification, tag check bit error verification, 1bit storage data error verification, and 2bit storage data error verification.

[0081] Accordingly, the verification result may include: at least one of a normal function verification sub-result and an abnormal test verification sub-result. The normal function verification sub-result may include: at least one of a read-write failure verification sub-result, a read-write hit verification sub-result, a write-back operation verification sub-result, an lru function verification sub-result, a block failure verification sub-result, a block failure and write-back verification sub-result, a global failure verification sub-result, and a global failure and write-back verification sub-result. The read-write failure verification sub-result includes at least one of a read failure verification sub-result and a write failure verification sub-result. The read-write hit verification sub-result includes at least one of a read hit verification sub-result and a write hit verification sub-result. The abnormal test verification sub-result may include: at least one of a tag data bit error verification sub-result, a tag check bit error verification sub-result, a 1-bit storage data error verification sub-result, and a 2-bit storage data error verification sub-result.

[0082] In the verification method of the above-mentioned secondary cache module, for the storage area of ​​the secondary cache module, the UVM_MEM method is used to build the storage class reference model of the secondary cache module, and the module-level white box verification of the secondary cache module is performed by reading and writing the secondary cache module and matching the backdoor reading operation of the storage model by the UVM_MEM method. Since the storage area corresponding to the two different storage logics is unchanged, even if there are two different storage logics in the storage logic inside the secondary cache module, only one set of storage models needs to be written and debugged, which can shorten the verification time of the secondary cache module and improve the verification efficiency of the secondary cache module. In addition, the method can realize functional testing, result correctness comparison and construction of test cases for abnormal situations during the verification process. In addition, the method can use the macro definition method to define the storage size, which is convenient for subsequent modification and optimization, so it is also suitable for the verification of other storage class modules, and this method supports backdoor reading and writing. When the error is injected, the storage data can be modified without affecting the logic of the module itself, and the error scenario can be constructed, which is simple and efficient. In addition, during the verification process, for two different sets of storage logic, it is only necessary to compare the data of the storage model according to the address and the corresponding storage logic to verify whether the module storage is correct. In addition, this method proposes a new white-box verification method for storage-type modules, which can ensure the efficiency of the entire project at the same time.

[0083] In an exemplary embodiment, as shown in FIG. 2 , the verification result includes a read failure verification sub-result, the target read / write data includes a first read address and first read data provided by an agent of a bus master connected to a digital signal processor, and a second read address and second read data provided by an agent of a bus slave connected to a double data rate synchronous dynamic random access memory, and various types of storage data include original data and associated data. Based on the target read / write data, the target read / write address and various types of storage data, the target secondary cache module is verified, and the specific process of obtaining the verification result of the target secondary cache module includes the following steps:

[0084] Step 201 , compare the first read address with part or all of the second read address to obtain a first read failure address comparison sub-result, and compare the first read data with part or all of the second read data to obtain a first read failure data comparison sub-result.

[0085] Step 202: Determine a first read failure comparison result according to a first read failure address comparison sub-result and a first read failure data comparison sub-result.

[0086] In one example, the terminal combines the first read fail address comparison sub-result and the first read fail data comparison sub-result to form a first read fail comparison result.

[0087] In one example, if the first read failure address comparison sub-result indicates that the address comparison is consistent, and the first read failure data comparison sub-result indicates that the data comparison is consistent, the terminal determines that the first read failure comparison result indicates that the comparison data is consistent. If the first read failure address comparison sub-result indicates that the address comparison is inconsistent, or the first read failure data comparison sub-result indicates that the data comparison is inconsistent, the terminal determines that the first read failure comparison result indicates that the comparison data is inconsistent.

[0088] Step 203 : compare the original data with the second read data to obtain a second read failure comparison result.

[0089] Step 204 , based on the preset associated data read failure verification rule and the target read / write address, the associated data is verified to obtain an associated data read failure verification result.

[0090] In an embodiment of the present application, the terminal compares the read tag data with [35:18] of the read operation address to obtain the tag data read invalidation verification sub-result. The terminal determines whether the valid data read out corresponds to the bit position of the read operation address [11:7] is 1. If the valid data read out corresponds to the bit position of the read operation address [11:7] is 1, it means it is valid, and the terminal determines that the valid data read invalidation verification sub-result indicates that the valid data read invalidation verification has passed. The terminal determines whether the dirty data read out are all 0. If the dirty data read out are all 0, it means that they have not been modified, and the terminal determines that the dirty data read invalidation verification sub-result indicates that the dirty data read invalidation verification has passed. The terminal determines whether the lock data read out are all 0. If the lock data read out are all 0, it means that they have not been locked, and the terminal determines that the lock data read invalidation verification sub-result indicates that the lock data read invalidation verification has passed. The terminal determines whether the number of ways involved in the read operation of the lru data read out is 0, and the others are all greater than 0. If the number of ways involved in the read operation of the read lru data is 0, and the others are greater than 0, it means that the lru value of the way in this group is the lowest, and the terminal determines that the lru data read invalidation verification sub-result indicates that the lru data read invalidation verification has passed. The terminal compares the read ecc data with the calculation result of the ecc_caculate function. If the read ecc data is consistent with the calculation result of the ecc_caculate function, the terminal determines that the ecc data read invalidation verification sub-result indicates that the ecc data read invalidation verification has passed. The terminal determines whether the read ecc_state data are all 0. If the read ecc_state data are all 0, it means that the ecc is valid, and the terminal determines that the ecc_state data read invalidation verification sub-result indicates that the ecc_state data read invalidation verification has passed. Then, the terminal determines the associated data read invalidation verification result based on the tag data read invalidation verification sub-result, the valid data read invalidation verification sub-result, the dirty data read invalidation verification sub-result, the lock data read invalidation verification sub-result, the lru data read invalidation verification sub-result, the ecc data read invalidation verification sub-result, and the ecc_state data read invalidation verification sub-result.

[0091] It can be understood that the specific process of determining the associated data read failure verification result based on the tag data read failure verification sub-result, the valid data read failure verification sub-result, the dirty data read failure verification sub-result, the lock data read failure verification sub-result, the lru data read failure verification sub-result, the ecc data read failure verification sub-result and the ecc_state data read failure verification sub-result is similar to the specific process of determining the first read failure comparison result based on the first read failure address comparison sub-result and the first read failure data comparison sub-result.

[0092] Step 205 : determining a read invalidation verification sub-result of the target L2 cache module based on the first read invalidation comparison result, the second read invalidation comparison result and the associated data read invalidation verification result.

[0093] In one example, the terminal uses the first read invalidation comparison result, the second read invalidation comparison result, and the associated data read invalidation verification result to form a read invalidation verification sub-result of the target secondary cache module.

[0094] In one example, if the first read invalidation comparison result indicates that the data comparison is consistent, and the second read invalidation comparison result indicates that the data comparison is consistent, and the associated data read invalidation verification result indicates that the associated data read invalidation verification has passed, then the terminal determines that the read invalidation verification sub-result of the target secondary cache module indicates that the read invalidation verification has passed. If the first read invalidation comparison result indicates that the data comparison is inconsistent, or the second read invalidation comparison result indicates that the data comparison is inconsistent, or the associated data read invalidation verification result indicates that the associated data read invalidation verification has not passed, then the terminal determines that the read invalidation verification sub-result of the target secondary cache module indicates that the read invalidation verification has not passed.

[0095] In the verification method of the above-mentioned secondary cache module, the first read address is compared with part or all of the second read address, the first read data is compared with part or all of the second read data, the original data is compared with the second read data, and the associated data is verified based on the preset associated data read invalidation verification rules and the target read and write addresses. Based on each comparison result and verification result, the read invalidation verification sub-result of the secondary cache module is determined, which can not only verify that the data stored in data_mem is correct, but also ensure that the original data and the associated data are correct and are stored in the correct location according to the cache storage logic, and can realize white box verification of read invalidation of the secondary cache module, thereby improving the accuracy of read invalidation verification of the secondary cache module, and then through the accuracy of verification of the secondary cache module.

[0096] In an exemplary embodiment, as shown in FIG3 , the verification result includes a write failure verification sub-result, the target read / write data includes a first write address and first write data provided by an agent of a bus master connected to a digital signal processor, and a second write address and second write data provided by an agent of a bus slave connected to a double data rate synchronous dynamic random access memory, and various types of storage data include original data and associated data. Based on the target read / write data, the target read / write address and various types of storage data, the target secondary cache module is verified, and the specific process of obtaining the verification result of the target secondary cache module includes the following steps:

[0097] Step 301 : Determine first expected data in a data storage of a write storage model according to a first write address, a second write address, first write data, and second write data.

[0098] In the embodiment of the present application, the first expected data is data in the data storage written into the storage model, which is data written by dsp_master_agt and data provided by ddr_slave_agt aligned according to the address and combined and modified according to the valid signal of the write select signal (wstrb).

[0099] Step 302: compare the original data with the first expected data to obtain a write failure comparison result.

[0100] Step 303: verify the associated data based on the preset associated data write failure verification rule and the target read / write address to obtain the associated data write failure verification result.

[0101] In an embodiment of the present application, the terminal compares the read tag data with the write operation address [35:18] to obtain the tag data write failure verification sub-result. The terminal determines whether the valid data read out and the bit corresponding to the read operation address [11:7] are 1. If the valid data read out and the bit corresponding to the read operation address [11:7] are 1, it means valid, and the terminal determines that the valid data read failure verification sub-result indicates that the valid data read failure verification has passed. The terminal determines whether the dirty data read out and the bit corresponding to the write operation address [11:7] are 1. If the dirty data read out and the bit corresponding to the write operation address [11:7] are 1, it means that it has been modified, and the terminal determines that the dirty data write failure verification sub-result indicates that the dirty data write failure verification has passed. The terminal determines whether the lock data read out are all 0. If the lock data read out are all 0, it means that it has not been locked, and the terminal determines that the lock data write failure verification sub-result indicates that the lock data write failure verification has passed. The terminal determines whether the number of ways involved in the read operation of the lru data read out is 0, and the others are all greater than 0. If the number of ways involved in the read operation of the read lru data is 0, and the others are greater than 0, it means that the lru value of the way in this group is the lowest, and the terminal determines that the lru data write failure verification sub-result indicates that the lru data write failure verification has passed. The terminal compares the read ecc data with the calculation result of the ecc_caculate function. If the read ecc data is consistent with the calculation result of the ecc_caculate function, the terminal determines that the ecc data write failure verification sub-result indicates that the ecc data write failure verification has passed. The terminal determines whether the read ecc_state data are all 0. If the read ecc_state data are all 0, it means that the ecc is valid, and the terminal determines that the ecc_state data write failure verification sub-result indicates that the ecc_state data write failure verification has passed. Then, the terminal determines the associated data write failure verification result based on the tag data write failure verification sub-result, the valid data write failure verification sub-result, the dirty data write failure verification sub-result, the lock data write failure verification sub-result, the lru data write failure verification sub-result, the ecc data write failure verification sub-result, and the ecc_state data write failure verification sub-result.

[0102] It can be understood that the specific process of determining the associated data write failure verification result based on the tag data write failure verification sub-result, the valid data write failure verification sub-result, the dirty data write failure verification sub-result, the lock data write failure verification sub-result, the lru data write failure verification sub-result, the ecc data write failure verification sub-result and the ecc_state data write failure verification sub-result is similar to the specific process of step 205.

[0103] Step 304: Determine a write failure verification sub-result of the target L2 cache module based on the write failure comparison result and the associated data write failure verification result.

[0104] It can be understood that the specific process of determining the write failure verification sub-result of the target secondary cache module based on the write failure comparison result and the associated data write failure verification result is similar to the specific process of step 205 .

[0105] In the verification method of the above-mentioned secondary cache module, the first expected data in the data storage of the write storage model is determined according to the first write address, the second write address, the first write data and the second write data, the original data is compared with the first expected data, and the associated data is verified based on the preset associated data write failure verification rules and the target read and write address, and the write failure verification sub-result of the target secondary cache module is determined based on the write failure comparison result and the associated data write failure verification result, which can not only verify that the data stored in data_mem is correct, but also ensure that the original data and the associated data are correct and are stored in the correct location according to the cache storage logic, and can realize white box verification of write failure of the secondary cache module, thereby improving the accuracy of write failure verification of the secondary cache module, and further improving the accuracy of verification of the secondary cache module.

[0106] In an exemplary embodiment, as shown in FIG4 , the verification result includes a read hit verification sub-result, the target read / write data includes a third read address and third read data corresponding to the current read hit provided by an agent of a bus master connected to a digital signal processor, and various types of storage data include and associated data. Based on the target read / write data, the target read / write address and various types of storage data, the target secondary cache module is verified, and the specific process of obtaining the verification result of the target secondary cache module includes the following steps:

[0107] Step 401 : determining a read hit comparison result according to a third read address and a third read data.

[0108] Wherein, in the case where the target read / write data also includes the fourth read address and the fourth read data corresponding to the last read failure provided by the agent of the bus master connected to the digital signal processor, the read hit comparison result is determined based on the read hit address comparison sub-result and the read hit data comparison sub-result, the read hit address comparison sub-result is obtained based on the comparison of the fourth read address with the third read address, and the read hit data comparison sub-result is obtained based on the comparison of the fourth read data with the third read data. In the case where the target read / write data also includes the third write address corresponding to the last write failure provided by the agent of the bus master connected to the digital signal processor, the read hit comparison result is obtained based on the comparison of the second expected data with the third read data, and the second expected data is determined based on the third write address.

[0109] In the embodiment of the present application, the second expected data is the data stored in data_mem.

[0110] Step 402 , based on the preset associated data read hit verification rule and the target read / write address, the associated data is verified to obtain an associated data read hit verification result.

[0111] In an embodiment of the present application, the terminal compares the read tag data with [35:18] of the read operation address to obtain the tag data read hit verification sub-result. The terminal determines whether the valid data read out corresponds to the read operation address [11:7] or not. If the valid data read out corresponds to the read operation address [11:7] or not, it indicates validity, and the terminal determines that the valid data read hit verification sub-result indicates that the valid data read hit verification has passed. If the previous operation of this read hit operation is a read failure, the terminal determines whether the dirty data read out is all 0. If the dirty data read out is all 0, it indicates that it has not been modified, and the terminal determines that the dirty data read hit verification sub-result indicates that the dirty data read hit verification has passed. The terminal determines whether the lock data read out is all 0. If the lock data read out is all 0, it indicates that it has not been locked, and the terminal determines that the lock data read hit verification sub-result indicates that the lock data read hit verification has passed. The terminal determines whether the number of ways involved in the read operation of the lru data read out is 0, and the others are all greater than 0. If the number of ways involved in the read operation of the read lru data is 0, and the others are greater than 0, it means that the lru value of the way in this group is the lowest, and the terminal determines that the lru data read hit verification sub-result indicates that the lru data read hit verification has passed. The terminal compares the read ecc data with the calculation result of the ecc_caculate function. If the read ecc data is consistent with the calculation result of the ecc_caculate function, the terminal determines that the ecc data read hit verification sub-result indicates that the ecc data read hit verification has passed. The terminal determines whether the read ecc_state data are all 0. If the read ecc_state data are all 0, it means that the ecc is valid, and the terminal determines that the ecc_state data read hit verification sub-result indicates that the ecc_state data read hit verification has passed. Then, the terminal determines the associated data read hit verification result based on the tag data read hit verification sub-result, valid data read hit verification sub-result, dirty data read hit verification sub-result, lock data read hit verification sub-result, lru data read hit verification sub-result, ecc data read hit verification sub-result and ecc_state data read hit verification sub-result.

[0112] It can be understood that the specific process of determining the associated data read hit verification result based on the tag data read hit verification sub-result, the valid data read hit verification sub-result, the dirty data read hit verification sub-result, the lock data read hit verification sub-result, the lru data read hit verification sub-result, the ecc data read hit verification sub-result and the ecc_state data read hit verification sub-result is similar to the specific process of step 205.

[0113] Step 403 : Determine the read hit verification sub-result of the target L2 cache module based on the read hit comparison result and the associated data read hit verification result.

[0114] It can be understood that the specific process of determining the read hit verification sub-result of the target L2 cache module based on the read hit comparison result and the associated data read hit verification result is similar to the specific process of step 205 .

[0115] In the verification method of the above-mentioned secondary cache module, the read hit comparison result is determined according to the third read address and the third read data, and the associated data is verified based on the preset associated data read hit verification rule and the target read and write address. Based on the read hit comparison result and the associated data read hit verification result, the read hit verification sub-result of the target secondary cache module is determined, which can not only verify that the data stored in data_mem is correct, but also ensure that the original data and the associated data are correct and are stored in the correct location according to the cache storage logic, and can realize white-box verification of the read hit of the secondary cache module, thereby improving the accuracy of the read hit verification of the secondary cache module, and then through the accuracy of the verification of the secondary cache module.

[0116] In an exemplary embodiment, as shown in FIG5 , the verification result includes a write hit verification sub-result, the target read / write data includes a fourth write address and fourth write data corresponding to the current write hit provided by an agent of a bus master connected to the digital signal processor, and the various types of storage data include original data and associated data. Based on the target read / write data, the target read / write address and the various types of storage data, the target secondary cache module is verified, and the specific process of obtaining the verification result of the target secondary cache module includes the following steps:

[0117] Step 501 : Determine third expected data corresponding to the current write hit according to a fourth write address and fourth write data.

[0118] Wherein, in the case where the target read / write data also includes the fourth read address and the fourth read data corresponding to the last read failure provided by the agent of the bus master connected to the digital signal processor, the third expected data is determined based on the fourth read address, the fourth read data, the fourth write address and the fourth write data. In the case where the target read / write data also includes the third write address and the third write data corresponding to the last write failure provided by the agent of the bus master connected to the digital signal processor, the third expected data is determined based on the second expected data, the fourth write address and the fourth write data, and the second expected data is determined based on the third write address and the third write data.

[0119] In the embodiment of the present application, the third expected data is the data that should actually be written in the current write hit, and the second expected data is the data that should actually be written in the previous write hit of the current write hit.

[0120] Step 502, compare the original data with the third expected data to obtain a write hit comparison result.

[0121] Step 503 , based on the preset associated data write hit verification rule and the target read / write address, the associated data is verified to obtain an associated data write hit verification result.

[0122] In an embodiment of the present application, the terminal compares the read tag data with the write operation address [35:18] to obtain the tag data write hit verification sub-result. The terminal determines whether the valid data read out and the bit corresponding to the read operation address [11:7] are 1. If the valid data read out and the bit corresponding to the read operation address [11:7] are 1, it means that it is valid, and the terminal determines that the valid data read failure verification sub-result indicates that the valid data read failure verification has passed. The terminal determines whether the dirty data read out and the bit corresponding to the write operation address [11:7] are 1. If the dirty data read out and the bit corresponding to the write operation address [11:7] are 1, it means that it has been modified, and the terminal determines that the dirty data write hit verification sub-result indicates that the dirty data write hit verification has passed. The terminal determines whether the lock data read out are all 0. If the lock data read out are all 0, it means that it has not been locked, and the terminal determines that the lock data write hit verification sub-result indicates that the lock data write hit verification has passed. The terminal determines whether the number of ways involved in the read operation of the lru data read out is 0, and the others are all greater than 0. If the number of ways involved in the read operation of the lru data is 0, and the others are greater than 0, it means that the lru value of the way in this group is the lowest, and the terminal determines that the lru data write hit verification sub-result indicates that the lru data write hit verification has passed. The terminal compares the read ecc data with the calculation result of the ecc_caculate function. If the read ecc data is consistent with the calculation result of the ecc_caculate function, the terminal determines that the ecc data write hit verification sub-result indicates that the ecc data write hit verification has passed. The terminal determines whether the read ecc_state data are all 0. If the read ecc_state data are all 0, it means that the ecc is valid, and the terminal determines that the ecc_state data write hit verification sub-result indicates that the ecc_state data write hit verification has passed. Then, the terminal determines the associated data write hit verification result based on the tag data write hit verification sub-result, valid data write hit verification sub-result, dirty data write hit verification sub-result, lock data write hit verification sub-result, lru data write hit verification sub-result, ecc data write hit verification sub-result and ecc_state data write hit verification sub-result.

[0123] It can be understood that the specific process of determining the associated data write hit verification result based on the tag data write hit verification sub-result, the valid data write hit verification sub-result, the dirty data write hit verification sub-result, the lock data write hit verification sub-result, the lru data write hit verification sub-result, the ecc data write hit verification sub-result and the ecc_state data write hit verification sub-result is similar to the specific process of step 205.

[0124] Step 504 : Determine the write hit verification sub-result of the target L2 cache module based on the write hit comparison result and the associated data write hit verification result.

[0125] It can be understood that the specific process of determining the write hit verification sub-result of the target L2 cache module based on the write hit comparison result and the associated data write hit verification result is similar to the specific process of step 205 .

[0126] In the verification method of the above-mentioned secondary cache module, the third expected data corresponding to the current write hit is determined according to the fourth write address and the fourth write data, the original data is compared with the third expected data, and the associated data is verified based on the preset associated data write hit verification rules and the target read and write addresses. Based on the write hit comparison result and the associated data write hit verification result, the write hit verification sub-result of the target secondary cache module is determined, which can not only verify that the data stored in data_mem is correct, but also ensure that the original data and the associated data are correct and are stored in the correct location according to the cache storage logic, and can realize white box verification of the write hit of the secondary cache module, thereby improving the accuracy of the write hit verification of the secondary cache module, and then through the accuracy of the verification of the secondary cache module.

[0127] In an exemplary embodiment, as shown in FIG6 , the verification result includes a write-back data verification sub-result, the target read-write data includes a fifth write address and fifth write data corresponding to a first write failure provided by an agent of a bus master connected to a digital signal processor, and a sixth write address, sixth write data, write-back address and write-back data corresponding to a first write failure provided by an agent of a bus slave connected to a double data rate synchronous dynamic random access memory, and based on the target read-write data, the target read-write address and various types of storage data, the target secondary cache module is verified, and the specific process of obtaining the verification result of the target secondary cache module includes the following steps:

[0128] Step 601, determining fourth expected data in the data storage of the write storage model according to the fifth write address, the sixth write address, the fifth write data and the sixth write data.

[0129] In the embodiment of the present application, the fourth expected data is the data that should actually be stored in data_mem.

[0130] Step 602, compare the write-back data with the fourth expected data to obtain a first write-back data comparison result.

[0131] Step 603, compare the write-back address with the fifth write address and the sixth write address to obtain a second write-back data comparison result.

[0132] In one example, the terminal compares the write-back address with the fifth write address and the sixth write address respectively to obtain a second write-back data comparison result.

[0133] Step 604 : Determine a write-back data verification sub-result based on the first write-back data comparison result and the second write-back data comparison result.

[0134] In the embodiment of the present application, it can be understood that the specific process of step 604 is similar to the specific process of step 205.

[0135] In the verification method of the above-mentioned secondary cache module, the fourth expected data in the data storage of the write storage model is determined according to the fifth write address, the sixth write address, the fifth write data and the sixth write data, the write-back data is compared with the fourth expected data, and the write-back address is compared with the fifth write address and the sixth write address to obtain the write-back data verification sub-result, which can realize white-box verification of the write-back data of the secondary cache module, improve the accuracy of the write-back data verification of the secondary cache module, and further improve the accuracy of the verification of the secondary cache module.

[0136] In one embodiment, the terminal performs read and write verification on the target secondary cache module through the verification system of the secondary cache module. The verification system of the secondary cache module includes: a virtual sequence generator (V_seq) and a basic test framework (Base_test). The basic test framework includes an environment (Env). The environment includes a configuration (Config), a storage model (Mem_model) corresponding to the storage area of ​​the target secondary cache module, a score comparison board (Scoreboard), a bus environment (AMBA_Env) and a design under test (DUT, i.e., the target secondary cache module). The bus environment includes: the agent of the advanced peripheral bus (APB) master (APB_Master_agent), the agent of the bus master connected to the digital signal processor (DSP) (DSP_Master_agent), the agent of the bus master connected to the bus interconnect (BUS_Master_agent), the agent of the bus slave connected to the double data rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM or DDR) (DDR_Slave_agent) and the agent of the bus slave connected to the bus interconnect (BUS_Slave_agent). The memory model includes: Tag_mem, Valid_mem, Dirty_mem, Lock_mem, Lru_mem, Data_mem, Ecc_mem and Ecc state_mem.

[0137] In one embodiment, a flowchart of the read-write invalidation verification of the target secondary cache module is shown in Figure 7. The process of performing read-write invalidation verification on the target secondary cache module includes: 1. The terminal configures the cacheability to the dut through apb_mater_agt, mainly configuring the dut to be in cacheable mode, and configuring the cacheable area, that is, the corresponding cacheable address segment. 2. The terminal performs read and write operations on the dut through dsp_mater_agt, reads the data of the cacheable address, or writes data to the cacheable address. At this time, the address segment data has not been stored inside the dut, that is, the data of the corresponding address in valid_mem is 0, and the storage data of the corresponding address in tag_mem does not match the address of the read and write operation, which is a read failure or a write failure. Regardless of the type of failure, the dut will convert this read and write operation into a read operation on ddr_slave_agt, and read the data into data_mem. If the reading is caused by a read failure, the system will synchronously update tag_mem, valid_mem, lru_mem, ecc_mem, and ecc_state_mem; if the reading is caused by a write failure, the system will increase and update dirty_mem to indicate that the data has been modified. 3. The terminal provides data to dut according to the read address and length of dut through ddr_slave_agt. 4. After ddr_slave_agt provides the data to dut, the terminal synchronously sends the address and data read this time to the scoreboard through ddr_slave_agt. 5. After dsp_master_agt receives the data read after the read failure, the terminal sends the address and data read this time to the scoreboard through dsp_master_agt; after dsp_master_agt receives the operation completion feedback after the write failure, the terminal sends the address and data written this time to the scoreboard through dsp_master_agt. 6. After the scoreboard receives the read transaction queue or write transaction queue provided by dsp_master_agt and the read transaction queue provided by ddr_salve_agt, the terminal sends all transactions to v_seq through the scoreboard.7. After v_seq receives the transaction queues provided by all scoreboards in this read and write operation, the terminal uses v_seq to read through the backdoor operation to read out all types of storage data stored in all storage class models inside dut through the initial read and write addresses of dsp_mater_agt, including data stored in data_mem, data stored in tag_mem, data stored in valid_mem, data stored in dirty_mem, data stored in lock_mem, data stored in lru_mem, data stored in ecc_mem, and data stored in ecc state_mem. Then, based on the read transaction queue or write transaction queue provided by dsp_master_agt, the read transaction queue provided by ddr_salve_agt, and various types of storage data, the terminal performs read invalidation verification or write invalidation verification on the target secondary cache module, and obtains the read invalidation verification sub-result or write invalidation verification sub-result of the target secondary cache module. Among them, the read invalidation verification sub-result or write invalidation verification sub-result is used as the judgment of whether this read and write invalidation test case passes or fails. It can be understood that the terminal performs read invalidation verification or write invalidation verification on the target secondary cache module based on the read transaction queue or write transaction queue provided by dsp_master_agt, the read transaction queue provided by ddr_salve_agt, and various types of storage data. The specific process of obtaining the read invalidation verification sub-result or write invalidation verification sub-result of the target secondary cache module is similar to the specific process of steps 201-205 or steps 301-304.

[0138] In one embodiment, a flowchart of read-write hit verification for the target secondary cache module is shown in FIG8 . The process of read-write hit verification for the target secondary cache module includes: 1. The terminal configures the DUT to be cacheable through apb_mater_agt, mainly configuring the DUT to be cacheable mode and configuring the cacheable area. 2. The terminal first performs a read failure operation or a write failure operation on the DUT through dsp_master_agt, and then keeps the read and write addresses unchanged, performs a read operation or a write operation, reads the data of the cacheable address, or writes data to the cacheable address. At this time, the DUT determines that the tag address is satisfied through address mapping, and the corresponding bit in valid_mem is 1, and the corresponding bit in dirty_mem is 0, then the DUT will not forward the operation to ddr_slave_agt, but will provide the data in the corresponding data_mem after address mapping to the dsp_master_agt, or receive the write address and data of the dsp_master_agt, and modify the data originally stored in the data_mem, which is a read hit or a write hit. If the first time is a read failure, then for this write operation, the corresponding bit position in dirty_mem must be set to 1 to indicate that it has been modified, otherwise it should remain unchanged at 1. And update lru_mem, ecc_mem, and ecc_state_mem synchronously. 3. After receiving the data read after the read hit, the terminal sends the address and data read this time to the scoreboard through dsp_master_agt; after receiving the operation completion feedback after the write hit, the terminal sends the address and data written this time to the scoreboard through dsp_master_agt. 4. After the scoreboard receives the read transaction queue or write transaction queue provided by dsp_master_agt and the read transaction queue provided by ddr_salve_agt, the terminal sends the transaction queue of the last read failure or write failure and the transaction queue of this read hit or write hit to v_seq through the scoreboard. 5. After v_seq receives the transaction queues provided by all scoreboards in this read and write operation, the terminal uses v_seq and the backdoor read operation to read out all kinds of data stored in all storage class models inside dut through the initial read and write addresses of dsp_mater_agt, including data stored in data_mem, data stored in tag_mem, data stored in valid_mem, data stored in dirty_mem, data stored in lock_mem, data stored in lru_mem, data stored in ecc_mem, and data stored in ecc state_mem.Then, the terminal performs a read hit verification or a write hit verification on the target secondary cache module based on the transaction queue of the last read failure or write failure and the transaction queue of the current read hit or write hit, as well as various types of storage data, and obtains the read hit verification sub-result or write hit verification sub-result of the target secondary cache module. Among them, the read hit verification sub-result or the write hit verification sub-result is used as the judgment of whether the current read and write hit test case passes or fails. It can be understood that the terminal performs a read hit verification or a write hit verification on the target secondary cache module based on the transaction queue of the last read failure or write failure and the transaction queue of the current read hit or write hit, as well as various types of storage data, and the specific process of obtaining the read hit verification sub-result or the write hit verification sub-result of the target secondary cache module is similar to the specific process of steps 401-403 or steps 501-504.

[0139] In one embodiment, a flowchart of the write-back operation verification of the target secondary cache module is shown in FIG9 . The process of writing back to the target secondary cache module includes: 1. The terminal configures the dut to be cacheable through apb_mater_agt, mainly to configure the dut to be cacheable mode, and configures the cacheable area, that is, the corresponding cacheable address segment. 2. The terminal first performs a write failure operation on the dut through dsp_master_agt, and writes data to the cacheable address. 3. The terminal provides data to the dut according to the read address and length of the dut through ddr_slave_agt. 4. After ddr_slave_agt provides the data to the dut, the terminal sends the address and data read this time to the scoreboard synchronously through ddr_slave_agt. 5. After dsp_master_agt receives the operation completion feedback after the write failure, the terminal sends the address and data written this time to the scoreboard through dsp_master_agt. 6. The terminal keeps the read and write address [17:7] unchanged, ensures that the cache_line remains unchanged, and changes the write address [35:18] to perform a read or write operation, causing a second read failure or write failure, that is, controlling different tag addresses and the same high-order address to construct a write failure or a read failure. At this time, dut determines that the tag address is not satisfied through address mapping, and detects that the corresponding bit in valid_mem is 1 and the corresponding bit in dirty_mem is 1. Then dut will write back the data originally stored in data_mem, and set the bit position that was originally 1 in dirty_mem to 0, and then respond according to the read failure or write failure operation. If it is a read failure, it will follow the read failure process, and if it is a write failure, it will follow the write failure process. 7. After dsp_master_agt receives the operation completion feedback after the write failure, the terminal sends the second read failure or write failure data to the scoreboard through dsp_master_agt. 8. The terminal receives the write-back data and address of dut through ddr_slave_agt. 9. The terminal sends the received write-back data and address, as well as the read-provided data of the second read failure or write failure conversion to the scoreboard through ddr_slave_agt, that is, these three operations, including 2 data providing and 1 data receiving, are all sent to the scoreboard.10. After the scoreboard receives the read transaction queue or write transaction queue provided by dsp_master_agt, the read transaction queue and the write-back transaction queue provided by ddr_salve_agt, the terminal sends the first write failure transaction queue (including the transaction queue written by dsp_master_agt for the first time and the transaction queue provided by ddr_salve_agt for the first time), the second read failure or write failure transaction queue (including the second read failure or write failure transaction queue of dsp_master_agt and the transaction queue provided by ddr_salve_agt for the second time) and the write-back transaction queue to v_seq through the scoreboard. 11. After v_seq receives the transaction queues provided by all scoreboards in this read and write operation, the terminal uses v_seq to read through the backdoor operation to read out all types of data stored in all storage class models inside dut through the initial read and write addresses of dsp_mater_agt, including data stored in data_mem, data stored in tag_mem, data stored in valid_mem, data stored in dirty_mem, data stored in lock_mem, data stored in lru_mem, data stored in ecc_mem, and data stored in ecc state_mem. Then, based on the transaction queue written by dsp_master_agt for the first time, the transaction queue provided by ddr_salve_agt for the first time, and various types of storage data, the terminal performs write failure verification on the target secondary cache module to obtain the first verification sub-result of the target secondary cache module. Then, the terminal performs read failure verification or write failure verification on the target secondary cache module based on the transaction queue of the second read failure or write failure of dsp_master_agt, the transaction queue provided by ddr_salve_agt for the second time, and various types of storage data, and obtains the second verification sub-result of the target secondary cache module. Then, the terminal performs write-back data verification on the target secondary cache module based on the transaction queue written by dsp_master_agt for the first time, the transaction queue provided by ddr_salve_agt for the first time, and various types of storage data, and obtains the write-back data verification sub-result of the target secondary cache module. Then, the terminal determines the write-back operation verification sub-result of the target secondary cache module according to the first verification sub-result, the second verification sub-result, and the write-back data verification sub-result. Among them, the write-back operation verification sub-result is used as the judgment of whether the write-back operation test case passes or not. It can be understood that the specific process of the first write failure verification and the second write failure verification is similar to the specific process of steps 301-304; the specific process of the second read failure verification is similar to the specific process of steps 201-205; the specific process of the write-back data verification is similar to the specific process of steps 601-602.

[0140] In one embodiment, the process of performing tag data error verification on the target secondary cache module includes: 1. The terminal performs cacheable configuration to dut through apb_mater_agt, mainly to configure dut to cacheable mode, and configure the cacheable area, that is, the corresponding cacheable address segment. 2. The terminal first performs a read failure or write failure operation on dut through dsp_mater_agt to read the data at the cacheable address, or write data to the cacheable address. 3. The terminal provides data to dut according to the read address and length of dut through ddr_slave_agt. 4. After ddr_slave_agt provides the data to dut, the terminal synchronously sends the read address and data to the scoreboard through ddr_slave_agt. 5. After dsp_master_agt receives the data read after the read failure, the terminal sends the address and data read this time to the scoreboard through dsp_master_agt; after dsp_master_agt receives the operation completion feedback after the write failure, the terminal sends the address and data written this time to the scoreboard through dsp_master_agt. 6. After the scoreboard receives the read transaction queue or write transaction queue provided by dsp_master_agt and the read transaction queue provided by ddr_salve_agt, the terminal sends all transactions to v_seq through scoreboard. 7. The terminal reads the storage data in the corresponding areas of all storage class models inside dut through the backdoor through v_seq. Then, based on the read transaction queue or write transaction queue provided by dsp_master_agt, the read transaction queue provided by ddr_salve_agt, and various types of storage data, the terminal performs read failure verification or write failure verification on the target secondary cache module to obtain the third verification sub-result of the target secondary cache module. 8. The terminal peeks the tag data out of the UVM_MEM backdoor, and according to the number of paths calculated by lru, changes a bit of the tag data [18:0] of the corresponding path from 1 to 0 or from 0 to 1, and then writes the modified data into the corresponding storage in tag_mem through the poke function backdoor of UVM_MEM, annotates a certain bit of the tag address to be read, keeps the address of the first read failure or write failure unchanged, performs a read operation on dut through dsp_master_agt, and repeats steps 2-7 in this embodiment.Under normal circumstances, this read operation should be a read hit, but because the storage address in tag_mem is modified by the backdoor, this read will cause a read failure. dsp_master_agt will send the read failure address and data to the scoreboard. After dut determines that the address in tag_mem is invalid, it will convert the read operation into a read of ddr_slave_agt. Then, based on the second read transaction queue provided by dsp_master_agt, the second read transaction queue provided by ddr_salve_agt, and various storage data, the terminal performs a read failure verification on the target secondary cache module to obtain the fourth verification sub-result of the target secondary cache module. Then, based on the third verification sub-result and the fourth verification sub-result, the terminal determines the tag data error verification sub-result of the target secondary cache module. It can be understood that the terminal performs read invalidation verification or write invalidation verification on the target secondary cache module based on the read transaction queue or write transaction queue provided by dsp_master_agt, the read transaction queue provided by ddr_salve_agt, and various types of storage data, and the specific process of obtaining the third verification sub-result of the target secondary cache module is similar to the specific process of steps 201-205 or steps 301-304; the terminal performs read invalidation verification on the target secondary cache module based on the read transaction queue provided by dsp_master_agt for the second time, the read transaction queue provided by ddr_salve_agt for the second time, and various types of storage data, and the specific process of obtaining the fourth verification sub-result of the target secondary cache module is similar to the specific process of steps 201-205. Among them, the flowchart of performing tag data error verification on the target secondary cache module through write invalidation operation is shown in Figure 10.

[0141] In one embodiment, the process of performing 1-bit storage data error verification on the target secondary cache module includes: 1. The terminal performs cacheable configuration to dut through apb_mater_agt, mainly to configure dut to cacheable mode, and configure the cacheable area, that is, the corresponding cacheable address segment. 2. The terminal first performs a read failure or write failure operation on dut through dsp_mater_agt to read the data of the cacheable address, or write data to the cacheable address. 3. The terminal provides data to dut according to the read address and length of dut through ddr_slave_agt. 4. After ddr_slave_agt provides the data to dut, the terminal synchronously sends the read address and data to the scoreboard through ddr_slave_agt. 5. After dsp_master_agt receives the data read after the read failure, the terminal sends the address and data read this time to the scoreboard through dsp_master_agt; after dsp_master_agt receives the operation completion feedback after the write failure, the terminal sends the address and data written this time to the scoreboard through dsp_master_agt. 6. After the scoreboard receives the read transaction queue or write transaction queue provided by dsp_master_agt and the read transaction queue provided by ddr_salve_agt, the terminal sends all transactions to v_seq through scoreboard. 7. The terminal reads the storage data in the corresponding areas of all storage class models inside dut through the backdoor through v_seq. Then, based on the read transaction queue or write transaction queue provided by dsp_master_agt, the read transaction queue provided by ddr_salve_agt, and various types of storage data, the terminal performs read failure verification or write failure verification on the target secondary cache module to obtain the third verification sub-result of the target secondary cache module. 8. The terminal changes 1 bit of the data read from the backdoor in data_mem, specifically, the data originally 1 is changed to 0, and the data originally 0 is changed to 1, and then the data is written to the original data_mem position through the backdoor write operation, and a certain bit of the data address to be read is annotated wrong, and then the same address is maintained, and the dut is read through dsp_master_agt, and steps 2-7 in this embodiment are repeated. Since the ecc calculation logic can modify 1 bit and detect 2 bit errors, this read will be a read hit. Then, based on the read transaction queue provided by dsp_master_agt for the second time, the read transaction queue provided by ddr_salve_agt for the second time, and various types of storage data, the terminal performs a read hit verification on the target secondary cache module, and obtains the fifth verification sub-result of the target secondary cache module.Then, the terminal determines the 1bit storage data error verification sub-result of the target secondary cache module based on the third verification sub-result and the fifth verification sub-result. It can be understood that the terminal performs a read hit verification on the target secondary cache module based on the read transaction queue provided by dsp_master_agt for the second time, the read transaction queue provided by ddr_salve_agt for the second time, and various types of storage data. The specific process of obtaining the fifth verification sub-result of the target secondary cache module is similar to the specific process of steps 401-403. Among them, the data in data_mem modified by the backdoor needs to be read through the UVM_MEM backdoor in this read hit comparison, confirming that the previously modified data is modified by the ecc logic and correctly written into data_mem, and comparing the data read by the backdoor with the data stored after the first read and write failure. If the data is consistent, the verification is passed. Among them, the flowchart of performing 1bit storage data error verification on the target secondary cache module through a write failure operation is shown in Figure 11.

[0142] In one embodiment, the specific process of the backdoor write operation can be: the terminal obtains the mem_model handle method in the same way as the backdoor read operation, and the poke(status, offset_addr, value) function provided by UVM_MEM is used here to store the data required to be written by the backdoor under a certain offset address offset_addr without passing through the front door logic.

[0143] It is understandable that other normal function verifications are based on basic read / write failure verification, read / write hit verification, and write-back operation verification. Other abnormal test verifications are similar to the tag data error verification process and the 1-bit storage data error verification process.

[0144] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0145] Based on the same inventive concept, the embodiment of the present application also provides a verification device for a secondary cache module for implementing the verification method for the secondary cache module involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in the embodiments of the verification device for one or more secondary cache modules provided below can refer to the limitations of the verification method for the secondary cache module above, and will not be repeated here.

[0146] In an exemplary embodiment, as shown in FIG. 12 , a verification device 1200 for a secondary cache module is provided, comprising: a construction module 1210 , a read-write module 1220 , a backdoor read module 1230 , and a verification module 1240 , wherein:

[0147] A construction module 1210 is used to construct a storage model corresponding to the storage area of ​​the target secondary cache module by using a memory model UVM_MEM device in universal verification device theory;

[0148] The read / write module 1220 is used to perform read / write operations on the target secondary cache module to obtain target read / write data and target read / write addresses;

[0149] A backdoor read module 1230 is used to perform a backdoor read operation on the storage model to obtain various types of storage data in all storage class models inside the target secondary cache module; wherein the read and write addresses corresponding to the read and write operations are consistent with the read and write addresses corresponding to the backdoor read operations;

[0150] The verification module 1240 is used to verify the target L2 cache module based on the target read / write data, the target read / write address and the various types of storage data to obtain a verification result of the target L2 cache module.

[0151] Optionally, the verification result includes a read failure verification sub-result, the target read / write data includes a first read address and first read data provided by an agent of a bus master connected to a digital signal processor, and a second read address and second read data provided by an agent of a bus slave connected to a double data rate synchronous dynamic random access memory, the various types of storage data include original data and associated data, and the verification module 1240 is specifically used to:

[0152] Compare the first read address with part or all of the second read address to obtain a first read failure address comparison sub-result, and compare the first read data with part or all of the second read data to obtain a first read failure data comparison sub-result;

[0153] Determine a first read failure comparison result according to the first read failure address comparison sub-result and the first read failure data comparison sub-result;

[0154] Comparing the original data with the second read data to obtain a second read failure comparison result;

[0155] Based on the preset associated data read failure verification rule and the target read / write address, the associated data is verified to obtain an associated data read failure verification result;

[0156] Based on the first read invalidation comparison result, the second read invalidation comparison result and the associated data read invalidation verification result, a read invalidation verification sub-result of the target secondary cache module is determined.

[0157] Optionally, the verification result includes a write failure verification sub-result, the target read / write data includes a first write address and first write data provided by an agent of a bus master connected to a digital signal processor, and a second write address and second write data provided by an agent of a bus slave connected to a double data rate synchronous dynamic random access memory, the various types of storage data include original data and associated data, and the verification module 1240 is specifically used to:

[0158] Determining first expected data written into the data storage of the storage model according to the first write address, the second write address, the first write data, and the second write data;

[0159] Comparing the original data with the first expected data to obtain a write failure comparison result;

[0160] Based on the preset associated data write failure verification rule and the target read / write address, the associated data is verified to obtain an associated data write failure verification result;

[0161] Based on the write failure comparison result and the associated data write failure verification result, a write failure verification sub-result of the target secondary cache module is determined.

[0162] Optionally, the verification result includes a read hit verification sub-result, the target read / write data includes a third read address and third read data corresponding to the current read hit provided by an agent of a bus master connected to the digital signal processor, the various types of storage data include and associated data, and the verification module 1240 is specifically used to:

[0163] Determine a read hit comparison result according to the third read address and the third read data; in a case where the target read / write data also includes a fourth read address and fourth read data corresponding to a previous read failure provided by an agent of a bus master connected to a digital signal processor, the read hit comparison result is determined based on a read hit address comparison sub-result and a read hit data comparison sub-result, the read hit address comparison sub-result is obtained based on a comparison between the fourth read address and the third read address, and the read hit data comparison sub-result is obtained based on a comparison between the fourth read data and the third read data; in a case where the target read / write data also includes a third write address corresponding to a previous write failure provided by an agent of a bus master connected to a digital signal processor, the read hit comparison result is obtained based on a comparison between second expected data and the third read data, and the second expected data is determined based on the third write address;

[0164] Based on the preset associated data read hit verification rule and the target read / write address, verify the associated data to obtain an associated data read hit verification result;

[0165] Based on the read hit comparison result and the associated data read hit verification result, a read hit verification sub-result of the target secondary cache module is determined.

[0166] Optionally, the verification result includes a write hit verification sub-result, the target read / write data includes a fourth write address and fourth write data corresponding to the current write hit provided by an agent of a bus master connected to the digital signal processor, the various types of storage data include original data and associated data, and the verification module 1240 is specifically used to:

[0167] determining, according to the fourth write address and the fourth write data, third expected data corresponding to the current write hit; in a case where the target read-write data also includes a fourth read address and fourth read data corresponding to a previous read failure provided by an agent of a bus master connected to the digital signal processor, the third expected data is determined based on the fourth read address, the fourth read data, the fourth write address and the fourth write data; in a case where the target read-write data also includes a third write address and third write data corresponding to a previous write failure provided by an agent of a bus master connected to the digital signal processor, the third expected data is determined based on the second expected data, the fourth write address and the fourth write data, and the second expected data is determined based on the third write address and the third write data;

[0168] Comparing the original data with the third expected data to obtain a write hit comparison result;

[0169] Based on a preset associated data write hit verification rule and the target read / write address, verify the associated data to obtain an associated data write hit verification result;

[0170] Based on the write hit comparison result and the associated data write hit verification result, a write hit verification sub-result of the target secondary cache module is determined.

[0171] Optionally, the verification result includes a write-back data verification sub-result, the target read-write data includes a fifth write address and fifth write data corresponding to a first write failure provided by an agent of a bus master connected to the digital signal processor, and a sixth write address, sixth write data, write-back address and write-back data corresponding to a first write failure provided by an agent of a bus slave connected to the double data rate synchronous dynamic random access memory, and the verification module 1240 is specifically used to:

[0172] Determining fourth expected data written into the data storage of the storage model according to the fifth write address, the sixth write address, the fifth write data, and the sixth write data;

[0173] Comparing the write-back data with the fourth expected data to obtain a first write-back data comparison result;

[0174] Comparing the write-back address with the fifth write-in address and the sixth write-in address to obtain a second write-back data comparison result;

[0175] A write-back data verification sub-result is determined based on the first write-back data comparison result and the second write-back data comparison result.

[0176] Each module in the verification device of the secondary cache module can be implemented in whole or in part by software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module.

[0177] In an exemplary embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be shown in FIG13. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit, and an input device. The processor, the memory, and the input / output interface are connected via a system bus, and the communication interface, the display unit, and the input device are connected to the system bus via the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner may be implemented through WIFI, a mobile cellular network, near field communication (NFC) or other technologies. When the computer program is executed by the processor, a verification method of a secondary cache module is implemented. The display unit of the computer device is used to form a visually visible picture, which may be a display screen, a projection device, or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device shell, or an external keyboard, touchpad or mouse.

[0178] Those skilled in the art will understand that the structure shown in FIG. 13 is merely a block diagram of a partial structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.

[0179] In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above-mentioned method embodiments when executing the computer program.

[0180] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0181] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0182] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0183] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0184] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0185] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A method for verifying a secondary cache module, characterized in that: The method comprises: The memory model UVM_MEM method in the universal verification methodology is used to construct a storage model corresponding to the storage area of ​​the target secondary cache module; Performing read and write operations on the target secondary cache module to obtain target read and write data and target read and write addresses; Performing a backdoor read operation on the storage model to obtain various types of storage data in all storage class models inside the target secondary cache module; wherein the read and write addresses corresponding to the read and write operations are consistent with the read and write addresses corresponding to the backdoor read operation; Based on the target read / write data, the target read / write address and the various types of storage data, the target secondary cache module is verified to obtain a verification result of the target secondary cache module.

2. The method according to claim 1, characterized in that The verification result includes a read failure verification sub-result, the target read / write data includes a first read address and first read data provided by an agent of a bus master connected to a digital signal processor, and a second read address and second read data provided by an agent of a bus slave connected to a double data rate synchronous dynamic random access memory, the various types of storage data include original data and associated data, and the verification of the target secondary cache module based on the target read / write data, the target read / write address and the various types of storage data to obtain a verification result of the target secondary cache module includes: Compare the first read address with part or all of the second read address to obtain a first read failure address comparison sub-result, and compare the first read data with part or all of the second read data to obtain a first read failure data comparison sub-result; Determine a first read failure comparison result according to the first read failure address comparison sub-result and the first read failure data comparison sub-result; Comparing the original data with the second read data to obtain a second read failure comparison result; Based on the preset associated data read failure verification rule and the target read / write address, the associated data is verified to obtain an associated data read failure verification result; Based on the first read invalidation comparison result, the second read invalidation comparison result and the associated data read invalidation verification result, a read invalidation verification sub-result of the target secondary cache module is determined.

3. The method according to claim 1, characterized in that: The verification result includes a write failure verification sub-result, the target read / write data includes a first write address and first write data provided by an agent of a bus master connected to a digital signal processor, and a second write address and second write data provided by an agent of a bus slave connected to a double data rate synchronous dynamic random access memory, the various types of storage data include original data and associated data, and the target secondary cache module is verified based on the target read / write data, the target read / write address and the various types of storage data to obtain a verification result of the target secondary cache module, including: Determining first expected data written into the data storage of the storage model according to the first write address, the second write address, the first write data, and the second write data; Comparing the original data with the first expected data to obtain a write failure comparison result; Based on the preset associated data write failure verification rule and the target read / write address, the associated data is verified to obtain an associated data write failure verification result; Based on the write failure comparison result and the associated data write failure verification result, a write failure verification sub-result of the target secondary cache module is determined.

4. The method according to claim 1, characterized in that: The verification result includes a read hit verification sub-result, the target read / write data includes a third read address and third read data corresponding to the current read hit provided by an agent of a bus master connected to a digital signal processor, the various types of storage data include and associated data, and based on the target read / write data, the target read / write address and the various types of storage data, the target secondary cache module is verified to obtain a verification result of the target secondary cache module, including: Determine a read hit comparison result according to the third read address and the third read data; in a case where the target read / write data also includes a fourth read address and fourth read data corresponding to a previous read failure provided by an agent of a bus master connected to a digital signal processor, the read hit comparison result is determined based on a read hit address comparison sub-result and a read hit data comparison sub-result, the read hit address comparison sub-result is obtained based on a comparison between the fourth read address and the third read address, and the read hit data comparison sub-result is obtained based on a comparison between the fourth read data and the third read data; in a case where the target read / write data also includes a third write address corresponding to a previous write failure provided by an agent of a bus master connected to a digital signal processor, the read hit comparison result is obtained based on a comparison between second expected data and the third read data, and the second expected data is determined based on the third write address; Based on the preset associated data read hit verification rule and the target read / write address, verify the associated data to obtain an associated data read hit verification result; Based on the read hit comparison result and the associated data read hit verification result, a read hit verification sub-result of the target secondary cache module is determined.

5. The method according to claim 1, characterized in that The verification result includes a write hit verification sub-result, the target read / write data includes a fourth write address and fourth write data corresponding to the current write hit provided by an agent of a bus master connected to a digital signal processor, the various types of storage data include original data and associated data, and the target secondary cache module is verified based on the target read / write data, the target read / write address and the various types of storage data to obtain a verification result of the target secondary cache module, including: determining, according to the fourth write address and the fourth write data, third expected data corresponding to the current write hit; in a case where the target read-write data also includes a fourth read address and fourth read data corresponding to a previous read failure provided by an agent of a bus master connected to the digital signal processor, the third expected data is determined based on the fourth read address, the fourth read data, the fourth write address and the fourth write data; in a case where the target read-write data also includes a third write address and third write data corresponding to a previous write failure provided by an agent of a bus master connected to the digital signal processor, the third expected data is determined based on the second expected data, the fourth write address and the fourth write data, and the second expected data is determined based on the third write address and the third write data; Comparing the original data with the third expected data to obtain a write hit comparison result; Based on a preset associated data write hit verification rule and the target read / write address, verify the associated data to obtain an associated data write hit verification result; Based on the write hit comparison result and the associated data write hit verification result, a write hit verification sub-result of the target secondary cache module is determined.

6. The method according to claim 1, characterized in that The verification result includes a write-back data verification sub-result, the target read-write data includes a fifth write address and fifth write data corresponding to a first write failure provided by an agent of a bus master connected to a digital signal processor, and a sixth write address, sixth write data, write-back address and write-back data corresponding to a first write failure provided by an agent of a bus slave connected to a double data rate synchronous dynamic random access memory, and the target secondary cache module is verified based on the target read-write data, the target read-write address and the various types of storage data to obtain a verification result of the target secondary cache module, including: Determining fourth expected data written into the data storage of the storage model according to the fifth write address, the sixth write address, the fifth write data, and the sixth write data; Comparing the write-back data with the fourth expected data to obtain a first write-back data comparison result; Comparing the write-back address with the fifth write-in address and the sixth write-in address to obtain a second write-back data comparison result; A write-back data verification sub-result is determined based on the first write-back data comparison result and the second write-back data comparison result.

7. A verification device for a secondary cache module, characterized in that: The device comprises: A construction module is used to construct a storage model corresponding to the storage area of ​​the target secondary cache module by using a memory model UVM_MEM device in universal verification device theory; A read / write module, used to perform read / write operations on the target secondary cache module to obtain target read / write data and target read / write addresses; A backdoor reading module, used to perform a backdoor reading operation on the storage model to obtain various types of storage data in all storage class models inside the target secondary cache module; wherein the read and write addresses corresponding to the read and write operations are consistent with the read and write addresses corresponding to the backdoor reading operations; The verification module is used to verify the target secondary cache module based on the target read-write data, the target read-write address and the various types of storage data to obtain a verification result of the target secondary cache module.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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