Partial reference memory using split logical block addresses

Abstract

The invention relates to a partial reference memory using split logical block addresses. A method includes receiving a memory operation including a logical block address (LBA). The method also includes splitting the LBA into a first portion and a second portion. The method further includes determining, using a logical-to-physical (L2P) table, a physical block of memory to map the first portion of the LBA to the physical block. The physical block includes a plurality of physical block addresses (PBAs). The method further includes combining the second portion of the LBA with the physical block to reference a physical block address (PBA) of the physical block. The method further includes performing the memory operation at the PBA of the physical block.

Description

Technical Field

[0001] The present disclosure relates generally to reference memory and, more particularly, to splitting a logical block address into portions and using a portion of the logical block address for reference memory. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] In one aspect, the present disclosure provides a method comprising: receiving a memory operation including a logical block address (LBA); splitting the LBA into a first part and a second part; using a logical-to-physical (L2P) table to determine a physical block of a memory to map the first part of the LBA to the physical block, wherein the physical block includes multiple physical block addresses (PBAs); combining the second part of the LBA with the physical block to reference a physical block address (PBA) of the physical block; and performing the memory operation at the PBA of the physical block.

[0004] In another aspect, the present disclosure provides a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: receive a memory operation comprising a logical block address (LBA); split the LBA into a first part and a second part; use a logical-to-physical (L2P) table to determine a physical block of a memory to map the first part of the LBA to the physical block, wherein the physical block comprises multiple physical block addresses (PBAs); combine the second part of the LBA with the physical block to reference a physical block address (PBA) of the physical block; and perform the memory operation at the PBA of the physical block.

[0005] In another aspect, the present disclosure provides a system comprising: a plurality of memory devices; and a processing device operably coupled to the plurality of memory devices to: receive a memory operation comprising a logical block address (LBA); split the LBA into a first part and a second part, wherein the first part of the LBA comprises one or more most significant bits of the LBA; determine a physical block of a memory using a logical-to-physical (L2P) table to map the first part of the LBA to the physical block, wherein the physical block comprises a plurality of physical block addresses (PBAs); combine the second part of the LBA with the physical block to reference a physical block address (PBA) of the physical block; and perform the memory operation at the PBA of the physical block. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and from the drawings of various embodiments of the present disclosure. However, the drawings should not be considered to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0007] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is described.

[0008] Figure 2 is a flow chart of an example method of partially referencing memory using split logical block addresses according to some embodiments of the present disclosure.

[0009] Figure 3 is another flow chart of partially referencing a memory using split logical block addresses according to some embodiments of the present disclosure.

[0010] Figure 4 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0011] Aspects of the present disclosure relate to partially referencing memory using split logical block addresses. The memory subsystem may be a storage device, a memory module, or a mixture of a storage device and a memory module. Figure 1 Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more components, such as memory devices, that store data. The host system may provide data to be stored at the memory subsystem and may request data to be retrieved from the memory subsystem.

[0012] The memory device may be a non-volatile memory device. A non-volatile memory device is a package of one or more dies. An example of a non-volatile memory device is a NAND memory device. Figure 1Other examples of non-volatile memory devices are described. A die in a package may be assigned to one or more channels for communication with a memory subsystem controller. Each die may be composed of one or more planes. Planes may be grouped into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND memory devices), each plane is composed of a set of physical blocks, which are groups of memory cells used to store data. A cell is an electronic circuit that stores information.

[0013] Depending on the cell type, a cell can store one or more bits of binary information and have various logic states related to the number of bits stored. The logic state can be represented by a binary value, such as "0" and "1" or a combination of such values. There are various types of cells, such as single-level cells (SLCs), multi-level cells (MLCs), three-level cells (TLCs), and four-level cells (QLCs). For example, an SLC can store one bit of information and have two logic states.

[0014] The memory subsystem typically uses a combination of logical addresses (e.g., logical block addresses "LBA") and physical addresses (e.g., physical block addresses "PBA") to perform memory operations (e.g., read and write operations). In particular, LBAs are used by the host system to generate memory requests (e.g., read and write requests), while PBAs are used by the memory subsystem to identify a memory element in a group of memory components to satisfy the memory request. For ease of reference, the present description refers to LBAs and PBAs, but other logical and physical addresses may be used. Furthermore, although both refer to "blocks," physical blocks and logical blocks may refer to different portions of memory. For example, a physical block may store multiple logical blocks.

[0015] To facilitate these multiple address spaces, the memory subsystem maintains a logical-to-physical (L2P) table that maps LBAs to PBAs. For example, for a memory subsystem that performs an out-of-place write operation, the memory subsystem locates a free memory element in a set of associated memory components to write the data associated with the write request to the free memory element. Thereafter, the memory subsystem records the LBA obtained in the write request and the PBA of the memory element written to the entry of the L2P table. Processes such as obsolete item collection, error correction, and wear leveling may cause the memory subsystem to move data from one physical location to another. By updating the L2P table, the memory subsystem can perform these processes without changing the logical addressing used by the host system.

[0016] Typically, the mapping of LBAs to PBAs in the L2P table occurs at the logical block address level. For example, a 4KB logical block address is mapped to a 4KB physical block address. Since conventional memory subsystems perform out-of-place write operations involving writing to a new PBA for each write command (including write commands generated from internal processes that move data), conventional memory subsystems update the L2P table for each write command.

[0017] Although recording logical to physical mappings at the LBA level allows the memory subsystem to manage memory components at a granular level, this flexibility comes at the expense of size. As non-volatile storage devices grow in size and volatile memory resources are limited, the memory subsystem cannot load the entire L2P table into main memory during normal operation. Instead, the memory subsystem maintains the entire L2P table in high-latency but sufficient non-volatile memory and only loads a subset of entries / mappings from the L2P table into a lower-latency but more limited volatile main memory. In this configuration, the memory subsystem swaps the relevant entries / mappings of the L2P table from non-volatile memory to a portion of the L2P table in the volatile media as needed. The process of moving and maintaining portions of the L2P table between different media adds considerable overhead to performing memory operations, including latency. This overhead may outweigh the benefits of fine granularity in addressing. This is especially true when this addressing scheme is used in write-in-place memory, because write-in-place memory reduces the need to move data (e.g., a process can overwrite data in an existing physical location instead of writing data to a new physical location).

[0018] Aspects of the present disclosure address the above and other deficiencies by loading a smaller granularity L2P table in a volatile memory. The L2P table maps a range of LBAs to a physical block of a non-volatile memory. Mapping a range of LBAs to a physical block of a non-volatile memory reduces the size of the L2P table without changing the logical block addressing. A mapping manager divides a received LBA into a first and a second portion or subset. The mapping manager uses the L2P table to map a first portion or subset of the LBA to a physical block of a non-volatile memory. The second portion or subset of the LBA indicates an offset within the physical block. The mapping manager combines the second portion / subset of the LBA with the determined physical block to reference a physical block address (PBA) (e.g., an offset within a physical block). This smaller granularity L2P table can be made small enough to be fully cached in a volatile memory or at least reduce the amount of exchange of L2P table entries between the volatile memory and the non-volatile memory, thereby reducing conventional address management overhead.

[0019] Figure 1An example computing system 100 is illustrated that includes a memory subsystem 110 in accordance with some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0020] The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage devices (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0021] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, automobile, or other transportation vehicle), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0022] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0023] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110 to, for example, write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0024] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Small Computer System Interface (SCSI), a Double Data Rate (DDR) memory bus, a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM slot interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120 . Figure 1 Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0025] Memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0026] Some examples of non-volatile memory devices (e.g., memory device 130) include non-and (NAND) type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can perform bit storage based on body resistance changes in combination with a stackable cross-gate data access array. In addition, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without previously erasing the non-volatile memory cells. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0027] Although nonvolatile memory devices such as NAND-type memories (e.g., 2D NAND, 3D NAND) and 3D cross-point arrays of nonvolatile memory cells are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), non-OR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0028] The memory subsystem controller 115 (or, for simplicity, the controller 115) may communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations (e.g., in response to commands dispatched by the controller 115 on a command bus). The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

[0029] The memory subsystem controller 115 may include a processing device 117 (processor) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0030] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 is illustrated as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem 110).

[0031] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130 and / or the memory device 140. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBA), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130 and / or the memory device 140, and convert responses associated with the memory device 130 and / or the memory device 140 into information for the host system 120.

[0032] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0033] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may manage memory device 130 externally (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0034] The memory subsystem 110 includes a mapping manager 113 that can split an LBA into multiple parts and use each of the multiple parts of the LBA to reference memory. The mapping manager 113 can map a first part of a received LBA to a physical block mapped to a range of the LBA. The mapping manager 113 uses a second part of the received LBA as an offset to reference the PBA of the physical block. In some embodiments, the controller 115 includes at least a portion of the mapping manager 113. For example, the controller 115 may include a processor 117 (processing device) that is configured to execute instructions stored in a local memory 119 for performing the operations described herein. In some embodiments, the mapping manager 113 is part of a host system 120, an application, or an operating system.

[0035] The mapping manager 113 can manage a complete L2P table in volatile memory. The mapping manager 113 updates the L2P table in volatile memory only in response to maintenance operations acting on physical blocks of non-volatile memory. Therefore, the mapping manager 113 does not need to query the non-volatile memory for entries / mappings of the L2P table. The limited management of the complete L2P table in volatile memory reduces the latency traditionally involved in performing memory operations. Additional details about the operation of the mapping manager 113 are described below.

[0036] Figure 2 is a flowchart of an example method of partially referencing memory using split logical block addresses according to some embodiments of the present disclosure. It should be appreciated that although a single L2P table is described, a processing device (eg, mapping manager 113) may manage multiple L2P tables cached in volatile memory.

[0037] Method 200 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 200 is performed by Figure 1 The mapping manager 113 of the embodiment of the present invention is executed. Although shown in a specific sequence or order, unless otherwise specified, the order of the process can be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0038] At operation 205, the processing device loads a full / complete copy of the L2P table as stored in non-volatile memory into volatile memory. Unlike conventional systems that map LBAs to PBAs and may only cache a subset of the full L2P table in volatile memory, since the L2P table maps ranges of LBAs to physical blocks of non-volatile memory, the entire smaller granularity L2P table may be cached in volatile memory. In some embodiments, the mapping manager 113 loads the L2P table during boot. In some embodiments, the mapping manager 113 loads a portion of the L2P table, but the smaller granularity of the L2P table allows the mapping manager 113 to reduce L2P entry swapping, flushing, and other overhead.

[0039] At operation 210, the processing device determines whether the received operation is a maintenance operation. The received operation may be a read operation that directs the mapping manager 113 to one or more LBAs of one or more locations / addresses of non-volatile memory containing data to be read. The received operation may also be a write operation that identifies data to be written to the one or more LBAs. The received operation may be an internal operation (e.g., originating from the memory subsystem 110) or an external operation (e.g., originating from the host system 120).

[0040] In some embodiments, the mapping manager 113 compares the received operation to a predetermined list of maintenance operations. Maintenance operations include read / write operations associated with internal management of the memory subsystem 110, including obsolete item collection, wear leveling, and the like. Additionally or alternatively, the mapping manager 113 determines that any operation received from the host system 120 is not a maintenance operation. If the received operation is a maintenance operation, then the operational flow moves to operation 215. If the received operation is not a maintenance operation, then the operational flow moves to operation 225.

[0041] At operation 215, the processing device performs a maintenance operation. For example, to perform a wear leveling operation, the mapping manager 113 moves data written to one or more first PBAs stored at a first physical block to one or more second PBAs stored at a second physical block of the non-volatile memory. In some embodiments, the mapping manager 113 performs a number of read / write operations equal to the number of PBAs of the physical block to move each of the PBAs of the physical block to the PBA of the second physical block. In other embodiments, the mapping manager 113 recognizes a single dedicated operation configured to move data of each of the PBAs of the physical block to the PBA of another physical block. In this way, instead of performing multiple read / write operations, a single dedicated command reads the data at the PBA of the first physical block and then writes the data to the PBA of the second physical block.

[0042] At operation 220, the processing device updates the L2P table in the volatile memory. As described herein, the L2P table cached in the volatile memory maps each LBA range to a corresponding physical block (e.g., mapping a first LBA range to a first physical block, mapping a second LBA range to a second physical block, etc.). In some embodiments, each entry of the L2P table maps the LBA range to a single physical block using a common value in a portion of the LBAs. For example, each LBA in the LBA range shares the same value in the most significant bit (MSB). Therefore, when the mapping manager 113 changes the physical block associated with the LBA range (as is typically performed during a maintenance operation), the mapping manager 113 updates the L2P table in the volatile memory. For example, the mapping manager 113 remaps the common MSB value mapped to the previous physical block to the new physical block. The mapping manager 113 synchronizes the L2P table in the volatile memory by refreshing the new mappings of one or more physical blocks of the L2P table affected by the maintenance operation to the L2P table stored in the non-volatile memory. Given that the granularity of the L2P table is smaller than that of a regular L2P table, the granularity of synchronization is at the physical block level.

[0043] At operation 225, the processing device determines a physical block that maps to the LBA. For example, the mapping manager 113 splits the LBA into multiple portions. The portions of the LBA may include one or more most significant bits, one or more least significant bits (LSBs), or some other combination of portions of the LBA. In a non-limiting example, a first portion of the LBA includes one or more MSBs of the LBA and a second portion of the LBA includes one or more LSBs of the LBA. The mapping manager 113 uses the values ​​read from the MSBs or otherwise determined to look up a mapping to a physical block in the L2P table, where a range of LBAs that share a common MSB value maps to a single physical block of memory. For example, the mapping manager 113 uses the first portion / MSB of the split LBA (i.e., excluding the second portion / LSB of the split LBA) to look up a mapping between the values ​​of the first portion and the physical block.

[0044] At operation 230, the processing device combines the second portion / LSB of the LBA with the physical block to reference the PBA of the physical block. The physical block of the non-volatile memory includes a range of PBAs. Each PBA is located at a position defined by an offset in each physical block. For example, the 12th PBA is located at an offset of 12 in the physical block. In a non-limiting example, the mapping manager 113 uses one or more LSBs of the LBA to reference the offset / PBA. In one embodiment, in addition to the split, the second portion / LSB of the LBA remains unchanged from receipt when combined with the physical block. For example, the mapping manager 113 does not use a table, scrambling or other algorithm or translation to map the second portion / LSB to a different value.

[0045] In one embodiment, the mapping manager 113 determines which bits of the LBA are used as offsets based on the number of PBAs per physical block. The larger the PBA range of a physical block, the more bits of the LBA used to reference the PBA of the physical block. In contrast, the smaller the PBA range of a physical block, the fewer bits of the LBA used to reference the PBA of the physical block.

[0046] In a non-limiting example, each physical block of non-volatile memory maps 64 LBAs to 64 PBAs. The entries of the L2P table map the MSB value to the physical block. The mapping manager 113 uses the MSB count and the LSB count to split the LBA. As described herein, the number of MSBs and / or LSBs depends on the number of physical blocks and the number of PBAs per physical block. In this example, 6 bits are required to address each of the 64 addresses of the physical block because the physical block includes 64 PBAs. Therefore, the mapping manager 113 maps at least 6 least significant bits of the LBA to identify the offset that identifies the location of the PBA within the physical block. The mapping manager 113 uses the remaining bits (i.e., the MSB) to find the physical block in the L2P table.

[0047] At operation 235, the processing device performs a memory operation (e.g., a read / write request not involved in the maintenance operation). If the memory operation is a read request, the read request is performed at the offset location of the physical block (i.e., the PBA). In one embodiment, the read operation is performed in a byte-addressable non-volatile memory. In general, the read operation involves applying a voltage to a word line that supplies power to a transistor (e.g., a memory cell of a memory subsystem). If the memory operation is a write request, the write operation is performed at the offset location of the physical block. As described herein, the in-situ write operation does not depend on the availability of the PBA. Therefore, the mapping manager 113 can perform a write operation to overwrite the data at the PBA. Since the L2P described herein does not map the LBA to the PBA (but maps the LBA to the physical block of the non-volatile memory), the mapping manager 113 does not need to update the L2P table cached in the volatile memory in response to the in-situ write operation. In some embodiments, mapping manager 113 updates the L2P table stored in non-volatile memory when memory subsystem 110 is powered off, during idle mode, or during any other time period that will not affect the performance of memory subsystem 110 .

[0048] In a non-limiting example, 256 physical blocks each map 64 LBAs to 64 PBAs. In an example, the mapping manager 113 receives a read request addressing a range of LBAs, where each LBA in the range represents a 14-bit address. The mapping manager 113 splits each 14-bit LBA into a first portion and a second portion, where the first portion includes 8 MSB values ​​that reference a physical block in the 256 physical blocks, and the second portion includes 6 LSB values ​​that reference an offset of the 64 PBAs of the physical block. The mapping manager 113 uses the L2P table described herein to match the MSB value to the physical block. Then, the mapping manager 113 uses the LSB value as an offset value from the starting point of the physical block. Subsequently, the mapping manager 113 performs a read operation at the PBA.

[0049] Figure 3 1 is a flow chart of an example method 300 for partially referencing memory using split logical block addresses according to some embodiments of the present disclosure. The method 300 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 300 is performed by Figure 1 The mapping manager 113 of the embodiment of the present invention is executed. Although shown in a specific sequence or order, unless otherwise specified, the order of the process can be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0050] At operation 305, the processing device receives a memory operation. The memory operation may be a read request or a write request. If the memory operation is a read request, the read request may indicate one or more LBAs that direct the processing device to one or more locations / addresses of the memory containing the data to be read. If the memory operation is a write request, the write request may identify the data to be written to the one or more LBAs.

[0051] At operation 310, the processing device splits the LBA into a first portion and a second portion. As described with reference to operation 225, the mapping manager 113 splits the LBA into a plurality of portions, where the portions of the LBA may include one or more most significant bits, one or more least significant bits, or some other combination of portions of bits of the LBA. In one embodiment, the first portion includes one or more MSBs of the LBA, and the second portion includes one or more LSBs of the LBA.

[0052] At operation 315, the processing device uses the L2P table and the first portion of the LBA to determine a physical block of memory. As described with reference to operation 225, the mapping manager 113 uses the L2P table to map the value determined from the MSB to a physical block, where a range of LBAs sharing a common MSB value is mapped to a single physical block of memory.

[0053] At operation 320, the processing device combines the second portion of the LBA with the physical block to reference the PBA of the physical block. The mapping manager uses one or more bits of the LSB as the second portion of the LBA as described with reference to operation 230. The one or more bits of the LSB indicate an offset of the physical block to reference the PBA of the physical block.

[0054] At operation 325, the processing device performs a memory operation at the PBA of the physical block. Referring to operation 235, the mapping manager performs a read request or a write request at the PBA referenced using an offset of the physical block.

[0055] Figure 4 An example machine illustrating a computer system 400 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 400 may correspond to a host system (e.g., Figure 1 ) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110 of the controller may be used to execute the operation of the controller (for example, execute the operating system to execute the corresponding Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client user machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client user machine in a cloud computing infrastructure or environment.

[0056] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Furthermore, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0057] The example computer system 400 includes a processing device 402, a main memory 404 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 406 (e.g., flash memory, static random access memory (SRAM)), etc.), and a data storage system 418, which communicate with each other via a bus 430.

[0058] The processing device 402 represents one or more general purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets or multiple processors implementing a combination of instruction sets. The processing device 402 may also be one or more special purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 402 is configured to execute instructions 426 for performing the operations and steps discussed herein. The computer system 400 may further include a network interface device 408 to communicate over a network 420.

[0059] The data storage system 418 may include a machine-readable storage medium 424 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 426 or software embodying any one or more of the methodologies or functions described herein. The instructions 426 may also reside completely or at least partially within the main memory 404 and / or within the processing device 402 during execution thereof by the computer system 400, the main memory 404 and the processing device 402 also constituting machine-readable storage media. The machine-readable storage medium 424, the data storage system 418, and / or the main memory 404 may correspond to Figure 1 Memory subsystem 110.

[0060] In one embodiment, instructions 426 include instructions for implementing instructions corresponding to a mapping manager (e.g., Figure 1 The machine-readable storage medium 424 is shown as a single medium in the example embodiment, but the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any one or more of the methodologies of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include (but not limited to) solid-state memory, optical media, and magnetic media.

[0061] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here and generally conceived to be a self-consistent sequence of operations leading to a desired result. Operations are those requiring physical manipulation of physical quantities. Typically, although not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0062] It should be remembered, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may involve actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0063] The present disclosure also relates to an apparatus for performing the operations herein. Such an apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. For example, a computer system or other data processing system (e.g., mapping manager 113) may perform computer-implemented methods 200 and / or 300 in response to its processor executing a computer program (e.g., sequence of instructions) contained in a memory or other non-transitory machine-readable storage medium. Such a computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0064] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used in conjunction with programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. The structures of a variety of these systems will appear as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0065] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form that can be read by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0066] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be appreciated that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings should be viewed in an illustrative rather than a restrictive sense.

Claims

1. A method comprising: receiving a memory operation including a logical block address LBA; Splitting the LBA into a first part and a second part; determining a physical block of memory using a logical-to-physical L2P table to map the first portion of the LBAs to the physical block, wherein the physical block includes a plurality of physical block addresses PBAs; combining the second portion of the LBA with the physical block to reference a physical block address PBA of the physical block; and The memory operation is performed at the PBA of the physical block.

2. The method of claim 1, wherein the first portion of the LBA includes one or more most significant bits of the LBA.

3. The method of claim 1, wherein the second portion of the LBA comprises one or more least significant bits.

4. The method of claim 1 , wherein performing the memory operation at the PBA of the physical block further comprises: An in-place write operation is performed to write data at the PBA.

5. The method according to claim 1, further comprising: The data written to the plurality of PBAs of the physical block is moved to a second plurality of PBAs of a second physical block using a single command.

6. The method according to claim 5, further comprising: The L2P table is updated by remapping a set of one or more most significant bits of the LBA to the second physical block.

7. The method according to claim 1, further comprising: The L2P table is loaded into a cache in volatile memory, wherein the loaded L2P table is a complete copy of the L2P table as stored in non-volatile memory.

8. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: receiving a memory operation including a logical block address LBA; Splitting the LBA into a first part and a second part; determining a physical block of memory using a logical-to-physical L2P table to map the first portion of the LBAs to the physical block, wherein the physical block includes a plurality of physical block addresses PBAs; combining the second portion of the LBA with the physical block to reference a physical block address PBA of the physical block; and The memory operation is performed at the PBA of the physical block.

9. The non-transitory computer-readable storage medium of claim 8, wherein the first portion of the LBA includes one or more most significant bits of the LBA.

10. The non-transitory computer-readable storage medium of claim 8, wherein the second portion of the LBA includes one or more least significant bits.

11. The non-transitory computer-readable storage medium of claim 8, wherein performing the memory operation at the PBA of the physical block further causes the processing device to: An in-place write operation is performed to write data at the PBA.

12. The non-transitory computer-readable storage medium of claim 8, wherein the processing device is further configured to: The data written to the plurality of PBAs of the physical block is moved to a second plurality of PBAs of a second physical block using a single command.

13. The non-transitory computer-readable storage medium of claim 12, wherein the processing device is further configured to: The L2P table is updated by remapping a set of one or more most significant bits of the LBA to the second physical block.

14. The non-transitory computer-readable storage medium of claim 8, wherein the processing device is further configured to: The L2P table is loaded into a cache in volatile memory, wherein the loaded L2P table is a complete copy of the L2P table as stored in non-volatile memory.

15. A system comprising: a plurality of memory devices; and a processing device operably coupled to the plurality of memory devices to: receiving a memory operation including a logical block address LBA; splitting the LBA into a first portion and a second portion, wherein the first portion of the LBA includes one or more most significant bits of the LBA; determining a physical block of memory using a logical-to-physical L2P table to map the first portion of the LBAs to the physical block, wherein the physical block includes a plurality of physical block addresses PBAs; combining the second portion of the LBA with the physical block to reference a physical block address PBA of the physical block; and The memory operation is performed at the PBA of the physical block.

16. The system of claim 15, wherein the second portion of the LBA includes one or more least significant bits.

17. The system of claim 15, wherein performing the memory operation at the PBA of the physical block further serves to: An in-place write operation is performed to write data at the PBA.

18. The system of claim 15, wherein the processing device is further configured to: The data written to the plurality of PBAs of the physical block is moved to a second plurality of PBAs of a second physical block using a single command.

19. The system of claim 18, wherein the processing device is further configured to: The L2P table is updated by remapping a set of one or more most significant bits of the LBA to the second physical block.

20. The system of claim 15, wherein the processing device is further configured to: The L2P table is loaded into a cache in volatile memory, wherein the loaded L2P table is a complete copy of the L2P table as stored in non-volatile memory.

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