Novel fault-tolerant programmable chip architecture and compiling method

Abstract

The invention discloses a novel fault-tolerant programmable chip architecture and a compiling method. The architecture comprises a global bus controller, a global bus, a plurality of programmable function blocks and a plurality of bus interface units, each programmable function block corresponds to one bus interface unit; the global bus controller issues an instruction to the programmable function block by using a global bus according to the compiling program; and the programmable function block performs self-inspection according to instruction requirements, when a fault unit is found, a blank unit is adopted to replace the fault unit until no blank unit exists, and a resource exhaustion state is reported to the global bus controller. According to the invention, a three-level architecture of system-function block-logic unit is used, and faults are diagnosed and repaired from bottom to top. According to the invention, the global bus and the local bus are separated, so that the fault occurrence rate is reduced; the problem of resource utilization rate is solved by adopting editable function block splitting combining coarse granularity and fine granularity.

Description

Technical Field

[0001] The present invention relates to the technical field of programmable logic devices, and in particular to a novel fault-tolerant programmable chip architecture and a compiling method. Background Art

[0002] Since its invention in the 1970s, programmable logic devices (PLDs) have always been more flexible than application-specific integrated circuits (ASICs). Its characteristics can be attributed to the flexibility to change the function of the device by changing the logic and interconnection of its internal circuits through programs. Since its invention, PLD devices have been widely used in the rapid prototyping of integrated circuits, but in recent years, they have also been used in reliability electronic systems. Reliability electronic systems require that their circuits can still function normally when a fault occurs.

[0003] The common practice of using PLD devices in reliable electronic systems is to divide the logic circuit into several logic blocks according to function and data dependence, and configure these logic blocks in the PLD device through EDA software. In addition to all the logic blocks, a blank block should be reserved inside the PLD device for fault tolerance protection. When an internal fault occurs, the PLD device should quickly locate the damaged part, shield the logic block where it is located, and configure its function in the blank block, and redirect the original system interconnection to the newly configured functional block. If this process can be completed within one data processing cycle, then the system will not be affected by the fault. Therefore, the reliability of the system depends to a large extent on the ability of fault self-detection and functional block reconstruction.

[0004] However, there are several practical problems with the existing technology:

[0005] 1) The impact of unified unit architecture on fault tolerance. The existing PLD architecture is a unified and uniform two-level architecture, and a device can be divided into two levels: "device-logic unit". Except for proprietary functional modules (such as DSP, SRAM, etc.), the structure of all programmable logic units is exactly the same and is evenly distributed in the chip core. However, from a functional point of view, we have three levels: "system-functional block-logic unit". This contradiction has caused that a logical functional block cannot be completely configured on a physically close logical unit. Moreover, several functional blocks are often configured in a piece of physical space in a sporadic and overlapping manner, and are closely connected to each other at the logical unit level. This "close connection" between logical units will make it impossible for the system to quickly locate the faulty logical block, and it is also impossible to easily and flexibly change the interconnection of functional blocks.

[0006] 2) The impact of the granularity of programmable logic units on the "performance-resource" relationship. According to the size of the function, logic units can be divided into two categories: fine-grained and coarse-grained, or three categories: fine-grained, medium-grained, and coarse-grained. For example, gate circuits belong to fine-grained, processing micro-cores belong to coarse-grained, multiplication-addition-accumulation units belong to medium-grained, and so on. In order to resolve the contradiction between the two-level hardware structure and the three-level functional structure, the general approach is to increase the granularity of programmable logic units, such as using uniform medium-grained and coarse-grained units for all, or inserting a small number of intermediate-grained and coarse-grained special units between fine-grained units. However, rigidly increasing the granularity of programmable units will inevitably lead to a waste of resources.

[0007] 3) The contradiction between the complexity, flexibility and effectiveness of the interconnection bus. Another problem with the unified unit architecture is the architecture of the on-chip interconnection bus. In order to achieve the global interconnection function, about 70% of the silicon resources in a PLD device are used as the global interconnection bus and its control logic. On the one hand, this interconnection mechanism greatly wastes the silicon efficiency of the chip, and on the other hand, it also becomes the biggest potential factor for failure. Once a part of the global interconnection fails, the overall function of the chip will be greatly affected.

[0008] 4) How to compile high-level languages ​​into configuration instructions for this programmable architecture is also a very complex software-hardware co-design. A compiler is needed that can convert high-level languages ​​into machine configuration instructions for a hierarchical fault-tolerant programmable chip architecture. In general, machine configuration instructions are divided into "inter-block data transfer instructions" and "functional block configuration bit streams." Among them, "inter-block data transfer instructions" are used to operate the global bus to transfer data between functional blocks; "functional block configuration bit streams" assign certain logical functions to the programmable logic units in the corresponding functional blocks. This is equivalent to the compiler not only automatically generating processor instructions, but also automatically optimizing the definition of the functional units in the processor. Due to the uniqueness of the hierarchical fault-tolerant programmable chip architecture, such compilers are currently difficult to implement. Summary of the invention

[0009] Therefore, the purpose of the present invention is to provide a new fault-tolerant programmable chip architecture, which adopts a three-level architecture of "system-functional block-logic unit" to provide bottom-up diagnosis and repair of faults, improve the efficiency of fault protection and improve the reliability of key electronic equipment in the control system while improving silicon efficiency.

[0010] In order to achieve the above-mentioned object, the present invention provides a novel fault-tolerant programmable chip architecture, comprising: a global bus controller, a global bus, a plurality of programmable function blocks, and a plurality of bus interface units; each of the programmable function blocks corresponds to a bus interface unit;

[0011] The global bus controller sends instructions to the programmable function blocks using the global bus according to the compiled program;

[0012] The programmable function block performs self-check according to the instruction requirements. When a faulty unit is found, a blank unit is used to replace the faulty unit until there are no more blank units, and the resource exhaustion status is reported to the global bus controller.

[0013] Further preferably, the programmable function block comprises a fixed number of programmable logic units, interconnection routing and self-checking units;

[0014] The programmable logic unit is used to store instructions;

[0015] The interconnection routing is used to convert the issued instructions and the stored instructions into the addresses of the corresponding programmable logic units;

[0016] The self-checking unit is used for fault detection, and when an error is found, an alarm is sent to the global bus controller through the status bus.

[0017] Further preferably, the global bus controller includes a program counter, a state detector and an address mapping table;

[0018] The program counter is connected to the global data bus and is used to generate the address of the next instruction sequence;

[0019] The address mapping table is connected to the global address bus and is used to convert instructions in the external or internal read-only memory into the physical port addresses of the corresponding programmable function blocks;

[0020] The status detector is used to obtain the health status of each programmable functional unit. When receiving a warning that the functional block resources are exhausted, its functions are immediately configured to the blank programmable functional block; and the content of the address mapping table is modified, the corresponding physical port address is changed, the faulty programmable functional block is shielded, and the newly configured programmable functional block is enabled.

[0021] The present invention also provides a compilation method for a novel fault-tolerant programmable chip architecture, comprising the following steps:

[0022] The compiler's front end parses the high-level language into an intermediate language;

[0023] Use the LLVM compiler to convert the intermediate language into standard single static assignment SSA form virtual machine instructions;

[0024] The virtual machine instructions in SSA form are converted into hardware description language HDL, data is transferred to the programmable function block according to the configuration instructions, and specific logical functions are determined for the programmable function block.

[0025] Further preferably, it also includes issuing machine configuration instructions using a hardware description language HDL, wherein the machine configuration instructions include inter-block data transmission instructions and a function block configuration bit stream; the inter-block data transmission instructions are used to operate the global bus to transfer data between programmable function blocks PFB, and the function block configuration bit stream assigns specific logic functions to the programmable logic units in the corresponding programmable function blocks PFB.

[0026] Further preferably, determining a specific logic function for a programmable function block includes dividing all programmable function blocks in a loop recursive optimization form, including:

[0027] S01, divide all programmable function blocks into coarse-grained divisions.

[0028] S02, generating inter-block transmission instructions and function block configuration bit streams according to the issued machine configuration instructions;

[0029] S03, judging the capacity of the largest programmable function block and the total number of programmable function blocks according to the inter-block transmission instruction and the function block configuration bit stream; when the total number of programmable function blocks exceeds the limit threshold, the splitting is terminated, otherwise, the programmable function blocks are finely divided;

[0030] S04, searching for fine-grained programmable function blocks with consistent functions, and updating the list of programmable function blocks;

[0031] S05. Generate inter-block transfer instructions and function block configuration bit streams again according to the generated new list, repeat the above S03-S04 process until the total number of programmable function blocks exceeds the limit threshold, and then end the splitting.

[0032] Further preferably, it also includes determining whether the capacity of the largest programmable functional block exceeds the first threshold value, and if so, subdividing the largest programmable functional block; if not, continuing to determine whether the total number of programmable functional blocks exceeds the quantity limit, and if so, terminating the division of programmable functional blocks, and if not, subdividing the largest programmable functional block.

[0033] The novel fault-tolerant programmable chip architecture and its compilation method disclosed in the present application use a three-level architecture of "system-functional block-logic unit" to provide bottom-up diagnosis and repair of faults. The characteristics of field programmable gate array (FPGA) are reflected in each functional block. A general compiler can be used to convert common high-level programming languages ​​into machine configuration instructions corresponding to the hardware, separate the global bus and the local bus, and reduce the occurrence of faults; a combination of coarse-grained and fine-grained editable functional block splitting is used to solve the problem of resource utilization. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1A schematic diagram of the structure of the novel fault-tolerant programmable chip architecture provided by the present invention.

[0035] Figure 2 A schematic diagram of a programmable logic function block provided by the present invention.

[0036] Figure 3 A structural schematic diagram of a global bus controller is provided for the present invention.

[0037] Figure 4 A schematic flow chart of a novel fault-tolerant programmable chip compilation method provided by the present invention. DETAILED DESCRIPTION

[0038] The present invention is further described in detail below through the accompanying drawings and specific embodiments.

[0039] like Figure 1 As shown, an embodiment of the present invention provides a novel fault-tolerant programmable chip architecture, comprising: a global bus controller 1, a global bus 2, a plurality of programmable function blocks 3, and a plurality of bus interface units 4; each of the programmable function blocks corresponds to a bus interface unit;

[0040] The global bus controller sends instructions to the programmable function blocks using the global bus according to the compiled program;

[0041] The programmable function block performs self-check according to the instruction requirements. When a faulty unit is found, a blank unit is used to replace the faulty unit until there are no more blank units, and the resource exhaustion status is reported to the global bus controller.

[0042] like Figure 2 As shown, further preferably, the programmable function block includes a fixed number of programmable logic units 5, interconnection routing 6 and self-checking units 7;

[0043] The programmable logic unit is used to store instructions;

[0044] The interconnection routing is used to convert the issued instructions and the stored instructions into the addresses of the corresponding programmable logic units;

[0045] The self-check unit is used for fault detection. When an error is found, an alarm is sent to the global bus controller through the status bus. Using the traditional dynamic reconstruction technology, the faulty unit is shielded and replaced with a blank unit. This repair process stops when there are no more blank programmable logic units in the programmable function block. This resource exhaustion state is reported to the global bus controller through the global status bus, requesting the implementation of a "programmable function block level" repair.

[0046] like Figure 3As shown, further, the global bus controller includes a program counter, a state detector and an address mapping table;

[0047] The program counter is connected to the global data bus and is used to generate the address of the next instruction sequence;

[0048] The address mapping table is connected to the global address bus and is used to convert the instructions in the external or internal read-only memory into the physical port address of the corresponding programmable function block; the address mapping table is an SRAM structure, and the state detector is used to obtain the health status of each programmable function unit. When receiving a warning that the function block resources are exhausted, its function is immediately configured to a blank programmable function block; and the content of the address mapping table is modified, the corresponding physical port address is changed, the faulty programmable function block is shielded, and the newly configured programmable function block is enabled. When the state checker receives a warning that the function block resources are exhausted, its function is immediately configured to a blank programmable function block. And by changing the content of the address mapping table unit, the physical port address corresponding to the instruction is changed, thereby shielding the faulty programmable function block and enabling the newly configured function block. This architecture can self-repair until there are no more available blank programmable function blocks in the chip.

[0049] like Figure 4 As shown, the present invention also provides a compilation method for a novel fault-tolerant programmable chip architecture, comprising the following steps:

[0050] The compiler's front end parses the high-level language into an intermediate language;

[0051] Use the LLVM compiler to convert the intermediate language into standard single static assignment SSA form virtual machine instructions;

[0052] The virtual machine instructions in SSA form are converted into hardware description language HDL, data is transferred to the programmable function block according to the configuration instructions, and specific logical functions are determined for the programmable function block.

[0053] Furthermore, it also includes issuing machine configuration instructions using a hardware description language HDL, wherein the machine configuration instructions include inter-block data transmission instructions and a function block configuration bit stream; the inter-block data transmission instructions are used to operate a global bus to transfer data between programmable function blocks PFB, and the function block configuration bit stream assigns specific logic functions to the programmable logic units in the corresponding programmable function blocks PFB.

[0054] like Figure 4 As shown, the specific logic functions for the programmable function blocks are determined, including dividing all programmable function blocks in the form of loop recursive optimization, including:

[0055] S01, divide all programmable function blocks into coarse-grained divisions,

[0056] S02, generating inter-block transmission instructions and function block configuration bit streams according to the issued machine configuration instructions;

[0057] S03. According to the inter-block transmission instruction and the function block configuration bit stream, the capacity of the largest programmable function block and the total number of programmable function blocks are determined; when the total number of programmable function blocks exceeds the limit threshold, the splitting is terminated, otherwise, the programmable function blocks are finely divided; it also includes determining whether the capacity of the largest programmable function block exceeds the first threshold, if so, the largest programmable function block is subdivided; if not, continue to determine whether the total number of programmable function blocks exceeds the quantity limit, if so, terminate the division of programmable function blocks, if not, the largest programmable function block is subdivided.

[0058] S04, searching for fine-grained programmable function blocks with consistent functions, and updating the list of programmable function blocks;

[0059] S05. Generate inter-block transfer instructions and function block configuration bit streams again according to the generated new list, and repeat the above-mentioned process of S03-S04 until the total number of programmable function blocks exceeds the limit threshold, and then end the splitting.

[0060] This compilation process is divided into three parts: front-end, middle-end and back-end processing. The front-end processing can use the front-end of a general compiler (such as GCC frontend, Clang, etc.) to convert a high-level language, such as C / C++, Java, Fortran, into a standard intermediate language (Intermediate Language). Then, by using the middle-end of the open source LLVM compiler, the intermediate language is compiled and converted into standard single static assignment (SSA) virtual machine instructions. LLVM's virtual machine instructions are independent of the physical machine. Therefore, in this method, the only thing that needs to be customized by the user is a compiler back-end that converts SSA into machine configuration instructions.

[0061] As mentioned above, the machine configuration instructions of the hierarchical fault-tolerant programmable chip architecture are divided into "inter-block data transfer instructions" and "function block configuration bit streams". Among them, "inter-block data transfer instructions" are used to operate the global bus to transfer data between programmable function blocks (PFBs);

[0062] The "function block configuration bitstream" assigns certain logical functions to the programmable logic units in the corresponding function block. The virtual machine instruction of LLVM is an intermediate representation in the form of SSA. This representation assumes that the virtual machine has an infinite number of registers, so it is particularly suitable for parallelizing instructions that conform to the SSA form at the register transfer level (RTL). In the present invention, the serial SSA is converted into a hardware description language (HDL), and then compiled into a function block configuration bitstream. After the function of the function block is determined, the inter-block data transfer instruction can be generated according to the data dependency. In the hierarchical fault-tolerant programmable chip architecture, this data transfer instruction still belongs to an RTL-level representation. Therefore, it has a natural affinity with the hardware description language.

[0063] It must be noted that in the hierarchical fault-tolerant programmable chip architecture, each functional block contains the same number of programmable logic units. Therefore, the process of forming the functional block configuration bit stream is a cyclic recursive optimization process: the granularity of all functional blocks should be gradually adjusted from the initial arbitrary division to a relatively even division, and the maximum logical function after the division should not exceed the maximum capacity of a single functional block. The number of functional blocks and the capacity of functional blocks are two constraints for optimization.

[0064] Obviously, the above embodiments are only examples for clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from them are still within the protection scope of the invention.

Claims

1. A new fault-tolerant programmable chip architecture, characterized in that: include: Global Bus Controller, A global bus, a plurality of programmable function blocks, and a plurality of bus interface units; each of the programmable function blocks corresponds to a bus interface unit; The global bus controller sends instructions to the programmable function blocks using the global bus according to the compiled program; The programmable function block performs self-check according to the instruction requirements. When a faulty unit is found, a blank unit is used to replace the faulty unit until there are no more blank units, and the resource exhaustion status is reported to the global bus controller.

2. The novel fault-tolerant programmable chip architecture according to claim 1 is characterized in that: The programmable function block includes a fixed number of programmable logic units, interconnect routing and self-test units; The programmable logic unit is used to store instructions; The interconnection routing is used to convert the issued instructions and the stored instructions into the addresses of the corresponding programmable logic units; The self-checking unit is used for fault detection, and when an error is found, an alarm is sent to the global bus controller through the status bus.

3. The novel fault-tolerant programmable chip architecture according to claim 1, characterized in that: The global bus controller includes a program counter, a state detector and an address mapping table; The program counter is connected to the global data bus and is used to generate the address of the next instruction sequence; The address mapping table is connected to the global address bus and is used to convert instructions in the external or internal read-only memory into the physical port addresses of the corresponding programmable function blocks; The status detector is used to obtain the health status of each programmable functional unit. When receiving a warning that the functional block resources are exhausted, its functions are immediately configured to the blank programmable functional block; and the content of the address mapping table is modified, the corresponding physical port address is changed, the faulty programmable functional block is shielded, and the newly configured programmable functional block is enabled.

4. A compilation method for a new fault-tolerant programmable chip architecture, characterized in that: The following steps are involved: The compiler's front end parses the high-level language into an intermediate language; Use the LLVM compiler to convert the intermediate language into standard single static assignment SSA form virtual machine instructions; The virtual machine instructions in SSA form are converted into hardware description language HDL, data is transferred to the programmable function block according to the configuration instructions, and specific logical functions are determined for the programmable function block.

5. The novel fault-tolerant programmable chip architecture according to claim 4 is characterized in that: It also includes issuing machine configuration instructions using a hardware description language HDL, wherein the machine configuration instructions include inter-block data transmission instructions and a function block configuration bit stream; the inter-block data transmission instructions are used to operate a global bus to transfer data between programmable function blocks PFB, and the function block configuration bit stream assigns specific logic functions to the programmable logic units in the corresponding programmable function blocks PFB.

6. The novel fault-tolerant programmable chip architecture according to claim 4, characterized in that: Determining specific logic functions for programmable function blocks includes dividing all programmable function blocks in a loop recursive optimization form, including: S01, divide all programmable function blocks into coarse-grained divisions. S02, generating inter-block transmission instructions and function block configuration bit streams according to the issued machine configuration instructions; S03, judging the capacity of the largest programmable function block and the total number of programmable function blocks according to the inter-block transmission instruction and the function block configuration bit stream; when the total number of programmable function blocks exceeds the limit threshold, the splitting is terminated, otherwise, the programmable function blocks are finely divided; S04, searching for fine-grained programmable function blocks with consistent functions, and updating the list of programmable function blocks; S05. Generate inter-block transfer instructions and function block configuration bit streams again according to the generated new list, and repeat the above-mentioned process of S03-S04 until the total number of programmable function blocks exceeds the limit threshold, and then end the splitting.

7. The novel fault-tolerant programmable chip architecture according to claim 4, characterized in that: It also includes determining whether the capacity of the largest programmable functional block exceeds a first threshold value. If so, the largest programmable functional block is subdivided; if not, continuing to determine whether the total number of programmable functional blocks exceeds a quantity limit. If so, the division of programmable functional blocks is terminated; if not, the largest programmable functional block is subdivided.

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