Clock tree based on gating sub-clock tree and design method

Abstract

The invention relates to an integrated circuit design, in particular to a clock tree based on a gating sub-clock tree and a design method, the gating sub-clock tree is a small clock tree constructed by taking a clock gating unit arranged at the middle position of a register in each operation macro-module as a new clock source point, and the small clock tree is a small clock tree constructed by taking the clock gating unit as a new clock source point. Each clock gating unit accurately controls the register clock in the corresponding operation macro module to overturn according to the working state information required by the digital signal processor, so as to eliminate the redundant state overturning in the circuit and reduce the dynamic power consumption of a chip; the bridging clock network is connected with the top-layer clock link and the gating sub-clock tree; the top-layer clock link is used for connecting a clock source signal to each clock gating unit in the gating sub-clock tree through a bridging clock network, and further connecting the clock source signal to a register in the corresponding operation macro-module through the clock gating unit; according to the technical scheme provided by the invention, the defect that the dynamic power consumption of the multi-core digital signal processor chip is difficult to conveniently reduce by utilizing a clock gating technology can be effectively overcome.

Description

Technical Field

[0001] The present invention relates to integrated circuit design, and in particular to a clock tree based on a gated sub-clock tree and a design method thereof. Background Art

[0002] High-performance digital signal processor chips are core components in high-speed automatic control, image processing, communications, radar and various signal processing applications. The continuous expansion of application areas has put forward higher requirements on the performance of digital signal processor chips. At the same time, due to the continuous improvement of their integration, the power consumption of chips has increased rapidly. Low power consumption has become an important indicator for measuring system performance, and power consumption control and management have become the primary consideration in processor design.

[0003] The power consumption of digital CMOS circuits mainly includes static power consumption and dynamic power consumption. Static power consumption is mainly caused by leakage power consumption, while dynamic power consumption mostly comes from the power consumption of charging and discharging the load capacitor when the device level in the circuit flips. Therefore, an important idea to reduce power consumption is to eliminate redundant state flips in the circuit by adding clock gating units in the circuit design, which requires the introduction of clock gating technology in processor design. For multi-core digital signal processor chips, users usually do not need multiple cores to run simultaneously during use, and the system clock is always jumping without the clock gating unit to shut down the clock, which will cause unnecessary power consumption.

[0004] In order to reduce dynamic power consumption, a common practice is to have the logic synthesis tool automatically insert clock gating units during the logic synthesis stage, and have the EDA tool automatically place the clock gating units during the back-end design stage. Existing hardware implementation circuits generally use EDA tools to directly generate control signals inside the circuit. Designers do not know the specific connection relationship and physical location of the clock gating units. The clock gating units and corresponding control logic are too complex, which makes timing optimization difficult and affects chip performance. There are uncontrollable risks for extremely large-scale processor designs. At the same time, if the clock gating units are not automatically inserted during the logic synthesis stage, the clock gating technology cannot be used to reduce dynamic power consumption. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, the present invention provides a clock tree and design method based on a gated sub-clock tree, which can effectively overcome the defect of the prior art that it is difficult to use clock gating technology to conveniently reduce the dynamic power consumption of a multi-core digital signal processor chip.

[0006] To achieve the above objectives, the present invention is implemented through the following technical solutions: A clock tree based on a gated sub-clock tree, comprising a gated sub-clock tree, a bridge clock network and a top-level clock link; The gated sub-clock tree is a small clock tree constructed with the clock gating unit set at the middle position of the register in each operation macro module as the new clock source point. Each clock gating unit accurately controls the register clock flip in the corresponding operation macro module according to the working status information required by the digital signal processor to eliminate redundant state flips in the circuit and reduce the dynamic power consumption of the chip; Bridge the clock network, connect the top-level clock link and the gated sub-clock tree, and achieve the connection of the entire clock network; The top-level clock link connects the clock source signal to each clock gating unit in the gated sub-clock tree through the bridge clock network, and then connects the clock source signal to the register in the corresponding operation macro module through the clock gating unit.

[0007] Preferably, the gated sub-clock tree includes a plurality of operation macro modules and a clock gating unit corresponding to each operation macro module; The clock gating unit is arranged at the middle position of the register in the corresponding operation macro module, receives the clock signal of the bridge clock network and the control signal sent by the chip, and adjusts the flip state of the register clock in the corresponding operation macro module by turning on or off under the control of the control signal. When the clock gating unit is turned off, the register clock in the corresponding operation macro module stops flipping; The operation macro module includes a register and a sub-buffer connected between the register and the corresponding clock gating unit. The sub-buffer is used to construct a sub-clock tree of the operation macro module to improve the driving capability of the sub-clock tree of the operation macro module.

[0008] Preferably, the bridge clock network comprises a second buffer unit; A second buffer unit, comprising a plurality of second buffers connected between the top-level clock link and the gated sub-clock tree, for synchronizing the clock signals of the clock gating units; The number of second buffers in the second buffer unit is configured according to the number of clock gating units.

[0009] Preferably, the top-level clock link comprises a first buffer unit; The first buffer unit includes a plurality of first buffers connected to the clock source signal and is used to establish a connection path between the chip clock source and the bridge clock network.

[0010] A clock tree design method based on a gated sub-clock tree, before clock tree synthesis, according to the physical position distribution and register distribution of each operation macro module, a clock gating unit is set at the middle position of the register in each operation macro module, and an operation macro module sub-clock tree is created with the clock gating unit as the new clock source point of the corresponding operation macro module, and a gated sub-clock tree with the clock gating unit as the starting point is generated, as well as a bridge clock network and a top-level clock link connecting the chip clock source and the gated sub-clock tree, so as to form a full-chip clock tree consisting of the gated sub-clock tree, the bridge clock network and the top-level clock link; Among them, the newly added clock gating unit on the full-chip clock tree is used to flip the register clock in the corresponding operation macro module to achieve clock management of each operation macro module, so as to eliminate redundant state flips in the circuit and reduce the dynamic power consumption of the chip.

[0011] Preferably, the method specifically comprises the following steps: S1. Configure the gated sub-clock tree: determine the specific location of the corresponding clock gating unit according to the physical location distribution and register distribution of each operation macro module, define the clock gating unit as the new clock source point of the corresponding operation macro module, and create the operation macro module sub-clock tree according to the configuration; S2, configuring a bridge clock network: configuring a corresponding number of second buffers according to the number of clock gating units to form a second buffer unit for synchronizing the clock signals of each clock gating unit; S3. Configure the top-level clock link: establish a connection path between the chip clock source and the bridge clock network through multiple first buffers, set the last-level first buffer connected to the bridge clock network in the middle of each clock gating unit, and insert a corresponding number of first buffers according to the driving capability requirements, lead the clock source signal to the center of the chip, achieve balanced clock distribution, and form a full-chip clock tree composed of a gated sub-clock tree, a bridge clock network and a top-level clock link. At the same time, the common path of the entire clock network accounts for a larger proportion of the total path length, reducing the difficulty of timing repair.

[0012] Preferably, a bridge clock network is configured in S2: a corresponding number of second buffers are configured according to the number of clock gating units to form a second buffer unit for synchronizing the clock signals of each clock gating unit, including: The last level first buffer in the top-level clock link is used as the clock source point of the bridge clock network, and the H-Tree design function of the EDA tool is used to complete the configuration of the bridge clock network.

[0013] Preferably, after configuring the top-level clock link in S3, the following steps are included: S4. Adjust the full-chip clock tree: By adjusting the location and number of buffers in the top-level clock link and bridge clock network, as well as the metal line width of each part, smaller clock deviation and clock path delay can be obtained. At the same time, while meeting the driving capability requirements, the number of buffers is minimized to reduce the dynamic power consumption of the chip.

[0014] Preferably, after adjusting the full chip clock tree in S4, the following steps are included: S5. Route and prune the full-chip clock tree: Route the full-chip clock tree and remove unused metal wires in the bridge clock network, that is, prune redundant trunks and branches to reduce capacitance and prevent antenna effect.

[0015] Compared with the prior art, the clock tree and design method based on the gated sub-clock tree provided by the present invention can be used for the design of multi-core digital signal processor chips with large scale, many computing macro modules and high requirements for low power consumption. The dynamic power consumption of the chip can be effectively reduced by designing the clock tree structure based on the gated sub-clock tree and implementing the circuit in hardware. Compared with the existing scheme, the present scheme does not need to insert the clock gating unit in the logic synthesis stage. It only needs to add a small number of clock gating units, control signals and control ports before the clock tree synthesis, and perform certain configuration to complete the design and implementation of the clock tree. It can not only effectively reduce the dynamic power consumption of the chip, but also make the implementation path simpler, more convenient and controllable. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 It is a schematic diagram of the structure of the clock tree in the present invention; Figure 2 It is a flowchart of the clock tree design method in the present invention. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0019] A clock tree based on a gated sub-clock tree, such as Figure 1 As shown, it includes gated sub-clock trees, bridge clock networks, and top-level clock links; The gated sub-clock tree is a small clock tree constructed with the clock gating unit set at the middle position of the register in each operation macro module as the new clock source point. Each clock gating unit accurately controls the register clock flip in the corresponding operation macro module according to the working status information required by the digital signal processor to eliminate redundant state flips in the circuit and reduce the dynamic power consumption of the chip; Bridge the clock network, connect the top-level clock link and the gated sub-clock tree, and achieve the connection of the entire clock network; The top-level clock link connects the clock source signal to each clock gating unit in the gated sub-clock tree through the bridge clock network, and then connects the clock source signal to the register in the corresponding operation macro module through the clock gating unit.

[0020] ① The gated sub-clock tree includes multiple operation macro modules and clock gating units corresponding to each operation macro module; The clock gating unit is arranged at the middle position of the register in the corresponding operation macro module, receives the clock signal of the bridge clock network and the control signal sent by the chip, and adjusts the flip state of the register clock in the corresponding operation macro module by turning on or off under the control of the control signal. When the clock gating unit is turned off, the register clock in the corresponding operation macro module stops flipping; The operation macro module includes a register and a sub-buffer connected between the register and the corresponding clock gating unit. The sub-buffer is used to construct a sub-clock tree of the operation macro module to improve the driving capability of the sub-clock tree of the operation macro module.

[0021] ② The bridge clock network includes a second buffer unit; A second buffer unit, comprising a plurality of second buffers connected between the top-level clock link and the gated sub-clock tree, for synchronizing the clock signals of the clock gating units; The number of second buffers in the second buffer unit is configured according to the number of clock gating units.

[0022] ③The top-level clock link includes the first buffer unit; The first buffer unit includes a plurality of first buffers connected to the clock source signal and is used to establish a connection path between the chip clock source and the bridge clock network.

[0023] Based on the above disclosed clock tree based on gated sub-clock tree, the technical solution of the present application also discloses a clock tree design method based on gated sub-clock tree: Before clock tree synthesis, a clock gating unit is set at the middle position of the register in each operation macro module according to the physical position distribution and register distribution of each operation macro module, and an operation macro module sub-clock tree is created with the clock gating unit as the new clock source point of the corresponding operation macro module, and a gated sub-clock tree starting from the clock gating unit is generated, as well as a bridge clock network and a top-level clock link connecting the chip clock source and the gated sub-clock tree, to form a full-chip clock tree consisting of a gated sub-clock tree, a bridge clock network and a top-level clock link; Among them, the newly added clock gating unit on the full-chip clock tree is used to flip the register clock in the corresponding operation macro module to achieve clock management of each operation macro module, so as to eliminate redundant state flips in the circuit and reduce the dynamic power consumption of the chip.

[0024] like Figure 2 As shown, the clock tree design method based on the gated sub-clock tree specifically includes the following steps: S1. Configure the gated sub-clock tree: determine the specific location of the corresponding clock gating unit according to the physical location distribution and register distribution of each operation macro module, define the clock gating unit as the new clock source point of the corresponding operation macro module, and create the operation macro module sub-clock tree according to the configuration; S2, configuring a bridge clock network: configuring a corresponding number of second buffers according to the number of clock gating units to form a second buffer unit for synchronizing the clock signals of each clock gating unit; S3. Configure the top-level clock link: establish a connection path between the chip clock source and the bridge clock network through multiple first buffers, set the last-level first buffer connected to the bridge clock network in the middle of each clock gating unit, and insert a corresponding number of first buffers according to the driving capability requirements, lead the clock source signal to the center of the chip, achieve balanced clock distribution, and form a full-chip clock tree composed of a gated sub-clock tree, a bridge clock network and a top-level clock link. At the same time, the common path of the entire clock network accounts for a larger proportion of the total path length, reducing the difficulty of timing repair.

[0025] Specifically, in S2, a bridge clock network is configured: a corresponding number of second buffers are configured according to the number of clock gating units to form a second buffer unit for synchronizing the clock signals of each clock gating unit, including: The last level first buffer in the top-level clock link is used as the clock source point of the bridge clock network, and the H-Tree design function of the EDA tool is used to complete the configuration of the bridge clock network.

[0026] Specifically, after the top-level clock link is configured in S3, it includes: S4. Adjust the full-chip clock tree: By adjusting the setting position and number of buffers in the top-level clock link and bridge clock network, as well as the metal line width of each part (generally, the metal lines in the upper layer are wider and thicker, with smaller resistance values, and more suitable for the clock tree), smaller clock deviation and clock path delay can be obtained. At the same time, while meeting the driving capability requirements, the number of buffers is minimized to reduce the dynamic power consumption of the chip.

[0027] Specifically, after adjusting the full chip clock tree in S4, it includes: S5. Route and prune the full-chip clock tree: Route the full-chip clock tree and remove unused metal wires in the bridge clock network, that is, prune redundant trunks and branches to reduce capacitance and prevent antenna effect.

[0028] The technical solution of the present application can be used for the design of multi-core digital signal processor chips with large scale, many computing macro modules and high requirements for low power consumption. The dynamic power consumption of the chip can be effectively reduced by designing a clock tree structure based on a gated sub-clock tree and implementing the circuit in hardware. Compared with the existing solutions, the present solution does not need to insert a clock gating unit in the logic synthesis stage. It only needs to add a small number of clock gating units, control signals and control ports before clock tree synthesis, and perform certain configurations to complete the design and implementation of the clock tree. It can not only effectively reduce the dynamic power consumption of the chip, but also make the implementation path simpler, more convenient and controllable.

[0029] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A clock tree based on a gated sub-clock tree, characterized in that: Includes gated sub-clock trees, bridge clock networks, and top-level clock links; The gated sub-clock tree is a small clock tree constructed with the clock gating unit set at the middle position of the register in each operation macro module as the new clock source point. Each clock gating unit accurately controls the register clock flip in the corresponding operation macro module according to the working status information required by the digital signal processor to eliminate redundant state flips in the circuit and reduce the dynamic power consumption of the chip; Bridge the clock network, connect the top-level clock link and the gated sub-clock tree, and achieve the connection of the entire clock network; The top-level clock link connects the clock source signal to each clock gating unit in the gated sub-clock tree through the bridge clock network, and then connects the clock source signal to the register in the corresponding operation macro module through the clock gating unit.

2. The clock tree based on the gated sub-clock tree according to claim 1, characterized in that: The gated sub-clock tree includes a plurality of operation macro modules and a clock gating unit corresponding to each operation macro module; The clock gating unit is arranged at the middle position of the register in the corresponding operation macro module, receives the clock signal of the bridge clock network and the control signal sent by the chip, and adjusts the flip state of the register clock in the corresponding operation macro module by turning on or off under the control of the control signal. When the clock gating unit is turned off, the register clock in the corresponding operation macro module stops flipping; The operation macro module includes a register and a sub-buffer connected between the register and the corresponding clock gating unit. The sub-buffer is used to construct a sub-clock tree of the operation macro module to improve the driving capability of the sub-clock tree of the operation macro module.

3. The clock tree based on the gated sub-clock tree according to claim 2, characterized in that: The bridge clock network includes a second buffer unit; A second buffer unit, comprising a plurality of second buffers connected between the top-level clock link and the gated sub-clock tree, for synchronizing the clock signals of the clock gating units; The number of second buffers in the second buffer unit is configured according to the number of clock gating units.

4. The clock tree based on the gated sub-clock tree according to claim 3, characterized in that: The top-level clock link includes a first buffer unit; The first buffer unit includes a plurality of first buffers connected to the clock source signal and is used to establish a connection path between the chip clock source and the bridge clock network.

5. A clock tree design method based on a gated sub-clock tree, used to design the clock tree based on a gated sub-clock tree as claimed in claim 1, characterized in that: Before clock tree synthesis, a clock gating unit is set at the middle position of the register in each operation macro module according to the physical position distribution and register distribution of each operation macro module, and an operation macro module sub-clock tree is created with the clock gating unit as the new clock source point of the corresponding operation macro module, and a gated sub-clock tree starting from the clock gating unit is generated, as well as a bridge clock network and a top-level clock link connecting the chip clock source and the gated sub-clock tree, to form a full-chip clock tree consisting of a gated sub-clock tree, a bridge clock network and a top-level clock link; Among them, the newly added clock gating unit on the full-chip clock tree is used to flip the register clock in the corresponding operation macro module to achieve clock management of each operation macro module, so as to eliminate redundant state flips in the circuit and reduce the dynamic power consumption of the chip.

6. The clock tree design method based on gated sub-clock trees according to claim 5, characterized in that: The specific steps include: S1. Configure the gated sub-clock tree: determine the specific location of the corresponding clock gating unit according to the physical location distribution and register distribution of each operation macro module, define the clock gating unit as the new clock source point of the corresponding operation macro module, and create the operation macro module sub-clock tree according to the configuration; S2, configuring a bridge clock network: configuring a corresponding number of second buffers according to the number of clock gating units to form a second buffer unit for synchronizing the clock signals of each clock gating unit; S3. Configure the top-level clock link: establish a connection path between the chip clock source and the bridge clock network through multiple first buffers, set the last-level first buffer connected to the bridge clock network in the middle of each clock gating unit, and insert a corresponding number of first buffers according to the driving capability requirements, lead the clock source signal to the center of the chip, achieve balanced clock distribution, and form a full-chip clock tree composed of a gated sub-clock tree, a bridge clock network and a top-level clock link. At the same time, the common path of the entire clock network accounts for a larger proportion of the total path length, reducing the difficulty of timing repair.

7. The clock tree design method based on gated sub-clock trees according to claim 6, characterized in that: In S2, a bridge clock network is configured: a corresponding number of second buffers are configured according to the number of clock gating units to form a second buffer unit for synchronizing the clock signals of each clock gating unit, including: The last level first buffer in the top-level clock link is used as the clock source point of the bridge clock network, and the H-Tree design function of the EDA tool is used to complete the configuration of the bridge clock network.

8. The clock tree design method based on gated sub-clock trees according to claim 6, characterized in that: After the top-level clock link is configured in S3, it includes: S4. Adjust the full-chip clock tree: By adjusting the location and number of buffers in the top-level clock link and bridge clock network, as well as the metal line width of each part, smaller clock deviation and clock path delay can be obtained. At the same time, while meeting the driving capability requirements, the number of buffers is minimized to reduce the dynamic power consumption of the chip.

9. The clock tree design method based on gated sub-clock trees according to claim 8, characterized in that: After adjusting the full chip clock tree in S4, including: S5. Route and prune the full-chip clock tree: Route the full-chip clock tree and remove unused metal wires in the bridge clock network, that is, prune redundant trunks and branches to reduce capacitance and prevent antenna effect.

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