Accelerating circuit applied to active noise reduction

Abstract

The invention claims to protect an acceleration circuit applied to active noise reduction, the acceleration circuit accelerates an operation process through a product accumulation unit acceleration circuit and a convolution operation unit acceleration circuit, the product accumulation unit acceleration circuit processes data in parallel by using an adder tree structure to realize a one-dimensional convolution process, and the convolution operation unit acceleration circuit accelerates the convolution operation process. Meanwhile, the current weight coefficient is updated according to the previous weight matrix and fed back to a pre-stage circuit, so that the operation efficiency is improved by about 74%, a secondary sound source can be generated in an accelerated manner, and spatial noise is counteracted; the convolution operation unit accelerates the simple and efficient data transfer of the circuit, accelerates the data transmission capability of the whole system, improves the calculation speed of the active noise control system, and has more efficient noise feedback capability.

Description

Technical Field

[0001] The present invention belongs to the technical field of noise reduction, and in particular relates to an active noise reduction technology capable of actively receiving noise and counteracting the noise source. Background Art

[0002] At present, the existing active noise reduction technology on the market can improve active noise control through phase compensation to achieve the purpose of noise reduction, but this implementation method can only achieve point attenuation, receive and process one-dimensional space, and require a certain transmission distance limit. This is caused by the circuit processing noise speed is not fast enough, resulting in many limitations of noise reduction equipment; for low-frequency narrowband noise, active noise control, that is, the method of offsetting noise signals through the principle of destructive interference of sound waves is more effective, and adaptive noise reduction system is generated, that is, while generating anti-noise signals, the anti-noise signals are actively repaired according to the changes in noise to complete active noise control, in which the real-time requirements are extremely strict, and the active noise output needs to be completely controlled at a speed of microseconds. The high-speed operation of logic gates can meet this strict real-time requirement, but it poses a great challenge to the efficient rate utilization of logic gates. Ordinary active noise reduction technology adopts a sequential execution structure, and the processing process is highly dependent on the increase of the main frequency to increase the speed, resulting in an increase in the cost of the equipment used. The excessively redundant code volume and large-scale sequential calculation volume make the active noise reduction effect unsatisfactory, so it is necessary to improve the acceleration process.

[0003] The present invention designs an acceleration circuit design for active noise reduction. The innovation of the present invention is that the acceleration circuit for active noise reduction mainly accelerates the operation process through the multiplication and accumulation unit acceleration circuit and the convolution operation unit acceleration circuit, wherein the multiplication and accumulation unit acceleration circuit uses the addition tree structure to process data in parallel to realize the one-dimensional convolution process, and at the same time updates the weight coefficient according to the previous weight matrix, and feeds back to the previous circuit, thereby improving the operation efficiency by about 74%, so that the secondary sound source can be accelerated to offset the spatial noise; in addition, the convolution operation unit acceleration circuit transfers data simply and efficiently, accelerating the data transmission capability of the overall system. Summary of the invention

[0004] The present invention aims to solve the above problems of the prior art. An acceleration circuit applied to active noise reduction is proposed. The technical solution of the present invention is as follows:

[0005] An acceleration circuit for active noise reduction, comprising: a multiplication-accumulation unit MAC, a convolution operation unit CONV, an external data access module Y_FIFO, a signal data cache module X_SRAM, a weight coefficient data cache module W_SRAM, an error signal data cache module E_SRAM, a data distributor, a data distributor and a data integrator, wherein the multiplication-accumulation unit adopts an addition tree structure to realize a one-dimensional convolution process; the convolution operation unit is used to realize the cumulative superposition of multiple groups of multiplication-accumulation units, extract a noise feature matrix, and output it to an external data access module; the external data access module is used to store the result data for reading by an external controller; the signal data cache module is used to store the result data .... The invention is used to store the original noise data; the weight coefficient data cache module is used to store the weight coefficient of the last multiplication and addition unit, and is used as the proportional coefficient with the original noise data in the signal data cache module; the error signal data cache module is used to store the deviation between the original data and the feedback data, and to make a small adjustment to the result; the data distributor is used to split a sequence value into multiple sub-sequence units and transmit them to the data distributor; the data distributor is used to mirror the sub-sequence units to each output port, and pass the sub-sequence units to the multiplication and addition unit and the convolution operation unit; the data integrator is used to integrate the results of the multiplication and addition unit into a new sequence and feed it back to the weight coefficient data cache module.

[0006] Furthermore, the multiplication and accumulation unit is composed of a multiplier, an adder and a D flip-flop. The multiplier is a dual-input port device, which multiplies data a and data b and outputs a multiplier mult, which is passed to the adder. The adder is also a dual-input port device. The D flip-flop is controlled by a global clock, and the D flip-flop latches data once at each rising edge of the clock. The output data will be fed back to the adder in a branch and added with the next mult multiplier. The corresponding operation formula of the multiplication and accumulation unit is: OUT=OUT+a*b, the clock frequency is 33MHz, and the time required for triggering and transmitting once is 30ns.

[0007] Furthermore, the convolution operation unit is composed of a multiplier and an adder. Two groups of multipliers and one group of adders constitute the pre-weight coefficient operation result. Finally, the results of all adders are summed, and the noise characteristic result is output and transmitted to the external data access module. The updated weight coefficient is transmitted through the multiplication and addition unit acceleration circuit. The convolution operation unit circuit can obtain the latest weight coefficient within the same cycle to ensure the real-time noise cancellation.

[0008] Furthermore, the external data access module has two high-speed shifters inside. The high-speed shifter adopts a D flip-flop structure and a 200 MHz trigger clock, which can quickly and sequentially store input data and facilitate the external controller to read data sequentially.

[0009] Furthermore, the signal data cache module is used to pre-process the original noise data, and the collected original noise data is processed in sequence in advance in the signal data cache module for the data distributor to segment the data sequence.

[0010] Furthermore, the weight coefficient data cache module is used to receive data from a data integrator, which integrates the array data composed of the multiplication and accumulation units, and the weight coefficient data cache module pre-processes the weight coefficient data.

[0011] Furthermore, the error signal data buffer module is input into the data distributor to perform error analysis on the original noise, so that the multiplication and accumulation unit can compare and update the weight coefficients.

[0012] Furthermore, the two input ports of the multiplication and accumulation unit receive the data from the error signal data cache module and the weight coefficient data cache module, multiply them and add them to the negative feedback of the result saved by the previous D flip-flop, and finally output them to the data integrator.

[0013] Furthermore, the two input ports of the convolution operation unit receive data from the signal data cache module and the weight coefficient data cache module, first perform a multiplication operation to multiply the frequency amplitude coefficients of the corresponding noise at each noise point, then perform a weighted operation through a cascade adder, and finally output it to the external data access module.

[0014] Furthermore, the convolution operation unit CONV is composed of a multiplier and an adder. Two groups of multipliers and one group of adders constitute the result of the pre-weight coefficient operation. Finally, the results of all adders are summed. The external data access module Y_FIFO adopts a first-in-first-out dual-port buffer for data transmission in an asynchronous clock domain, which can cache the data transmitted by the convolution operation unit CONV and concentrate the data to prevent data loss. The signal data cache module X_SRAM, the weight coefficient data cache module W_SRAM, and the error signal data cache module E_SRAM adopt a static random access memory design. Compared with the dynamic random access memory DRAM design, this design has a higher cache speed and is faster for storing small batches of data. It does not require a refresh operation to re-cache data. The data distributor transmits the same data to each output port at a unified time according to external needs. The data distributor uses an address-selected data line to select one of multiple data for transmission to the output port. The data integrator merges multiple external incoming data according to a certain order and transmits them to the output port.

[0015] The advantages and beneficial effects of the present invention are as follows:

[0016] (1) The multiplication-accumulation unit acceleration circuit designed in the present invention utilizes an addition tree structure to rapidly process data in parallel to implement a one-dimensional convolution process. At the same time, the feedback loop is used to compare the weight matrix of the previous operation, update the weight coefficients of this operation, and feed back to the previous circuit, thereby improving the operation efficiency of the operation process by about 74%, thereby accelerating the generation of secondary sound sources and more quickly offsetting spatial noise.

[0017] (2) The convolution operation unit acceleration circuit designed in the present invention utilizes a distributed network to efficiently and quickly transfer data, thereby accelerating the data transmission capability of the overall system, and can update and obtain the latest weight coefficients within the same cycle without having to be completed in the next cycle, thereby improving the real-time performance of the noise reduction system. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 The present invention provides a hardware circuit design framework diagram of a preferred embodiment;

[0019] Figure 2 The invention provides a multiplication-accumulation unit acceleration circuit design diagram;

[0020] Figure 3 The present invention provides a convolution operation unit acceleration circuit design diagram;

[0021] Figure 4 The present invention provides a design diagram of the operation circuit structure of a multiplication and accumulation unit and a convolution operation unit. DETAILED DESCRIPTION

[0022] The following will describe the technical solutions in the embodiments of the present invention in detail in conjunction with the accompanying drawings in the embodiments of the present invention. The described embodiments are only part of the embodiments of the present invention.

[0023] The technical solution of the present invention to solve the above technical problems is:

[0024] The present invention discloses an acceleration circuit design method for active noise reduction. The hardware circuit design framework is as follows Figure 1 As shown, the multiplication and accumulation unit acceleration circuit design is as follows Figure 2 As shown in Figure 2, the convolution operation unit acceleration circuit design is as follows: Figure 3 As shown, the circuit structure design of the multiplication and accumulation unit and the convolution operation unit is as follows Figure 4 As shown in the figure, the overall computing efficiency of the acceleration circuit design is increased by 76%, which can be well applied in active noise reduction systems. Figure 4 In the convolution operation unit, CONV (convolution operation unit) MAC (multiplication and accumulation unit)

[0025] X_SRAM (signal data cache module) W_SRAM (weight coefficient data cache module) MUL (multiplier) E_SRAM (error signal data cache module) Y_FIFO (external data access module) ADD (adder) Dispatcher (data distributor) DMUX (data distributor) Reg (data register).

[0026] The active noise reduction acceleration circuit is mainly composed of a multiplication and accumulation unit (MAC), a convolution operation unit (CONV), an external data access module (Y_FIFO), a signal data cache module (X_SRAM), a weight coefficient data cache module (W_SRAM), an error signal data cache module (E_SRAM), a data distributor, a data distributor and a data integrator. First, the original noise data is transmitted into the signal data cache module and the error signal data cache module. The signal data cache module is used to store the original noise data and pre-process the data, including sequential numbering in the memory, so that the data distributor can segment the data sequence; the error signal data cache module receives the deviation of the original data and the feedback data, performs error analysis on the original noise, and inputs the result into the multiplication and accumulation unit for comparison and update of the weight coefficient. After that, the signal data cache module and the error signal data cache module will perform data preprocessing and transmit it to the data distributor. The data distributor splits a sequence value into multiple subsequence units and transmits them to the data distributor. The data distributor copies the subsequence units to each output port and transmits them to the multiplication accumulation array composed of multiplication accumulation units and the convolution operation array composed of convolution operation units. The multiplication accumulation unit adopts an addition tree structure, and its core consists of a multiplier, an adder and a D flip-flop. The multiplier receives data a and data b from two input ports, multiplies the two and outputs the multiplier mult to the adder. The adder receives the multiplier mult and the data latched by the D flip-flop last time. At each rising edge of the clock (the clock frequency is 33MHz, that is, each transmission takes 30ns), the D flip-flop transmits data to the adder once to realize the accumulation operation. This structure can significantly improve the parallel computing capability. Compared with serial computing, the performance is improved by about 74%. The weight coefficient data cache module receives the data from the data integrator and preprocesses the weight coefficient data. The data integrator is responsible for integrating the results of the multiplication and accumulation unit into a new sequence and feeding it back to the weight coefficient data cache module. The weight coefficient data cache module stores the weight coefficients of the last multiplication and accumulation unit, which is used to perform proportional operations with the original noise data in the signal data cache module. The convolution operation unit consists of multiple groups of multiplication and addition operations. Each group of multipliers and adders forms the result of the pre-weight coefficient operation. The results of all adders are finally summed and the noise characteristic results are output. This unit receives the data output by the multiplication and accumulation unit and the data of the weight coefficient data cache module, performs convolution operations, extracts the noise characteristic matrix, and transmits it to the external data access module. The external data access module receives the data of the convolution operation unit and is internally configured with two high-speed shifters to ensure that the data can be stored in sequence quickly and conveniently read by the external controller.

[0027] The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions.

[0028] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0029] The above embodiments should be understood to be only used to illustrate the present invention and not to limit the protection scope of the present invention. After reading the contents of the present invention, technicians can make various changes or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. An acceleration circuit for active noise reduction, characterized in that: include: A multiplication-accumulation unit MAC, a convolution operation unit CONV, an external data access module Y_FIFO, a signal data cache module X_SRAM, a weight coefficient data cache module W_SRAM, an error signal data cache module E_SRAM, a data distributor, a data distributor and a data integrator, wherein the multiplication-accumulation unit adopts an addition tree structure to implement a one-dimensional convolution process; the convolution operation unit is used to implement cumulative superposition of multiple groups of multiplication-accumulation units, extract a noise feature matrix, and output it to an external data access module; the external data access module is used to store the result data for reading by an external controller; the signal data cache module is used to store original noise data ; The weight coefficient data cache module is used to store the weight coefficient of the previous multiplication and addition unit, and is used as a proportional coefficient with the original noise data in the signal data cache module; the error signal data cache module is used to store the deviation between the original data and the feedback data, and to make small adjustments to the results; the data distributor is used to split a sequence value into multiple sub-sequence units and transmit them to the data distributor; the data distributor is used to mirror the sub-sequence units to each output port, and pass the sub-sequence units to the multiplication and addition unit and the convolution operation unit; the data integrator is used to integrate the results of the multiplication and addition units into a new sequence and feed it back to the weight coefficient data cache module.

2. The acceleration circuit for active noise reduction according to claim 1, characterized in that: The multiplication and accumulation unit is composed of a multiplier, an adder and a D flip-flop. The multiplier is a dual-input port device. The multiplier outputs the multiplier mult by multiplying data a and data b and passes it to the adder. The adder is also a dual-input port device. The D flip-flop is controlled by a global clock. The D flip-flop latches the data once at each rising edge of the clock. The output data is fed back to the adder in a branch path and added with the next mult multiplier. The corresponding operation formula of the multiplication and accumulation unit is: OUT=OUT+a*b. The clock frequency is 33MHz and the time taken for triggering and transmitting once is 30ns.

3. The acceleration circuit for active noise reduction according to claim 1, characterized in that: The convolution operation unit is composed of a multiplier and an adder. Two groups of multipliers and one group of adders constitute the pre-weight coefficient operation result. Finally, the results of all adders are summed, and the noise characteristic result is output and transmitted to the external data access module. The updated weight coefficient is transmitted through the multiplication and accumulation unit acceleration circuit. The convolution operation unit circuit can obtain the latest weight coefficient within the same cycle to ensure the real-time noise cancellation.

4. The acceleration circuit for active noise reduction according to claim 1, characterized in that: The external data access module has two high-speed shifters inside. The high-speed shifter adopts a D flip-flop structure and a 200MHz trigger clock, which can quickly store input data in sequence and facilitate the external controller to read data in sequence.

5. The acceleration circuit for active noise reduction according to claim 1, characterized in that: The signal data buffer module is used to pre-process the original noise data, and the collected original noise data is processed in sequence number in advance in the signal data buffer module for the data distributor to segment the data sequence.

6. The acceleration circuit for active noise reduction according to claim 1, characterized in that: The weight coefficient data cache module is used to receive data from a data integrator, which integrates the array data composed of the multiplication and accumulation units. The weight coefficient data cache module pre-processes the weight coefficient data.

7. The acceleration circuit for active noise reduction according to claim 1, characterized in that: The error signal data buffer module inputs the data distributor to perform error analysis on the original noise so that the multiplication and accumulation unit can compare and update the weight coefficients.

8. The acceleration circuit for active noise reduction according to claim 1, characterized in that: The two input ports of the multiplication and accumulation unit receive the data of the error signal data cache module and the weight coefficient data cache module, multiply them and add them with the negative feedback of the result saved by the previous D flip-flop, and finally output them to the data integrator.

9. The acceleration circuit for active noise reduction according to claim 1, characterized in that: The two input ports of the convolution operation unit receive data from the signal data cache module and the weight coefficient data cache module, first perform a multiplication operation to multiply the frequency amplitude coefficients of the corresponding noise at each noise point, then perform a weighted operation through a cascade adder, and finally output it to the external data access module.

10. The acceleration circuit for active noise reduction according to claim 1, characterized in that: The convolution operation unit CONV is composed of a multiplier and an adder. Two groups of multipliers and one group of adders form the result of the pre-weight coefficient operation. Finally, the results of all adders are summed. The external data access module Y_FIFO adopts a first-in-first-out dual-port buffer for data transmission in an asynchronous clock domain, which can cache the data transmitted by the convolution operation unit CONV and concentrate the data to prevent data loss. The signal data cache module X_SRAM, the weight coefficient data cache module W_SRAM, and the error signal data cache module E_SRAM adopt a static random access memory design. Compared with the dynamic random access memory DRAM design, this design has a higher cache speed and is faster for storing small batches of data. It does not require a refresh operation to re-cache data. The data distributor transmits the same data to each output port at a unified time according to external needs. The data distributor uses an address-selected data line to select one of multiple data for transmission to the output port. The data integrator merges multiple external incoming data according to a certain order and transmits them to the output port.

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