Memory interface circuit

Abstract

A memory interface circuit includes a driver stage and logic circuitry to provide a control code to the driver stage. The driver stage has a plurality of branches, each branch including a pull-up (PU) transistor, a pull-down (PD) transistor, and a resistor. The PU transistor has a first source / drain terminal coupled with a power supply node, a second source / drain terminal coupled with an intermediate node, and a gate coupled to receive bits of a PU control code. A PD transistor has a first source / drain terminal coupled with the intermediate node, a second source / drain terminal coupled with a ground node, and a gate coupled to receive bits of a PD control code. A resistor has a first end coupled with the intermediate node and a second end coupled with a pin of the memory interface circuit.

Description

Technical Field

[0001] The present disclosure relates generally to memory interface circuits, and more specifically to driver stages thereof, especially with respect to Double Data Rate 5-th generation (DDR5) Synchronous Dynamic Random Access Memory (SDRAM) and Low Power DDR5 (LPDDR5) or their successors. Background Art

[0002] The Joint Electron Device Engineering Council (JEDEC) released the JESD79-5 standard for DDR5 SDRAM in July 2020. DDR5 allows on-die termination (ODT) features for pins including DQ and DQS, as well as loopback (LB) mode. The ODT feature is designed to improve the signal integrity (SI) of the memory channel by allowing the memory controller to independently change the termination resistance of any or all memory devices. The LB mode can be used by the DDR5 MEM PHY to verify the transmitter / receiver performance without the need for actual write / read operations on the memory array. Summary of the invention

[0003] In one aspect, a memory interface circuit includes a driver stage and a logic circuit. The driver stage has multiple branches, each branch including: a pull-up (PU) transistor having a first source / drain terminal coupled to a power supply node, a second source / drain terminal coupled to an intermediate node, and a gate coupled to receive a bit of a PU control code; a pull-down (PD) transistor having a first source / drain terminal coupled to an intermediate node, a second source / drain terminal coupled to a ground node, and a gate coupled to receive a bit of a PD control code; and a resistor having a first end coupled to the intermediate node and a second end coupled to a pin of the memory interface circuit. The logic circuit is used to provide the PU control code and the PD control code to the driver stage.

[0004] In another aspect, an apparatus for a computing system includes: a processor; a memory controller communicatively coupled to the processor; and the above-mentioned memory interface circuit coupled to the memory controller.

[0005] In another aspect, a non-transitory storage medium stores instructions or data for manufacturing a device including the above-mentioned memory interface circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In the accompanying drawings, similar reference numerals generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, and emphasis is generally placed on illustrating the exemplary principles of the present disclosure. In the following description, the present disclosure may be described with reference to the following drawings, in which:

[0007] Figure 1 An exemplary system according to some embodiments of the present disclosure is illustrated;

[0008] Figure 2 A schematic diagram of a driver stage in a MEM PHY according to an embodiment of the present disclosure is illustrated;

[0009] Figure 3 The diagram shows the signals obtained at the pads of the driver stage;

[0010] Figure 4 illustrates a schematic diagram of a MEM PHY according to some embodiments of the present disclosure;

[0011] Figure 5 The figure shows the simulation results of PU and PD control codes for DDR5 and LPDDR5 under various process, voltage and temperature (PVT) conditions;

[0012] Figure 6 and Figure 7 illustrates an example of a DDR5 driver configuration during an input / output loopback (IOLB) test;

[0013] Figure 8 and Fig. 9 illustrates an example of LPDDR5 driver configuration during IOLB testing; and

[0014] Fig.10 The figure shows the simulated eye diagram of a typical test case. DETAILED DESCRIPTION

[0015] In the following detailed description, many specific details are set forth to provide a thorough understanding of some examples. However, those of ordinary skill in the art will appreciate that some examples may be implemented without these specific details. In other cases, well-known methods, processes, components, units and / or circuits are not described in detail to avoid obscuring the discussion.

[0016] Figure 1An exemplary system 100 according to some embodiments of the present disclosure is illustrated. System 100 may be a computing system. System 100 includes a system-on-chip (SoC) 110 coupled to a memory device 120 by a transmission line 130. System 100 may be included in any of the following: a laptop, a desktop computer, a handheld personal computer (PC), a personal digital assistant (PDA), an engineering workstation, a server, a disaggregated server, a network device, a network hub, a switch, a router, an embedded processor, a digital signal processor (DSP), a graphics device, a video game device, a set-top box, a microcontroller, a cellular phone, a portable media player, a handheld device, and various other electronic devices.

[0017] SoC 110 is an integrated circuit (IC) and includes a processor 112, optionally one or more caches 114, a memory controller 116, and a memory interface circuit, which is also referred to as MEM PHY 118 in the present disclosure. Processor 112 can be, for example, a central processing unit (CPU) with one or more general-purpose cores, a coprocessor with several specialized cores mainly for graphics and / or science (throughput), a network or communication processor, a compression engine, a graphics processor, a GPGPU (general-purpose graphics processing unit), a high-throughput many integrated core (MIC) coprocessor (including 30 or more cores), an embedded processor, etc. Cache 114 can be coupled to processor 112 and can include one or more intermediate level caches, such as level 2 (L2), level 3 (L3), level 4 (4) or other levels of cache, such as last level cache (LLC), and / or combinations of these. In some embodiments, cache 114 can be integrated into processor 112.

[0018] The memory controller 116 communicates with the processor 112 or the cache 114. The memory controller 116 is coupled to the memory device 120 via the MEM PHY 118, and may provide various commands to the memory device 120 to perform memory operations. Examples of memory commands may include timing commands for controlling the timing of various operations, access commands for accessing the memory (e.g., read commands for performing read operations and write commands for performing write operations), and mode register write and read commands for performing mode register write and read operations. The MEM PHY 118 may include a physical layer for signals, frequencies, timings, drivers, detailed operating parameters, and functions required for efficient communication between the memory controller 116 and the memory device 120. The MEM PHY 118 may support features of the DDR and / or LPDDR protocols defined by JEDEC. The memory controller 116 and the MEM PHY 118 may communicate via an internal bus, such as a Scalable PHY Interface for DDR (SPID) or a DDR PHY Interface (DFI). Although the memory controller 116 and MEM PHY 118 are Figure 1 Although shown as a separate element in FIG. 1 , MEMPHY 118 may be part of memory controller 116 in some embodiments.

[0019] The memory device 120 may include a dynamic RAM (DRAM). For example, the memory device 120 may correspond to a DDR SDRAM, a LPDDR SDRAM, a graphic DDR (GDDR) SDRAM, or a Rambus DRAM (RDRAM). In some embodiments, the memory device 120 may include a static RAM (SRAM), a high bandwidth memory (HBM), or a processor-in-memory (PIM). Hereinafter, for simplicity of description, the memory device 120 will be described by taking a DDR5 or LPDDR5 device as an example, and the MEM PHY 118 will be described by taking a DDR5 / LPDDR5 MEM PHY as an example. However, it should be understood that the inventive concept is not limited thereto.

[0020] The transmission line 130 may include one or more signal lines that physically or electrically connect the SoC 110 to the memory device 120. The transmission line 130 may include, for example, a clock signal line, a command / address (C&A) bus, and a data bus, etc. The opposite ends of the transmission line 130 may be connected to a pin of the MEM PHY 118 and a pin of the memory device 120, respectively. The term "pin" refers broadly to an electrical interconnection associated with an IC, and may include, for example, a pad or other electrical contact point on the IC. In the present disclosure, the pin of the MEM PHY 118 connected to the transmission line 130 is sometimes referred to as the proximal end, and the pin on the memory device 120 is referred to as the distal end.

[0021] Although Figure 1 SoC 110 is illustrated as a single IC, but in some embodiments, processor 112 and cache 114 may be located on an IC or die, while memory controller 116 and MEM PHY 118 may be located on another separate IC or die. In some embodiments, SoC 110 may be replaced by other devices, such as having multiple ICs in one package (System-In-a-Package) or multiple ICs in multiple packages, or by a stacked tile / chiplet design. Other configurations are also considered within the scope of the present disclosure.

[0022] MEM PHY 118 includes control logic circuits and various functional blocks to implement various functions. MEM PHY 118 also includes a driver stage to directly communicate signals with memory device 120. The driver stage includes a transmitter (also referred to as a "transmit path" or "TX path") and a receiver (also referred to as a "receive path" or "RX path"), both of which are coupled to the pins of MEM PHY 118.

[0023] MEM PHY 118 can be configured in a write mode or a read mode. During normal operation, in the write mode, the transmitter of MEM PHY 118 sends data, and the receiver of memory device 120 receives the data through transmission line 130. At this time, the transmitter of MEM PHY 118 is configured to have an appropriate resistance (often referred to as "RON") to drive the load at the far end, and the memory device 120 provides an appropriate resistance for ODT. Writing a data bit "1" will result in a high level voltage (VOH) at the near end, while writing a data bit "0" will result in a low level voltage (VOL) at the near end. In the read mode, the transmitter of memory device 120 sends data, and the receiver of MEM PHY 118 receives data through transmission line 130. At this time, the transmitter of MEM PHY 118 is configured to provide ODT to achieve signal integrity goals. The specific values ​​of RON and ODT are configured by memory controller 116. The input at the receiver of MEM PHY 118 will always be in a high impedance state.

[0024] Conventionally, the transmitter of the MEM PHY 118 can only be configured to RON or ODT individually, but not both at the same time. However, during LB operation, the data pattern is written and read back inside the MEM PHY 118, rather than being read from the memory device 120. Therefore, there is a problem that, in an Input / Output Loopback (IOLB) high volume manufacturing (HVM) test, the MEM PHY 118 is connected to the tester instead of the memory device 120, so when the MEM PHY 118 transmits and receives at the near end at the same time, the tester must provide appropriate termination to simulate the ODT of the memory device 120. However, in a Sort / Class IOLB test, a tester, such as a Sort Test Interface Unit / Test Interface Unit (SIU / TIU) platform, may not be able to ensure that all pins to be tested are properly terminated. Here, as those skilled in the art will understand, sorting is a step in the IC test flow that is done at the wafer level before the wafer is separated into dies and placed into packages, while classification is a step done in the assembly / test factory after packaging.

[0025] If the data bits cannot all be routed on the SIU / TIU platform with proper shielding or spacing, serious crosstalk issues may occur during IOLB testing. One solution to this problem is to run the IOLB test without termination. In this case, engineers may remove some routing from the SIU in simulation. However, this will provide a full swing (i.e., from VOL to VOH) at the pin being tested (for example, from 0V to 1.1V for DDR5, or from 0V to 0.5V for LPDDR5), and the receiver is not tested in a realistic voltage margin and input common mode, because during normal operating mode, the VOL of DDR5 is typically about half of 1.1V instead of zero, and the VOH of LPDDR5 is about half of 0.5V. In addition, in reality, for other HVM tests, the data bits still need to be routed to the SIU / TIU, and if there is no proper termination, the test board routing and short stubs will still introduce reflection problems at that time. Another solution to the crosstalk problem is to skip some channels in the IOLB test. This can overcome the crosstalk during IOLB, but some data channels will not be tested, or the HVM runtime must be increased to cover all channels in multiple test cycles.

[0026] Figure 2 FIG. 2 illustrates a schematic diagram of a driver stage 200 in the MEM PHY 118 according to an embodiment of the present disclosure, and Figure 3 The diagram shows a signal obtained at pad 240 of driver stage 200. Driver stage 200 may include a TX path and an RX path 230 both connected to pad 240. Pad 240 may be connected to Figure 1 The proximal end of the depicted MEM PHY 118 corresponds to and may be connected to a pin of the memory device 120 , such as a data input / output (I / O) pin (DQ) or a data strobe pin (DQS). Figure 2 The embodiment of FIG. 2 is a two-segment design, where the TX path includes a first segment 210 and a second segment 220 .

[0027] In this embodiment, the first section 210 is used to transmit data. The first section 210 includes a series of pull-up (PU) transistors coupled to the power node Vddq, a series of pull-down (PD) transistors coupled to the ground node Vss, and a series of resistors. Figure 2 The PU transistor is composed of a PU resistor RON UP The series connected switch S1 is modeled by the PD transistor and the PD resistor RON DN The series connected switch S2 is modeled. Here, RON UPis formed by the resistor and the on-resistance of the PU transistor, and its value can be adjusted by switching on different PU transistors. Similarly, RON DN is formed by the resistor and the on-resistance of the PD transistor, and its value can be adjusted by turning on different PD transistors. The node between switches S1 and S2 is coupled to pad 240. Figure 2 In the embodiment, the power node is shown as Vddq; however, it should be noted that in the present disclosure, Vddq can be used to represent both the power node and the voltage on the power node. According to the definition of JEDEC, the voltage Vddq can be 1.1V for DDR5 and 0.5V for LPDDR5.

[0028] The second segment 220 is used to provide ODT on the MEM PHY 118. The second segment 220 may have a series of transistors and resistors that are the same or similar to the first segment 210, but in this case, the resistor R ODT Modeled as , one end of the resistor is coupled to the termination node and the other end is coupled to the pad 240. Resistor R ODT It can be formed by the on-resistance of the resistor and transistor in the second section 220. If the driver stage 200 is used in the MEM PHY 118 for DDR5, the termination node is placed at the potential of Vddq. If the driver stage 200 is used in the MEM PHY 118 for LPDDR5, the termination node is at Vss. This is because DDR5 and LPDDR5 have different requirements for termination: DDR5 requires Vddq termination, while LPDDR5 requires Vss termination.

[0029] For DDR5 IOLB testing, to transmit logic 1, switch S1 is turned on and switch S2 is turned off. At this time, the voltage on pad 240 will be To transmit a logic 0, switches S1 and S2 are both turned on. At this point, the voltage on pad 240 will be VOL = RON DN / (RON DN +ODT Vddq )*Vddq, where ODT Vddq It's RON UP and R ODT During LB mode of DDR5, the input common mode voltage (Vcm) of RX path 230 is Vcm=(VOH+VOL) / 2, and the swing amplitude at pad 240 is

[0030] For LPDDR5 IOLB testing, to transmit a logic 1, both switches S1 and S2 are turned on. At this point, the voltage on pad 240 will be VOH=ODTVss / (RON UP +ODT Vss )*Vddq, where ODT Vss It's RON DN and R ODT To transmit a logic 0, switch S2 is turned on and switch S1 is turned off. At this point, the voltage on pad 240 will be During LB mode of LPDDR5, we have Vcm = (VOH + VOL) ​​ / 2, and the swing amplitude at pad 240 is

[0031] use Figure 2 With the two-segment configuration, the voltage Vcm of the RX path 230 during LB mode will continue to remain at or very close to the value in the actual functional mode. This will result in better coverage in LB mode and improve HVM test quality. Depending on whether the MEMPHY is used for DDR5 or LPDDR5, it can also adjust the Vcm based on the resistance in the segment, and DDR5 will have a higher Vcm than LPDDR5.

[0032] Nevertheless, having two segments for the driver stage 200 will require more power in operation, and the design will also require a larger layout area and increase the complexity of metal routing. It will also result in larger pad capacitance and performance degradation in higher speed modes (e.g., LPDDR5@9600MT / s). The two segments only work simultaneously in LB mode. In normal functional mode, the write mode only uses the first segment of RON, and the read mode only uses the second segment of ODT, which means that having two segments at the same time will be a waste of power and layout area. According to some embodiments of the present disclosure, a single-segment configuration for a driver stage is provided and will be described below.

[0033] Figure 4 The schematic diagram of the MEM PHY 118 according to some embodiments of the present disclosure is illustrated. The MEM PHY 118 includes a driver stage 400, and a compensation block 490 to be described later. The driver stage 400 includes an RX path 480 and a TX path. The RX path 480 may be of conventional design, and its description will be omitted herein. The TX path includes multiple branches. Figure 4 , six branches are illustrated as 410, 420, 430, 440, 450 and 460. However, this is just an example, and the TX path may include more or fewer branches, such as 4, 5, 7 or 8 branches. The TX path may also include a static branch 470.

[0034] Branch 410 includes a PU transistor 412 and a PD transistor 414. Branch 410 may optionally include a second PU transistor 418. In the illustrated embodiment, PU transistor 412 is a P-type MOSFET (PMOS), and PD transistor 414 and second PU transistor 418 are N-type MOSFETs (NMOS). These are merely examples, and other types of transistors or switching elements may be used instead. Transistors 412, 414, and 418 may each have an on-resistance. Branch 410 also includes a resistor 416 to improve the linearity of the impedance of driver stage 400. In some embodiments, on-chip resistor 416 and transistor 412 may be designed to provide a substantially 1:1 resistance ratio, but other ratios are also applicable based on the designer's need to balance power, wafer area, and performance. It will be clear from the following that among transistors 412, 414, and 418, at most only one transistor will be turned on at the same time. For example, in a period when PU transistor 412 is turned on and transistors 414 and 418 are turned off, the impedance (or effective resistance) from branch 410 seen at pad 240 for this period will be the combination of the resistance from resistor 416 and PU transistor 412. In another period when PD transistor 414 is turned on and transistors 412 and 418 are turned off, the impedance from branch 410 seen at pad 240 for this period will be the combination of the resistance from resistor 416 and PD transistor 414. PU transistor 412 is coupled to PD transistor 414 at an intermediate node, and the intermediate node is coupled to pad 240 via resistor 416. Pad 240 may be a pin of MEM PHY 118, such as DQ or DQS.

[0035] Branches 420, 430, 440, 450 and 460 each have a structure similar to branch 410. Each of them has a PU transistor, a PD transistor, a resistor and an optional second PU transistor. The sizes of the PU transistors (and PD transistors) of different branches are set to have different on-resistances, and the resistors in branches 410-460 have different resistance values. For example, transistors can be designed and manufactured to have channels with different widths. The PU transistor 412 in branch 410 has the maximum resistance among the PU transistors, the PD transistor 414 in branch 410 has the maximum resistance among the PD transistors, the second PU transistor 418 in branch 410 has the maximum resistance among the second PU transistors, and the resistor 416 in branch 410 has the maximum resistance among the resistors. If the on-resistance of the PU transistor 412 in branch 410 is taken as the "unit resistance", the on-resistance of the PU transistor in branch 420 is half of the unit resistance, the on-resistance of the PU transistor in branch 430 is one-quarter of the unit resistance, and so on. In other words, the on-resistance of the PU transistor of each branch is half of the on-resistance of the PU transistor of the next branch. Therefore, the on-resistance of the PU transistor in branch 460 is approximately 1 / 32 of the unit resistance. Similarly, the on-resistance of the PD transistor in branches 410-460 is 32:16:8:4:2:1, the on-resistance of the second PU transistor in branch 410-416 is 32:16:8:4:2:1, and the resistance of the resistor in branch 410-460 is 32:16:8:4:2:1. Figure 4 The driver stage 400 illustrated in FIG. 4 actually provides a binary weighted architecture.

[0036] Static branch 470 also has PU transistors, PD transistors, resistors, and an optional second PU transistor similar to branches 410-460. In one embodiment, the on-resistance of each transistor in static branch 470 can be half of the corresponding on-resistance of branch 410, and the resistor in static branch 470 can also have a resistance of half of resistor 416. In other embodiments, the resistor in static branch 470 can have other values ​​depending on the specific design. Including static branch 470 in driver stage 400 can provide weak pull-up or pull-down functions in some operating modes of MEM PHY 118.

[0037] A second PU transistor 418 is coupled in parallel with PU transistor 412. PU transistor 412 and second PU transistor 418 may operate for different types of memory protocols. For example, PU transistor 412 may operate when MEM PHY 118 is used for DDR5 technology, while second PU transistor 418 may operate when MEM PHY 118 is used for LPDDR5 technology. Including a second PU transistor in the branch enables driver stage 400 to be a combined DDR5 / LPDDR5 driver.

[0038] like Figure 4 As shown, PU transistor 412 has a first source / drain terminal coupled to power supply node vddqg, a second source / drain terminal coupled to an intermediate node of branch 410, and a gate coupled to receive the least significant bit (LSB) of the PU control code (en_puvddq_gate) from compensation block 490. PD transistor 414 has a first source / drain terminal coupled to an intermediate node of branch 410, a second source / drain terminal coupled to a ground node, and a gate coupled to receive the LSB of the PD control code (en_pd_gate) from compensation block 490. In the illustrated embodiment, the PU and PD control codes each have 6 bits, and more generally, the PU and PD control codes each have the same number of bits as the number of branches. The PU and PD transistors in branches 420-460 each have a configuration similar to branch 410, and their gates receive respective bits of the PU and PD control codes. For example, the PU transistor in branch 420 receives bits of the PU control code. <1> , and the PD transistor in branch 460 receives the bit of the PD control code <5> The compensation block 490 includes logic circuitry 495 for generating the PU and PD control codes and may include one or more full-swing level shifters (FSLS, not shown) to convert the PU and PD control codes and data patterns suitable for input to the gates of transistors in the driver stage 400. Level shifters are well known in the art as part of the pre-driver stage and will not be described in detail.

[0039] exist Figure 4In some embodiments, the PU transistor of static branch 470 receives a PU control bit (en_puvddq_gate_stat) from compensation block 490, and the PD transistor of static branch 470 receives a PD control bit (en_pd_gate_stat) from compensation block 490. The PU and PD control bits may be transmitted via a connection independent of the PU and PD control codes described above; however, in some embodiments, they may be provided as yet another bit in the PU and PD control codes, respectively.

[0040] According to the JEDEC specification, if the MEM PHY 118 is used for DDR5, the power node vddqg is at a voltage of 1.1 V, and if the MEM PHY 118 is used for LPDDR5, the power node vddqg is at a voltage of 0.5 V. Changing the voltage of the power node vddqg will easily transform the DDR5 MEM PHY into the LPDDR5 MEM PHY.

[0041] The operation of the driver stage 400 in the IOLB test will be described below.

[0042] In analog circuit design, it is often necessary to run simulations under different conditions of process, voltage and temperature (PVT), and the circuit may exhibit different performance under different PVTs. At each PVT, the compensation block 490 (especially its logic circuit 495) will decide which branches are used in write mode to implement RON, and which branches are used in read mode to provide ODT functions. In order to make a decision, the compensation block 490 can retrieve the PU and PD control codes from the hardware registers (not shown). The hardware registers store the mapping between the PU and PD control codes and different PVTs so that the resistances RON and ODT can be compensated to predetermined values ​​that can be specified in the JEDEC standard (for example, 30 ohms for RON and 50 ohms for ODT). The PU and PD control codes are gated using the data pattern for transmission at the pad 240.

[0043] Figure 5 The figure shows the simulation results of PU and PD control codes for DDR5 and LPDDR5 under various PVT conditions. Figure 5 In the figure, the x-axis represents different combinations of PVT parameters (generally represented by letters A to L), and the y-axis represents the PU control code 520 and the PD control code 510, which are respectively used to achieve 30 ohm RON under a certain PVT. From the simulation, the PU control code is generally in the range of 26 to 45, and the PD control code is generally in the range of 35 to 57. In addition, the PD control code is always higher than the PU control code, with a difference of 5 to 10. Figure 5The data of may be stored in hardware registers and retrieved by the compensation block 490 to control the driver stage 400 during normal functional operation. Figure 5 It shows that if the PU control code most suitable for a specific PVT is selected from the hardware register, the PD control code for this PVT can be roughly known even without querying the hardware register, and vice versa.

[0044] According to an embodiment of the present disclosure, both RON and ODT can be simultaneously implemented based on the signal integrity analysis goal in the IOLB test. To this end, based on the PU and PD control codes from the compensation block 490, a subset of the branches 410-460 can be configured to provide RON for transmission, while another subset of the branches can be configured to provide ODT at the same time. To this end, in the IOLB test, the compensation block 490 overrides the retrieved PU or PD control code in certain periods.

[0045] If the MEM PHY 118 is used for DDR5, then when the TX path of the driver stage 400 is to transmit a logic 1 during the IOLB test, the compensation block 490 will transmit the PU and PD control codes retrieved from the hardware register so that the PU transistor of each branch selected based on the bit of the PU control code is turned on, and the PD transistors of all branches are turned off. As a result, one or more branches corresponding to the logic 1 in the PU control code form a path with a compensated PU RON (e.g., approximately 30 ohms). The voltage on pin 240 will be VOH=1.1V. When the TX path is to transmit a logic 0 during the IOLB test, the compensation block 490 will overturn the retrieved PU and PD control codes to turn on both the PD path and the ODT path. To this end, compensation block 490 sets the PU control code so that the PU transistor of each of the first subset of branches 410-460 is turned on, and the PU transistors of the remaining branches are turned off, and sets the PD control code so that the PD transistor of each of the second subset of branches is turned on, and the PD transistors of the remaining branches are turned off. As a result, the first subset of branches (corresponding to a logic 1 in the PU control code) forms an ODT path, and the on-resistance of its PU transistors and the resistors in these branches form the ODT of driver stage 400. The second subset of branches (corresponding to a logic 1 in the PD control code) forms a RON path, and the on-resistance of these PD transistors and the resistors in these branches form the RON of driver stage 400. The voltage on pin 240 will be VOL, which is a fraction of the voltage vddqg and can be calculated using a resistive voltage divider model.

[0046] If the MEM PHY 118 is used for LPDDR5, then when the TX path of the driver stage 400 is to transmit a logic 0 during the IOLB test, the compensation block 490 will transmit the PU and PD control codes retrieved from the hardware register so that the PD transistor of each branch selected based on the bit of the PD control code is turned on, and the PU transistors of all branches are turned off. As a result, one or more branches corresponding to the logic 1 in the PD control code form a path with a compensated PD RON (e.g., approximately 30 ohms). The voltage on pin 240 will be VOL=0V. When the TX path is to transmit a logic 1 during the IOLB test, the compensation block 490 will overturn the retrieved PU and PD control codes to turn on both the PU path and the ODT path. To this end, compensation block 490 sets the PD control code so that the PD transistor of each of the first subset of branches 410-460 is turned on and the PD transistors of the remaining branches are turned off, and sets the PU control code so that the PU transistor of each of the second subset of branches is turned on and the PU transistors of the remaining branches are turned off. As a result, the first subset of branches (corresponding to a logic 1 in the PD control code) forms a RON path, and the on-resistance of its PU transistors and the resistors of these branches form the RON of driver stage 400. The second subset of branches (corresponding to a logic 1 in the PU control code) forms an ODT path, and the on-resistance of its PU transistors and the resistors of these branches form the ODT of driver stage 400. The voltage on pin 240 will be VOH, which is a fraction of the voltage vddqg and can be calculated using a resistive voltage divider model.

[0047] Generally speaking, during the loopback mode, in the period of driving logic 1 for DDR5 or driving logic 0 for LPDDR5, the PU and PD control codes of the driver stage 400 will be those codes retrieved from the hardware register. However, in the period of driving logic 0 for DDR5 or driving logic 1 for LPDDR5, the compensation block 490 will overturn the retrieved PU and PD control codes to enable both RON and ODT paths at the same time. According to some embodiments of the present disclosure, for DDR5 MEM PHY, the PU and PD control codes are overturned so that the PD RON branch and the PU ODT branch are mutually exclusive. That is, in any branch, the PU transistor and the PD transistor should not be turned on at the same time. This will avoid potential problems, such as electromigration (EM), because if too much current flows through a node or network, the metal connection may melt and cause problems such as short circuits or open circuits. The PU and PD control codes are overturned so that the PD RON and PU ODT impedances are not too strong (i.e., they will not have too low ohmic values). This will avoid potential issues with large IR drops. Similarly, for LPDDR5 MEM PHY, the PU and PD control codes can be overridden so that the PU RON branch and the PD ODT branch are mutually exclusive and the PU RON and PD ODT impedances are not too strong.

[0048] According to some embodiments of the present disclosure, the compensation block 490 (more specifically, its logic circuit 495) can set the PU and PD control codes based on a look-up table (LUT) in the MEMPHY 118 to overturn the retrieved PU and PD control codes. Table 1 below shows an example of such a LUT. The LUT can be implemented as hardware logic, and since the driver branches 410-460 are configured in the same binary manner, the LUT can be used for both DDR5 and LPDDR5. In order to obtain half the voltage swing during the IOLB test, ideally, the ratio will always be RON:ODT=1:1. However, when determining the ratio of RON / ODT, factors such as input common mode, driver impedance, and technology, equipment and frequency (Technology, Gear and Frequency, TGF) conditions are further considered. The example provided in Table 1 can meet the requirements of RON / ODT branch mutual exclusion (i.e., performing a logical AND operation between the PU and PD control codes always results in a logical 0) and reasonable impedance as described above, while providing a voltage swing and common mode close to normal operation. In the example pair in Table 1, codes 32 and 20 can be applied in most cases to override the retrieved PU and PD control codes. If a non-correlation is found between the actual silicon data and the simulation modeling (sil2sim), or if the test is intended to be run at a lower power, other codes in Table 1 can be used. In addition, during MEM PHY initialization, other algorithms or automated measures can be introduced to select code pairs from Table 1 based on TGF and the retrieved PU and PD control codes. This can improve the accuracy of IOLB testing and prevent reliability issues therein.

[0049]

[0050]

[0051] Table 1

[0052] Please note, Figure 2 The two-stage design always compensates RON and ODT to a substantially fixed impedance value, because the on-resistance and resistors forming RON or ODT can be freely configured based on the actual PVT. Figure 4For a single-stage design, the PU and PD transistors will need to provide both RON and ODT, subject to the limitations described above. Because the code selection is limited, RON and ODT may not always be compensated to fixed values ​​(e.g., 30 ohms and 50 ohms), but may vary to some extent under different PVTs. Therefore, it is expected that the performance of a single-stage design in signal integrity testing will be lower than that of a two-stage design. However, it provides great advantages in power consumption and layout area compared to a two-stage design, and the performance in signal integrity is still much better than the case where no termination is provided on the tester.

[0053] Reference Figure 6 and Figure 7 Describes an example of DDR5 driver configuration during IOLB testing and will refer to Figure 8 and Fig. 9 Describes an example of LPDDR5 driver configuration during IOLB testing. For simplicity, Figure 6-Figure 9 The RX path is not shown in the figure.

[0054] Figure 6 The driver stage 400 for DDR5 is shown when configured to transmit logic 1. During this period, the driver stage 400 is expected to exhibit RON, for example, about 30 ohms, but ODT does not need to be provided. All PU transistors in the branches 410-460 and the static branch 470 are turned on, while all PD transistors and second PU transistors in the branches 410-460 and the static branch 470 are turned off. As a result, the driver stage 400 exhibits RON, which is the parallel resistance of all resistors in the branches 410-460 and the static branch 470 (including the on-resistance of the PU transistors). Although in the illustrated embodiment, the PU transistors in all branches 410-460 are turned on, in actual situations, only the PU transistors in one or some of the branches 410-460 (which are selected based on the retrieved PU control code) are turned on, while the other PU transistors are turned off. The pre-layout simulation shows that the voltage at the pad 240 is VOH=1.1V.

[0055] Figure 7The driver stage 400 for DDR5 is shown when configured to transmit a logic 0. During this period, the driver stage 400 is expected to exhibit RON because the TX path is transmitting, but it is expected that the driver stage 400 also provides ODT because the RX path is receiving. In the illustrated example, the PU transistors in branches 410, 420, 440, 460 and the static branch 470 are turned off, while the PU transistor 432 in branch 430 and the PU transistor 452 in branch 450 are turned on. The PD transistors in branches 410-450 and the static branch 470 are turned off, while the PD transistor 464 in branch 460 is turned on. The second PU transistors in all branches 410-460 and the static branch 470 are turned off. As a result, driver stage 400 exhibits RON, which is the parallel resistance of resistor 436 in branch 430 (including the on-resistance of PU transistor 432) and resistor 456 in branch 450 (including the on-resistance of PU transistor 452), and also exhibits ODT, which is the resistance of resistor 466 in branch 460 (including the on-resistance of PD transistor 464). Pre-layout simulations show that the voltage at pad 240 is VOL=0.48V to 0.52V at different PVTs. Figure 6 , Vcm is calculated to be 0.78V to 0.81V.

[0056] Figure 8 The driver stage 400 for LPDDR5 is shown when configured to transmit logic 0. During this period, in the illustrated example, all PD transistors in the branches 410-460 and the static branch 470 are turned on, while all PU transistors and the second PU transistors in the branches 410-460 and the static branch 470 are turned off. As a result, the driver stage 400 exhibits RON, which is the parallel resistance of all resistors in the branches 410-460 and the static branch 470 (including the on-resistance of the PD transistors). Although in the illustrated embodiment, the PD transistors in all branches 410-460 are turned on, in actual situations, only the PD transistors in one or some of the branches 410-460 (which are selected based on the retrieved PU control code) are turned on, while the other PD transistors are turned off. The pre-layout simulation shows that the voltage at the pad 240 is VOL=0V.

[0057] Fig. 9The driver stage 400 for LPDDR5 is shown when configured to transmit a logic 1. During this period, in the illustrated example, the second PU transistors in branches 410-450 and static branch 470 are turned off, while the second PU transistor 468 in branch 460 is turned on. The PD transistors in branches 410, 420, 440, 460 and static branch 470 are turned off, while the PD transistor 434 in branch 430 and the PD transistor 454 in branch 450 are turned on. The PU transistors in all branches 410-460 and static branch 470 are turned off. As a result, driver stage 400 exhibits RON, which is the parallel resistance of resistor 436 in branch 430 (including the on-resistance of PD transistor 434) and resistor 456 in branch 450 (including the on-resistance of PD transistor 454), and also exhibits ODT, which is the resistance of resistor 466 in branch 460 (including the on-resistance of PU transistor 468). Pre-layout simulations show that the voltage at pad 240 is VOH=0.29V to 0.31V at different PVTs. Figure 8 , Vcm is about 0.145V to 0.155V.

[0058] Table 2 provides estimated data for the DDR5 IOLB mode when the PD control code is 10 higher than the PU control code and RON is 30 ohms. In the example of Table 2, the pair of codes 32 and 20 in Table 1 is used. The following is an example showing how the data in Table 2 is obtained even when the actual resistance of the transistors and resistors are unknown. Assume that under a specific PVT condition corresponding to the row shown in bold in Table 2, the PU control code 30 (column 3) is retrieved during the period used to drive a logic 1. Then, since the actual control code is 32 (as shown in FIG. 1 ), the PU control code 30 (column 3) is retrieved during the period used to drive a logic 1. Figure 6 As shown, considering the resistance of the PU transistor and resistor in the static branch 470, which is half of the unit resistance and is equivalent to an additional "2" added to the PU control code), and the parallel resistance of the branch and the static branch is 30 ohms, the unit resistance can be derived as 32*30=960 ohms, as shown in the 4th column. Since the PD control code is 10 higher than the PU control code, the PD control code if retrieved will be 40 (column 1), and the unit resistance of the PD transistor and resistor can be derived as (40+2)*30=1260 ohms, as shown in the 2nd column. In the period for driving logic 0, the compensation block 490 overturns the retrieved PU control code to 20 and overturns the PD control code to 32. As a result, in this period, ODT will be formed by resistors 436 and 456 (including the on-resistance of PU transistors 432 and 452), and RON will be provided by resistor 466 (including the on-resistance of PD transistor 464), as shown in the 2nd column. Figure 7As shown. Therefore, ODT can be derived as 960 / 20=48 ohms (column 6), and RON can be derived as 1260 / 32=39.38 ohms (column 5), VOL can be calculated as 39.38 / (39.38+48)*1.1=0.50V, and Vcm is (VOH+VOL) / 2=0.80V (columns 7 and 10). The current flowing through the driver stage 400 is 1.1 / (39.38+48)=12.6mA (column 11). Considering that the data pattern in the LB test is alternating like 101010..., the average current during the data pattern is 12.6 / 2=6.3mA (column 12) because almost no current flows during the driving logic "1" period.

[0059] As mentioned above Figure 5 As described, the retrieved PU control codes (column 3) are generally in the range of 26 to 45. The estimated data in Table 2 show that in this range, RON is in the range of 35.63 to 53.44 ohms, and ODT is in the range of 42 to 70.5 ohms. These values ​​are close to the expected values ​​of 30 ohms for RON and 50 ohms for ODT (although not fixedly compensated to these two values), and relatively appropriate termination can be achieved. The voltage swing at the near end is from VOL = (0.47V ~ 0.50V) to VOH = 1.1V, which means that the driver stage can be tested at substantially realistic voltages. The average current in the IOLB test is between 7.1mA and 4.4mA, allowing very low power consumption.

[0060]

[0061] Table 2

[0062] Table 3 provides estimated data for the DDR5 IOLB mode when the PD control code is 5 higher than the PU control code and RON is 30 ohms. The calculation of the data can be similar to that of Table 2, and the description will be omitted. In the example of Table 3, a pair of codes 32 and 24 in Table 1 is used. Compared with the 20 branches of ODT, using 24 branches for ODT will achieve a stronger impedance, and a stronger impedance is generally beneficial for supporting higher data rates. It should be noted that the codes 32 / 20 and 32 / 24 used in Tables 2-5 are only examples. Any combination of the codes listed in Table 1 can be used in MEM PHY 118 to meet certain design requirements.

[0063]

[0064]

[0065] Table 3

[0066] Table 4 provides estimated data for LPDDR5 IOLB mode when the PD control code is 10 higher than the PU control code and RON is 30 ohms. In the example of Table 4, the pair of codes 32 and 20 in Table 1 is used. The data can be calculated similarly to Table 2, but with reference to Figure 8 and Fig. 9 As mentioned above Figure 5 As mentioned, the retrieved PD control codes (column 1) are generally in the range of 35 to 57. The estimated data in Table 4 show excellent performance in this range.

[0067]

[0068]

[0069] Table 4

[0070] Table 5 provides estimated data for LPDDR5 IOLB mode when the PD control code is 5 higher than the PU control code and RON is 30 ohms. The pair of codes 32 and 20 in Table 1 is used. The calculation of the data can be similar to Table 4 and will be omitted.

[0071]

[0072]

[0073] Table 5

[0074] Table 6 below provides data obtained from simulations of several signal integrity test cases for the LPDDR5 design, and Fig.10 The eye diagrams from the simulations of typical test cases No. 1, No. 4, and No. 8 in Table 6 are shown. In test case No. 1, the MEM PHY does not provide ODT, and the tester provides a 50 ohm termination at the far end. In test cases Nos. 2-7, the MEM PHY Figure 8 and Fig. 9 In test case No. 8, the MEM PHY does not provide ODT, nor does the tester, and slight crosstalk is assumed. Fig.10 As shown in the eye diagram and the data in Table 6, although good far-end termination may be most desirable in terms of signal integrity, a single-segment configuration of the MEM PHY driver stage according to the present disclosure can achieve reasonable results and is much better than the unterminated case. The embodiments of the present disclosure enable the tester designer to avoid the additional work and cost of properly routing and shielding all pins (e.g., DQ / DQS) within the MEM PHY layout area, and the single-segment configuration does not require the same Figure 2In addition, embodiments of the present disclosure allow for very low power operation. It is estimated that a MEMPHY according to the present disclosure will have a power consumption of less than 1.5*10 -12 Power consumption is in joules / bit (1.5 pj / b).

[0075]

[0076] Table 6

[0077] Although the above embodiments are described with DDR5 / LPDDR5 as an example, the present disclosure is not limited thereto, but may be applied to its successors, server DDR5, or any other memory technology that allows loopback mode. In addition, although a binary weighted architecture for the TX path is illustrated, the present disclosure is not limited thereto; other embodiments may have different resistance ratios between branches and use different encoding schemes for the PU / PD control codes accordingly.

[0078] Embodiments of the present disclosure may also be implemented as independent intellectual property (IP) designs. Semiconductor IP blocks are reusable units of ICs. IP blocks may be licensed to one or more parties for integration into silicon packages. Designers of field programmable gate arrays (FPGAs) and SoC systems may use IP blocks as building blocks. For this purpose, a storage medium, such as a non-transitory storage medium, may be provided. The storage medium may store instructions or data that reflect a circuit design to implement a driver stage or MEM PHY as described above. These instructions, when executed by a computer, or when these data are used in a computer, may result in the manufacture (e.g., in a semiconductor manufacturing facility) of an IC or other device so that the IC or device includes a driver stage or MEM PHY as described above.

[0079] The following examples disclose various aspects of the present disclosure:

[0080] In Example 1, a memory interface circuit may include a driver stage and a logic circuit. The driver stage has multiple branches, each branch including a pull-up (PU) transistor, a pull-down (PD) transistor, and a resistor. The PU transistor has a first source / drain terminal coupled to a power supply node, a second source / drain terminal coupled to an intermediate node, and a gate coupled to receive a bit of a PU control code. The PD transistor has a first source / drain terminal coupled to the intermediate node, a second source / drain terminal coupled to a ground node, and a gate coupled to receive a bit of a PD control code. The resistor has a first end coupled to the intermediate node and a second end coupled to a pin of the memory interface circuit. The logic circuit provides the PU control code and the PD control code to the driver stage.

[0081] Example 2 includes the memory interface circuit of Example 1, wherein the logic circuit is configured to provide the PU control code and the PD control code such that in a first period of a loopback mode: for each of a first subset of the branches, the PU transistor is turned on and the PD transistor is turned off so that the resistor provides at least a portion of an on-die termination (ODT) for the driver stage, and for each of a second subset of the branches, the PU transistor is turned off and the PD transistor is turned on so that the resistor provides at least a portion of a transmitter resistance for the driver stage. A result of a logical AND operation between the PU control code and the PD control code is a logical 0.

[0082] Example 3 includes the memory interface circuit as described in Example 2, wherein the logic circuit is further configured to provide the PU control code and the PD control code so that in the second period of the loopback mode, the PU transistor of each of one or more of the branches is turned on and the PD transistors of all branches are turned off.

[0083] Example 4 includes the memory interface circuit of Example 3, wherein the driver stage further includes an additional branch, the additional branch including a PU transistor, a PD transistor, and a resistor. The PU transistor has a first source / drain terminal coupled to a power supply node, a second source / drain terminal coupled to an intermediate node, and a gate coupled to receive a PU control bit from the logic circuit. The PD transistor has a first source / drain terminal coupled to the intermediate node, a second source / drain terminal coupled to a ground node, and a gate coupled to receive a PD control bit from the logic circuit. The resistor has a first end coupled to the intermediate node and a second end coupled to the pin. In the first time period, both the PU transistor and the PD transistor of the additional branch are turned off, and in the second time period, the PU transistor of the additional branch is turned on and the PD transistor of the additional branch is turned off.

[0084] Example 5 includes the memory interface circuit as described in Example 3, wherein the logic circuit is coupled to retrieve the PU control code for the second time period from a hardware register, and set the PU control code and the PD control code for the first time period based on a lookup table (LUT) in the memory interface circuit.

[0085] Example 6 includes the memory interface circuit of Example 5, wherein the number of branches is 6, and the PU control code is set to 20 and the PD control code is set to 32 for the first period.

[0086] Example 7 includes a memory interface circuit as described in any one of Examples 1-6, wherein, in the first time period, the pin exhibits a low level voltage (VOL) that complies with the Joint Electron Devices Engineering Council (JEDEC) DDR standard, and in the second time period, the pin exhibits a high level voltage (VOH) that complies with the JEDEC DDR standard.

[0087] Example 8 includes the memory interface circuit of Example 1, wherein the logic circuit is configured to provide the PU control code and the PD control code such that in a first period of a loopback mode: for each of a first subset of the branches, the PD transistor is turned on and the PU transistor is turned off so that the resistor provides at least a portion of a transmitter resistance for the driver stage, and for each of a second subset of the branches, the PD transistor is turned off and the PU transistor is turned on so that the resistor provides at least a portion of an on-die termination (ODT) for the driver stage. A result of a logical AND operation between the PU control code and the PD control code is a logic 0.

[0088] Example 9 includes the memory interface circuit as described in Example 8, wherein the logic circuit is further configured to provide the PU control code and the PD control code so that in the second period of the loopback mode, the PD transistor of each of one or more of the branches is turned on and the PU transistors of all branches are turned off.

[0089] Example 10 includes the memory interface circuit of Example 9, wherein the driver stage further includes an additional branch, the additional branch including a PU transistor, a PD transistor, and a resistor. The PU transistor has a first source / drain terminal coupled to a power supply node, a second source / drain terminal coupled to an intermediate node, and a gate coupled to receive a PU control bit from the logic circuit. The PD transistor has a first source / drain terminal coupled to the intermediate node, a second source / drain terminal coupled to a ground node, and a gate coupled to receive a PD control bit from the logic circuit. The resistor has a first end coupled to the intermediate node and a second end coupled to the pin. In the first time period, the PD transistor and the PU transistor of the additional branch are both turned off, and in the second time period, the PD transistor of the additional branch is turned on and the PU transistor of the additional branch is turned off.

[0090] Example 11 includes a memory interface circuit as described in Example 9, wherein the logic circuit is coupled to retrieve the PD control code for the second time period from a hardware register, and set the PD control code and the PU control code for the first time period based on a lookup table (LUT) in the memory interface circuit.

[0091] Example 12 includes the memory interface circuit of Example 11, wherein the number of branches is 6, and the PD control code is set to 20 and the PU control code is set to 32 for the first period.

[0092] Example 13 includes a memory interface circuit as described in any one of Examples 8-12, wherein, in the first time period, the pin exhibits a high level voltage (VOH) that complies with the Joint Electron Devices Engineering Council (JEDEC) low power DDR (LPDDR) standard, and in the second time period, the pin exhibits a low level voltage (VOL) that complies with the JEDEC LPDDR standard.

[0093] Example 14 includes the memory interface circuit of any of Examples 1-13, wherein each of the branches further comprises a second PU transistor coupled in parallel with the PU transistor, the second PU transistor being turned off in both the first time period and the second time period.

[0094] Example 15 includes a memory interface circuit as described in any one of Examples 1-14, wherein, from the most significant bit (MSB) to the least significant bit (LSB) of the PU control code, the sizes of the PU transistors and PD transistors of the branches are set so that the on-resistance of the PU transistor of the branch corresponding to the bit is half of the on-resistance of the PU transistor of the next branch, and the on-resistance of the PD transistor of the branch corresponding to the bit is half of the on-resistance of the PD transistor of the next branch, and the resistance of the resistor of the branch corresponding to the bit is half of the resistance of the resistor of the next branch.

[0095] Example 16 includes a memory interface circuit as described in Example 4 or 10, wherein the on-resistance of the PU transistor of the additional branch is half of the on-resistance of the PU transistor of the branch corresponding to the least significant bit of the PU control code, the on-resistance of the PD transistor of the additional branch is half of the on-resistance of the PD transistor of the branch corresponding to the least significant bit of the PD control code, and the resistance of the resistor of the additional branch is half of the resistance of the resistor of the branch corresponding to the least significant bit of the PU control code.

[0096] Example 17 includes the memory interface circuit of Example 6, wherein the retrieved PU control code is in the range of 26 to 45.

[0097] Example 18 includes the memory interface circuit of Example 12, wherein the retrieved PD control code is in the range of 35 to 57.

[0098] Example 19 includes the memory interface circuit of any of Examples 1-18, wherein the power supply node provides a voltage of 1.1 V or 0.5 V.

[0099] In Example 20, an apparatus for a computing system includes a processor, a memory controller communicatively coupled to the processor; and a memory interface circuit as described in any of Examples 1-19 coupled to the memory controller.

[0100] In Example 21, a non-transitory storage medium having instructions or data stored thereon so that a device including the memory interface circuit of any one of Examples 1-19 is manufactured.

[0101] Discussion herein utilizing terms such as “process,” “compute,” “calculate,” “determine,” “establish,” “analyze,” “examine,” and the like may refer to operations (or operations) and / or processes (or processes) of a computer, computing platform, computing system, or other electronic computing device that manipulate and / or transform data represented as physical (e.g., electronic) quantities within the computer's registers and / or memories into other data similarly represented as physical quantities within the computer's registers and / or memories or other information processing media that may store instructions to perform the operations and / or processes.

[0102] As used herein, the terms "plurality" and "plurality" include, for example, "multiple" or "two or more." For example, "a plurality of items" includes two or more items.

[0103] The terms "group," "set," "sequence," and the like refer to a number equal to or greater than one.

[0104] Any term expressed in plural form without expressly stating "plurality" or "multiple" similarly refers to a number equal to or greater than one.

[0105] The words “exemplary” or “illustrative” are used herein to mean “serving as an example, instance, demonstration, or illustration.” Any aspect, embodiment, or design described herein as “exemplary” or “illustrative” is not necessarily to be construed as preferred or advantageous over other aspects, embodiments, or designs.

[0106] As used herein, unless otherwise indicated, the use of ordinal adjectives "first," "second," "third," etc. to describe common objects simply indicates that different instances of similar objects are referenced and is not intended to imply that the objects so described must be in a given sequence in time, space, ranking, or in any other manner.

[0107] The phrases “at least one” and “one or more” may be understood to include numerical quantities greater than or equal to one, for example, one, two, three, four, [...], etc. The phrase “at least one of” with respect to a group of elements may be used herein to mean at least one element from the group consisting of these elements.

[0108] The term "data" when used herein may be understood to include information in any suitable analog or digital form, for example, information provided in the form of a signal or stream, a portion of a signal or stream, a group of signals or streams, or the like. In addition, the term "data" may also be used to refer to a reference to information, for example, in the form of a pointer. However, the term "data" is not limited to the above examples, but may take various forms and / or represent any information understood in the art.

[0109] Although the present invention has been specifically shown and described with reference to specific embodiments, it will be understood by those skilled in the art that various changes in form and details may be made thereto without departing from the spirit and scope of the present invention as defined in the appended claims. The scope of the present invention is thus indicated by the appended claims, and therefore it is intended to include all changes within the equivalent meaning and scope of the claims.

Claims

1. A memory interface circuit, comprising: The driver stage has multiple branches, each branch includes: a pull-up (PU) transistor having a first source / drain terminal coupled to the power supply node, a second source / drain terminal coupled to the intermediate node, and a gate coupled to receive a bit of the PU control code; a pull-down (PD) transistor having a first source / drain terminal coupled to the intermediate node, a second source / drain terminal coupled to a ground node, and a gate coupled to receive a bit of a PD control code; and a resistor having a first end coupled to the intermediate node and a second end coupled to a pin of the memory interface circuit, and A logic circuit is used to provide the PU control code and the PD control code to the driver stage.

2. The memory interface circuit according to claim 1, wherein: The logic circuit is configured to provide the PU control code and the PD control code so that in a first period of the loopback mode: For each of the first subset of the branches, the PU transistor is turned on and the PD transistor is turned off such that the resistor provides at least a portion of an on-die termination (ODT) for the driver stage, and For each of the second subset of the branches, the PU transistor is turned off and the PD transistor is turned on so that the resistor provides at least a portion of a transmitter resistance for the driver stage, and The result of the logical AND operation between the PU control code and the PD control code is logic 0.

3. The memory interface circuit according to claim 2, wherein: The logic circuit is also configured to provide the PU control code and the PD control code so that in a second period of the loopback mode, the PU transistor of each of one or more of the branches is turned on and the PD transistors of all branches are turned off.

4. The memory interface circuit according to claim 3, wherein: The driver stage further comprises an additional branch comprising: a PU transistor having a first source / drain terminal coupled to the power supply node, a second source / drain terminal coupled to the intermediate node, and a gate coupled to receive the PU control bit from the logic circuit; a PD transistor having a first source / drain terminal coupled to the intermediate node, a second source / drain terminal coupled to a ground node, and a gate coupled to receive a PD control bit from the logic circuit; and a resistor having a first end coupled to the intermediate node and a second end coupled to the pin, and Wherein, in the first time period, both the PU transistor and the PD transistor of the additional branch are turned off, and in the second time period, the PU transistor of the additional branch is turned on and the PD transistor of the additional branch is turned off.

5. The memory interface circuit as claimed in claim 3, wherein: The logic circuit is coupled to retrieve the PU control code for the second period from a hardware register and set the PU control code and the PD control code for the first period based on a lookup table (LUT) in the memory interface circuit.

6. The memory interface circuit as claimed in claim 5, wherein: The number of the branches is 6, and the PU control code is set to 20 and the PD control code is set to 32 for the first period.

7. The memory interface circuit according to any one of claims 1 to 6, wherein: During the first period, the pin exhibits a low level voltage (VOL) compliant with a Joint Electron Device Engineering Council (JEDEC) DDR standard, and during the second period, the pin exhibits a high level voltage (VOH) compliant with the JEDEC DDR standard.

8. The memory interface circuit according to claim 1, wherein: The logic circuit is configured to provide the PU control code and the PD control code so that in a first period of the loopback mode: For each of the first subset of the branches, the PD transistor is turned on and the PU transistor is turned off so that the resistor provides at least a portion of a transmitter resistance for the driver stage, and For each of the second subset of the branches, the PD transistor is turned off and the PU transistor is turned on so that the resistor provides at least a portion of an on-die termination (ODT) for the driver stage, and The result of the logical AND operation between the PU control code and the PD control code is logic 0.

9. The memory interface circuit of claim 8, wherein: The logic circuit is also configured to provide the PU control code and the PD control code so that in a second period of the loopback mode, the PD transistor of each of one or more of the branches is turned on and the PU transistors of all branches are turned off.

10. The memory interface circuit of claim 9, wherein: The driver stage further comprises an additional branch comprising: a PU transistor having a first source / drain terminal coupled to the power supply node, a second source / drain terminal coupled to the intermediate node, and a gate coupled to receive the PU control bit from the logic circuit; a PD transistor having a first source / drain terminal coupled to the intermediate node, a second source / drain terminal coupled to a ground node, and a gate coupled to receive a PD control bit from the logic circuit; and a resistor having a first end coupled to the intermediate node and a second end coupled to the pin, and Wherein, in the first time period, both the PD transistor and the PU transistor of the additional branch are turned off, and in the second time period, the PD transistor of the additional branch is turned on and the PU transistor of the additional branch is turned off.

11. The memory interface circuit according to claim 9, wherein: The logic circuit is coupled to retrieve the PD control code for the second period from a hardware register and set the PD control code and the PU control code for the first period based on a lookup table (LUT) in the memory interface circuit.

12. The memory interface circuit of claim 11, wherein: The number of the branches is 6, and for the first period, the PD control code is set to 20 and the PU control code is set to 32.

13. The memory interface circuit according to any one of claims 8 to 12, wherein: During the first period, the pin exhibits a high level voltage (VOH) that complies with the Joint Electron Device Engineering Council (JEDEC) low power DDR (LPDDR) standard, and during the second period, the pin exhibits a low level voltage (VOL) that complies with the JEDEC LPDDR standard.

14. The memory interface circuit according to any one of claims 1 to 13, wherein: Each of the branches also includes a second PU transistor coupled in parallel with the PU transistor, the second PU transistor being turned off in both the first period and the second period.

15. The memory interface circuit according to any one of claims 1 to 14, wherein: From the most significant bit (MSB) to the least significant bit (LSB) of the PU control code, the sizes of the PU transistor and the PD transistor of the branch are set so that: the on-resistance of the PU transistor of the branch corresponding to the bit is half of the on-resistance of the PU transistor of the next branch, the on-resistance of the PD transistor of the branch corresponding to the bit is half of the on-resistance of the PD transistor of the next branch, and the resistance of the resistor of the branch corresponding to the bit is half of the resistance of the resistor of the next branch.

16. The memory interface circuit according to claim 4 or 10, wherein: The on-resistance of the PU transistor of the additional branch is half of the on-resistance of the PU transistor of the branch corresponding to the least significant bit of the PU control code, the on-resistance of the PD transistor of the additional branch is half of the on-resistance of the PD transistor of the branch corresponding to the least significant bit of the PD control code, and the resistance of the resistor of the additional branch is half of the resistance of the resistor of the branch corresponding to the least significant bit of the PU control code.

17. The memory interface circuit of claim 6, wherein: The retrieved PU control code is in the range of 26 to 45.

18. The memory interface circuit of claim 12, wherein: The retrieved PD control codes are in the range of 35 to 57.

19. An apparatus for a computing system, comprising: processor; a memory controller communicatively coupled to the processor; as well as The memory interface circuit of any one of claims 1-18 coupled to the memory controller.

20. A non-transitory storage medium having instructions or data stored thereon, for causing a device including the memory interface circuit according to any one of claims 1 to 18 to be manufactured.

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