Memory device and memory system

Abstract

The invention relates to a memory device and a memory system. An example memory device includes a first core die, a second core die, and a base die stacked in a first direction. The base die is configured to output data of the memory cells provided by the first core die and the second core die at different burst lengths based on a mode signal through a through-via. The through via passes through the first core die and the second core die in the first direction.

Description

Technical Field

[0001] The present disclosure relates to memory devices, including memory devices for exchanging data of the number of data input / output pins with external devices and memory devices for reducing the cost of processes related to the size and pitch of the configuration of the external devices, and the present disclosure relates to memory systems including these memory devices. Background Art

[0002] As the amount of data to be processed by electronic devices increases, memory devices with high capacity and high bandwidth are required. In order to increase memory integration, a three-dimensional (3D) arrangement method for stacking memory chips has been developed from the existing two-dimensional (2D) arrangement method.

[0003] A high bandwidth memory (HBM) device may include vertically stacked semiconductor chips, and the semiconductor chips may be electrically connected through through vias such as through silicon vias (TSVs).

[0004] However, since the number of data input / output pins and the number of data input / output of the high-bandwidth memory device are fixed at relatively high values, the number of data input / output pins and the data transfer rate of the high-bandwidth memory device need to be configured differently to accommodate interconnectivity with an external device (e.g., a processor) that may have a greater or lesser number of data input / output pins and operate at a lower data transfer rate than the high-bandwidth memory device. Summary of the invention

[0005] In some implementations, a memory device includes: a first core die and a second core die, the first core die and the second core die being stacked along a first direction, the first core die including a first memory cell and the second core die including a second memory cell; and a base die, the base die being stacked along the first direction together with the first core die and the second core die, the base die being configured to output data of the first memory cell and the second memory cell provided by the first core die and the second core die with different burst lengths based on a mode signal through a through-path, the through-path passing through the first core die and the second core die in the first direction.

[0006] In some implementations, a memory device includes: a first core die and a second core die, the first core die and the second core die are stacked along a first direction, the first core die includes a first memory cell and the second core die includes a second memory cell; and a base die, the base die is stacked along the first direction together with the first core die and the second core die, the base die is configured to output data of the first memory cell and the second memory cell provided by the first core die and the second core die through a through-path, the through-path passes through the first core die and the second core die in the first direction, the base die includes a first data bump and a second data bump, a first data register, a second data register, and a multiplexer, the first data bump and the second data bump are connected to an external pad on one side and are configured to output the data, the first data register is connected to the first data bump, the second data register is connected to the second data bump, and the multiplexer is arranged between the first data register and the second data register.

[0007] In some implementations, a storage system includes: a storage device, the storage device including a first core die, a second core die, and a base die stacked along a first direction, the first core die including a first storage unit, the second core die including a second storage unit, the base die being configured to output data of the first storage unit and the second storage unit provided by the first core die and the second core die through a through-path, and the through-path passes through the first core die and the second core die in the first direction to a first data bump; and a memory controller, the memory controller being configured to exchange data with the storage device through the second data bumps, wherein the number of the second data bumps is less than the number of the first data bumps. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 An example configuration of a storage system is shown.

[0009] Figure 2 An example of a storage system is shown.

[0010] Figure 3 An example configuration of a core die stack is shown.

[0011] Figure 4 Shows Figure 2 An example magnified view of a predetermined area.

[0012] Figure 5 and Figure 6 An example base die and an example underside of a memory controller of a memory system are shown.

[0013] Figure 7 A configuration of another example of a memory device is shown.

[0014] Figure 8 An example of a memory device is shown.

[0015] Fig. 9 and Fig.10 A timing diagram is shown regarding the operation of an example of a memory device.

[0016] Fig.11 A configuration of another example of a memory device is shown.

[0017] Fig.12 and Fig.13 A timing diagram regarding the operation of another example of a memory device is shown.

[0018] Figures 14 to 16 Another example of a storage system is shown.

[0019] Fig.17 and Fig.18 A timing diagram regarding the operation of another example of a memory device is shown.

[0020] Fig.19 Another example of a storage system is shown.

[0021] Fig. 20 Another example of a storage system is shown.

[0022] Fig.21 A perspective view showing a configuration of an example of a system device to which a storage system is applied.

[0023] Fig. 22 A perspective view showing the configuration of another example of a system device to which the storage system is applied. DETAILED DESCRIPTION

[0024] In the following detailed description, only certain implementations of the present disclosure have been shown and described simply by way of illustration. As those skilled in the art will appreciate, the described implementations may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

[0025] The drawings and description are to be regarded as illustrative in nature and not restrictive, and like reference numerals designate like elements throughout the specification.

[0026] For better understanding and ease of description, the size and thickness of each configuration shown in the drawings are arbitrarily shown, but the present disclosure is not limited thereto. In the drawings, for clarity, the thickness of layers, films, panels, regions, etc. are magnified. For ease of explanation, the thickness of some layers and regions is exaggerated.

[0027] It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on another element," it can be directly on the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. The terms "on" or "over" mean being positioned on or below an object part, and do not necessarily mean being positioned on the upper side of an object part based on the direction of gravity.

[0028] Unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0029] The phrase “in a top view” means observing an object part from the top, and the phrase “in a cross-sectional view” means observing a cross section in which the object part is vertically cut from the side.

[0030] Figure 1 An example configuration of a storage system is shown.

[0031] refer to Figure 1 , a memory system 1 includes a memory device 10 and a memory controller 20 .

[0032] The memory device 10 may include memory channels MCHa to MCHh (refer to Figure 3 ), and is not limited thereto, it may be a dynamic random access memory (DRAM) such as a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate (LPDDR) SDRAM, a graphic double data rate (GDDR) SDRAM, or a memory bus dynamic random access memory (RDRAM). The memory channels MCHa to MCHh may include a memory cell array having memory cells.

[0033] The memory controller 20 may provide various signals to the memory device 10 through a memory interface, pins or bumps to control memory operations such as writing and reading. The memory controller 20 may have an additional die shape, and depending on the implementation, it may be installed in a system on chip (SoC) die, a graphics processing unit (GPU) die, and a central processing unit (CPU) die.

[0034] For example, the memory controller 20 may provide a command CMD and an address ADDR to the memory device 10 to access data DQ on a cell in the memory device 10. According to some implementations, the memory controller 20 may provide a mode signal MODE_SEL together with the command CMD and the address ADDR to the memory device 10, and may control an operation mode of the memory device 10 for memory operation, and the technical scope of the present disclosure is not limited thereto.

[0035] In addition, the memory device 10 may exchange data DQ with the memory controller 20 through the first data pads dp1_1 to dp1_N and the second data pads dp2_1 to dp2_M between the memory controller 20 and the memory device 10. M may be less than N, but is not limited thereto. According to some implementations, a ratio of the number of the second data pads dp2_1 to dp2_M to the number of the first data pads dp1_1 to dp1_N may be 1:n, and n may be an integer equal to or greater than 2.

[0036] The memory controller 20 can access the memory device 10 according to a request from a host (HOST). The memory controller 20 can communicate with the host by using various types of protocols, and for example, the memory controller 20 can communicate with the host by using an interface protocol such as PCI-E (Peripheral Component Interconnect Express), ATA (Advanced Technology Attachment), SATA (Serial ATA), PATA (Parallel ATA) or SAS (Serial Attached SCSI). In addition, other various types of interface protocols such as USB (Universal Serial Bus), MMC (Multimedia Card), ESDI (Enhanced Small Disk Interface) or IDE (Integrated Drive Electronics) can be applied to the protocol between the host and the memory controller 20.

[0037] Figures 2 to 4 An example of a storage system is shown. Figure 5 and Figure 6 An example base die of a memory device and an example underside of a memory controller are shown.

[0038] refer to Figures 1 to 6 , the memory system 1 includes a memory device 10 , a memory controller 20 , an interposer 30 , and a printed circuit board (PCB) 40 .

[0039] The memory device 10 may include a memory die 100 including four core dies 100_1 to 100_4 stacked along a third direction Z and a base die 200. First bumps MB may be formed between the stacked core dies 100_1 to 100_4 and the base die 200, and through silicon vias TSV (a through via) passing through the core dies 100_1 to 100_4 may be formed in the stacked first bumps MB.

[0040] The first direct access bump dab, the first power bump pb1, the first command and address bump cab1, and the first data bump db1 may be disposed on the lower side of the base die 200 with respect to the third direction Z. Although not shown, the base die 200 may include a data input / output buffer 295 (refer to FIG. 1 ) connected to the first data bump db1 and transmitting / receiving data. Figure 7 ).

[0041] refer to Figure 2 and Figure 3 Although only four core dies are shown, one or more embodiments are not limited thereto, and the core dies may be variously configured to have more than four or less than four. In addition, the base die 200 may not be stacked on the lower portion of the stacked core dies, but on the upper portion thereof.

[0042] Figure 3 A configuration of four stacked core dies 100_1 to 100_4 is shown, and the respective stacked core dies 100_1 to 100_4 may include two memory channels MCHa and MCHc, MCHb and MCHd, MCHe and MCHg, and MCHf and MCHh, and the respective memory channels MCHa to MCHh may include a predetermined number of memory banks.

[0043] Memory channels MCHa, MCHb, MCHe, and MCHf may be disposed on the left side of the core dies 100_1 to 100_4 with respect to the XY plane, and memory channels MCHc, MCHd, MCHg, and MCHh may be disposed on the right side of the core dies 100_1 to 100_4 with respect to the XY plane. Memory channels MCHa to MCHh may be respectively divided into the top and bottom of the corresponding core dies 100_1 to 100_4 and then may be disposed. The corresponding data terminals DQ1a to DQ4a, DQ1b to DQ4b, DQ1e to DQ4e and DQ1f to DQ4f and the corresponding command and address terminals CATa, CATb, CATe and CATf may be included in the divided and set memory channels MCHa, MCHb, MCHe and MCHf, and the corresponding data terminals DQ1c to DQ4c, DQ1d to DQ4d, DQ1g to DQ4g and DQ1h to DQ4h and the corresponding command and address terminals CATc, CATd, CATg and CATh may be included in the divided and set memory channels MCHc, MCHd, MCHg and MCHh. The first data group DG1 may be transmitted through the data terminals DQ1a, DQ1b, DQ1e and DQ1f, and the second data group DG2 may be transmitted through the data terminals DQ2a, DQ2b, DQ2e and DQ2f. In this way, the third data group DG3 to the eighth data group DG8 can be sent through the other data terminals DQ3a to DQ4h. The first command and address group CAG1 can be sent through the command and address terminals CATa, CATb, CATe and CATf, and the second command and address group CAG2 can be sent through the command and address terminals CATc, CATd, CATg and CATh.

[0044] Although not shown, Figure 7 The data input / output buffer 295 shown may be connected to corresponding data terminals DQ1a to DQ4a, DQ1b to DQ4b, DQ1c to DQ4c, DQ1d to DQ4d, DQ1e to DQ4e, DQ1f to DQ4f, DQ1g to DQ4g, and DQ1h to DQ4h.

[0045] refer to Figure 3 , the data terminal and the command and address terminals can be Figure 2 The first bump MB is shown. In addition, the line vertically passing through the data terminal and the command and address terminal may be a TSV.

[0046] Assuming that n-bit data is input / output through corresponding data terminals DQ1a-DQ4a, ..., DQ1h-DQ4h, a total of 32n-bit data can be input / output through all data terminals. Assuming that k-bit commands and addresses are input / output through corresponding command and address terminals CATa to CATh, a total of 8k-bit commands and addresses can be input / output through all command and address terminals.

[0047] like Figure 3 As shown, the second data group DG2 to the eighth data group DG8 are arranged in the same line as that corresponding to the first data group DG1, and the second command and address group CAG2 is arranged in the same line as that corresponding to the first command and address group CAG1.

[0048] Figure 2 and Figure 3 The illustrated core dies 100_1 to 100_4 may be manufactured as a memory device for respectively storing data input to a selected memory cell from among memory cells of a memory cell array through a data terminal or outputting data stored in the selected memory cell through a data terminal in response to commands and addresses received through command and address terminals.

[0049] The second command and address bump cab1, the second data bump db2, the second power bump pb2, and the first control signal bump cdb may be disposed on a lower side of the memory controller 20. Although not shown, the memory controller 20 may include a buffer connected to the second data bump db2.

[0050] The first bump MB, the first direct access bump dab, the first and second power bumps pb1 and pb2, the first and second command and address bumps cab1 and cab2, the first and second data bumps db1 and db2, and the first control signal bump cdb may be micro bumps.

[0051] The second direct access bump DAFB, the third power bump PBFB, and the second control signal bump CDFB may be disposed on the lower side of the adapter board 30. The adapter board 30 may include a direct line dal for connecting the first direct access bump dab and the second direct access bump DAFB, a command and address line cal for connecting the first command and address bump cab1 and the second command and address bump cab2, and a control signal line cdl for connecting the first data bump db1, the second data bump db2, the data line dl, the first control signal bump cdb, and the second control signal bump CDFB.

[0052] like Figures 4 to 6As shown, the first data bump db1 includes 1 to N first data bumps db1_1 to db1_N, and the second data bump db2 includes 1 to M second data bumps db2_1 to db2_M. According to some implementations, the number of the second data bumps db2 may be less than the number of the first data bumps db1, and the ratio of M to N may be 1 to n, and n is an integer equal to or greater than 2. According to some implementations, n may be 2 or 4. Figure 4 , Figure 5 and Figure 6 As shown, a ratio of the number of the second data pads dp2_1 to dp2_M to the number of the first data pads dp1_1 to dp1_N is 1 to 2, but other ratios may be used.

[0053] The first data bump db1 may include a data pad. For example, the first_x data bump db1_x and the first_y data bump db1_y included in the first data bump db1 may include a first_x data pad dp1_x and a first_y data pad dp1_y. In addition, the second data bump db2 may include data pads, respectively. For example, the second_a data bump db2_a included in the second data bump db2 may include a second_a data pad dp2_a.

[0054] The first data bump db1 and the second data bump db2 may be electrically connected through the adapter pads FP_x and FP_a and the data line dl_a provided on the upper side of the adapter board 30. According to some implementations, the first_x data bump db1_x and the first_y data bump db1_y may be connected to the xth adapter pad FP_x, and the xth adapter pad FP_x may be connected to the ath data line dl_a and the ath adapter pad FP_a, and data may be transmitted to / received from the second_a data pad dp2_a. According to some implementations, the ratio between the number of adapter pads connected to the data bump db1 and the number of data bumps db1 may be 1 to n, and n may be an integer equal to or greater than 2.

[0055] According to some implementations, the second data bump db2 and the data line d1 may correspond one-to-one, and the second data bump db2_a and the first data line d1_a may correspond to each other. According to some implementations, the number of data lines d1 may be less than the number of first data bumps db1, and the ratio of the number of first data bumps db1 to data lines d1 may be equal to the ratio of the number of first data bumps db1 to second data bumps db2. According to some implementations, the ratio between the number of data lines d1 and the number of first data bumps db1 may be 1 to n, and n may be an integer equal to or greater than 2, such as 2 or 4. Figure 4 , Figure 5 and Figure 6 As shown, a ratio between the number of data lines d1 and the number of first data bumps db1 may be 1:2.

[0056] The memory system 1 can provide a memory controller and an interposer for reducing the cost of a process related to a size and pitch of a configuration through a ratio of the number of second data pads dp2_1 to dp2_M to the number of first data pads dp1_1 to dp1_N and a ratio of data lines d1 to the number of first data bumps db1.

[0057] Although not shown, the interposer 30 may additionally include power lines for connecting the first power bump pb1 and the third power bump PBFB and connecting the second power bump pb2 and the third power bump PBFB. The second direct access bump DAFB, the third power bump PBFB, and the second control signal bump CDFB may be flip chip bumps.

[0058] The direct access ball DAB, the power ball PB, and the control signal ball CDB may be disposed on a lower side of the PCB 40 .

[0059] The second direct access bump DAFB may be connected to the direct access ball DAB, the third power bump PBFB may be connected to the power ball PB, and the second control signal bump CDFB may be connected to the control signal ball CDB on the PCB 40 .

[0060] Figure 7 A configuration of another example of a memory device is shown. Figure 8 An example of a memory device is shown.

[0061] refer to Figure 7 and Figure 8 The memory device 10 includes a memory cell array 110, a row decoder 120, a sense amplifier 170, a control logic circuit 210, an address register 220, a memory body control logic 230, a refresh control circuit 245, a column address (CA) latch 250, a row address multiplexer (RA MUX) 260, a column decoder 270, an input / output (I / O) gating circuit 290, and a data input / output buffer 295.

[0062] The memory cell array 110 may include a predetermined number of memory banks (not shown) included in the memory channels MCHa to MCHh. According to some implementations, the sense amplifier 170, the row decoder 120, and the column decoder 270 may include a bank sense amplifier and a bank row decoder connected to the corresponding memory banks, but are not limited thereto.

[0063] The memory cell array 110 may include word lines WL, bit lines BL, and memory cells MC disposed at points where the word lines WL and the bit lines BL intersect.

[0064] The control logic circuit 210 may control the operation of the memory device 10. For example, the control logic circuit 210 may generate a control signal so that the memory device 10 may perform a write operation or a read operation. The control logic circuit 210 may include a command decoder 211 for decoding a command CMD provided by the memory controller 20 and a mode register 212 for setting an operation mode of the memory device 10.

[0065] For example, the command decoder 211 may decode a write enable signal, a row address strobe signal, a column address strobe signal, and a channel select signal to generate a control signal CTL corresponding to the command CMD.

[0066] The mode register 212 may store setting information for setting an operation mode of the memory device 10. The memory controller 20 may perform a mode register write operation MRW to store the setting information in the mode register 212. The memory controller 20 may perform a mode register read operation MRR to receive the setting information stored in the mode register 212 from the memory device 10.

[0067] The address register 220 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller 20. The address register 220 may provide the received bank address BANK_ADDR to the bank control logic 230 and may provide the received row address ROW_ADDR to the row address multiplexer 260.

[0068] The bank control logic 230 may generate a bank control signal in response to the bank address BANK_ADDR. The row decoder 120 and the column decoder 270 may activate corresponding banks in response to the bank control signal.

[0069] The row address multiplexer 260 may receive the row address ROW_ADDR from the address register 220 and may receive the refresh row address REF_ADDR from the control logic circuit 210. The row address multiplexer 260 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output by the row address multiplexer 260 may be applied to the row decoder 120.

[0070] The column address latch 250 may receive the column address COL_ADDR from the address register 220 and may temporarily store the column address COL_ADDR. The column address latch 250 may gradually increase the column address COL_ADDR in the burst mode. The column address latch 250 may apply the temporarily stored or gradually increased column address to the column decoder 270.

[0071] The column decoder 270 may activate a sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the input / output gating circuit 290 in association with the bank activated by the bank control logic 230 .

[0072] The input / output gating circuit 290 may include an input / output data gating circuit, an input data masking logic, data registers 291_0 to 291_2n-1, and multiplexers 292_0 to 292_n-1. The input / output gating circuit 290 may receive a control signal CTL from the control logic circuit 210, and may receive a mode signal MODE_SEL from the memory controller 20. According to some implementations, such as Figure 5 As shown, the mode signal MODE_SEL may be input to the input / output gating circuit 290 through the first command and address bump cab1.

[0073] The corresponding data registers 291_0 to 291_2n-1 may input / output data DQ[0] to DQ[2n-1] to / from the first data pads dp1_0 to dp1_2n-1 through the data input / output buffer 295. For ease of description, Figure 5 The reference numerals of the first data pads dp1_1 to dp1_N are shown to be different from Figure 8 The reference numerals of the first data pads dp1_0 to dp1_2n-1 are shown, but according to the technical scope of the present disclosure, Figure 5 and Figure 8 The corresponding configurations shown are the same. According to some implementations, Figure 5 N can be equal to Figure 8 2n.

[0074] The bit lines corresponding to the burst length BL may be accessed simultaneously to support a burst mode at a burst length indicating the maximum number of column positions for accessing the bit lines by the memory device 10. The data registers 291_0 to 290_2n-1 may temporarily store the simultaneously accessed bits in sequence in the burst mode, and the burst length may be set to 8 as shown in the drawing, but is not limited thereto.

[0075] The multiplexers 292_0 to 292_n-1 may be disposed between the even-numbered data registers 291_0, ..., 291_2n-2 and the odd-numbered data registers 291_1, ..., 291_2n-1. In the present disclosure, the multiplexers 292_0 to 292_n-1 may determine the data path input / output according to the input mode signal MODE_SEL. In addition, the multiplexers 292_0 to 292_n-1 may work as a multiplexer or a demultiplexer according to the operation of the memory device 10.

[0076] In a read operation of the memory device 10, the multiplexers 292_0 to 292_n-1 may output the data DQ[0], ..., DQ[2n-2] output by the even-numbered data registers 291_0, ..., 291_2n-2 to the even-numbered first data pads dp1_0, ..., dp1_2n-2 through the data input / output buffer 295 according to the mode signal MODE_SEL. The multiplexers 292_0 to 292_n-1 may output the data DQ[0], ..., DQ[2n-2] output by the even-numbered data registers 291_0, ..., 291_2n-2 to the odd-numbered data registers 291_1, ..., 291_2n-1 according to the mode signal MODE_SEL.

[0077] According to some implementations, data pads connected to data registers disposed on respective sides of a multiplexer located between the data registers may be connected to a transfer board pad.

[0078] For example, the first_0 data pad dp1_0 connected to the 0th data register 291_0 and the first_1 data pad dp1_1 connected to the first data register 291_1 may correspond to Figure 4 The first_x data pad dp1_x and the first_y data pad dp1_y of the transfer board 30, and the first_0 data pad dp1_0 and the first_1 data pad dp1_1 may be connected to one transfer board pad provided on the transfer board 30. The description about the first_0 data pad dp1_0 and the first_1 data pad dp1_1 may be respectively applicable to the even-numbered first data pads dp1_0, ..., dp1_2n-2 and the odd-numbered first data pads dp1_1, ..., dp1_2n-1.

[0079] The data input / output buffer 295 may synchronize the data DQ input / output by the memory controller 20 with the data clock WCK and may distinguish input data from output data. According to some implementations, the data input / output buffer 295 may receive a mode signal MODE_SEL and may control the operation of an input interface or an output interface.

[0080] According to some implementations, the memory cell array 110, the row decoder 120, and the sense amplifier 170 may be included in the memory die 100, and the control logic circuit 210, the address register 220, the memory body control logic 230, the refresh control circuit 245, the column address latch 250, the row address multiplexer 260, the column decoder 270, the input / output gating circuit 290, and the data input / output buffer 295 may be included in the base die 200.

[0081] Fig. 9 and Fig.10 A timing diagram is shown regarding the operation of an example of a memory device.

[0082] You can refer to Fig. 9 describe Figures 1 to 8 The first operation mode of the memory device 10 and may refer to Fig.10 describe Figures 1 to 8 The second operation mode of the memory device 10 is as follows.

[0083] refer to Figures 7 to 9 , before the 0th time t0, the mode signal MODE_SEL at the first level MODE1 is input to the multiplexers 292_0 to 292_n-1. The multiplexers 292_0 to 292_n-1 of the memory device 10 can operate in the first operation mode based on the mode signal MODE_SEL at the first level MODE1. In the first operation mode, the multiplexers 292_0 to 292_n-1 of the memory device 10 can output data with a first burst length through the odd-numbered first data pads dp1_1, ..., dp1_2n-1 from among the first data pads.

[0084] For example, at the 0th time t0, a read command is input, and from the first time t1 to the third time t3, the first data DQ[1] and the 0th data DQ[0] may be output to the 1st_1 data pad dp1_1 with a burst length of 16.

[0085] From the first time t1 to the second time t2, the first_1 data register 291_1 may output the first data DQ[1] to the first_1 data pad dp1_1 through the data input / output buffer 295, and the 0th multiplexer 292_0 may provide the 0th data DQ[0] provided to the first_0 data register 291_0 to the first_1 data register 291_1.

[0086] From the second time t2 to the third time t3, the 0th data register 291_0 may not perform an output operation to the 1st_0 data pad dp1_0. The first data register 291_1 may output the 0th data DQ[0] provided by the 0th multiplexer 292_0 to the 1st_1 data pad dp1_1 through the data input / output buffer 295.

[0087] From the first time t1 to the third time t3, the description of the operation of the 0th data register 291_0, the first data register 291_1, and the 0th multiplexer 292_0 can be applied to the even-numbered first data registers 291_0, ..., 291_2n-2, the odd-numbered first data registers 291_1, ..., 291_2n-1, and the multiplexers 292_0 to 292_n-1. As described above, in the first operation mode, DQ[1] and DQ[0] can be output only through the first_1 data pad dp1_1 with a burst length of, for example, 16. The first operation mode may also be referred to as a half mode.

[0088] refer to Fig.10 , before the fourth time t4, the mode signal MODE_SEL on the second level MODE2 may be input to the multiplexers 292_0 to 292_n-1. The multiplexers 292_0 to 292_n-1 of the memory device 10 may operate in the second operation mode based on the mode signal MODE_SEL under the second level MODE2. In the second operation mode, the multiplexers 292_0 to 292_n-1 of the memory device 10 may output data through the first data pads dp1_0 to dp1_2n-1 with a second burst length that is less than the first burst length. According to some implementations, the ratio of the second burst length to the first burst length is 1 to n, and n is an integer equal to or greater than 2.

[0089] For example, at the fourth time t4, a read command is input, and after a delay, the 0th data DQ[0] and the first data DQ[1] may be outputted at a burst length of 8 on the first_0 data pad dp1_0 and the first_1 data pad dp1_1, respectively, for the fifth time t5 to the sixth time t6.

[0090] From the fifth time t5 to the sixth time t6, the 0th data register 291_0 can output the 0th data DQ[0] to the 1st_0 data pad dp1_0 through the 0th multiplexer 292_0 and the data input / output buffer 295, and the first data register 291_1 can output the first data DQ[1] to the 1st_1 data pad dp1_1 through the data input / output buffer 295.

[0091] From the fifth time t5 to the sixth time t6, the description of the operation of the 0th data register 291_0, the first data register 291_1, and the 0th multiplexer 292_0 can be applied to the even-numbered first data registers 291_0, ..., 291_2n-2, the odd-numbered first data registers 291_1, ..., 291_2n-1, and the multiplexers 292_0 to 292_n-1. As described above, in the second operation mode, DQ[1] and DQ[0] can be output through the first_1 data pad dp1_1 and the first_0 data pad dp1_0, respectively, with a burst length of 8. The second operation mode can also be referred to as a full mode.

[0092] refer to Fig. 9 and Fig.10 , the first minimum burst section tCCD_M1 in the first operation mode MODE1 for the burst mode is twice the second minimum burst section tCCD_M2 in the second operation mode MODE2 for the burst mode. That is, the first burst mode of the first operation mode (e.g., half mode) is twice as large as the second burst mode of the second operation mode (e.g., full mode).

[0093] The device has been described as operating in different operation modes depending on the level of the mode signal MODE_SEL, and the mode signal MODE_SEL for changing the operation mode of the multiplexers 292_0 to 292_n-1 is not limited thereto.

[0094] The memory device 10 can adjust bumps for inputting / outputting data through the mode signal MODE_SEL without any change in configuration, thereby commonly exchanging data with an external device in terms of the number of data bumps.

[0095] Fig.11 A configuration of another example of a memory device is shown.

[0096] Can be used with Figure 7 The memory device 10 is described in comparison Fig.11 The memory device 10' is described in detail, and for ease of description, the differences between them will be focused on. Figure 7 The description of the corresponding configuration of the storage device 10 is replaced.

[0097] refer to Figure 8 and Fig.11 The input / output gating circuit 290 receives setting information SI about the burst mode MODE from the mode register 212 of the control logic circuit 210, and the setting information SI is latched and input to the multiplexers 292_0 to 292_n-1, and can control the operation of the multiplexers 292_0 to 292_n-1.

[0098] The multiplexers 292_0 to 292_n-1 may determine an input / output data path according to the latched setting information SI.

[0099] The multiplexers 292_0 to 292_n-1 may output the data DQ[0], ..., DQ[2n-2] output by the even-numbered data registers 291_0, ..., 291_2n-2 to the even-numbered first data pads dp1_0, ..., dp1_2n-2 through the data input / output buffer 295 according to the setting information SI. In addition, the multiplexers 292_0 to 292_n-1 may output the data DQ[0], ..., DQ[2n-2] output by the even-numbered data registers 291_0, ..., 291_2n-2 to the odd-numbered data registers 291_1, ..., 291_2n-1 according to the setting information SI.

[0100] Fig.12 and Fig.13 A timing diagram regarding the operation of another example of a memory device is shown.

[0101] You can refer to Fig.12 describe Fig.11 The first operation mode MODE1 of the memory device 10 ′ can be referred to Fig.13 describe Fig.11 The memory device 10 ′ performs a second operation mode MODE2 .

[0102] refer to Fig.11 and Fig.13 For the seventh time t7 before the eighth time t8, the memory controller 20 may perform a first mode register write MRW1 operation for the burst mode MODE from among the settings of the mode register 212. The first mode register write MRW1 may correspond to Fig. 9 The first operation mode MODE1. Instead Figure 8The mode signal MODE_SEL is inputted, and the setting information SI on which the first mode register write MRW1 operation is performed may be inputted to the multiplexers 292_0 to 292_n-1. The multiplexers 292_0 to 292_n-1 inputted with the setting information SI may be connected with the multiplexers 292_0 to 292_n-1 inputted with the setting information SI. Figure 8 and Fig. 9 The multiplexers 292_0 to 292_n-1 shown for the mode signal MODE_SEL on the first level MODE1 operate in a similar manner.

[0103] The description of the operation of the first data registers 291_0 to 291_2n-1 and the multiplexers 292_0 to 292_n-1 for the eighth time t8 to the eleventh time t11 may be used. Fig. 9 The description of the operation of the first data registers 291_0 to 291_2n-1 and the multiplexers 292_0 to 292_n-1 for the 0th time t0 to the third time t3 is replaced.

[0104] For the twelfth time t12 before the thirteenth time t13, the memory controller 20 may perform the second mode register write MRW2 operation at the burst mode MODE from among the settings of the mode register 212. The second mode register write MRW2 may correspond to Fig.10 The second operation mode MODE2. The setting information SI of the second mode register write MRW2 operation can be used Figure 8 The mode signal MODE_SEL is replaced by the mode signal MODE_SEL and can be input to the multiplexers 292_0 to 292_n-1. The multiplexers 292_0 to 292_n-1 input with the setting information SI can be used in the same manner as the multiplexers input with Figure 8 and Fig.10 The multiplexers 292_0 to 292_n-1 operate in a similar manner to the mode signal MODE_SEL at the second level MODE2.

[0105] The description of the operation of the first data registers 291_0 to 291_2n-1 and the multiplexers 292_0 to 292_n-1 for the thirteenth time t13 to the fifteenth time t15 can be used as follows: Fig.10 The description of the operation of the first data registers 291_0 to 291_2n-1 and the multiplexers 292_0 to 292_n-1 for the 0th time t0 to the third time t3 is replaced.

[0106] Figures 14 to 16 Another example of a storage system is shown.

[0107] Can be used with Figure 4 , Figure 6 and Figure 8The memory device 10 and the memory controller 20 are described in comparison Figures 14 to 16 The memory device 10″ and the memory controller 20″ are described in detail, and for ease of description, the differences between them will be focused on. The configurations of the memory device 10″ and the memory controller 20″ that are not described will be replaced with the configurations of the memory device 10″ and the memory controller 20″. Figure 4 , Figure 6 and Figure 8 The description of the corresponding configurations of the memory device 10 and the memory controller 20 is replaced.

[0108] The first data bump db1 may include data pads, respectively. For example, the first_x data bump db1_x, the first_y data bump db1_y, the first_z data bump db1_z, and the first_w data bump db1_w included in the first data bump db1 may include a first_x data pad db1_x, a first_y data pad db1_y, a first_z data pad db1_z, and a first_w data pad db1_w. In addition, the second data bump db2″ may include data pads, respectively. For example, the second_a data bump db2_a included in the second data bump db2″ may include a second_a data bump dp2_a.

[0109] The first data bump db1 and the second data bump db2" may be electrically connected through the transfer board pads FP_x and FP_a and the data line dl_a provided on the upper side of the transfer board 30. According to some implementations, the included first_x data bump db1_x, first_y data bump db1_y, first_z data bump db1_z, and first_w data bump db1_w may be connected to the xth transfer board pad FP_x, and the xth transfer board pad FP_x may be connected to the ath data line dl_a and the ath transfer board pad FP_a to send / receive data to / from the second_a data pad dp2_a.

[0110] like Fig.14 As shown, a ratio of the number of data lines d1 to the number of first data bumps db1 may be 1 to 4, and a ratio of the number of second data bumps db2″ to the number of first data bumps db1 may be 1 to 4.

[0111] The input / output gating circuit 290″ may include data registers 291″_0 to 291″_4m-1. The corresponding data registers 291″_0 to 290″_4m-1 may input / output data DQ[0] to DQ[4m-1] to / from the first data pads dp1_0 to dp1_4m-1 through the data input / output buffer 295. According to some implementations, Figure 8The 2n can be equal to Fig.16 of 4m.

[0112] The 4Xth multiplexer 292"_0, ..., 292"_4m-4 can be set between the 4Xth data register 291"_0, ..., 291"_4m-4 and the (4X+1)th data register 291"_1, ..., 291"_4m-3, and the (4X+1)th multiplexer 292"_1, ..., 292"_4m-3 can be set between the (4X+1)th data register 291"_1, ..., 291"_4m-3. …, 291”_4m-3 and the (4X+2)th data register 291”_2, …, 291”_4m-2, and the (4X+2)th multiplexer 292”_2, …, 292”_4m-2 can be set between the (4X+2)th data register 291”_2, …, 291”_4m-2 and the (4X+3)th data register 291”_3, …, 291”_4m-1. X can be an integer equal to or greater than 0, and can be less than m.

[0113] In the present disclosure, multiplexers 292"_0, ..., 292"_4m-2 may determine data path input / output according to input mode signal MODE_SEL. In addition, multiplexers 292"_0, ..., 292"_4m-2 may operate as multiplexers or demultiplexers according to the operation of memory device 10.

[0114] According to some implementations, data pads connected to four data registers with a multiplexer disposed between the four data registers may be connected to a transfer board pad.

[0115] For example, the first_0 data pad dp1_0 connected to the 0th data register 291″_0, the first_1 data pad dp1_1 connected to the first data register 291″_1, the first_2 data pad dp1_2 connected to the second data register 291″_2, and the first_3 data pad dp1_3 connected to the third data register 291″_3 may correspond to Fig.14The first_x data pad dp1_x, the first_y data pad dp1_y, the first_z data pad dp1_z and the first_w data pad dp1_w, and the first_0 data pad dp1_0, the first_1 data pad dp1_1, the first_2 data pad dp1_2 and the first_3 data pad dp1_3 may be connected to one transfer board pad disposed on the transfer board 30. The description about the first_0 data pad dp1_0, the first_1 data pad dp1_1, the first_2 data pad dp1_2, and the first_3 data pad dp1_3 may be applicable to the 4Xth first data pad dp1_0, ..., dp1_4m-4, the (4X+1)th first data pad dp1_1, ..., dp1_4m-3, the (4X+2)th first data pad dp1_2, ..., dp1_4m-2, and the (4X+3)th first data pad dp1_3, ..., dp1_4m-1. X may be an integer equal to or greater than 0, and may be less than m.

[0116] Fig.17 and Fig.18 A timing diagram regarding the operation of another example of a memory device is shown.

[0117] You can refer to Fig.17 describe Figures 14 to 16 The first operating mode of the memory device 10" and may refer to Fig.18 describe Figures 14 to 16 The second operation mode of the memory device 10 ” is implemented.

[0118] refer to Figures 14 to 18 , before the sixteenth time t16, the mode signal MODE_SEL on the first level MODE1 can be input to the multiplexers 292"_0, ..., 292"_4m-2. The multiplexers 292"_0, ..., 292"_4m-2 of the memory device 10" can operate in the first operating mode based on the mode signal MODE_SEL on the first level MODE1. In the first operating mode, the multiplexers 292"_0, ..., 292"_4m-2 of the memory device 10 can output data with a first burst length through the (4X+3)th first data pad dp1_3, ..., dp1_4m-1 from among the first data pads.

[0119] For the seventeenth time t17, a read command is input, and after a delay, for the seventeenth time t17 to the twenty-first time t21, the third data DQ[3], the second data DQ[2], the first data DQ[1] and the 0th data DQ[0] can be output on the first_3 data pad dp1_3 with a burst length of 32.

[0120] For the seventeenth time t17 to the eighteenth time t18, the third data register 291"_3 can output the third data DQ[3] to the first_3 data pad dp1_3 through the data input / output buffer 295, the second multiplexer 292"_2 can output the second data DQ[2] provided by the second data register 291"_2 to the third data register 291"_3, the first multiplexer 292"_1 can output the first data DQ[1] provided by the first data register 291"_1 to the second data register 291"_2, and the 0th multiplexer 292"_0 can output the 0th data DQ[0] provided by the 0th data register 291"_0 to the first data register 291"_1.

[0121] For the eighteenth time t18 to the nineteenth time t19, the third data register 291"_3 can output the second data DQ[2] to the first_3 data pad dp1_3 through the data input / output buffer 295, the second multiplexer 292"_2 can output the first data DQ[1] provided by the second data register 291"_2 to the third data register 291"_3, and the first multiplexer 292"_1 can output the 0th data DQ[0] provided by the first data register 291"_1 to the second data register 291"_2.

[0122] For the nineteenth time t19 to the twentieth time t20, the third data register 291"_3 can output the first data DQ[1] to the first_3 data pad dp1_3 through the data input / output buffer 295, and the second multiplexer 292"_2 can output the 0th data DQ[0] provided by the second data register 291"_2 to the third data register 291"_3.

[0123] For the twentieth time t20 to the twenty-first time t21, the third data register 291 ″_3 may output the 0th data DQ[0] to the first_3 data pad dp1_3 through the data input / output buffer 295 .

[0124] For the eighteenth time t18 to the twenty-first time t21, the 0th data register 291_0 may not perform an output operation to the first_0 data pad dp1_0. For the nineteenth time t19 to the twenty-first time t21, the first data register 291_1 may not perform an output operation to the first_1 data pad dp1_1. For the twentieth time t20 to the twenty-first time t21, the second data register 291_2 may not perform an output operation to the first_2 data pad dp1_2.

[0125] For the seventeenth time t17 to the twenty-first time t21, the description of the operation of the 0th data register 291"_0, the first_1st data register 291"_1, the second data register 291"_2, the third data register 291"_3, the 0th multiplexer 292"_0, the second multiplexer 292_1, and the second multiplexer 292"_2 can be respectively applied to the 4Xth first data register 291"_1, ..., 291"_4m-4, the (4X+1)th first data register 291"_3, 91"_0, ..., 291"_4m-3, the (4X+2)th first data register 291"_2, ..., 291"_4m-2, the (4X+3)th first data register 291"_3, ..., 291"_4m-1, the 4Xth multiplexer 292"_0, ..., 292"_4m-4, the (4X+1)th multiplexer 292"_1, ..., 292"_4m-3 and the (4X+2)th multiplexer 292"_2, ..., 292"_4m-2. X can be an integer equal to or greater than 0, and can be less than m.

[0126] Before the twenty-second time t22, the mode signal MODE_SEL on the second level MODE2 may be input to the multiplexers 292"_0, ..., 292"_4m-2. The multiplexers 292"_0, ..., 292"_4m-2 of the memory device 10" may operate in the second operating mode based on the mode signal MODE_SEL on the second level MODE2. In the second operating mode, the multiplexers 292"_0, ..., 292"_4m-2 of the memory device 10" may output data through the first data pads dp1_0 to dp1_4m-1 with a second burst length that is less than the first burst length.

[0127] For the twenty-second time t22, a read command is input, and after a delay, for the twenty-third time t23 to the twenty-fourth time t24, the 0th data DQ[0], the first data DQ[1], the second data DQ[2] and the third data DQ[3] can be output on the first_0 data pad dp1_0, the first_1 data pad dp1_1, the first_2 data pad dp1_2 and the first_3 data pad dp1_3 with a burst length of 8.

[0128] For the twenty-third time t23 to the twenty-fourth time t24, the 0th data register 291”_0 can output the 0th data DQ[0] to the first_0 data pad dp1_0 through the 0th multiplexer 292”_0 and the data input / output buffer 295, the first_1 data register 291”_1 can output the first data DQ[1] to the first_1 data pad dp1_1 through the first multiplexer 292”_1 and the data input / output buffer 295, the second data register 291”_2 can output the second data DQ[2] to the first_2 data pad dp1_2 through the second multiplexer 292”_2 and the data input / output buffer 295, and the third data register 291”_3 can output the third data DQ[3] to the first_3 data pad dp1_3 through the data input / output buffer 295.

[0129] For the twenty-third time t23 to the twenty-fourth time t24, the description of the operation of the 0th data register 291"_0, the first data register 291"_1, the second data register 291"_2, the third data register 291"_3, the 0th multiplexer 292"_0, the second multiplexer 292_1 and the second multiplexer 292"_2 can be respectively applied to the 4Xth first data register 291"_1, ..., 291"_4m-4, the (4X+1)th first data register 291"_3, the 0th multiplexer 292"_0, the second multiplexer 292_1 and the second multiplexer 292"_2. 1"_0, ..., 291"_4m-3, the (4X+2)th first data register 291"_2, ..., 291"_4m-2, the (4X+3)th first data register 291"_3, ..., 291"_4m-1, the 4Xth multiplexer 292"_0, ..., 292"_4m-4, the (4X+1)th multiplexer 292"_1, ..., 292"_4m-3 and the (4X+2)th multiplexer 292"_2, ..., 292"_4m-2. X can be an integer equal to or greater than 0, and can be less than m.

[0130] refer to Fig.17 and Fig.18 , a first minimum burst section tCCD_M1 in the first operation mode MODE1 for the burst mode is four times greater than a second minimum burst section tCCD_M2 in the second operation mode MODE2 for the burst mode.

[0131] Fig.19 Another example of a storage system is shown.

[0132] Can be used with Figure 5 The base die 200 is compared to describe Fig.19The base die 200c of FIG. 1 is a base die 200c of FIG. 1 , and for ease of description, the differences between them will be focused on. The configuration of the base die 200c not described will be replaced with the configuration of FIG. Figure 5 The description of the corresponding configuration of the base die 200 is replaced.

[0133] refer to Fig.19 , the first direct access bump dab of the base die 200 c includes a mode bump MoB for receiving the mode signal MODE_SEL and controls an operation mode in a burst mode of the memory device without intervention of a memory controller.

[0134] Fig. 20 Another example of a storage system is shown.

[0135] Can be used with Figure 1 and Figure 2 The storage system 1 is compared to describe Fig. 20 The storage system 1d of FIG. 1 is described below, and for ease of description, the differences between them will be focused on. The configuration of the storage system 1d not described will be described with reference to FIG. Figure 1 and Figure 2 The description of the corresponding configuration of the storage system 1 is replaced.

[0136] refer to Fig. 20 The memory system 1d is manufactured using a 3D package. The memory device 10d of the memory system 1d may be disposed on the upper side of the memory controller 20d without disposing an additional interposer with respect to the third direction Z.

[0137] That is, the first direct access bump dab, the first power bump pb1, the first command and address bump cab1, and the first data bump db1 may be disposed on the upper side of the memory controller 20d.

[0138] The first direct access bump dab and the second direct access bump DAFB may be connected to each other in the memory controller 20d. The first power bump pb1 and the third power bump PBFB may be connected to each other in the memory controller 20d.

[0139] The memory controller 20 d may receive a control signal and data through the second control signal bump CDFB, and may transmit a channel command, an address, and channel data to the first command and address bump cab1 and the first data bump db1 .

[0140] From the perspective of the number of data input / output bumps, a memory system according to some implementations can universally exchange data with an external device through a mode signal without any change in configuration.

[0141] A storage system according to some implementations may adjust the number of data input / output bumps that are actually operated from among the data input / output bumps to mitigate the size and pitch requirements of the configuration for the external device, and may reduce the cost of the process associated with the size and pitch of the configuration for the external device.

[0142] Fig.21 A perspective view showing a configuration of an example of a system device to which a storage system is applied.

[0143] refer to Fig.21 , the system apparatus 1000 is a semiconductor package, and may be a memory module including at least one memory device 1010 mounted on a package substrate 1040 such as a printed circuit board, and a system on chip (SOC) 1020 .

[0144] The interposer 1030 may be further selectively disposed on the package substrate 1040. The memory device 1010 may be formed in a chip-on-chip (CoC) type. The memory device 1010 may include a memory die 1100 having at least one core die stacked on a base die 1200. The memory die 1100 and the base die 1200 may be connected to each other through a through silicon via (TSV).

[0145] The base die 1200 may include an input / output gating circuit and a data input / output buffer for gating the input / output data of the memory die 1100, and the base die 1200 may control the operation of the input / output gating circuit and the data input / output buffer according to an externally input mode signal, thereby adjusting the number of data bumps for inputting / outputting data to / from the system on chip 1020. When the reference Figures 1 to 20 When implementing the described method, the input / output gating circuit and the data input / output buffer can perform memory operations.

[0146] The memory device 1010 may be, for example, a high bandwidth memory (HBM) equal to or greater than 500 GB / sec to 1 TB / sec.

[0147] Fig. 22 A perspective view showing another example of a system device to which the storage system is applied.

[0148] refer to Fig. 22 , the system device 2000 is a dual in-line memory module (DIMM) system in which semiconductor chips are mounted on respective sides of a printed circuit board, and it may include a memory module 2002 having at least one PCB 2030 and a memory controller 2020. The memory controller 2020 may be mounted on a main board 2040, and the PCB 2030 may be electrically connected to the main board 2040 through a connection socket.

[0149] The memory device 2010 may be formed in a chip-on-chip (CoC) type and may be mounted on a corresponding side of the PCB 2030. The memory controller 2020 and the memory device 2010 may be electrically connected to each other through buses in the PCB 2030 and the main board 2040. According to some implementations, the memory device 2010 may have a stacked structure of a memory die and a base die.

[0150] The base die may include an input / output gating circuit and a data input / output buffer, and the base die may control the operation of the input / output gating circuit and the data input / output buffer according to a mode signal input to the outside, and may adjust the number of data bumps for inputting / outputting data to / from the memory controller 2020. When the reference Figures 1 to 20 When the implementation described is performed, the input / output gating circuit and the data input / output buffer can perform memory operations. Figures 1 to 20 The described implementations are applied to perform memory operations.

[0151] The memory device 2010 may be, for example, a high bandwidth memory (HBM) equal to or greater than 500 GB / sec to 1 TB / sec.

[0152] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of what may be claimed, but rather as descriptions of features that may be specific to a particular implementation of a particular invention. Certain features described in this specification in the context of a separate implementation can also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation can also be implemented individually or in any suitable sub-combination in multiple implementations. Moreover, although features may be described above as working in certain combinations, and even initially claimed as such, one or more features from the claimed combination may be removed from the combination in some cases, and the claimed combination may be directed to a sub-combination or a variation of the sub-combination.

[0153] While the disclosure has been described in conjunction with what are presently considered to be practical implementations, it should be understood that the disclosure is not limited to the disclosed implementations and / or examples, but on the contrary is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A storage device, comprising: a first core die and a second core die, the first core die and the second core die being stacked in a first direction, the first core die comprising a first memory cell and the second core die comprising a second memory cell; as well as A base die is stacked together with the first core die and the second core die along the first direction, and the base die is configured to output data of the first storage unit and the second storage unit provided by the first core die and the second core die with different burst lengths based on a mode signal through a through-path, and the through-path passes through the first core die and the second core die in the first direction.

2. The memory device according to claim 1, wherein: The base die is further configured to: output the data in a first burst length in a first operation mode and in a second burst length in a second operation mode based on the mode signal, and A ratio of the first burst length to the second burst length is 1 to n, where n is an integer equal to or greater than 2.

3. The memory device according to claim 1, wherein: A first data bump and a second data bump configured to output the data are disposed on one side of the base die, The base die includes a first data register connected to the first data bump, a second data register connected to the second data bump, and a multiplexer disposed between the first data register and the second data register, and The multiplexer is configured to provide the first data obtained from the first data register to the first data bump in a first operation mode based on the mode signal.

4. The memory device according to claim 3, wherein: The multiplexer is further configured to provide the first data obtained from the first data register to the second data register in a second operation mode different from the first operation mode.

5. The memory device according to claim 3, wherein: At a first time in a second operation mode different from the first operation mode, the second data register is configured to output second data to the second data bump, and the first data register is configured not to output data to the first data bump.

6. The memory device according to claim 3, wherein: The base die includes bumps configured to receive the mode signal on a side of the base die, and The multiplexer is further configured to receive the mode signal through the bump.

7. The memory device according to claim 1, wherein: A first data bump, a second data bump, a third data bump, and a fourth data bump configured to output data are disposed on one side of the base die, and The base die includes a first data register connected to the first data bump, a second data register connected to the second data bump, a third data register connected to the third data bump, a fourth data register connected to the fourth data bump, a first multiplexer arranged between the first data register and the second data register, a second multiplexer arranged between the second data register and the third data register, and a third multiplexer arranged between the third data register and the fourth data register.

8. A storage device, comprising: a first core die and a second core die, the first core die and the second core die being stacked in a first direction, the first core die comprising a first memory cell and the second core die comprising a second memory cell; as well as A base die, the base die being stacked together with the first core die and the second core die along the first direction, the base die being configured to: output data of the first storage unit and the second storage unit provided by the first core die and the second core die through a through-path, the through-path passing through the first core die and the second core die in the first direction, the base die comprising a first data bump and a second data bump, a first data register, a second data register, and a multiplexer, the first data bump and the second data bump being connected to an external pad on one side and being configured to output the data, the first data register being connected to the first data bump, the second data register being connected to the second data bump, and the multiplexer being arranged between the first data register and the second data register.

9. The memory device according to claim 8, wherein: The base die is further configured to output the data in different burst lengths based on an external mode signal.

10. The memory device according to claim 9, wherein: One side of the base die includes a bump configured to receive the mode signal, and The multiplexer is configured to receive the mode signal through the bump.

11. The memory device according to claim 9, wherein: The base die is further configured to: output the data in a first burst length in a first operation mode and in a second burst length in a second operation mode based on the mode signal, and A ratio of the first burst length to the second burst length is 1 to n, where n is an integer equal to or greater than 2.

12. The memory device according to claim 11, wherein: The multiplexer is further configured to provide the first data obtained from the first data register to the second data register in the second operation mode.

13. The memory device according to claim 11, wherein: At a first time in the second operation mode, the second data bump is configured to output second data to the external pad, and the first data bump is configured not to output data to the external pad.

14. The memory device according to claim 8, wherein: The base die includes a data bump having the first data bump and the second data bump, The data bump is combined with an external pad including the external pad and is configured to: output the data of the first storage unit and the second storage unit, and The number of the external pads is smaller than the number of the data bumps.

15. The memory device according to claim 14, wherein: A ratio of the number of the external pads to the number of the data bumps is 1 to n, where n is an integer equal to or greater than 2.

16. A storage system, comprising: A memory device, the memory device comprising a first core die, a second core die and a base die stacked in a first direction, the first core die comprising a first memory cell, the second core die comprising a second memory cell, the base die being configured to: output data of the first memory cell and the second memory cell provided by the first core die and the second core die through a through-path, and the through-path passes through the first core die and the second core die to a first data bump in the first direction; as well as A memory controller is configured to exchange data with the memory device through second data bumps, wherein the number of the second data bumps is smaller than the number of the first data bumps.

17. The storage system according to claim 16, wherein: The base die is further configured to output the data in different burst lengths based on a mode signal provided by the memory controller.

18. The storage system according to claim 17, wherein: The base die is further configured to: output the data in a first burst length in a first operation mode and in a second burst length in a second operation mode based on the mode signal, and A ratio of the first burst length to the second burst length is 1 to n, where n is an integer equal to or greater than 2.

19. The storage system according to claim 16, wherein: The base die includes a first data register and a second data register, each of which is connected to one of the first data bumps, and a multiplexer, wherein the first data register and the second data register are each connected to one of the first data bumps, and the multiplexer is disposed between the first data register and the second data register.

20. The storage system according to claim 16, wherein: A ratio of the number of the second data bumps to the number of the first data bumps is 1 to n, where n is an integer equal to or greater than 2.

Images