Dynamic random access memory (DRAM) component for memory module

Abstract

Embodiments of the present disclosure relate to a dynamic random access memory (DRAM) component for a memory module. The memory module includes a module interface; a first stack of memory components including a first data interface coupled to the module interface; and a second data interface; a second stack of memory components including a third data interface coupled to the second data interface of the first stack, where the second data interface and the third data interface are connected using a point-to-point topology in a linear chain; and a fourth data interface; and a command and address (CA) interface coupled to the first stack and the second stack, where the CA interface is to receive a first command and a second command from a memory controller; controlling timing of a first access slot at the module interface for data related to the first command; and controlling timing of a second access slot at the module interface for data associated with the second command.

Description

[0001] Related Applications Citations

[0002] This application is a divisional application of the invention patent application with application number 202010905199.8, application date October 28, 2015, and invention name “Dynamic Random Access Memory (DRAM) Component for Memory Module”. Technical Field

[0003] Embodiments of the present disclosure relate to a dynamic random access memory (DRAM) component for a memory module Background Art

[0004] A computing memory system is typically composed of one or more dynamic random access memory (DRAM) integrated circuits (referred to herein as DRAM devices) connected to one or more processors. Multiple DRAM devices may be arranged on a memory module such as a dual in-line memory module (DIMM). A DIMM includes a series of DRAM devices mounted on a printed circuit board (PCB) and is typically designed for use in personal computers, workstations, servers, and the like. There are a variety of different types of memory modules, including: unbuffered DIMMs (UDIMMs), in which both the command / address and data buses are directly attached to the DRAM components; registered DIMMs (RDIMMs), in which the command / address bus is buffered, but the data bus is not buffered; and load-reduced DIMMs (LRDIMMs), in which cache chips exist for both the command / address bus and the data bus. In general, due to the poor electrical signal transmission properties of the memory channel, the higher the capacity and bandwidth requirements of the memory channel, the more buffering is required to achieve the desired performance.

[0005] Successive generations of DRAM parts have appeared on the market as photolithographic feature sizes have been scaled down smoothly. As a result, the storage capacity of the devices has increased with each generation. As transistor performance has improved, each generation has seen an increase in the signaling rate of the interface.

[0006] Unfortunately, one metric of memory system design that has not shown comparable improvement is the maximum number of modules that a single memory channel can support. As signaling rates increase, the maximum number of modules decreases.

[0007] The main reason for this reduction is the link topology used in standard memory systems. As more modules are added to the system, signal integrity degrades and high-speed signaling becomes increasingly difficult. Today's typical memory systems are limited to one or two modules when operating at maximum signaling rates.

[0008] Some future memory systems may be limited to a single rank of devices (or a single rank of devices stacked) on a single module at the highest signaling rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present disclosure is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings.

[0010] Figure 1 is a block diagram of a four-processor computing system with a memory system including multiple channels with 2 DIMMs per channel according to one embodiment.

[0011] Figure 2 A physical connection topology of signal transmission links in a conventional memory system according to one implementation is shown.

[0012] Figure 3A is a block diagram of an RDIMM memory system having two memory modules of 72×8 DRAM according to one embodiment.

[0013] Figure 3B is a block diagram of an RDIMM memory system having one memory module with 18×8 DRAM and continuity modules according to one embodiment.

[0014] Figures 4A-4C is a block diagram of RDIMMs with different numbers of DRAM stacks according to various embodiments.

[0015] Figure 5 is a block diagram of a memory system having multiple DRAM stacks arranged in a chain, wherein the DRAM components include two primary DQ interfaces, according to one embodiment.

[0016] Figure 6A-6B A read transaction directed to a memory system having two modules present is shown according to one embodiment.

[0017] Figure 7A-7B A read transaction directed to a system with a single DRAM module and continuity module presentation is shown according to one embodiment.

[0018] Figures 8A-8B A direct transfer between two DRAM stacks on the same module is shown according to one embodiment.

[0019] Figures 9A-9B A direct transfer between two DRAM stacks on different modules is shown according to one embodiment.

[0020] Fig.10The incremental read latency seen by the controller component for various module and channel configurations according to one embodiment is shown.

[0021] Fig.11 Additional details are shown for the receive to transmit path between the DQa interface and the DQb interface in the master DRAM component according to one embodiment.

[0022] Fig.12 The timing relationship with two sets of waveforms is shown according to one embodiment.

[0023] Figures 13A-13B A memory module with a DB buffer according to another embodiment is shown.

[0024] Figures 14A-14B A memory module with a DB buffer and a half-rate auxiliary DQ link according to another embodiment is shown.

[0025] Figures 15A-15B Two memory modules with clocked DQ links are shown according to another embodiment.

[0026] Figures 16A-16B A memory module with clocked DQ links according to another embodiment is shown.

[0027] Fig.17 is a timing diagram of a write operation of a DQ buffer according to one embodiment.

[0028] Fig.18 is a timing diagram of a write operation of a DQ buffer according to another embodiment.

[0029] Fig.19 According to one embodiment, Fig.17 and Fig.18 The timing examples can be combined together to automatically track drift between the DQS and CK domains over an arbitrarily large range.

[0030] Fig. 20 Another memory system with an alternative DQ topology is shown according to one embodiment.

[0031] Fig.21 A system configuration is shown in which a single DRAM module contains nine DRAM stacks according to another embodiment.

[0032] Fig. 22 is a block diagram of a memory module having multiple DRAM stacks arranged in a ring where each DRAM stack includes two data interfaces according to one embodiment.

[0033] Fig.23 According to one embodiment, Fig. 22Timing diagram of the read operation of the memory module.

[0034] Fig.24 is a block diagram of a memory module having a plurality of DRAM stacks arranged in at least two groups in a linear chain, wherein each DRAM stack includes two data interfaces, according to another embodiment.

[0035] Fig.25 According to another embodiment, Fig.24 Timing diagram of the read operation of the memory module.

[0036] Fig.26 is a block diagram of a memory module 2600 having a plurality of DRAM stacks arranged in at least two groups in a linear chain, wherein each DRAM stack includes two data interfaces, according to another embodiment.

[0037] Fig. 27 is a block diagram of a standard stack of memory components in which each memory component includes a single data interface according to one implementation.

[0038] Fig.28 is a block diagram of a stack of memory components in which each memory component includes two data interfaces according to one implementation.

[0039] Fig.29 is a block diagram of a stack of memory components where the stack includes two data interfaces and each memory component includes one data interface according to one embodiment.

[0040] Fig. 30A Block diagram of a stack of memory components wherein the stack includes two data interfaces and each memory component includes one data interface according to another embodiment.

[0041] Fig. 30B is a side view of a memory module having two stacks, each stack including two data interfaces and each memory component including one data interface according to one embodiment.

[0042] Fig.31 The diagram illustrates a pass-through path through a dual-port stack according to one embodiment.

[0043] Fig.32 Illustrated is a pass-through path through a stack having two data interfaces according to one implementation. DETAILED DESCRIPTION

[0044] Embodiments described herein describe technologies for dynamic random access memory (DRAM) components of high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). A DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode, and the first data interface is selectively coupled to the controller component in a second mode, and the second data interface is selectively coupled to a second DRAM component in a second mode. Other embodiments herein describe technologies for dual-port die with stacked dynamic random access memory (DRAM) components for high-performance, high-capacity RDIMMs. A memory module may include a module interface, a command and address (CA) interface connected to a shared bus, and at least two groups of stacked memory components. Each stack of memory components includes two data interfaces connected in a linear chain using a point-to-point topology. A first stack in the first group includes a first data interface coupled to a module interface and a second data interface coupled to a second stack in the second group. Other embodiments herein describe technologies for dual-port stacking of DRAM components of high-performance, high-capacity RDIMMs. An apparatus includes a packaging substrate including at least two packaging interfaces and a dual-port stack including a plurality of uniform memory components stacked on the packaging substrate. A first memory component of the dual-port stack includes a first external data interface connected to a first packaging interface of at least two packaging interfaces on the packaging substrate and a first internal data interface connected to all other memory components in the dual-port stack. A second memory component in the stack includes a second external data interface connected to a second packaging interface of at least two packaging interfaces on the packaging substrate and a second internal data interface connected to all other memory components in the dual-port stack.

[0045] As described above, as more modules are added to a memory system, signal integrity may degrade, reducing the signal rate. Therefore, in order to operate at the maximum signal rate, traditional memory systems are limited to one or two modules. The embodiments described herein are directed to memory systems with an increased number of memory modules and an increased number of memory blocks per module. Embodiments of the memory modules may be constructed using standard memory components with little or no modification. Embodiments of the memory components may be used in legacy memory systems with potential signal rate and capacity limitations as well as in memory systems with higher signal rate and capacity. The embodiments described herein may be compatible with standard error detection and correction (EDC) encodings, including standard (Hamming) ECC bit encodings, standard "chip kill" symbol encodings, or similar encodings in the art, such as technologies, SDDC, Extended ECC, Advanced ECC, and Chipspare or similar technologies that spread bits across multiple memory chips (ie, integrated circuit dies).

[0046] In one embodiment, the DRAM component may include a group of memory cells and boot logic coupled to the group of memory cells. The boot logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component (e.g., a memory controller of a processor) in a first mode. In a second mode, the first data interface is selectively coupled to the controller component and the second data interface is selectively coupled to the second DRAM component. The first mode may be when the DRAM component is in a DIMM and it is inserted into a logical memory system, and the second mode is when the DRAM component is in a DIMM and it is inserted into an improved memory system as described herein.

[0047] In another embodiment, a memory module includes a printed circuit board having first, second, and third data line sets and first and second pin sets, the first pin set coupled to the first data line set and the second pin set coupled to the second data line set. A first DRAM component may be located at a first location on the printed circuit board, and a second DRAM component may be located at a second location on the printed circuit board. The first DRAM component includes a first data interface coupled to the first data line set and a second data interface coupled to the third data line set. The second DRAM component includes a first data interface coupled to the third data line set and a second data interface coupled to the second data line.

[0048] In another embodiment, the DRAM component includes a set of memory cells, such as memory cells organized into one or more memory bank groups. The DRAM component also includes a guide logic that can be configured to guide data to the memory cells and guide data from the memory cells and guide data from other DRAM components. In one embodiment, the guide logic includes a first receiver coupled to a first data link set, a first transmitter coupled to the first data link set, a second receiver coupled to a second data link set, and a second transmitter coupled to the second data link set. The guide logic also includes a plurality of multiplexers to facilitate data paths between three data link sets of the DRAM component. In one example, the guide logic also includes a first multiplexer having an output coupled to the first transmitter, a second multiplexer having an output coupled to the second transmitter, a third multiplexer, a fourth multiplexer having an output coupled to an input of the first multiplexer and an input of the second multiplexer, a fifth multiplexer having an output coupled to the memory cell set, and a sixth multiplexer coupled to an output of the third data link set. The first receiver is coupled to an input of the second multiplexer and to an input of the third multiplexer. The second receiver is coupled to the input of the first multiplexer and to the input of the third multiplexer. The output of the third multiplexer is coupled to the input of the fifth multiplexer and to the input of the sixth multiplexer. The third data link set is coupled to the input of the fifth multiplexer and to the input of the fourth multiplexer. The memory cell set is coupled to the input of the fourth multiplexer and to the input of the sixth multiplexer.

[0049] In another embodiment, a memory module includes a printed circuit board (PCB) having a first set of data lines, a second set of data lines, and a third set of data lines and a first set of pins and a second set of pins, the first pin being coupled to the first set of data lines. The memory module includes a first DRAM component stack located at a first location on the PCB, a second DRAM component stack located at a second location on the PCB, a third DRAM component stack located at a third location on the PCB, and a fourth DRAM component stack located at a fourth location on the PCB. The first DRAM component stack includes a first data interface coupled to the first set of data lines and a second data interface coupled to the second set of data lines. The second DRAM component stack includes a first data interface coupled to the second set of data lines and a second data interface coupled to the third set of data lines. The third DRAM component stack includes a first data interface coupled to the third set of data lines and a second data interface coupled to the fourth set of data lines. The fourth stack of DRAM components includes a first data interface coupled to a fourth set of data lines.

[0050] As used herein, a DRAM stack includes one or more DRAM dies stacked in one or more packages stacked in a single location on a memory module. In a typical single die package (SDP) embodiment, the DRAM stack includes only one DRAM die and one package. Alternative embodiments may include a single package that accommodates a stack of multiple DRAM dies, such as a 3DS die stack with through silicon via (TSV) connections or a dual die package (DDP) with two DRAM dies in a single package.

[0051] In another embodiment, the memory package includes a package substrate, the package substrate includes at least two data interfaces and a stack of memory components stacked on the package substrate. The stacked memory components are isomorphic. Each of the memory components includes an external data interface connected to a subset of the stacked memory components and an internal data interface connected to all memory components of the stack. The external data interfaces of at least two memory components are coupled to at least two data interfaces on the package substrate. Data access can be performed on any memory component in the stack by using the topmost die or the bottommost die as the main data interface (also referred to as the external data interface). The stack can transfer data from the first main interface in the main interface to the second main interface in the main interface through the auxiliary interface. The auxiliary interface in this context may also be referred to as an internal interface. The internal interface as described herein may not be coupled to the package, and the main interface is used to couple to external components.

[0052] Figure 11 is a block diagram of a four-processor computing system 100 having a memory system including multiple channels, wherein each channel has 2 DIMMs, according to one embodiment. The computing system 100 includes four processor sockets, wherein each socket includes multiple memory channels. In the depicted embodiment, each channel includes two DIMMs 102. In this computing system, the DIMMs 102 can be RDIMMs that have buffers on the command / address channels (these command / address buffers are often referred to as "RCD" chips), but no buffers on the data bus (data bus buffer chips are often referred to as "DB buffers"), and are arranged in a "point-to-point" DQ topology (discussed in detail below) that can achieve signal rates up to 6.4Gb / s per DQ signal. This architecture allows a maximum module capacity of two sockets per channel (2SPC). The 2SPC can be populated with DIMMs of 1DIMM per channel (1DPC) or two DIMMs per channel (2DPC). The minimum DQ link granularity per DRAM chip (where each chip contains a 3D "stack" of two or more DRAM dies) can be four (i.e., each DRAM is "x4" wide; x4 DQ link granularity is also called a "nibble"). This granularity is a result of the timing used by the memory system. There is a timing link DQS that accompanies each group of four DQ links (e.g., a differential strobe with two interconnect lines). The timing link DQS can also be thought of as a data strobe link. It is not possible to divide the DQ nibble between two DRAM stacks; the four links (plus the timing strobe) must be connected to the same DRAM stack.

[0053] In one embodiment, DIMM 102 includes a printed circuit board having a first set of data lines, a second set of data lines, and a third set of data lines, and a first set of pins and a second set of pins, the first set of pins being coupled to the first set of data lines, and the second set of pins being coupled to the second set of data lines. A first DRAM component of DIMM 102 located at a first site on the printed circuit board includes a first data interface coupled to the first set of data lines and a second data interface coupled to the third set of data lines. A second DRAM component located at a second site on the printed circuit board includes a first data interface coupled to the third set of data lines and a second data interface coupled to the second set of data lines. The first data interface may be arranged into a first half byte, and the second data interface may be arranged into a second half byte, the first half byte and the second half byte each including a corresponding timing link, such as a data strobe link.

[0054] In another embodiment, the DIMM 102 includes a registered clock driver (RCD) component. The printed circuit board includes a first set of CA lines and a second set of CA lines and a fourth set of pins coupled to the first set of CA lines. The second set of CA lines is coupled between the RCD component and the first point and between the RCD component and the second point.

[0055] In one implementation, the first DRAM component is part of a first DRAM stack at a first location, and the second DRAM component is part of a second DRAM stack at a second location. The first DRAM stack may include a primary DRAM component and a plurality of secondary DRAM components. The second DRAM stack includes a primary DRAM component and a plurality of second DRAM components.

[0056] In another implementation, DIMM 102 includes a third DRAM stack located at a third site on the printed circuit board and a fourth DRAM stack located at a fourth site on the printed circuit board. The first DRAM stack, the second DRAM stack, the third DRAM stack, and the fourth DRAM stack can be connected in a chain between the first pin set and the second pin set. The third DRAM stack can include a third DRAM component having a first data interface coupled to a first subset of a third data line set and a second data interface coupled to a second subset of the third data line set. The fourth DRAM stack can include a fourth DRAM component having a first data interface coupled to a third subset of the third data line set and a second data interface coupled to a fourth subset of the third data line set. The implementation can also include an RCD component, a CA line, and pins as described above.

[0057] In one implementation, during a write operation, the first data interface is configured to receive data and the second data interface is configured to retransmit data. This can be used for multiple memory bank write operations. During a read operation, the second data interface is configured to receive data and the first data interface is configured to retransmit data. This can be used for multiple memory bank read operations.

[0058] In one implementation, the DRAM component includes a set of memory cells that form a first bank group and a second bank group. The first data interface can access at least one of the first bank group or the second bank group. In another implementation, the DRAM component includes a set of memory cells organized into a single group.

[0059] In one embodiment, the DRAM component of DIMM 102 includes a set of memory cells and a boot logic coupled to the set of memory cells. The boot logic includes a first data interface and a second data interface. The first data interface and the second data interface are selectively coupled to the controller component in a first mode. In a second mode, the first data interface is selectively coupled to the controller component and the second data interface is selectively coupled to the second DRAM component. In one embodiment, the first data interface is arranged into a first half byte and the second data interface is arranged into a second half byte, and the first half byte and the second half byte each include a corresponding timing link.

[0060] In another embodiment, the first DRAM component is part of a first DRAM stack and the second DRAM component is part of a second DRAM stack. In another embodiment, the boot logic includes a third data interface selectively coupled to the first data interface and the second data interface. The third data interface is coupled to a set of through silicon via (TSV) links in the first DRAM stack for write operations to or read operations from the auxiliary DRAM component of the first DRAM stack. In another embodiment, the first DRAM component is a main DRAM component of the first DRAM stack, and the second DRAM component is another main DRAM component of the second DRAM stack or at least one of the auxiliary DRAM components of the second DRAM stack. In another embodiment, the first DRAM component is an auxiliary DRAM component of the DRAM stack, and the second DRAM component is at least one of the main DRAM component of the DRAM stack or another auxiliary DRAM component.

[0061] DIMM 102 and the DRAM components of DIMM 102 are described in more detail below with respect to FIGS. 3-20 , following the following description of a standard memory system.

[0062] Link topology in a standard system

[0063] Figure 2 FIG. 2 shows the physical connection topology of the signal transmission link of the RDIMM 202 in the conventional memory system 200 according to one embodiment. The signal transmission link can be considered as a high-speed signal link. There are two types of links: CA (control address) link and DQ (data) link. These signals can be transmitted by such as Figure 1The controller component 204 of the memory controller on one of the processors of the RDIMM 202 transmits (and is received in the case of a DQ link). These signals are typically received by the buffer component of the RDIMM 202 (and transmitted in the case of a DQ link). The RDIMM 202 can use the buffer component 206 to receive the primary CA link from the controller component. The CA information received on the primary CA link can be retransmitted on the secondary CA link at a small delay (postponement) cost. In this implementation, the DQ link is not buffered, and the primary DQ link is connected to the DRAM component 208 from the controller component through the module slot.

[0064] In one implementation, the DRAM components 208 are assembled into a high-density 3D stack (using "through silicon via" ("TSV") connections for intra-stack die-to-die interconnection), as illustrated. The DQ link is coupled to the bottom-most DRAM component, and the master DRAM retransmits the DQ information onto the TSV link to the slave DRAM component (such as during a write operation). In the case of a read operation, the DQ information on the TSV link from the selected slave DRAM is received by the master DRAM and retransmitted to the controller component 204. In some implementations, the TSV link is implemented using through silicon via technology. This is also referred to as 3D die stacking. Typically, the TSV link can operate at a lower signaling rate than the main link, but has more links, so the bandwidth is matched.

[0065] exist Figure 2 , it is assumed that the primary DQ link operates at the highest possible signaling rate. This maximizes the data bandwidth available to the controller component 204 through the x72 DQ channels. The highest DQ signaling rate can only be achieved through a point-to-point interconnect topology. Without the advantages of some embodiments described herein, this would limit the memory channel to a single module with a single memory block (rank) of DRAM stacks on the module 202, where the DRAM capacity is "n*#of DRAM stacks", where "n" is the number of DRAM dies in the 3D stack.

[0066] As described herein, the minimum DQ link granularity for each DRAM stack can be four (x4) or half a byte. This granularity is a result of the timing used by the memory system. There is a timing link DQS (e.g., a differential strobe with two interconnect lines) that accompanies each set of four DQ links. In this implementation, it is not possible to divide a DQ half a byte between two DRAM stacks. That is, four links (plus the timing strobe) must be connected to the same DRAM stack.

[0067] The two constraints of point-to-point DQ topology and x4 DQ granularity allow a x72 DQ channel to connect to only 18 DRAM stacks at the maximum signaling rate. If more memory modules are added to the channel, or more memory banks are added to the module, the signaling rate may need to be reduced.

[0068] Some conventional memory systems may use buffer components in the path of the DQ link on the memory module. These are called LRDIMMs (Load Reduction-Dual In-line Memory Modules). These modules can support more DRAM stacked memory blocks on the module, but have higher manufacturing costs due to the additional buffer components on the memory module. The capacity-performance tradeoff of RDIMM limits memory system designers. Embodiments of high-performance, high-capacity registered memory modules described herein can solve or reduce this problem and can provide significantly higher storage capacity at the highest possible signal transfer rate.

[0069] Memory system with high performance, large capacity registered memory modules

[0070] Figure 3A is a block diagram of an RDIMM memory system 300 having two memory modules with 72×8 DRAM according to one embodiment. As described below, the physical connection topology of the RDIMM memory system 300 is different from the physical connection topology of the conventional memory system 200. The signal transmission links can be considered as high-speed signal links. There are two types of links: CA (control address) links and DQ (data) links. These signals can be transmitted by Figure 1 The controller component 304 of the memory controller on one of the processors of the DRAM module 308 transmits (and receives, in the case of DQ links). These signals are typically received (and transmitted, in the case of DQ links) by the buffer component of the RDIMM 302. The RDIMM 302 can use the buffer component 306 to receive the primary CA link from the controller component. The CA information received on the primary CA link can be retransmitted on the secondary CA link at a small delay (postponement) cost. In this implementation, the DQ link is not buffered, and the primary DQ link is connected from the controller component 304 to the DRAM component 308 through the module slot.

[0071] In one implementation, as shown, DRAM components 308 are assembled into a high-density TSV (through silicon via) stack as described. DQ links are coupled to the bottom-most DRAM components, and the master DRAM retransmits DQ information onto the TSV links to the auxiliary DRAM components (e.g., during write operations). In the case of a read operation, the DQ information on the TSV link from the selected auxiliary DRAM is received by the master DRAM and retransmitted to the controller component 304. In some implementations, the TSV links are implemented by through silicon via technology or 3D die stacking as described herein.

[0072] exist Figure 3A , it is assumed that the main DQ link operates at the highest possible signaling rate. This maximizes the data bandwidth available to the controller component 204 through the x72 DQ channels. Unlike the conventional memory system 200, which requires a single memory block of DRAM stacks in a single module to obtain the highest DQ signaling rate, the RDIMM memory system 300 includes a point-to-point interconnect topology in which four DRAM stacks are arranged in a chain. As described herein, the minimum DQ link granularity for each DRAM stack can be four (x4), also referred to as a half-byte with a timing link DQS (e.g., a differential selection with two interconnect lines) that accompanies each group of four DQ links.

[0073] The capacity of the RDIMM memory system 300 can be increased by a factor of 4 at the highest possible signaling rate through three modifications, including a first modification that adds a second DQ nibble interface to the DRAM component 308. The second DQ nibble interface connects to the four DQ links and the DQS timing link (a differential signal with two conductors). Details of one embodiment of this interface are described below with respect to Figure 5 In one embodiment, the first interface or the second interface of the DRAM component 308 can be connected to the controller component 304 and the first interface or the second interface can be connected to another DRAM component 308 in another DRAM stack at another device site on the printed circuit board. In addition, the first interface or the second interface can be used to access the DRAM core (e.g., a collection of memory cells of the DRAM component). The two interfaces can also be used to transfer data of another DRAM connected thereto.

[0074] exist Figure 3A In the embodiment, each set of four DRAM stacks are connected in a ring, wherein the first DRAM stack and the last DRAM stack are connected to the module slot.

[0075] By changing the second modification of the interconnect pattern of the primary DQ nibble groups, the capacity of the RDIMM memory system 300 can be increased by a factor of 4 at the highest possible signaling rate. Figure 3AThis is illustrated for one pair of nibbles, but another eight pairs of nibbles have exactly the same pattern.

[0076] Two nibble groups are designated as DQu 310 and DQv 312 at the controller component 304. The point-to-point interconnects for four DQ links and differential DQS links are connected to the module slots from the controller interface via the motherboard substrate. Two nibble groups are connected to different module slots. The third nibble group is designated as DQt 314, and the corresponding interconnects on the motherboard are connected between the two module slots. The motherboard circuit diagram can allow two modules 302, 316 to be accessed in parallel by the controller component 304. The access is performed by DQu and DQv nibble groups 310, 312. DQt nibble group 314 will not be used in this configuration example.

[0077] By changing the primary CA link to a third modification of the point-to-point topology, the capacity of the RDIMM memory system 300 can be increased by a factor of 4 at the highest possible signaling rate. This is possible because the memory system used by the normal multi-drop topology is forced to operate at a lower signaling rate. That is, a single multi-drop CA bus can be replaced by two point-to-point CA buses, each of which is half the width and operates at twice the signaling rate. These two point-to-point buses are Figure 3A In the drawings, they are designated as CAx 318 and CAy 320 .

[0078] Improved Module-System Example lxB

[0079] Figure 3B 366 and a continuity module 366. The RDIMM memory system 350 is a block diagram of an RDIMM memory system 350 having a memory module 352 having 18×8 DRAMs and a continuity module 366 according to one embodiment. In this embodiment, there is a single DRAM module 352 in the first slot. The second slot is occupied by the continuity module 366. For each nibble group pair, the continuity module 366 connects the DQt nibble group 314 to the DQu nibble group 310. The CAy link 320 is not connected in the continuity module 366, and the CAx link 318 is connected to the RCD component 356. The RDIMM 352 includes a 366-bit 10 ... Figure 3A This illustrates the use of the above description of the DRAM stack. Figure 3A The three modifications described above allow for a range of capacities. Due to the number of modules that can fill the channel slots, a capacity factor of 2x can be achieved in this embodiment. In another embodiment, another capacity factor of 4x can be achieved by changing the number of DRAM stacks on the module. A module with 9 DRAM stacks is shown in FIG. Figure 4C middle.

[0080] It should be noted that the primary DQ and primary CA links can utilize a point-to-point topology over the entire capacity range. This allows channel capacity to be adjusted independently of performance.

[0081] Module Overview

[0082] Figures 4A-4C is a block diagram of RDIMMs with different numbers of DRAM stacks according to various embodiments.

[0083] Figure 4A An RDIMM 400 is shown having thirty-six DRAM stacks. Figure 4B An RDIMM 410 is shown having eighteen DRAM stacks. Figure 4C An RDIMM 420 is shown with nine DRAM stacks. This configuration may provide additional flexibility in bundling of DRAM stacks on the module. In other implementations, the internal DRAM design may be modified so that a single module with nine DRAM stacks can provide full data bandwidth to the controller component. This modification may add some cost to the DRAM but may add additional 2x capacity range. Fig. 20 This modification is described in more detail.

[0084] DRAM Interface Details

[0085] Figure 5 is a block diagram of a memory system 500 having multiple DRAM stacks arranged in a chain, wherein the DRAM components include two primary DQ interfaces, according to one embodiment. The memory system 500 includes 36 device stacks, four of which are in Figure 5 . Each DRAM stack 508 includes a main DRAM component and seven auxiliary DRAM components. The main DRAM 502 of the first DRAM stack 508 in the ring is coupled to the first half-byte group DQu 310 via a first interface 510 (also referred to as the first DQ half-byte interface). The second interface 512 is coupled to the second DRAM component in another DRAM stack (the second DRAM stack in the ring in this implementation). The main DRAM 502 in the last DRAM stack 508 in the ring is coupled to the second half-byte group DQt 312 via the second interface 512 (also referred to as the second DQ half-byte interface) of the main DRAM component in the ring. In other embodiments, the ring or chain may include more or fewer sites of DRAM stacks, such as the two DRAM stacks described herein. It should be noted that in the module partial view, the two DRAM stacks are connected to the slot connection via one interface, and (in Figure 5), one of the DRAM stacks is connected to the slot connection via one interface and to the other DRAM stack via a second interface. For example, the first DRAM stack is connected to the memory controller component via the module slot and the second DRAM stack is connected to the third DRAM stack. The third DRAM stack is connected to the fourth DRAM stack, and the fourth DRAM stack is connected to the memory controller via the memory slot.

[0086] The first interface 510 and the second interface 512 of the main DRAM component support the above system example. The two DQ nibble interfaces 510, 512 are marked as DQa and DQb on the main DRAM component. Each interface is connected to four external DQ links and one DQS timing link (usually connected to a differential signal of two external wires).

[0087] In some implementations, the two interfaces on the master DRAM of the DRAM stack may be identical and may be programmed or otherwise configured with static control register fields or using some equivalent technique. This static configuration method may allow the same DRAM stack to be connected in an asymmetric manner. In other implementations, the DRAMS may be specifically manufactured as either a master component or a slave component.

[0088] like Figure 5 As shown in the exploded view at the bottom left, one of the DRAM stacks 508 includes a main DRAM 502 stacked with seven auxiliary DRAMs 504. In other implementations, other stacking configurations are possible. The main DRAM 502 and the auxiliary DRAMs 504 are connected to a set of TSV buses 514. These TSV buses 514 are generally wider and slower than the main bus. They are physically implemented by TSV (Through Silicon Via) technology or some equivalent method. These TSV buses include links for data (TSV DQ) and command addresses (TSV CA) (not shown separately).

[0089] In this implementation, the auxiliary DRAM 504 typically has a pair of primary DQ nibble interfaces and a primary CA interface, all of which are disabled by a control register field. The primary DRAM 502 has a pair of primary DQ nibble interfaces 510, 512 and a primary CA interface 516, all of which are enabled by a control register field. These primary interfaces 510, 512, 516 are connected to the TSV interface 522. The connection details of these interfaces are described in Figure 5 is shown in an exploded view on the right.

[0090] DRAM components (in Figure 5The main components (illustrated in the exploded view on the right side of FIG) include a collection of memory cells, such as one or more memory banks 518 and steering logic 520. In one embodiment, the steering logic provides paths and connections between the main interfaces 510, 512, and 516. The DQa and DQb interfaces 510, 512 each include a receiver 521 and a transmitter 522 for four DQ links. Additional details of these interfaces are described herein.

[0091] The receiver 521 of each interface may be connected to the transmitter 522 of the other interface to allow data to pass through the master DRAM 502. A pass-through operation is required when the selected DRAM stack is not directly connected to the interface of the master socket.

[0092] In another embodiment, the DRAM component 502 includes a set of memory cells, such as memory cells organized into one or more memory bank groups. The DRAM component 502 also includes a guide logic that can be configured to guide data to the memory cells and guide data from the memory cells and other DRAM components. In one embodiment, the guide logic includes a first receiver 521 coupled to a first data link set, a first transmitter 522 coupled to the first data link set, a second receiver 521 coupled to a second data link set, and a second transmitter 522 coupled to the second data link set. The guide logic also includes a plurality of multiplexers 523 (not individually labeled) to facilitate data paths between three data link sets from the DRAM component. In one example, the guide logic also includes: a first multiplexer having an output coupled to the first transmitter, a second multiplexer having an output coupled to the second transmitter, a third multiplexer, a fourth multiplexer having an output coupled to an input of the first multiplexer and an input of the second multiplexer, a fifth multiplexer having an output coupled to the memory cell set, and a sixth multiplexer having an output coupled to the third data link set. The first receiver is coupled to the input of the second multiplexer and to the input of the third multiplexer. The second receiver is coupled to the input of the first multiplexer and to the input of the third multiplexer. The output of the third multiplexer is coupled to the input of the fifth multiplexer and to the input of the sixth multiplexer. The third data link set is coupled to the input of the fifth multiplexer and to the input of the fourth multiplexer. The memory cell set is coupled to the input of the fourth multiplexer and to the input of the sixth multiplexer.

[0093] Data from the receiver 521 of either interface may also be directed to a DRAM repository 518 for write operations. The repository 518 may belong to the primary DRAM or one of the secondary DRAMs. For example, if the write data enters a repository on the secondary DRAM, the primary data is retransmitted on the TSV DQ link 514. The primary CA command address information about the CA link 516 is also retransmitted on the TSV CA link 514. However, if the write data enters a repository on the primary DRAM, the primary data is written directly to the primary repository. In some implementations, the primary repository may be written with a configurable delay so that the repository behavior of the primary DRAM matches that of the secondary DRAM. In some implementations, when a write operation is directed to the primary DRAM, the primary CA command address information is typically not retransmitted on the secondary CA link.

[0094] The storage repository 518 can also be accessed by a read operation, as well as the read data transmitted by either interface of the main DRAM 502. The storage repository 518 can belong to the main DRAM 502, or it can belong to one of the auxiliary DRAMs. For example, if the read data comes from a storage repository on the auxiliary DRAM, the main CA command address information about the CA link 516 is retransmitted on the TSV CA link 514 in the case of a write operation. The TSV read data (from the TSV link 514) is retransmitted on the main DQ link (510 or 512). If the read data comes from a storage repository on the main DRAM, the data is read directly from the main storage repository. This can also be implemented with configurable delays, so the storage repository behavior of the main DRAM matches the storage repository behavior of the auxiliary DRAM. In some implementations, when the read operation is directed to the main DRAM, the main CA command address information is typically not retransmitted on the auxiliary CA link.

[0095] In another embodiment, the steering logic further comprises: a first receiver coupled to a first set of ports coupled to a first set of data lines arranged in a first nibble; a first transmitter coupled to the first set of ports; a second receiver coupled to a second set of ports to couple to a second set of data lines arranged in a second nibble; a second transmitter coupled to the second set of ports; a first multiplexer having an output coupled to the first transmitter; a second multiplexer having an output coupled to the second transmitter; a third multiplexer; a fourth multiplexer having an output coupled to an input of the first multiplexer and an input of the second multiplexer; a fifth multiplexer having an output coupled to a set of memory cells; and a sixth multiplexer having an output coupled to a set of TSV links. The first receiver is coupled to an input of the second multiplexer and to an input of the third multiplexer. The second receiver is coupled to an input of the first multiplexer and to an input of the third multiplexer. The output of the third multiplexer is coupled to an input of the fifth multiplexer and to an input of the sixth multiplexer. The set of TSV links is coupled to the input of the fifth multiplexer and to the input of the fourth multiplexer.The set of memory cells is coupled to the input of the fourth multiplexer and to the input of the sixth multiplexer.

[0096] Transaction Details - Two Modules

[0097] Figure 6A-6B A read transaction is shown for a memory system having two modules according to one embodiment. Fig. 6A The figure shows the reference Figure 6B A portion of the timing diagram shows a module and controller component for a read transaction. The portion of the module shows the interconnection of one of the nine pairs of DQ byte groups and the interconnection of the two main CA buses CAx and CAy. The two modules are labeled "module x" and "module y" to match the connections of the main CA buses. The timing diagram shows the waveforms of the various CA and DQ buses.

[0098] In this implementation, the timing diagram indicates the nominal signaling rates of the various buses, assuming a master DQ signaling rate of 6.4 Gb / s. As the master DQ rate changes, the relative signaling rates of the buses may increase or decrease proportionally.

[0099] In the depicted embodiment, each of the two read transactions includes an activate command (labeled "A" or "ACT"), a read command (labeled "R" or "RD"), and read data (labeled "36bx16"). The commands and data for each transaction may be pipelined. This means that they occupy fixed timing positions relative to the transaction. This also means that transactions may overlap with other transactions.

[0100] It should be noted that in this embodiment, the timing intervals used are shorter than those presented in conventional memory systems. For example, the ACT to RD command interval (tRCD) is shown as 6.25ns, but may be approximately 12.5ns for an actual DRAM component. This compression of the timing scale is done for clarity and may not affect technical accuracy, as pipeline timing can be used equally well for a tRCD delay of 6.25ns.

[0101] exist Figure 6B The three other timing intervals shown in BUF-CA Interval, t RL Interval and t BUF-DQ .t BUF-CA The interval (0.93ns) is the propagation delay required by the RCD buffer component to retransmit the information on the primary CA link to the secondary CA link. It should be noted that 0.93ns and 3.125ns are derived from multiple cycles of the 3.125Ghz clock. RL The interval (3.125ns) is the column read delay between the RD command and the read data provided by the DRAM. BUF-DQ The (0.93ns) interval is the propagation delay required to retransmit the information on the DQxab link to the main DQu link through the DRAM on the module x component. This is because the DRAM accessed on module x has no direct connection to the controller.

[0102] It should be noted that accesses on module y can have a configurable delay (t BUF-DQ ), so that the read data is returned to the controller on the DQu and DQv main links at approximately the same time. This incremental delay may make it easier for the controller component to manage the memory pipeline.

[0103] It should be noted that the timing diagram for a write transaction may be similar, but with different fixed timing positions of commands and data.

[0104] In this implementation, the transaction granularity shown is 64 bytes; that is, there are enough command slots to allow each master DQu and DQv slot to be filled with data. Each transaction performs random row activation and column access for each 64 bytes (e.g., "36bx16" because the data bus is 36b wide and switches 16 times per read / write command). It should be noted that other transaction granularities are possible.

[0105] It should also be noted that each byte is assumed to be 9b in size. This extra size may account for the complications of EDC (Error Detection and Correction) codes.

[0106] In some implementations, if there is a bank conflict in the transaction stream, and the transaction stream switches between read and write operations, it is necessary to skip a data slot. This form of bandwidth inefficiency may exist in all memory systems. It should be noted that in some embodiments, the modifications made to the RDIMM memory system with a DRAM component having two interfaces as described herein do not introduce additional resource conflicts.

[0107] refer to Figure 6B From the timing diagram, it can be seen that the "x" and "y" transactions begin with an activate command "A" on the CAx and CAy buses. These buses have a point-to-point topology and a signaling rate of 1.6GB / s (one quarter the signaling rate of the point-to-point DQ bus).

[0108] In one embodiment, the RCD buffer components on each module can receive the main CA bus and retransmit the information on the CAxb and CAya module buses. The CA module bus operates at 0.8 Gb / s, half the speed of the main CA bus and 1 / 8 the speed of the main DQ bus. This is possible because the module CA bus has a multi-drop topology; each of the four module CA buses connects to approximately 1 / 4 of the DRAM stacks on the module.

[0109] refer to Figure 6B The timing diagram shows that the "x" and "y" transactions continue with the read command "R" on the CAx and CAy buses. This is retransmitted on the CAxb and CAya module buses. In this example, two read transactions have accessed two of the four DRAM stacks in the set of four DRAM stacks connected to the DQu and DQv nibble groups. The two transactions each access one of the eight DRAMs in the selected stack.

[0110] In the case of accessing the main DRAM, some additional delay may be added to the access time so that the data being read is transmitted on the main DQ in the same opposite slot. Figure 5 The details of the incremental delay described are not given in Figure 6A-6B This incremental delay may make it easier for the controller component to manage the memory pipeline.

[0111] Back to Fig. 6A , it can be seen that the "x" transaction accesses the lower DRAM stack. This means that the read data may be driven onto the DQxab main link to the upper DRAM stack, and then returned to the controller on the DQu main link.

[0112] exist Figure 6BAs can be seen in the timing diagram, incremental delay is added to the "y" transaction so that the read data DQu and DQv arrive at the controller at approximately the same time. In this example, the retransmission delay from DQxab to the DQ bus is approximately three clock cycles (e.g., approximately one nanosecond). This example provides a serialization delay of one cycle (e.g., two data bits per clock cycle) plus two additional clock cycles of clock skew between the two DRAM stacks (±1 clock cycle).

[0113] It should be noted that Figure 6B In the example, the other DRAM stacks in the set of four DRAM stacks can be accessed with high-order address bits set differently in the CAx and CAy commands. Figure 6B In , the DQt master bus is not used; the interface circuitry on the DRAM stack connected to this bus can be disabled by a control register field.

[0114] Transaction Details - One Module

[0115] Figure 7A-7B A read transaction for a system with a single DRAM module and a continuity module is shown according to one embodiment. In this example, one RDIMM module is placed in one slot and a continuity module is placed in another slot. Fig. 7A The block diagram shows a portion of the controller components with interconnections of one pair of nine DQ nibble groups and two main CA buses CAx and CAy. The continuity module is labeled "module x" and the DRAM modules are labeled "module y" matching the connections of the main CA buses. The continuity module connects the DQu bus to the DQt bus; each of the four DQ links and the DQS link are connected with a controlled impedance line that matches (approximately) the impedance of the main board lines. The CAx bus is not connected to anything on the continuity module.

[0116] Figure 7B The timing diagram shows the waveforms of various CA and DQ buses. The timing diagram also indicates the nominal signaling rates of the various buses, assuming a master DQ signaling rate of 6.4 Gb / s. As the master DQ rate changes, the relative signaling rates of the buses may increase or decrease proportionally.

[0117] In this example, each of the two read transactions includes an activate command (labeled "A" or "ACT"), a read command (labeled "R" or "RD"), and read data (labeled "36bx16"). The commands and data for each transaction may be pipelined. This means that they may occupy a fixed point in time with respect to the transaction, and transactions may overlap with other transactions.

[0118] It should be noted that the fixed timing positions may be slightly offset from those in other configurations (e.g. Figure 6B This may not cause scheduling issues in the controller because these configurations are static. The configuration can be detected at system initialization and after the appropriate control register fields are set, the configuration may not be changed.

[0119] The timing intervals used are shorter than those present in conventional memory systems. For example, the ACT to RD command interval (tRCD) is shown as 6.25ns, but may be approximately 12.5ns for an actual DRAM component. This compression of the timing scale is done for clarity and does not affect the technical accuracy, and pipeline timing can work equally well with a tRCD delay of 6.25ns.

[0120] Figure 7B Other timing intervals are shown in BUF-CA Interval, t RL Interval. t BUF-CA The interval (0.93ns) is the propagation delay required by the RCD buffer component to retransmit the information on the primary CA link to the secondary CA link. RL The interval (3.125ns) is the column read delay between the RD command and the read data required by the DRAM. Figure 6B t BUF-DQ The gap does not occur in this example because all DRAM stacks have a direct primary connection to the controller. In other one module configurations, if a DRAM stack needs to pass its data through another DRAM stack on the module, a propagation delay may occur.

[0121] It should be noted that the diagram for a write transaction may be similar, but with different fixed timing positions of commands and data.

[0122] In this example, the transaction granularity shown is 64 bytes; that is, there are enough command slots to allow each master DQu and DQv slot to be filled with data. Each transaction performs random row activation and column access for each 64 bytes ("36bx16"). Other transaction granularities are possible.

[0123] It should be noted that each byte is assumed to be 9b in size. This additional size takes into account the syndrome of EDC (error detection and correction) codes. In some implementations, if there is a repository conflict in the transaction stream, and the transaction stream switches between read and write operations, it is necessary to skip the data slot. This form of bandwidth inefficiency may exist in all memory systems. It should be noted that, as described herein, no additional resource conflicts are introduced by the modifications that have been made to the RDIMM memory system.

[0124] refer to Figure 7B , it can be seen that the "x" and "y" transactions begin with an activate command "A" on the CAy bus. The CAx bus is not used in this configuration. These buses have a point-to-point topology and a signaling rate of 1.6GB / s (one quarter the signaling rate of the point-to-point DQ bus).

[0125] The RCD buffer components on the y module receive the main CAy bus and retransmit the information on the CAyb and CAya module buses. The CA module bus operates at 0.8Gb / s, half the speed of the main CA bus and 1 / 8 the main DQ speed. This is possible because the module CA bus has a multi-drop topology; each of the four module CA buses connects to approximately 1 / 4 of the DRAM stacks on the module.

[0126] refer to Figure 7B , it can be seen that the "ya" and "yb" transactions continue the read command "R" on the CAy bus. This is retransmitted on the CAyb and CAya module buses. The two read transactions have accessed the two DRAM stacks connected to the DQu and DQv nibble groups. The two transactions have each accessed one of the eight DRAMs in each selected stack.

[0127] In the case of accessing the main DRAM, some additional delay may be added to the access time so that the data being read is emitted on the main DQ in the same relative time slot (details not shown in Figure 7). This incremental delay may make it easier for the controller component to manage the memory pipeline.

[0128] refer to Fig. 7A , it can be seen that the "yb" transaction accesses the lower DRAM stack. This means that the read data can be driven through the continuity module onto the DQt main link and then returned to the controller on the DQu main link. The incremental propagation time of the "yb" read data through the continuity module may be small enough to be absorbed in the clock skew management circuitry, so the read data on DQu and DQv will arrive at the controller at approximately the same time.

[0129] Direct delivery options within modules

[0130] Figures 8A-8B A direct transfer between two DRAM stacks on the same module is shown according to one embodiment. Fig. 8A shows how the interface logic can accommodate direct transfer between two DRAM stacks on the same module. Fig. 7A Similar to the example of , both slots are populated with DRAM modules.

[0131] This pass-through option is possible because the DRAM interface already requires the necessary interface logic to support the maximum capacity modules and systems (this is the logic shown in Figure 6).

[0132] Fig. 8A The figure shows a portion of a controller component having a module and interconnection of one of the nine pairs of DQ nibbles and interconnection of two main CA buses CAx and CAy. The two modules are labeled "module x" and "module y" to match the connections of the main CA buses. Figure 8B The timing diagram shows the waveforms of various CA and DQ buses. The timing diagram also indicates the nominal signaling rates of the various buses, assuming a master DQ signaling rate of 6.4 Gb / s. As the master DQ rate changes, the relative signaling rates of the buses may increase or decrease proportionally.

[0133] In this example, a transfer operation may involve a read transaction in one DRAM stack and a write transaction in a second DRAM stack (within the same module). This may be performed simultaneously on each module so that four transactions occur. Fig. 6A and 7A twice as much as in the read transaction example.

[0134] In one implementation, each of the two read transactions includes an activate command (labeled "A" or "ACT"), a read command (labeled "R" or "RD"), and read data (labeled "36bx16"). Each of the two write transactions includes an activate command (labeled "A" or "ACT"), a write command (labeled "W" or "WR"), and write data (labeled "36bx16").

[0135] In this case, the write data used is generated by the read transaction. The timing of the write transaction (tWL) is configured to approximately match the timing of the read transaction (tWL) relative to the interval from the column command to the column date. RL ), data is passed on a shared DQ bus between the DRAM stacks (DQyab and DQxab in this case).

[0136] It should be noted that the timing is described as matching "approximately". This language recognizes that each DRAM component can accommodate a small amount of variation in the timing of its interface. This may be because the locations where data is received and transmitted may drift within a small range during system operation.

[0137] In one embodiment, the interface is designed to accommodate such dynamic drift, with the result that any drift (within an allowed range) may not affect the operation of the memory system.

[0138] In one implementation, the controller may need to consider the use of the memory bank when the command-to-data interval of a write operation matches a read operation, when a pass-through transaction or write transaction to a DRAM stack is followed by a read transaction to the same DRAM stack. This resource management is a key function performed by some memory controllers. In some implementations, the commands and data of each transaction can be pipelined. This means that they occupy a fixed timing position relative to the transaction, and also means that the transaction overlaps with other transactions.

[0139] In the depicted embodiment, the timing intervals used may be shorter than those present in a typical system. For example, the ACT to RD command interval (tRCD) is shown as 6.25ns, but may be approximately 12.5ns for an actual DRAM component. The compression of the time scale is done for clarity and does not affect technical accuracy; pipeline timing may work equally well with a tRCD delay of 6.25ns. Figure 7B Two additional timing intervals are shown.

[0140] exist Figure 8B The other two time intervals shown in BUF-CA Interval, t RL Interval. t BUF-CA The interval (0.93ns) is the propagation delay required for the RCD buffer component to retransmit the information on the primary CA link to the secondary CA link. RL The interval (3.125ns) is the column read delay between the RD command and the read data required by the DRAM. In this example, t BUF-DQ The gap does not occur because each DRAM read stack has a direct connection to the DRAM write stack destination. In other configurations, if the DRAM read stack needs to pass its data through another DRAM stack on the module to the DRAM write stack destination, this propagation delay may occur.

[0141] In this implementation, the transaction granularity shown is 64 bytes; that is, there are enough command slots to allow each master DQu and DQv slot to be filled with data. Each transaction performs random row activations and column accesses for each 64 bytes ("36bx16"). Other transaction granularities are possible. It should also be noted that each byte is assumed to be 9b in size. This extra size can account for the syndrome of the EDC (Error Detection and Correction) code.

[0142] Back to Figure 8B From the timing diagram, it can be seen that the "x" and "y" transactions begin with an activate command "A" on the CAx and CAy buses. These buses have a point-to-point topology and a signaling rate of 1.6GB / s (one quarter the signaling rate of the point-to-point DQ bus).

[0143] In one embodiment, the RCD buffer components on each module can receive the main CA bus and retransmit information on the CAxa, CAxb, Cya, and CAyb module buses. It should be noted that all four CA module buses can be used to transfer transactions.

[0144] In one embodiment, the CA module bus operates at 0.8 Gb / s, half the speed of the main CA bus and 1 / 8 the speed of the main DQ bus. This is possible because the module CA bus has a multi-drop topology; each of the four module CA buses connects to approximately 1 / 4 of the DRAM stacks on the module.

[0145] Return to Figure 8B In the timing diagram, it can be seen that the "x" and "y" transactions continue with two read commands "R" and two write commands "W" on the CAx and CAy buses. This is retransmitted as two read commands "RD" and two write commands "WR" on the CAxa, CAxb, Cya, and CAyb buses. In this example, the two read transactions have accessed two of the four DRAM stacks, and the two write transactions have accessed the other two DRAM stacks.

[0146] Fig. 8A One of the nine DRAM stack sets in the module is shown. Each of the four transactions has accessed one of the eight DRAMs in each selected stack.

[0147] In the case of accessing the primary DRAM, some additional delay may be added to the access time so that the data being read is emitted on the primary DQ in the same relative slot (note that this detail is not described in detail in the example above). Fig. 8A , but previously in Figure 5 This incremental delay makes it easier for the controller to manage the memory pipeline.

[0148] Return to Fig. 8A , it can be seen that the "x" read transaction accesses the upper DRAM stack. The read data can be driven onto the DQxab main link to the lower DRAM stack to be written to the selected DRAM. In the depicted embodiment, it can be seen that the "y" read transaction accesses the upper DRAM stack. The read data can be driven onto the DQyab main link to the lower DRAM stack to be written to the selected DRAM.

[0149] It should be noted that Fig. 8A In the embodiment of the present invention, different DRAM stacks in a DRAM stack set may be accessed with high-order address bits set differently in CAx and CAy commands.

[0150] Also note that in Fig. 8AIn the present invention, the DQu, DQv, and DQt main buses may not be used; the interface circuits on the DRAM stack connected to this bus may be disabled by a control register field during a transfer operation in one implementation.

[0151] Direct transfer option between modules

[0152] Figures 9A-9B A direct transfer between two DRAM stacks on different modules is shown according to one embodiment. Fig. 9A shows how the interface logic can accommodate direct transfer between two DRAM stacks on different modules. Fig. 7A Likewise, two of the slots are populated with DRAM modules.

[0153] Fig. 9A The figure shows a portion of a controller component with interconnection of one of the nine pairs of DQ byte groups and interconnection of two main CA buses CAx and CAy. The two modules are labeled "module x" and "module y", matching the connections of the main CA buses.

[0154] Fig. 9B The timing diagram shows waveforms for various CA and DQ buses. The timing diagram also indicates the nominal signaling rates for the various buses, assuming a master DQ signaling rate of 6.4 Gb / s. As the master DQ rate changes, the relative signaling rates of the buses may increase or decrease proportionally.

[0155] In this example, the transfer operation involves a read transaction in one DRAM stack and a write transaction in a second DRAM stack (within a different module). This can be performed simultaneously with two additional read transactions, so that four transactions occur, which is Fig. 6A and 7A twice as much as in the read transaction example.

[0156] In one implementation, each of the three read transactions includes an activate command (labeled "A" or "ACT"), a read command (labeled "R" or "RD"), and read data (labeled "36bx16"). A single write transaction may include an activate command (labeled "A" or "ACT"), a write command (labeled "W" or "WR"), and write data (labeled "36bx16").

[0157] In this case, the write data used is generated by one of the read transactions. The timing of the write transaction is configured to approximately match the read transaction relative to the interval from the column command to the column date. The data is passed on a shared DQ bus between the two modules (DQt).

[0158] In one implementation, the controller may need to consider the use of the memory bank when the command-to-data interval of a write operation matches a read operation, when a pass-through transaction or write transaction to a DRAM stack is followed by a read transaction to the same DSRM stack. This resource management is a key function performed by some memory controllers. In some implementations, the commands and data for each transaction can be pipelined. This means that they occupy a fixed timing position relative to the transaction, and also means that transactions overlap with other transactions.

[0159] In the depicted embodiment, the timing intervals used may be shorter than those found in conventional systems. For example, the ACT to RD command interval (tRCD) is shown as 6.25ns, but may be approximately 12.5ns for an actual DRAM component. The compression of the time scale is done for clarity and does not affect technical accuracy; pipeline timing can work equally well with a tRCD delay of 6.25ns. Fig. 9B Two other timing intervals are shown in .

[0160] Fig. 9B Two other time intervals are shown, namely t BUF-CA Interval, t RL Interval. t BUF-CA The interval (0.93ns) is the propagation delay required by the RCD buffer component to retransmit the information on the primary CA link to the secondary CA link. RL The interval (3.125ns) is the column read delay between the RD command and the read data required by the DRAM. BUF-DQ The gap does not appear in this example because each DRAM stack has a direct connection to its destination (e.g., to a controller or DRAM write stack). In other configurations, this propagation delay may occur if the DRAM read stack needs to pass its data through another DRAM stack on the module to the DRAM write stack destination.

[0161] In this implementation, the transaction granularity shown is 64 bytes; that is, there are enough command slots to allow each master DQu and DQv slot to be filled with data. Each transaction performs random row activation and column access for each 64 bytes ("36bx16"). Other transaction granularities are possible. It should also be noted that each byte is assumed to be 9b in size. This additional size can take into account the syndrome of EDC (Error Detection and Correction) codes.

[0162] Back to Fig. 9B , it can be seen that the "x" and "y" transactions begin with an activate command "A" on the CAx and CAy buses. These buses have a point-to-point topology and a signaling rate of 1.6GB / s (one quarter the signaling rate of the point-to-point DQ bus).

[0163] The RCD buffer unit on each module receives the main CA bus and retransmits the information on the CAxa, CAxb, Cya and CAyb module buses. It should be noted that all four CA module buses can be used to transfer transactions.

[0164] In one embodiment, the CA module bus operates at 0.8 Gb / s, half the speed of the main CA bus and 1 / 8 the speed of the main DQ bus. This is because the module CA bus has a multi-drop topology; each of the four module CA buses connects to approximately 1 / 4 of the DRAM stacks on the module.

[0165] Back to Fig. 9B , it can be seen that the "x" and "y" transactions continue with three read commands "R" and one write command "W" on the CAx and CAy buses. This is retransmitted as three read commands "RD" and one write command "WR" on the CAxa, CAxb, CAya, and CAyb buses. In this example, three read transactions have accessed three of the four DRAM stacks, and a write transaction has accessed another DRAM stack.

[0166] Fig. 9B One of the nine DRAM stack sets on the module is shown. Each of the four transactions has accessed one of the eight DRAMs in each selected stack.

[0167] In the case of accessing the primary DRAM, some additional delay can be added to the access time so that the data being read is emitted on the primary DQ in the same relative time slot (note that this detail is not shown in FIG. 8 , but is previously described in Figure 5 This incremental delay makes it easier for the controller to manage the memory pipeline.

[0168] Back to Fig. 9B , it can be seen that the "x" read transaction accesses the upper DRAM stack. The read data may be driven onto the DQu main link to the controller. In the depicted embodiment, it can be seen that the "y" read transaction accesses the upper DRAM stack. The read data may be driven onto the DQv main link to the controller component. The second "y" read transaction accesses the lower DRAM stack. The read data may be driven onto the DQt main link to the lower DRAM stack of module "x" to be written to the selected DRAM.

[0169] It should be noted that Fig. 9A In the embodiment of the present invention, different DRAM stacks in a DRAM stack group can be accessed with high-order address bits set differently in CAx and CAy commands.

[0170] In addition, note that Fig. 9AIn , the DQxab and DQyab master buses may not be used; the interface circuits on the DRAM stacks connected to the bus may be disabled by command decoding logic in each stack's master DRAM.

[0171] Incremental Delay Table

[0172] Fig.10 The incremental read latency seen by the controller components for various module and channel configurations according to one embodiment is shown. In this embodiment, the table uses a delay unit that makes some assumptions about DRAM-to-DRAM communication. The previous examples assumed that this delay unit is approximately three clock cycles (about one nanosecond). The delay from the DQ interface of one DRAM stack to the DQ interface of a different DRAM stack consists of two components: [1] one cycle of serialization delay (two data bits per clock cycle) plus [2] two additional clock cycles of clock skew between the two DRAM stacks (+1 clock cycle). Using a 3.2GHz clock, these three clock cycles are slightly less than one nanosecond. The delay table is organized according to: [1] the number of slots per channel (one SPC or two SPCs), [2] the number of DIMMs per channel (one DPC or two DPCs), and [3] the number of DRAM stacks per module (e.g., thirty-six, eighteen, or nine). Each stack can accommodate (typically) four or eight DRAMs.

[0173] The Incremental Latency column indicates the additional read latency seen by the worst case DRAM stack compared to the minimum capacity example.

[0174] The table shows that only a pair of the largest capacity modules (with 36 devices stacked) can see the maximum incremental delay (+3 units, or about 3ns). The three other configurations may see smaller incremental delays (+1 unit or about 1ns). The remaining configurations see no incremental delays. These incremental delays are relatively small compared to the ~30ns read delay for row / column access and the ~50ns for the memory bank cycle time. Alternatively, in other embodiments, other delays for various configurations can be implemented.

[0175] DQ-DQS phase pattern and domain crossing details for DRAM interface

[0176] Fig.11 Additional details of the receive to transmit path between the DQa and DQb interfaces in the main DRAM component are shown in accordance with one embodiment. The reverse path from DQb to DQa may be similar. The first order details are shown earlier in Figure 5 Most DRAMs operate in a clock domain created from the CLK link that accompanies the CA bus. This domain is shown in blue in Figure 9 and is labeled BTRANSMIT.

[0177] There is a small portion of the interface on the left that operates in the domain of the received DQS timing signal of the DQA interface. It is labeled ARECEIVE. Fig.11 The block 1110 at the bottom contains the control logic required to perform the domain crossover function between the ARECEIVE and BTRANSMIT domains. This block 1110 operates in the BTRANSMIT domain. The domain crossover logic is described in detail below. Multiplexers 1112 and 1114 can be used to enable the modified memory system described above. These blocks can be multiplexer circuits with selector inputs driven according to the control register field (the selector signals are marked as "MODER" and "MODET"). The selector signal can be used to adjust the phase relationship between DQ and DQS for receiving and transmitting blocks.

[0178] Fig.11 The domain crossing logic is also shown. The domain crossing logic can set the control register fields to specific values ​​to illustrate how the interface is initially configured and maintained. The accompanying timing diagram shows the waveforms of the six internal nodes, as well as the data in and data out signals.

[0179] In the depicted embodiment, each master data link DQIN (ARECEIVE domain) is sampled by the master timing link DQSIN on both the rising and falling edges (because MODER=0, a zero degree delay is inserted into the DQS path). This may result in two sampled values, Y and Z, being held at the outputs of the DQYO and DQZO registers in the DQS domain. It should be noted that the DQS-EN signal is formed in the CK domain (as shown in the delay adjustment logic 1110) and the DQSIN signal is gated. In some cases, this may be extended if the data transfer is longer. This example assumes that the DQS and CK signals are aligned so that the SKP[1] value sampled by DQS from CK+90° is low. The DLY0.5 control value is set by the SKP[1] in the previous WR transfer, so the control value is also lower.

[0180] Fig.12A timing relationship with two sets of waveforms 1210, 1220 is shown according to one embodiment. The top set of waveforms 1210 shows the DQIN and DQSIN timing relationship of the ARECEIVE domain. When MODER is 1, DQSIN is edge-aligned; DQSIN and DQIN produce approximately aligned transitions (in phase). When MODER is zero, DQSIN is center-aligned; DQSIN and DQIN produce unaligned (out-of-phase) transitions. The alignment is approximately 90°, which means that the DQSIN transition is approximately in the middle between the DQIN transitions. In some cases, the modified DRAM interface may need to receive data in either phase-aligned manner. For example, center alignment can be used to write data, and edge alignment can be used to read data. For certain system configurations, the configurability of this mode of the DRAM interface can allow the DRAM to pass read or written data from one interface to another.

[0181] The bottom set of waveforms 1220 shows the DQOUT and DQSOUT timing relationship for the ATRANSMIT domain. When MODER is zero, DQSOUT is edge aligned; DQSOUT and DQOUT produce approximately aligned transitions (in phase). When MODER is 1, DQSOUT is center aligned; DQSOUT and DQOUT produce misaligned (out of phase) transitions. The alignment is approximately 90°, which means that the DQSOUT transitions are approximately halfway between the DQOUT transitions.

[0182] In some cases, the modified DRAM interface may need to receive data in either phase alignment. For example, center alignment may be used for write data, and edge alignment may be used for read data. For certain system configurations, the configurability of this mode of the DRAM interface may allow the DRAM to pass read or written data from one interface to another.

[0183] DRAM modules with DB buffer

[0184] Figures 13A-13B A memory module with a DB buffer according to another embodiment is shown. The system includes two DRAM modules connected to a controller component. Each of the 9 pairs of primary DQ nibble groups (DQu and DQv) is connected to the two modules, with a third primary DQt nibble group connecting the modules. This interconnect pattern on the motherboard allows the system to be configured with two DRAM modules (as shown in FIG6 ) or one DRAM module and a continuity module (as shown in FIG7 ).

[0185] Fig.13AThe memory module of FIG. 6 differs from the memory module of FIG. 6 in the way the components are connected on the module. Each pair of primary DQ nibble groups is connected to a DB buffer component. There are nine DB buffer components on each module. These DB buffer components operate in parallel.

[0186] In other embodiments, other functionally equivalent embodiments may merge two or more DB buffers together. For example, each module may have three DB components, each DB component connected to three pairs of main DB nibble groups.

[0187] In this implementation, each DB buffer has four nibble groups of auxiliary links, each with four DQ data links and a differential DQS timing link. These auxiliary links run at the same data rate as the primary link (6.4Gb / s, as shown in Figure 6). Each auxiliary nibble group is connected to a DRAM stack similar to that shown in the previous system configuration (see e.g. Figure 5 )’s DRAM stack.

[0188] Alternatively, each secondary nibble group may be connected to a single DRAM component, similar to the primary DRAM shown in the DRAM stack in the previous system configuration (see, e.g., Figure 5 ). In this case, there may be no auxiliary DRAM and no TSV connections.

[0189] A third alternative could be Fig.13A A pair of stacked DRAM packages is placed in each DRAM site in the 100M-100M-2. Four sets of DRAM package pairs will be connected to each DB buffer part.

[0190] In the first two cases, the secondary DQ link may have a simple point-to-point topology, allowing a signaling rate that matches that of the primary DQ link.

[0191] In a third alternative, the auxiliary DQ link may have a point-to-two-point topology, which will have a slightly reduced signaling rate relative to the other two alternatives.

[0192] It should be noted that the second and third options are that the module can accommodate 72 DRAM components without relying on TSV stacking technology (e.g., 36 device sites per module with two DRAMs stacked at each device site). Package stacking technology is more mature than TSV technology, and this option can provide cost advantages for certain module capacities.

[0193] In this embodiment, the DRAM stack (or a single DRAM) may only require a single nibble group interface compared to Figure 6. In contrast, the DB buffer component will have two nibble group interfaces.

[0194] These interfaces can be similar to Figure 5The DQa and DBb interfaces shown in the main DRAM in FIG. 2. The control register fields can be used at initialization to set the configuration mode (ie, number of modules present, number of DRAM stacks present, etc.).

[0195] Fig. 13B The timing diagram is similar to Figure 6B The timing diagram of the master CA and master DQ links is shown in Figure 1. The waveforms of the master CA and master DQ links and the 3.2 GHz master clock signal are shown. The master CA link has Fig. 6A 1 / 4 of the signaling rate of the DQ link shown (6.4 Gb / s). Other embodiments may have other signaling rates.

[0196] Fig.13A The configuration of the DRAM component in the module can avoid the cost of the second interface, but the additional DB component may increase the cost of the module.

[0197] DRAM Module w / DB (Half Rate Assist)

[0198] Figures 14A-14B A memory module with a DB buffer and a half-rate auxiliary DQ link according to another embodiment is shown. The system includes two DRAM modules connected to a controller component. Each of the 9 pairs of primary DQ nibbles (DQu and DQv) is connected to two modules, with the third primary DQt nibble connecting the modules. This interconnect pattern on the motherboard allows the system to be configured with two DRAM modules (such as Fig. 6A ) or a DRAM module and a continuity module (such as Fig. 7A shown).

[0199] Fig.14A The way the components on the module are connected is different from Fig. 6A .exist Fig.14A In the , each pair of primary DQ nibbles is connected to a DB buffer part. There are nine DB buffer parts on each module. These DB buffer parts operate in parallel.

[0200] In other embodiments, other functionally equivalent embodiments may merge more than two DB buffers together. For example, each module may have three DB components, each DB component connected to three pairs of main DB nibble groups.

[0201] In this implementation, each DB buffer has four nibble groups of auxiliary links, each with four DQ data links and a differential DQS timing link. These auxiliary links run at 1 / 2 the data rate of the primary link; the primary link runs at 6.4 Gb / s and the auxiliary links run at 3.2 Gb / s. Each auxiliary nibble group is connected to a DRAM stack similar to that shown in the previous system configuration (see e.g. Figure 5 ).

[0202] Alternatively, each secondary nibble group may be connected to a single DRAM component, similar to the primary DRAM shown in the DRAM stack in the previous system configuration (see, e.g., Figure 5 ). In this case, there may be no auxiliary DRAM and no TSV connections.

[0203] A third option could be to connect each secondary nibble group to a pair of package-stacked DRAM parts. The secondary link topology for this option is point-to-point, but this will not be a problem because the secondary data links intentionally run at half the rate of the primary data links.

[0204] The second and third options may allow a module to hold 72 DRAM components without relying on TSV stacking technology (e.g., thirty-six device sites per module with two DRAMs stacked at each device site). Package stacking technology is more mature than TSV technology, and this option may provide cost advantages for certain module capacities.

[0205] In some embodiments, the DRAM interface of these three options may only need to run at half the speed of the main link, with only the controller and DB components running at the highest signaling rate (6.4Gb / s in this example). One consequence of this may be that the DRAM pairs must be accessed so that their 3.2Gb / s data rates can be aggregated to a 6.4Gb / s data rate. This is Fig.14A The two shadow DRAM pairs being accessed are indicated in each transaction.

[0206] like Fig.13A As shown, Fig.14A The system in can be configured so that each DRAM stack (or single DRAM) has only a single nibble group interface. In contrast, the DB buffer component will have two main nibble group interfaces.

[0207] These interfaces can be similar to Figure 5 The DQa and DBb interfaces shown in the main DRAM in FIG. 2. The control register fields can be used to set the configuration mode (ie, number of modules present, number of DRAM stacks present, etc.) at initialization.

[0208] Fig. 14B The timing diagram is similar to Fig. 6A The timing diagram of the master CA and master DQ links is shown in Figure 1. The waveforms of the master CA and master DQ links and the 3.2 GHz master clock signal are shown. The master CA link has Fig. 6A 1 / 4 of the signaling rate of the DQ link shown (6.4 Gb / s). Other embodiments may have other signaling rates.

[0209] In this implementation, for each transaction, each DRAM in the active DRAM pair can each provide data 4bx8 to the DB component at 3.2Gb / s. Each DB component will provide data 4bx16 at 6.4Gb / s on the main link. Nine DB components will provide data 36bx16 at 6.4Gb / s on the main link.

[0210] like Fig.13A As shown, Fig.14A One possible advantage of the configuration is that the DRAM components can avoid the cost of a second interface, but the additional DB components may increase the cost of the module. It should be noted that the memory modules can utilize slower DRAMs (half rate interface speeds), resulting in potential cost savings. In addition, these slower DRAMs may use a shallower x8 prefetch that is compatible with legacy components. Furthermore, in some cases, one of the options may utilize package stacked DRAMs (multi-drop auxiliary link topology running at half rate interface speeds), which also results in potential cost savings.

[0211] Two DRAM modules with clocked DQ links

[0212] Figures 15A-15B Two memory modules with timing DQ links according to another embodiment are shown. The system includes two DRAM modules connected to a controller component. The main DQ links have been grouped into thirty-six pairs of single DQ data links. In addition, the controller interface and the DRAM interface have been modified so that the timing signals required to transmit and receive data do not communicate with the link accompanying the data (the DQS link used in Figure 6). Instead, the clock link CLK included in the CA group is used as the frequency and phase source for DQ and CA. The timing events for transmitting and receiving data are synthesized from the CLK link using a phase interpolation circuit. The phase interpolation required for each DRAM can be generated by a process at initialization and maintained by a periodic calibration process.

[0213] This change to the timing system can provide a benefit: the minimum number of links connected to a single DRAM is no longer limited by the size of the data link group that shares the DQS timing signal. This means that instead of each DRAM containing two nibble groups (x4) of DQ interfaces (as shown in Figure 6), each DRAM can contain two data link groups, each of which is a link (x1). The result can be seen in Fig.15A 72 data links are connected to the controller component, each data link is connected to one master DRAM (of the DRAM stack). There is room for thirty-six DRAM stacks on each of the two modules, which means that there is no need to couple any of the DRAM stacks on the modules together (e.g., in FIG. 4 ).

[0214] exist Fig.15AIn , each DRAM has two xl DQ interfaces (similar to Figure 4, but one bit wide instead of four bits wide). Fig.14A In a two module configuration, one DQ interface of each DRAM of one module is connected to a motherboard trace to one DQ bit of each DRAM of the other module. This path is not used in a two module configuration.

[0215] Fig. 15B The timing diagram of FIG6 is similar to the timing diagram of FIG6. The waveforms of the master CA and master DQ links are shown with a 3.2 GHz master clock signal. The master CA link has a signaling rate (6.4 Gb / s) of 1 / 4 of the DQ link shown in FIG6. Other embodiments may have other signaling rates.

[0216] Fig.15A One possible advantage of the configuration is that the DRAM component can avoid the latency cost of passing data through the DRAM in high capacity configurations. The DRAM can also avoid the cost of a second x4 DQ interface (but an interface with configurable widths - {x1, x2, x4} can be implemented to support the same configuration listed in Figure 8). When using this alternative embodiment, it may be necessary to modify the interface timing of the DRAM and controller components.

[0217] A DRAM module with clocked DQ links

[0218] FIG. 16A to FIG. 16B A memory module with a timed DQ link according to another embodiment is shown. The system includes a DRAM module connected to a controller component. The main DQ links have been grouped into thirty-six pairs of individual DQ data links. In addition, the controller interface and DRAM interface have been modified so that the timing signals required to transmit and receive data are not communicated with the link that accompanies the data (the DQS link used in FIG. 7 ). It should be noted that the timing method can be similar to Fig. 15B The timing used in

[0219] The clock link CLK included in the CA group is used as the frequency and phase source for DQ and CA. The timing events for transmitting and receiving data are synthesized from the CLK link using a phase interpolation circuit. The phase interpolation value required for each DRAM can be generated by a process at initialization and maintained by a periodic calibration process.

[0220] This change to the clock system can produce the following benefits: The minimum number of links connected to a single DRAM is no longer limited by the size of the data link group that shares the DQS timing signal. This means that instead of each DRAM containing two nibble groups (x4) of DQ interfaces (as shown in Figure 6), each DRAM can contain two data link groups, each of which is a link (x1). The result can be seen in Fig.16A72 data links connect to the controller component, and each pair of data links connects to one master DRAM (of a DRAM stack). There is room for thirty-six DRAM stacks on a single module, which means that there is no need to couple any of the DRAM stacks in a module together (e.g., Figure 5 middle).

[0221] In this embodiment, Fig.16A The second slot contains a continuity module instead of a DRAM module, such as Fig.15A In the case of Fig.16A In a module configuration, two DQ interfaces of each DRAM of a module are connected to the controller component, with half of the connections flowing through the continuity module. The topology is shown in Figure 7, but each DRAM has two x1 interfaces instead of two x4 interfaces.

[0222] Fig. 16B The timing diagram of FIG7 is similar to the timing diagram of FIG7. The waveforms of the master CA and master DQ links are shown with a 3.2 GHz master clock signal. The master CA link has a signaling rate (6.4 Gb / s) of 1 / 4 of the DQ link shown in FIG7. Other embodiments may have other signaling rates.

[0223] Fig.16A One possible advantage of the configuration is that the DRAM components can avoid the latency cost of passing data through the DRAM in high capacity configurations. The DRAM can also avoid the cost of a second x4 DQ interface, but can be implemented with an interface with configurable widths - {x1, x2, x4} to support the same configuration listed in Figure 8. The interface timing of the DRAM may have to be modified in this alternative embodiment.

[0224] The accompanying timing diagram shows the waveforms of the six internal nodes as well as the data-in and data-out signals.

[0225] WR timing details DQ_BUF_SKP[1] = 0

[0226] Fig.17 is a timing diagram for a write operation of a DQ buffer according to one embodiment. Fig.17The diagram illustrates what happens when a new SKP[1] sample value does not match the previous sample value due to drift between the DQS and CK domains. A low value on the DLY0.5 control causes the DQY0 and DQZ0 values ​​to pass through the multiplexer in the phase adjustment block. Assume a value of 00 on the DLY123[1:0] control, which also causes the DQY0 and DQZ0 values ​​to pass through the multiplexer in the cycle adjustment block. The DQY0 and DQZ0 values ​​can be sampled through the DQY2 and DQZ2 registers, and may have crossed into the CK domain (BTRANSMIT domain) at this time. The DQY2 and DQZ2 registers drive the output multiplexer, which in turn drives the output drivers of the auxiliary link group.

[0227] The DQS output can be created from the delay adjustment logic. The DQS can be driven with the CK+90° signal because the MODET=1 value causes a 90 degree delay to be inserted into the DQS value. If the value of the DLY123[1:0] control is assumed to be 11, the DQYO and DQZO values ​​may be delayed by three pipeline cycles. The data and timing signals may appear on the auxiliary link 3*tCK later than in the previous case. This allows the delay through the DQS to CK domain crossing to be adjusted in one cycle increments.

[0228] WR timing details DQ_BUF_SK[1]=1

[0229] Fig.18 is a timing diagram for a write operation of a DQ buffer according to another embodiment. Fig.18 Similar to Fig.17 , except that it assumes that the DQS and CK signals are aligned so that the SKP[1] value sampled by DQS from CK+90° is high.

[0230] Fig.18 The waveforms of the six internal nodes are shown in Figure 1, along with the primary data input and secondary data output signals. Each primary data link DQIN is sampled by the primary timing link DQSIN at both the rising and falling edges, resulting in two sampled values ​​Y and Z being held at the DQY0 and DQZ0 register outputs in the DQS domain.

[0231] It should be noted that the DQS-EN signal is formed in the CK domain and gates the DQSIN signal. If the data transfer is longer, this delay may be extended.

[0232] This example assumes that the DQS and CK signals are aligned so that the SKP[1] value sampled by DQS from CK+90° is high. The DLY0.5 control value is set by the SKP[1] value in the previous WR transfer, so the control value is also high.

[0233] Fig.18The diagram illustrates what happens when a new SKP[1] sample value does not match the previous sample value due to drift between the DQS and CK domains. A high value on the DLY0.5 control causes the DQY0 and DQZ0 values ​​to be sampled by the DQY1 and DQZ1 registers and pass through the multiplexer in the phase adjustment block. Assume a value of 00 on the DLY123[1:0] control, which causes the DQY1 and DQZ1 values ​​to also pass through the multiplexer in the cycle adjustment block. The DQY1 and DQZ1 values ​​may be sampled by the DQY2 and DQZ2 registers and may have crossed into the CK domain at this time. The DQY2 and DQZ2 registers drive the output multiplexer, which in turn drives the output drivers of the auxiliary link group.

[0234] The DQS output can be created from the delay adjustment logic. The CK+90° signal can be used to drive the DQS output because the MODET=1 value causes a 90 degree delay to be inserted into the DQS value. If the value of the DLY123[1:0] control is assumed to be 11, the DQY0 and DQZ0 values ​​may be delayed by three cycles of the pipeline. Data and timing signals may appear on the auxiliary link 3*tCK later than in the previous case. This allows the delay through the DQS to CK domain crossing to be adjusted in increments of one cycle.

[0235] Automatic tracking of timing drift

[0236] Fig.19 According to an embodiment Fig.17 and Fig.18 The timing examples can be combined together to automatically track the drift between the DQS and CK domains over an arbitrarily large range.

[0237] Fig.19 Assuming the domain crossing logic has been initialized, the delay from the column write command on the CA bus and the write data for that command is a constant 3.00*tCK. It should be noted that for descriptive purposes, the values ​​illustrated may be smaller than what would be seen in an actual system in order to fit within the timing diagram.

[0238] In timing diagram 1910, the write strobe arrives 1.125*tCK after the write command. The sampled SKP[1:0] value is "01". The new DLY0.5 phase value is set from SKP[1] and the new DLY123[1:0] period value is "01" (the same value set at the previous initialization).

[0239] In timing diagram 1920, the DQS timing is shifted relative to the CK domain, so the write strobe arrives 1.375*tCK after the write command. The sampled SKP[1:0] value is "11". The new DLY0.5 phase value is set from SKP[1]. Because SKP[1] and the old DLY0.5 phase value are different, and because SKP[0] is high, the new DLY123[1:0] may need to be increased or decreased (relative to the old DLY123[1:0] value) to keep the command-to-data delay constant at 3.00tCK; in this example it is decreased.

[0240] In summary, the DQS timing signal for each transfer can sample CK and CK+90° (in the case of a write) and retain this information in the SKP[1:0] register. In the idle interval before the next transfer, the DLY0.5 and DLY123[1:0] values ​​(stored in the control register in the CK domain) can be updated to reflect the SKP[1:0] in the previous transfer. These new DLY0.5 and DLY123[1:0] values ​​are used on the next transfer.

[0241] In one implementation, this sequence can occur automatically on each pass and can allow the cross-domain logic to accommodate an arbitrarily large range of DQS to CK drifts during system operation. After the initialization process sets the control registers to the appropriate values, no further maintenance operations are required to support this automatic tracking.

[0242] Replace DQ topology

[0243] Fig. 20 Another memory system with an alternative DQ topology according to one embodiment is shown. The DQ topology can be considered a point-to-two-point DQ topology. The system includes four DRAM modules connected to a controller component. Each of the 9 pairs of primary DQ nibble groups (DQu and DQv) is connected to four modules. The third primary DQt0 nibble group connects the x0 and y0 modules. The fourth primary DQt1 nibble group connects the x1 and yl modules. This interconnection pattern on the motherboard may allow the system to be configured with two pairs of DRAM modules or a single pair of DRAM modules (e.g., x0 / y0 pairs).

[0244] In other embodiments, the interconnection mode can also support one and three module configurations using continuity modules. In this embodiment, the primary DQ and primary CA links have a point-to-two-point topology instead of the point-to-point topology shown and described above with respect to FIG.

[0245] This configuration may result in lower signaling rates on the primary DQ and primary CA links, but may provide a higher capacity for the memory system, such as twice that of those modules described above.

[0246] Can be Fig. 20 DRAM interface modifications as described herein are used in DRAMs of the present invention. In these embodiments, DRAM to DRAM transfer scenarios can be supported so that module capacities can have the same range as described in the previous memory system.

[0247] In some implementations, another link may be used to perform memory bank selection. A primary CA link may be received by a pair of modules. An address link or a chip select link may be used to direct access to one of the two modules sharing a CA link.

[0248] DRAM Interface Details - Dual Bank Group

[0249] Fig.21 A system configuration is shown in which a single DRAM module contains nine DRAM stacks according to another embodiment. This configuration represents the minimum possible configuration when using 72 DQ link channels and a DRAM stack with two x4 DQ nibble interfaces.

[0250] One option for this configuration could be to increase the column access granularity to 128B. Each of the nine DRAM stacks would provide a burst of 8b×16 column blocks. This is twice the width of the 4bx16 column blocks used in the Figure 6 system.

[0251] It should be noted that in this configuration, modifications to the interface logic may be minimal, as the width of the column access paths may only need to be increased.

[0252] A second option for this configuration may be to keep the column access granularity fixed to 4b×16 and increase the concurrency of the DRAM interface and the core.

[0253] In some implementations, the DRAM memory banks are divided into two independently accessible groups (A and B). Each of the two memory bank groups can execute independent transaction flows, performing independent row accesses and column accesses.

[0254] It may be necessary to double the CA interface of the DRAM to enable this second concurrent access ( Fig. 20 This is accomplished by linking CAxa and CAxb in this minimal module configuration (similar to Figure 5 This is achieved by connecting the ) shown in FIG. 1 to each DRAM stack.

[0255] There may be enough bandwidth on the primary CA link to support the second access because other configurations (such as in Figure 6) are executing two independent transaction streams and directing them to the CAxa and CAxb module links.

[0256] Fig. 20The modified DRAM may also need to be able to direct the two master interfaces (DQv and DQt) to the two memory bank groups. A second TSV DQ link is also required to allow data to be directed to the memory bank group on the auxiliary DRAM.

[0257] In an alternative core configuration, each DRAM in the stack may have only a single bank group. In this alternative embodiment, the controller component can direct two transaction streams to two different DRAMs (but not the same DRAM) in the stack.

[0258] This can simplify the DRAM core and save cost. The steering logic can be included in the interface as well as the second TSV DQ link. The controller component can check the request queue to ensure that the same DRAM is not used in every transaction pair.

[0259] In an architecture of a DRAM stack with two data interfaces, the return bus can be optimized to minimize the variation in data return delay. This optimization can be referred to as leveling or deskewing the data return delay. If the data return delay is not deskewed (or leveled), then the memory module topology as described in detail below can be managed as a pipeline with multiple stages. This is possible because the stack is arranged in a daisy chain topology rather than a multi-point bus. The embodiments described herein can give lower average data delay, improved bandwidth, reduced address bus contention, or any combination thereof. Due to the lower intermediate bus connection, as described herein, the embodiments described herein can result in a DQ / DQS bus that is easier to time. In some implementations, delayed reads (D) can be used to alleviate address bus contention.

[0260] In one implementation, the memory module has at least two groups of stacked memory components, each stack having two data interfaces connected to a point-to-point topology in a linear chain. The CA interface of the memory module is connected to a shared bus. The first stack of the first group is connected to a module interface (e.g., connected to a pin of the memory module). The stack of memory modules is configured so that the access slots at the module interfaces of the first group and the second group are offset in time. The stack of memory components can have a variable delay to create a pipeline for accessing the slots at the module interface. In one implementation, the offset between the access slots is managed by a memory controller, such as a pipeline for accessing the slots. In another implementation, the read delay of each stack is the same.

[0261] In other implementations, a memory controller coupled to the memory module can send commands to the memory module, and the memory module can change the delay based on the type of command. For example, the RCD component can receive commands, and the RCD component can control the delay of stacks in different groups to create a pipeline to access the slots. In one implementation, the CA links of each group can be independent, but shared within the group. For example, a first CA link is coupled between the RCD component and the first group of stacked memory components, and a second CA link is coupled between the RCD component and the second group of stacked memory components. The first CA link can be shared between multiple stacks in the first group, and the second CA link can be shared between multiple stacks in the second group.

[0262] In one implementation, the memory module may receive a read command or a delayed read command from the memory controller. The memory component stack may be programmed with a first delay in response to the read command and a second delay in response to the read delay command, wherein the first delay is less than the second delay, as described herein.

[0263] Fig. 22 2200 is a block diagram of a memory module having multiple DRAM stacks arranged in a ring, wherein each DRAM component includes two data interfaces, according to one embodiment. The memory module 2200 includes four stacks of memory components: a first stack 2212, a second stack 2214, a third stack 2216, and a fourth stack 2218. The first data interface of the first stack 2212 is coupled to the module interface 2210 via a first DQ link (DQ0). The module interface 2210 (DQu) is arranged as a first nibble and includes a corresponding timing link. The first data interface of the third stack 2216 is coupled to the second data interface of the first stack 2212 via a second DQ link (DQ1). The first data interface of the second stack 2214 is coupled to the second data interface of the third stack 2216 via a third DQ link (DQ2). The first data interface of the fourth stack 2218 is coupled to the second data interface of the second stack 2214 via a fourth DQ link (DQ3).

[0264] In one implementation, the memory module 2200 also includes an RCD component 2202 coupled to the module interface via a primary CA link 2204 (CAx). A first secondary CA link 2206 is coupled between the RCD component 2202 and a first stack 2212. The first secondary CA link 2206 is shared with a second stack 2214. A second secondary CA link 2208 is coupled between the RCD component 2202 and a fourth stack 2218. The second secondary CA link 2208 is shared with a third stack 2216. It should be noted that the memory module 2200 may include additional stacks arranged in the same topology as these four stacks.

[0265] The following describes how the RCD component 2202 and the four stacks 2212-2218 handle read operations.

[0266] Fig.23 According to one embodiment, Fig. 22 23. The RCD component 2202 receives a first read command (R) 2302. The RCD component 2202 sends the first read command on the first auxiliary CA link 2206, which causes a first access 2304 at the first stack 2212. The RCD component 2202 receives a second read command (R) 2306. The RCD component 2202 sends a second read command on the second auxiliary CA link 2208, which causes a second access 2308 at the third stack 2216. The RCD component 2202 receives a third read command (R) 2310. The RCD component 2202 sends a third read command on the first auxiliary CA link 2206, which causes a third access 2312 at the second stack 2214. The RCD component 2202 receives a fourth read command (R) 2314. The RCD component 2202 sends a fourth read command on the second auxiliary CA link 2208, which causes a fourth access 2316 at the fourth stack 2218.

[0267] like Fig.23 As shown, the RCD component 2202 must wait for a delay between when the first read command 2302 and the third read command 2310 are signaled on the first auxiliary CA link 2206. Similarly, the RCD component 2202 must wait for a delay between when the second read command 2306 and the fourth read command 2314 are signaled on the second auxiliary CA link 228. This delay is labeled t CC There is a read delay (t RL ). The time to access data on the corresponding data interface is called an access slot. The access time of an access slot is equal to t CC There may also be a delay between the two Auxiliary CA links when they signal the read command. The delay between two consecutive read commands is denoted as t CC -t B The stacks are accessed at different times so that the intermediate stacks can route data through the ring, resulting in a first access slot 2320 at the module interface 2210, followed by a second access slot 2322, followed by a third access slot 2324, followed by a fourth access slot 2326.

[0268] like Fig.23As shown, there are various access time slots where slots are free. This topology may also present some possible timing issues. To compensate for potential timing issues, this topology uses speed matching buffers. These speed matching buffers may be difficult to implement. As mentioned above, speed matching buffers may be used to prevent bus contention, such as buffer delay t B Reflected, so that the data can be sequentially available at the module interface (DQu), such as Fig.23 shown.

[0269] Fig.24 2400 is a block diagram of a memory module 2400 having multiple DRAM stacks arranged in at least two groups in a linear chain according to another embodiment, wherein each DRAM stack includes two data interfaces. The memory module 2400 includes stacks of four memory components arranged in a first group 2411 and a second group 2413. The first group 2411 includes a first stack 2412 and a third stack 2415. The second group 2413 includes a second stack 2414 and a fourth stack 2418. The first data interface of the first stack 2412 is coupled to the module interface 2410 via a first DQ link (DQ0). The module interface 2410 (DQu) is arranged into a first nibble and includes a corresponding timing link. The first data interface of the second stack 2414 is coupled to the second data interface of the first stack 2412 via a second DQ link (DQ1). The first data interface of the third stack 2416 is coupled to the second data interface of the second stack 2414 via a third DQ link (DQ2). The first data interface of the fourth stack 2418 is coupled to the second data interface of the third stack 2416 via a fourth DQ link (DQ3).

[0270] In one embodiment, the memory module 2400 includes an RCD component 2402 coupled to a module interface via a primary CA link 2404 (CAx). A first secondary CA link 2406 is coupled between the RCD component 2402 and a first stack 2412. The first secondary CA link 2406 is shared with a third stack 2416. A second secondary CA link 2408 is coupled between the RCD component 2402 and a fourth stack 2418. The second secondary CA link 2408 is shared with a second stack 2414. It should be noted that the memory module 2400 may include additional stacks arranged in the same topology as these four stacks.

[0271] The following describes how the RCD component 2402 and the four stacks 2412-2418 handle read operations.

[0272] Fig.25 According to another embodiment Fig.242404. The RCD component 2402 receives a first command 2502 as a delayed read command (D) followed by a second command 2504 as a read command (R). The RCD component 2402 sends the first command 2502 on a first secondary CA link 2406, which results in a first access 2506 at a first stack 2412, and sends the second command 2504 on a second secondary CA link 2408, which results in a second access 2508 at a second stack 2414. The RCD component 2402 receives a third command 2510 as a delayed read command (D) followed by a fourth command 2512 as a read command (R). The RCD component 2402 sends the third command 2510 on the first secondary CA link 2406, which results in a third access 2514 at a third stack 2416, and sends the fourth command 2512 on the second secondary CA link 2408, which results in a fourth access 2516 at a fourth stack 2418. It should be noted that the delayed read command (D) may be encoded into one or more signals in various ways. For example, once the delayed read (D) is received on the primary CA link, the RCD component may add additional delay on the secondary CA link of a particular stack. Fig.25 As shown, the time between receiving a read command (R) on the primary CA link and sending the command on the first secondary CA link is different from the time between receiving a delayed read command (D) on the primary CA link and sending the command on the second secondary CA link. This allows simultaneous access to both stacks because they are separate groups. Moreover, because the accessed stacks are separate groups, data can be passed to the non-accessed stack (in another group) as an intermediate transfer to reduce data return delays and address bus contention, as described herein. Conversely, Fig.23 The read command (R) in shows the same timing response between receiving the command on the primary CA link and sending the command on the secondary CA connection.

[0273] Although the RCD component 2402 must still wait between the first command 2502 on the first auxiliary CA link 2406 and the third command 2510 being sent, the RCD component 2402 can send the first command 2502 on the first auxiliary CA link 2406 and the second command 2504 on the second auxiliary CA link 2408. Similarly, the RCD component 2402 can simultaneously send the third command 2510 on the first auxiliary CA link 2406 and the fourth command 2512 on the second auxiliary CA link 2408. The first command 2502 results in a first access slot 2520, and the second command 2504 results in a second access slot 2522. The first access slot 2520 and the second access slot 2522 are offset in time. The third command 2510 results in a third access slot 2524, and the fourth command 2512 results in a fourth access slot 2526. The third access slot 2524 and the fourth access slot 2526 are offset in time. Fig.25 As shown, the link slots limit the intervals at which each set of four columns can be accessed.

[0274] It should be noted that Fig.23 As shown, the access slots at the module interface are contiguous, but different from Fig.23 In comparison, the auxiliary data bus has less address bus contention and fewer access time slots are idle.

[0275] In another embodiment, a memory module includes a memory interface, a CA interface connected to a shared bus, and at least two groups of stacked memory components, wherein each memory component stack includes two data interfaces connected to a point-to-point topology in a linear chain. A first stack in a first group of at least two stacked memory components includes a first data interface coupled to the module interface and a second data interface coupled to a second stack in a second group of the at least two stacked memory components. In this topology, a first access slot at the module interface for the first group is offset in time from a second access slot at the module interface for the second group. That is, the access slots at the module interface for the group are offset in time to reduce data return delays and address bus connections.

[0276] In another embodiment, the memory controller is coupled to the memory module and uses an offset between the first access slot and the second access slot as a pipeline for slot access. As described above, the two groups can each include two stacks for a total of four stacks in the portion of the memory module. As described above, the memory module can include more portions having four stacks divided into two groups with auxiliary CA links. For example, there may be a total of 36 device sites with a stack at each device site. Alternatively, the two groups can each include only one stack, such as Fig.26 In other embodiments, the two groups may include more than two stacks, such as Fig.24A group can have any number of stacks, as long as adjacent stacks in a linear chain are in different groups so they can be accessed over separate CA links.

[0277] In an implementation of two groups of two respective stacks, the first group includes a first stack and a third stack, and the second group includes a second stack and a fourth stack. Similar to the first access slot and the second access slot being offset in time, the third access slot and the fourth access slot at the module interface are also offset in time. The second stack includes a first data interface coupled to the first stack in the first group and a second data interface coupled to the third stack in the first group. The third stack includes a first data interface coupled to the second stack in the second group and a second data interface coupled to the fourth stack in the second group.

[0278] In another embodiment, a memory module includes a printed circuit board having a first set of data lines, a second set of data lines, and a third set of data lines and a first set of pins and a second set of pins, the first pins being coupled to the first set of data lines. The memory module also includes four stacks: a first stack of DRAM components located at a first location on the printed circuit board; a second stack of DRAM components located at a second location on the printed circuit board; a third stack of DRAM components located at a third location on the printed circuit board; and a fourth stack of DRAM components located at a fourth location on the printed circuit board. The first stack of DRAM components includes a first data interface coupled to the first set of data lines and a second data interface coupled to the second set of data lines. The second stack of DRAM components includes a first data interface coupled to the second set of data lines and a second data interface coupled to the third set of data lines. The third stack of DRAM components includes a first data interface coupled to the third set of data lines and a second data interface coupled to the fourth set of data lines. The fourth stack of DRAM components includes a first data interface coupled to the fourth set of data lines.

[0279] In another embodiment, a memory module includes an RCD component arranged on a printed circuit board. The printed circuit board includes a first set, a second set, and a third set of command and address (CA) line sets and a third set of pins, the third set of pins being coupled to the first set of CA lines. The first set of CA lines is coupled to the RCD component, and the second set of CA lines is coupled between the RCD component and the first site and between the RCD component and the third site. The third set of CA lines is coupled between the RCD component and the second site and between the RCD component and the fourth site.

[0280] In various embodiments described herein, a DRAM component includes: a set of memory cells; a first set of data links; a second set of data links; a third set of data links; a first receiver coupled to the first set of data links; a first transmitter coupled to the first set of data links; a second receiver coupled to the second set of data links; a second transmitter coupled to the second set of data links; a first multiplexer having an output coupled to the first transmitter; a second multiplexer having an output coupled to the second transmitter; a third multiplexer; a fourth multiplexer having an output coupled to an input of the first multiplexer and an input of the second multiplexer; a fifth multiplexer having an output coupled to the set of memory cells; and a sixth multiplexer having an output coupled to the third set of data links. The first receiver is coupled to an input of the second multiplexer and to an input of the third multiplexer. The second receiver is coupled to an input of the first multiplexer and to an input of the third multiplexer. The output of the third multiplexer is coupled to an input of the fifth multiplexer and to an input of the sixth multiplexer. The third data link set is coupled to the input of the fifth multiplexer and to the input of the fourth multiplexer. The memory cell set is coupled to the input of the fourth multiplexer and to the input of the sixth multiplexer. Alternatively, the DRAM component may include more or fewer components to facilitate data transfer between other DRAM components in the stack and other DRAM components on other stacks, as described herein.

[0281] During operation, if Fig.25 As shown, the first data from the first stack is passed to the module interface at the first access slot in the first cycle. The second data from the second stack is passed to the first stack in the first cycle. The third data from the third stack is passed to the second stack in the first cycle. The fourth data from the fourth stack is passed to the third stack in the first cycle. In addition, the second data is passed to the module interface of the second access slot in the second cycle. The third data is passed from the second stack to the first stack in the second cycle, and the fourth data is passed from the third stack to the second stack in the second cycle. Then, the third data is passed to the module interface at the third access slot in the third cycle, and the fourth data is passed from the second stack to the first stack in the third cycle. Then, the fourth data is passed to the module interface at the fourth access slot in the fourth cycle.

[0282] Fig.2626 is a block diagram of a memory module 2600 having multiple DRAM stacks according to another embodiment, wherein the multiple DRAM stacks are arranged in at least two groups in a linear chain, wherein each DRAM stack includes two data interfaces. The memory module 2600 includes two stacks of memory components arranged in a first group 2611 and a second group 2613. The first group 2611 includes only a first stack 2612. The second group 2613 includes only a second stack 2614. The first data interface of the first stack 2612 is coupled to the module interface 2610 via a first DQ link (DQ0). The module interface 2610 (DQu) is arranged into a first nibble and includes a corresponding timing link. The first data interface of the second stack 2614 is coupled to the second data interface of the first stack 2612 via a second DQ link (DQ1).

[0283] In one embodiment, the memory module 2600 includes an RCD component 2602 coupled to a module interface via a primary CA link 2604 (CAx). A first secondary CA link 2606 is coupled between the RCD component 2602 and a first stack 2612. A second secondary CA link 2608 is coupled between the RCD component 2602 and a second stack 2414. It should be noted that the memory module 2400 may include additional stacks arranged in the same topology as these two stacks.

[0284] In one embodiment, during a first cycle of operation, first data from a first stack is delivered to the module interface at a first access slot, and second data from a second stack is delivered to the first stack. The second data is delivered to the module interface at a second access slot during a second cycle.

[0285] It should be noted that the above Figure 22-26 The described embodiment shows only a portion of a memory module. In one implementation, there may be 36 device sites with stacks, with a total of 36 stacks on the memory module. In other embodiments, the device sites may vary based on the application. Therefore, the memory module may include more stacks and groups than those illustrated and described herein. It should also be noted that the memory module may be implemented in a system. For example, a system may include a motherboard substrate, as described herein, on which a memory controller and one or more memory modules may be arranged.

[0286] The above embodiments are directed to dual-port dies. The following embodiments are directed to dual-port stacking of DRAM components for high-performance, high-capacity RDIMMs. A stacked pair of dual-port dies described herein can be manufactured using a die including a single DQ / DQS. The various embodiments described above may be referred to as a dynamic point-to-point (DPP) stacking structure or DPP stacking. In some cases, the DPP stacking architecture is implemented with a buffer. In other cases, the DPP stacking architecture is implemented with a stack. The DPP stacking architecture is able to achieve higher bus speeds by reducing the load on the DQ / DQS bus. The DPP stacking architecture also achieves higher system capacity by combining multiple modules in a given access. Fig. 27 A standard (non-DPP stacked) DDR3 DSDRAM topology is illustrated, where each die has only one DQ / DQS interface. Fig.28 The figure shows the topology of a DPP stack where each die has two DQ / DQS interfaces. Having two DQ / DQS interfaces may lead to multiple engineering challenges such as noise, crosstalk between independent interfaces, additional buffering and peripheral logic, etc. Dual-port dies may require changing the standard DRAM die in various ways. Fig.29 30 illustrates a topology where each die has only one DQ / DQS interface, but enables higher bus speeds and higher system capacity for DPP stacking. In these embodiments, the idea is that each package requires two DQ / DQS interfaces, but not each die. In these embodiments, a configuration can be used where the existing DQ / DQS interface on a standard die can be reused to create a DPP stacking architecture where the package includes two data interfaces instead of separate dies. In some embodiments, depending on how 3DS is implemented, the topology may include additional TSVs to allow one of the data interfaces to connect to the package interface, or the topology may include top-level bonding or additional F2F microballs to form connections for two ports on the die stack, each with a single DQ / DQS interface. It should be noted that in other embodiments, there may be more than two dies in the stack, where each die is dual-ported. It should also be noted that in other embodiments, there may be more than two dies in the stack, where each stack is dual-ported.

[0287] Fig. 272700 is a block diagram of a standard stack of memory components according to one embodiment, each memory component including a single data interface. The standard stack 2700 is illustrated as having two memory components. In this implementation, a first memory component 2702 and a second memory component 2704 are isomorphic. However, since the data interface 2706 of the second memory component 2704 is not used, the transmitter, receiver, and multiplexer coupled to the data interface are power-gated. Access to the second memory component 2704 is accessed via the data interface 2708 of the first memory component and the auxiliary interface 2710 coupled to all memory components in the stack 2700. The auxiliary interface 2710 can be implemented using TSV.

[0288] Fig.28 2800 is a block diagram of a stack of memory components according to an embodiment, each memory component including two data interfaces. Stack 2800 is illustrated as having two memory components. In this implementation, a first memory component 2802 and a second memory component 2804 are isomorphic. The first memory component includes a first data interface 2806 and a second data interface 2808. The second memory component also includes two data interfaces. However, since the data interface of the second memory component 2804 is not used, the transmitter, receiver and multiplexer coupled to the data interface are power-gated. Access to the second memory component 2804 is accessed via the data interface 2806 or the data interface 2808 of the first memory component and the auxiliary interface 2810 coupled to all memory components in the stack 2800. The auxiliary interface 2810 can be implemented using TSV.

[0289] Fig.29 2900 is a block diagram of a stack of memory components according to one embodiment, wherein the stack 2900 includes two data interfaces and each memory component includes one data interface. The stack 2900 is illustrated as having two memory components, however, the stack 2900 may include more than two memory components in the stack. In this embodiment, the first memory component 2902 and the second memory component 2904 are isomorphic. The first memory component 2902 includes a first data interface 2906, and the second memory component 2904 includes a second data interface 2908. The transmitter, receiver, and multiplexer of the second memory component 2904 are used and are therefore not power-gated. The second memory component 2904 may be accessed via the first data interface 2906 or the second data interface 2908. In some cases, the second memory component 2904 is accessed via the first data interface of the first memory component 2902 and the auxiliary interface 2910 coupled to all memory components in the stack 2900. In other cases, the second memory component 2904 is accessed via the second data interface 2908. The auxiliary interface 2910 can be implemented using TSV. Fig.29 As shown, additional TSVs 2912 may be used to connect a second data interface (DQS / DQ) 2908 to the first memory component 2902, also referred to as a base chip, to connect to a second packaging interface.

[0290] It should be noted that in this embodiment, the auxiliary interface 2910 may still include multiple (hundreds in size) wide TSVs for internal interfaces, but additional TSVs (tens) are used to pull data lines from the second data interface 2908 to the first memory component 2902.

[0291] In some cases, the first memory component 2902 is closer to the package substrate than the second memory component 2904. For example, the first memory component 2902 is the closest or bottommost memory component in the stack 2900, and the second memory component 2904 is the farthest or topmost memory component in the stack 2900. The stack 2900 can include zero or more intermediate memory components between the first memory component 2902 and the second memory component 2904. It should be noted that there are other embodiments that connect the data interface to the two package interfaces. For example, the wire bonding connection can be as follows with respect to Figures 30A-30B Use as shown and described.

[0292] Fig. 30A is a block diagram of a stack 3000 of memory components according to another embodiment, wherein the stack 3000 includes two data interfaces and each memory component includes one data interface. Fig. 30B is a side view of a memory module having two stacks, each stack including two data interfaces and each memory component including one data interface according to one embodiment. Figures 30A-30B, stack 3000 is illustrated as having two memory components, however, stack 3000 may include more than two memory components in the stack. In the present embodiment, first memory component 3002 and second memory component 3004 are isomorphic. First memory component 3002 includes first data interface 3006, and second memory component 3004 includes second data interface 3008. Transmitter, receiver and multiplexer of second memory component 3004 are used, and therefore are not power gated. Access to second memory component 3004 may be accessed via first data interface 3006 or second data interface 3008. In some cases, second memory component 3004 is accessed via first data interface 3006 of first memory component 3002 and auxiliary interface 3010 coupled to all memory components in stack 3000. In other cases, second memory component 3004 is accessed via second data interface 3008. Auxiliary interface 3010 may be implemented using TSV. However, unlike the case where additional TSVs are used to connect the data interface of the second memory component 3004 to the second package interface Fig.29 , stack 3000 uses wire bonding connection 3020. Wire bonding connection 3020 can be a natural bonding interface. Fig. 30A As shown, wire bond connections 3020 may be bonded on top of stack 3000 .

[0293] In some cases, first memory component 3002 is closer to the package substrate than second memory component 3004. For example, first memory component 3002 is the closest or bottommost memory component in stack 3000, while second memory component 3004 is the furthest or topmost memory component in stack 3000. Stack 3000 may include zero or more intermediate memory components between first memory component 3002 and second memory component 3004.

[0294] In another embodiment, if Fig. 30A As shown, stack 3000 is arranged on a first packaging substrate 3022. First packaging substrate 3022 includes two packaging interfaces. A data interface of first memory component 3002 is coupled to the first packaging interface, and a data interface of second memory component 3004 is coupled to the second packaging interface via wire bonding connection 3020.

[0295] In another embodiment, a memory package includes a packaging substrate including at least two data interfaces and a stack of homogeneous memory components stacked on the packaging substrate. A first memory component includes an external data interface connected to a subset of the stacked memory components and an internal data interface connected to all of the memory components in the stack. In some cases, the external data interface is connected to only one of the memory components. However, in other embodiments, when the stack has more than two memory components, one of the at least two data interfaces can be connected to more than one memory component in the stack. In either embodiment, the external data interfaces of at least two of the memory components in the stack are coupled to at least two data interfaces on the packaging substrate. Although Figures 30A-30B Only two memory components are shown, but there may be more than two components, and Figures 30A-30B The two memory components illustrated in are the topmost and bottommost memory components in the stack. The external data interfaces of the two memory components are coupled to at least two data interfaces on the package substrate, while the external data interface of the middle memory component is not coupled to at least two data interfaces on the package substrate. The internal data interfaces of all memory components are connected to all other memory components in the stack. As described herein, stacks of homogeneous memory components can each include a single set of primary interfaces and a set of secondary interfaces, also referred to as a single DQ / DQs, where the memory components include only external data interfaces and internal data interfaces.

[0296] In one embodiment, the second memory component 3004 is the topmost memory component. The external data of the topmost memory component is coupled to the first data interface on the package substrate. The first memory component 3002 is the bottommost memory component. The bottommost memory component is arranged closer to the topmost memory component on the package substrate 3022. The external data interface of the bottommost memory component is coupled to the second data interface on the package substrate.

[0297] Access to any one of the memory components in the stack may be made through at least one of the first data interface or the second data interface. The memory component stack may pass data from the first data interface to the second data interface through the internal data interface and pass data from the second data interface to the first data interface through the internal data interface. In one embodiment, the memory components include boot logic to enable bypass paths through the memory component stack, such as with respect to Fig.31 In some embodiments, the internal data interfaces of the memory components in the stack are not coupled to the packaging substrate, but the first external interface of the first memory component in the stack is coupled to the packaging substrate and the second external interface of the second memory component in the stack is coupled to the packaging substrate.

[0298] In another embodiment, the first packaging substrate includes two or more packaging interfaces and a dual-port stack including a plurality of homogeneous memory components stacked on the packaging substrate. The dual-port stack includes a first memory component of the dual-port stack. The first memory component includes a first external data interface of a first packaging interface connected to two packaging interfaces on the packaging substrate and a first internal data interface connected to all other memory components in the dual-port stack. The second memory component of the dual-port stack includes a second external data interface connected to a second packaging interface on the packaging substrate and a second internal data interface connected to all other memory components of the dual-port stack. In another embodiment, the dual-port stack includes a third memory component. The third memory component includes a third external data interface not connected to the two packaging interfaces on the packaging substrate and a third internal data interface connected to all other memory components in the dual-port stack. In another embodiment, the dual-port stack includes a fourth memory component. The fourth memory component includes a fourth external data interface not connected to the two packaging interfaces on the packaging substrate and a fourth internal data interface connected to all other memory components in the dual-port stack. In other embodiments, the dual-port stack may include more than four components.

[0299] refer to Fig. 30A , the first packaging substrate 3022 is arranged on the memory module substrate 3030. The second packaging substrate 3032 is arranged on the side opposite to the first packaging substrate 3022. The second dual-port stack 3034 can be arranged on the second packaging substrate 3032 in a manner similar to the stack 3000. The second packaging substrate 3032 includes at least two additional packaging interfaces. The second dual-port stack 3034 may include two or more homogeneous memory components stacked on the second packaging substrate 3032. The second dual-port stack 3034 may be a third memory component, the third memory component having a third external data interface connected to the third packaging interface on the second packaging substrate 3032 and a third internal data interface connected to all other memory components in the second dual-port stack 3034. The second dual-port stack 3034 may also include a fourth memory component, the fourth memory component having a fourth external data interface connected to the fourth packaging interface on the second packaging substrate 3032 and a fourth internal data interface connected to all other memory components in the second dual-port stack 3034.

[0300] like Fig. 30AAs illustrated in the embodiment of the present invention, the first memory component 3002 is located at the first side of the dual-port stack 3000 arranged on the first surface of the packaging substrate 3022, and the second memory component 3004 is located at the second side of the dual-port stack 3000 arranged farthest from the first surface of the packaging substrate 3022. The dual-port stack 3000 and the first packaging substrate 3022 are arranged on the first surface of the memory module substrate, and the second dual-port stack 3034 and the second packaging substrate 3032 are arranged on the second surface of the memory module substrate. As described herein, the topmost memory component can be connected to the corresponding packaging substrate using wire bonding interconnects. Alternatively, as described herein, the data interface of one of the memory components can be connected to the packaging substrate via an additional TSV.

[0301] In one embodiment, the memory components of the dual port stack 3000 or the second dual port stack 3034 each include boot logic that can be programmed to enable a bypass path through the stack of memory components, such as with respect to Fig.31 As shown and described.

[0302] Fig.31 A through path 3120 through a dual port stack 3100 is shown according to one embodiment. The dual port stack 3100 includes a first memory component 3102 and a second memory component 3104 stacked on a packaging substrate. It should be noted that more memory components may be part of the stack, but for ease of description, the depicted embodiment is illustrated and described with respect to two memory components in the stack. The dual port stack 3100 and Fig.32 The stack 3200 in FIG. 1 is different in that it includes two ports per stack (or per package) rather than two ports per stack (or per package). Fig.32 Each memory component shown has two ports. The dual-port stack 3100 can handle bypass operations. Data can be received on the second external interface 3106 by the boot logic in the second memory component 3104. The second external interface 3106 is coupled to the second package interface on the package substrate. The boot logic can transmit data through the internal data interface 3108, which can be a TSV connecting all memory components in the dual-port stack 3100. The boot logic in the first memory component 3102 receives data from the internal data interface 3108 and transmits the data through the first external interface 3110. The first external interface 3110 is coupled to the first package interface on the package substrate. For comparison, bypass operations using a stack with dual-port memory components are described in detail. Fig.32 Give a description.

[0303] Fig.32A through path 3220 through a stack 3200 with two data interfaces according to one implementation is illustrated. The stack 3200 includes a first memory component 3202 and a second memory component 3204. The first memory component 3202 includes two data interfaces coupled to a package interface on a package substrate. Since the data interface of the second memory component 3204 is not used, these interfaces and the corresponding boot logic are power gated. Data is received on the first data interface and the boot logic transmits data on the second data interface, and vice versa.

[0304] According to a first aspect of the present disclosure, a memory module is provided, comprising: a module interface; a first memory component stack, comprising: a first data interface, coupled to the module interface; and a second data interface; a second memory component stack, comprising: a third data interface, coupled to the second data interface of the first stack, wherein the second data interface and the third data interface are connected using a point-to-point topology in a linear chain; and a fourth data interface; and a command and address (CA) interface, coupled to the first stack and the second stack, wherein the CA interface is used to: receive a first command and a second command from a memory controller; control the timing of a first access slot at the module interface for data associated with the first command; and control the timing of a second access slot at the module interface for data associated with the second command.

[0305] In some embodiments, wherein the CA interface for controlling the timing of the second access slot is used to insert a configurable delay such that the second access slot is offset in time from the first access slot at the module interface.

[0306] In some embodiments, wherein the fourth data interface is coupled to the module interface, and wherein the CA interface is used to control the timing of the first access slot and the timing of the second access slot to occur simultaneously.

[0307] In some embodiments, the memory module further includes: a third memory component stack, including: a fifth data interface, coupled to the fourth data interface of the second stack using the point-to-point topology in the linear chain; and a sixth data interface, wherein the CA interface is also used to: receive a third command from the storage controller; and control the timing of a third access slot at the module interface for data associated with the third command.

[0308] In some embodiments, wherein the CA interface for controlling the timing of the third access slot is used to insert a second configurable delay such that the third access slot is offset in time from the first access slot and the second access slot at the module interface.

[0309] In some embodiments, wherein the sixth data interface is coupled to the module interface, and wherein the CA interface is used to control the timing of the first access slot and the timing of the third access slot to occur simultaneously.

[0310] In some embodiments, the memory module also includes: a fourth memory component stack, including: a seventh data interface, coupled to the sixth data interface of the third stack using the point-to-point topology in the linear chain; and an eighth data interface, wherein the CA interface is also used to: receive a fourth command from the storage controller; and control the timing of a fourth access slot at the module interface for data associated with the fourth command.

[0311] In some embodiments, eight data interfaces are coupled to the module interface, wherein the CA interface is used to control the timing of the first access slot and the timing of the fourth access slot to occur at a first time, wherein the CA interface is used to control the timing of the second access slot and the timing of the third access slot to occur at a second time, and the second time is after a configurable delay after the first time.

[0312] In some embodiments, wherein the CA interface for controlling the timing of the fourth access slot is used to insert a second configurable delay such that the third access slot is offset in time from the first access slot and the second access slot at the module interface.

[0313] In some embodiments, the memory module further includes: a third memory component stack, including: a fifth data interface, coupled to the fourth data interface of the second stack using the point-to-point topology in the linear chain; and a sixth data interface; a fourth memory component stack, including: a seventh data interface, coupled to the sixth data interface of the third stack using the point-to-point topology in the linear chain; and an eighth data interface, coupled to the module interface, wherein the CA interface includes: a first auxiliary CS link, coupled to the first stack and the second stack; and a second auxiliary CS link, coupled to the third stack and the fourth stack.

[0314] In some embodiments, the memory module also includes: a third memory component stack, including: a fifth data interface, which is coupled to the second data interface of the first stack using the point-to-point topology in the linear chain; and a sixth data interface; a fourth memory component stack, including: a seventh data interface, which is coupled to the sixth data interface of the third stack using the point-to-point topology in the linear chain; and an eighth data interface, which is coupled to the module interface, wherein the CA interface includes: a first auxiliary CS link, which is coupled to the first stack and the third stack; and a second auxiliary CS link, which is coupled to the second stack and the fourth stack.

[0315] According to a second aspect of the present disclosure, a memory module is provided, comprising: a module interface; a first memory component stack, a second memory component stack, a third memory component stack and a fourth memory component stack; and a buffer component coupled to a primary command and address (CA) bus, a first auxiliary CA link and a second auxiliary CA link, wherein: the first stack comprises a first data interface and a second data interface coupled to the module interface; the first stack is coupled to the first auxiliary CA link; the fourth stack comprises a third data interface and a fourth data interface coupled to the module interface; the fourth stack is coupled to the second auxiliary CA link; the second stack comprises a fifth data interface and a sixth data interface coupled to the second data interface of the first stack; and the third stack comprises a seventh data interface coupled to the sixth data interface of the second stack and an eighth data interface coupled to the fourth data interface of the fourth stack.

[0316] In some embodiments, wherein the first auxiliary CS link is coupled to the second stack and the second auxiliary CS link is coupled to the third stack.

[0317] In some embodiments, the buffer component is used to: receive a first command, a second command, a third command, and a fourth command from a storage controller; control the timing of a first access slot at the module interface for data associated with the first command; control the timing of a second access slot at the module interface for data associated with the second command; control the timing of a third access slot at the module interface for data associated with the third command; and control the timing of a fourth access slot at the module interface for data associated with the fourth command, wherein the first access slot, the second access slot, the third access slot, and the fourth access slot are sequential access slots.

[0318] In some embodiments, the buffer component for controlling the timing of the second access slot is used to insert a configurable delay so that the second access slot is offset in time from the first access slot at the module interface, and the buffer component for controlling the timing of the fourth access slot inserts the configurable delay so that the fourth access slot is offset in time from the third access slot at the module interface.

[0319] In some embodiments, wherein the first auxiliary CS link is coupled to the third stack and the second auxiliary CS link is coupled to the second stack.

[0320] In some embodiments, the buffer component is used to: receive a first command, a second command, a third command, and a fourth command from a storage controller; control the timing of a first access slot at the module interface for data associated with the first command; control the timing of a second access slot at the module interface for data associated with the second command; control the timing of a third access slot at the module interface for data related to the third command; and control the timing of a fourth access slot at the module interface for data associated with the fourth command, wherein the first access slot, the second access slot, the third access slot, and the fourth access slot are sequential access slots.

[0321] In some embodiments, the buffer component for controlling the timing of the second access slot is used to insert a configurable delay so that the second access slot is offset in time from the first access slot at the module interface, and the buffer component for controlling the timing of the fourth access slot is used to insert a configurable delay so that the fourth access slot is offset in time from the third access slot at the module interface.

[0322] According to a third aspect of the present disclosure, a memory module is provided, comprising: a module interface, including a first data link and a second data link; a first memory component stack; a second memory component stack; and a buffer component coupled to a main command and address (CA) bus, wherein: the first stack comprises a first data interface and a second data interface coupled to the first data link; and the second stack comprises a third data interface coupled to the second data link and a fourth data interface coupled to the second data interface of the first stack.

[0323] In some embodiments, the first stack includes a first dynamic random access memory (DRAM) component and a second DRAM component, wherein the first DRAM component includes: a set of memory cells; a command and address (CA) interface coupled to the set of memory cells; and boot logic coupled to the set of memory cells, wherein the boot logic includes: a first internal data interface coupled to the first data interface of the first stack; a second internal data interface coupled to the second data interface of the first stack; and a third internal data interface selectively coupled to the first data interface and the second data interface, wherein the third data interface is used to couple to a set of through silicon via (TSV) links in the first stack for accessing the second DRAM component of the first stack.

[0324] According to a fourth aspect of the present disclosure, a dynamic random access memory (DRAM) component is provided, comprising: a memory cell set; a first data link set; a second data link set; a third data link set; a first receiver coupled to the first data link set; a first transmitter coupled to the first data link set; a second receiver coupled to the second data link set; a second transmitter coupled to the second data link set; a first multiplexer having an output coupled to the first transmitter; a second multiplexer having an output coupled to the second transmitter; a third multiplexer; a fourth multiplexer having an output coupled to an input of the first multiplexer and an input of the second multiplexer; a fifth multiplexer having an output coupled to the first multiplexer; a fifth multiplexer having an output coupled to ... first multiplexer having an output coupled to the first multiplexer; a second multiplexer having an output coupled to the second multiplexer; a fifth multiplexer having an output of a set of memory cells; and a sixth multiplexer having an output coupled to the third set of data links, wherein the first receiver is coupled to the input of the second multiplexer and to the input of the third multiplexer, wherein the second receiver is coupled to the input of the first multiplexer and to the input of the third multiplexer, wherein the output of the third multiplexer is coupled to the input of the fifth multiplexer and to the input of the sixth multiplexer, wherein the third set of data links is coupled to the input of the fifth multiplexer and to the input of the fourth multiplexer, and wherein the set of memory cells is coupled to the input of the fourth multiplexer and to the input of the sixth multiplexer.

[0325] In some embodiments, the third set of data lines is a set of through silicon via (TSV) links.

[0326] In some embodiments, the DRAM component further includes a command address (CA) link set.

[0327] In some embodiments, the set of memory cells is organized into a plurality of memory bank groups.

[0328] According to a fifth aspect of the present disclosure, a memory module is provided, comprising: a printed circuit board, comprising: a first data line set, a second data line set and a third data line set; and a first pin set and a second pin set, the first pin set being coupled to the first data line set, and the second pin set being coupled to the second data line set; a first dynamic random access memory (DRAM) component, located at a first location on the printed circuit board, wherein the first DRAM component comprises a first data interface coupled to the first data line set and a second data interface coupled to the third data line set; and a second DRAM component, located at a second location on the printed circuit board, wherein the second DRAM component comprises a first data interface coupled to the third data line set and a second data interface coupled to the second data line.

[0329] In some embodiments, the memory module also includes a temporary clock driver (RCD) component, and wherein the printed circuit board includes: a first command and address (CA) line set and a second command and address (CA) line set; and a fourth pin set, wherein the fourth pin set is coupled to the first CA line set, wherein the second CA line set is coupled between the RCD and the first location and between the RCD and the second location.

[0330] In some embodiments, the first DRAM component is part of a first DRAM stack at the first location and the second DRAM component is part of a second DRAM stack at the second location, wherein the first DRAM stack includes a primary DRAM component and a plurality of secondary DRAM components, and wherein the second DRAM stack includes a primary DRAM component and a plurality of secondary DRAM components.

[0331] In some embodiments, the memory module further includes: a third DRAM stack located at a third location on the printed circuit board; and a fourth DRAM stack located at a fourth location on the printed circuit board, wherein the first DRAM stack, the second DRAM stack, the third DRAM stack and the fourth DRAM stack are connected in a chain between the first pin set and the second pin set, wherein the third DRAM stack includes a third DRAM component, the third DRAM component having a first data interface and a second data interface, the first data interface being coupled to a first subset of the third data line set, and the second data interface being coupled to a second subset of the third data line set, wherein the fourth DRAM stack includes a fourth DRAM component, the fourth DRAM component having a first data interface and a second data interface, the first data interface being coupled to a third subset of the third data line set, and the second data interface being coupled to a fourth subset of the third data line set.

[0332] In some embodiments, the memory module also includes a temporary clock driver (RCD) component, and wherein the printed circuit board includes: a first command and address (CA) line set and a second command and address (CA) line set; and a fourth pin set, wherein the fourth pin set is coupled to the first CA line set, wherein the second CA line set is coupled between the RCD and the first location and between the RCD and the second location.

[0333] In some embodiments, the first DRAM component includes: a set of memory cells; a first set of data links; a second set of data links; a third set of data links; a first receiver coupled to the first set of data links; a first transmitter coupled to the first set of data links; a second receiver coupled to the second set of data links; a second transmitter coupled to the second set of data links; a first multiplexer having an output coupled to the first transmitter; a second multiplexer having an output coupled to the second transmitter; a third multiplexer; a fourth multiplexer having an output coupled to an input of the first multiplexer and an input of the second multiplexer; a fifth multiplexer having an output coupled to the set of memory cells; a fifth multiplexer having an output coupled to the first multiplexer ... second multiplexer; a fifth multiplexer having an output coupled to the first multiplexer; a fifth multiplexer having an output coupled to the first multiplexer; a fifth multiplexer having an output coupled to the first multiplexer; a fifth multiplexer having an output coupled to the second multiplexer; a fifth multiplexer having an output coupled to the first multiplexer; a fifth multiplexer having an output coupled to the second multiplexer; a fifth multiplexer having an output coupled to the first multiplexer; a fifth multiplexer having an output coupled to the first multiplexer; a fifth multiplexer having an output coupled to the second multiplexer; a fifth multiplexer having an output coupled to the first multiplexer; a fifth multiplexer having an output coupled to the and a sixth multiplexer having an output coupled to the third set of data links, wherein the first receiver is coupled to the input of the second multiplexer and to the input of the third multiplexer, wherein the second receiver is coupled to the input of the first multiplexer and to the input of the third multiplexer, wherein the output of the third multiplexer is coupled to the input of the fifth multiplexer and to the input of the sixth multiplexer, wherein the third set of data links is coupled to the input of the fifth multiplexer and to the input of the fourth multiplexer, wherein the set of memory cells is coupled to the input of the fourth multiplexer and to the input of the sixth multiplexer.

[0334] In some embodiments, wherein the first data interface is arranged into a first nibble and the second data interface is arranged into a second nibble, the first nibble and the second nibble each include a corresponding timing link.

[0335] In some embodiments, wherein during a write operation, the first data interface is configured to receive data and the second data interface is configured to retransmit the data.

[0336] In some embodiments, wherein during a read operation, the second data interface is configured to receive data and the first data interface is configured to retransmit the data.

[0337] In some embodiments, the first DRAM component includes: a set of memory cells organized into a first memory bank group and a second memory bank group, wherein the first data interface is configured to access at least one of the first memory bank group or the second memory bank group.

[0338] According to a sixth aspect of the present disclosure, a memory module is provided, comprising: a module interface; at least two groups of stacked memory components, wherein each stack of memory components includes two data interfaces connected using a point-to-point topology in a linear chain, wherein a first stack in a first group of the at least two groups of stacked memory components includes: a first data interface coupled to the module interface; and a second data interface coupled to a second stack in a second group of the at least two groups of stacked memory components; and a command and address (CA) interface connected on a shared bus, wherein a first access slot at the module interface of the first group is offset in time from a second access slot at the module interface of the second group.

[0339] In some embodiments, the offset between the first access slot and the second access slot is controlled by a memory controller coupled to the memory module as a pipeline of slot accesses.

[0340] In some embodiments, wherein the CA interface includes a remanent clock driver (RCD) component, the RCD component is coupled to the memory controller via a primary CA link, coupled to the first group using a first secondary CA link, and coupled to the second group using a second secondary CA link, wherein the RCD component is operable to receive a first command or a second command from the memory controller on the primary CA link, wherein the at least two groups of stacked memory components are programmed with a first delay in response to the first command and are programmed with a second delay in response to the second command, and wherein the first delay is less than the second delay.

[0341] In some embodiments, wherein the CA interface includes a remanent clock driver (RCD) component, the RCD component is coupled to the memory controller via a primary CA link, coupled to the first group using a first secondary CA link, and coupled to the second group using a second secondary CA link, wherein the RCD component is operable to receive a read command or a delayed read command from the memory controller on the primary CA link, wherein the at least two groups of stacked memory components are programmed with a first delay in response to the read command and are programmed with a second delay in response to the delayed read command, and wherein the first delay is less than the second delay.

[0342] In some embodiments, wherein the first group of the at least two groups of stacked memory components includes the first stack and the third stack, wherein the second group of the at least two groups of stacked memory components includes the second stack and the fourth stack, wherein the third access slot at the module interface of the first group is offset in time from the fourth access slot at the module interface of the second group.

[0343] In some embodiments, wherein: the second stack in the first group includes: a first data interface, coupled to the first stack in the first group; and a second data interface, coupled to the third stack in the first group; and the third stack in the first group includes: a first data interface, coupled to the second stack in the second group; and a second data interface, coupled to the fourth stack in the second group.

[0344] In some embodiments, first data from the first stack is passed to the module interface at the first access slot in a first cycle, second data from the second stack is passed to the first stack in the first cycle, third data from the third stack is passed to the second stack in the first cycle, and fourth data from the fourth stack is passed to the third stack in the first cycle.

[0345] In some embodiments, the second data is passed to the module interface at the second access slot in a second cycle, wherein the third data is passed from the second stack to the first stack in the second cycle, and wherein the fourth data is passed from the third stack to the second stack in the second cycle.

[0346] In some embodiments, the third data is transferred to the module interface at the third access slot in a third cycle, and the fourth data is transferred from the second stack to the first stack in the third cycle.

[0347] In some embodiments, the fourth data is transferred to the module interface at a fourth access slot in a fourth cycle.

[0348] In some embodiments, wherein the first group of the at least two groups of stacked memory components includes only the first stack, wherein the second group of the at least two groups of stacked memory components includes only the second stack, wherein the CA interface includes a register clock driver (RCD) component, the RCD component is coupled to the memory controller via a primary CA link, is coupled to the first stack using a first secondary CA link, and is coupled to the second stack using a second secondary CA link.

[0349] In some embodiments, first data from the first stack is passed to the module interface at the first access slot in a first cycle, second data from the second stack is passed to the first stack in the first cycle, and second data is passed to the module interface at the second access slot in a second cycle.

[0350] In some embodiments, wherein the module interface is arranged into a first nibble, the first nibble includes a corresponding timing link.

[0351] According to the seventh aspect of the present disclosure, a memory module is provided, comprising: a printed circuit board, comprising: a first data line set, a second data line set and a third data line set; and a first pin set and a second pin set, the first pin set being coupled to the first data line set; a first dynamic random access memory (DRAM) component stack, located at a first location on the printed circuit board, wherein the first DRAM component stack comprises a first data interface coupled to the first data line set and a second data interface coupled to the second data line set; a second DRAM component stack, located at a second location on the printed circuit board, wherein the second DRAM component stack comprises a first data interface coupled to the second data line set and a second data interface coupled to the third data line set; a third DRAM component stack, located at a third location on the printed circuit board, wherein the third DRAM component stack comprises a first data interface coupled to the third data line set and a second data interface coupled to the fourth data line set; and a fourth DRAM component stack, located at a fourth location on the printed circuit board, wherein the fourth DRAM component stack comprises a first data interface coupled to the fourth data line set.

[0352] In some embodiments, a temporary clock driver (RCD) component is also included and arranged on the printed circuit board, and wherein the printed circuit board includes: a first set, a second set and a third set of command and address (CA) line sets; and a third pin set, wherein the third pin set is coupled to the first CA line set, wherein the first CA line set is coupled to the RCD component, wherein the second CA line set is coupled between the RCD component and the first location and between the RCD component and the third location, and wherein the third CA line set is coupled between the RCD component and the second location and between the RCD component and the fourth location.

[0353] In some embodiments, the first DRAM component of the first DRAM component stack includes: a memory cell set; a first data link set; a second data link set; a third data link set; a first receiver coupled to the first data link set; a first transmitter coupled to the first data link set; a second receiver coupled to the second data link set; a second transmitter coupled to the second data link set; a first multiplexer having an output coupled to the first transmitter; a second multiplexer having an output coupled to the second transmitter; a third multiplexer; a fourth multiplexer having an output coupled to an input of the first multiplexer and an input of the second multiplexer; a fifth multiplexer having an output coupled to the memory cell set ... first multiplexer having an output coupled to the first multiplexer a first receiver coupled to an input of the second multiplexer and to an input of the third multiplexer, wherein the second receiver is coupled to an input of the first multiplexer and to an input of the third multiplexer, wherein the output of the third multiplexer is coupled to an input of the fifth multiplexer and to an input of the sixth multiplexer, wherein the third data link set is coupled to an input of the fifth multiplexer and to an input of the fourth multiplexer, wherein the memory cell set is coupled to an input of the fourth multiplexer and to an input of the sixth multiplexer.

[0354] According to an eighth aspect of the present disclosure, there is provided a system, comprising: a motherboard substrate;

[0355] A memory controller arranged on the motherboard substrate; a memory module arranged on the motherboard substrate and coupled to the memory controller; wherein the memory module comprises: a module interface; at least two groups of stacked memory components, wherein each stacked memory component comprises two data interfaces connected using a point-to-point topology in a linear chain, wherein a first stack in a first group of the at least two groups of stacked memory components comprises: a first data interface coupled to the module interface; and a second data interface coupled to a second stack in a second group of the at least two groups of stacked memory components; and a command and address (CA) interface connected on a shared bus, wherein a first access slot at the module interface of the first group is offset in time from a second access slot at the module interface of the second group.

[0356] In some embodiments, wherein the memory controller is operable to control an offset between the first access slot and the second access slot as a pipeline of slot accesses.

[0357] In some embodiments, the at least two groups of stacked memory components are programmed with a first delay in response to a first command from the memory controller and are programmed with a second delay in response to a second command from the memory controller, and wherein the first delay is less than the second delay.

[0358] In some embodiments, wherein the first stack of the first group is programmed with a first delay, and wherein the second stack of the second group is programmed with a second delay, wherein the first delay and the second delay are the same.

[0359] In some embodiments, wherein the CA interface includes a register clock driver (RCD) component, the RCD component is coupled to the memory controller via a primary CA link, coupled to the first group using a first secondary CA link, and coupled to the second group using a second secondary CA link.

[0360] According to a ninth aspect of the present disclosure, a memory package is provided, comprising: a packaging substrate comprising at least two data interfaces; and a memory component stack stacked on the packaging substrate, wherein the stacked memory components are homogeneous, wherein each of the memory components comprises: an external data interface connected to a subset of the stacked memory components; and an internal data interface connected to all of the stacked memory components, and wherein the external data interfaces of at least two of the memory components are coupled to the at least two data interfaces on the packaging substrate.

[0361] In some embodiments, each of the memory components includes a single set of primary and secondary interfaces including only the external data interface and the internal data interface.

[0362] In some embodiments, each of the memory components includes boot logic for enabling a bypass path through the stack of memory components.

[0363] In some embodiments, the memory component stack includes: a top-most memory component, wherein the external data interface of the top-most memory component is coupled to a first data interface of the at least two data interfaces on the packaging substrate; and a bottom-most memory component, which is arranged on the packaging substrate closer than the top-most memory component, wherein the external data interface of the bottom-most memory component is coupled to a second data interface of the at least two data interfaces on the packaging substrate.

[0364] In some embodiments, access to any one of the memory components in the stack is performed through at least one of the first data interface or the second data interface.

[0365] In some embodiments, wherein the memory component stack is operable to transfer data from the first data interface to the second data interface through the internal data interface, and to transfer data from the second data interface to the first data interface through the internal data interface.

[0366] In some embodiments, the internal data interface is not coupled to the packaging substrate.

[0367] In some embodiments, the external interface of a first memory component of the memory component stack is coupled to the packaging substrate, and wherein the external interface of a second memory component of the memory component stack is not coupled to the packaging substrate.

[0368] According to the tenth aspect of the present disclosure, a device is provided, comprising: a packaging substrate comprising at least two packaging interfaces; and a dual-port stack comprising a plurality of homogeneous memory components stacked on the packaging substrate, wherein: a first memory component of the plurality of homogeneous memory components comprises: a first external data interface, the first external data interface being connected to a first packaging interface among the at least two packaging interfaces on the packaging substrate; and a first internal data interface, the first internal data interface being connected to all other memory components of the plurality of homogeneous memory components in the dual-port stack; and a second memory component of the plurality of homogeneous memory components comprises: a second external data interface, the second external data interface being connected to a second packaging interface among the at least two packaging interfaces on the packaging substrate; and a second internal data interface, the second internal data interface being connected to all other memory components of the plurality of homogeneous memory components in the dual-port stack.

[0369] In some embodiments, wherein: a third memory component among the multiple homogeneous memory components comprises: a third external data interface, which is not connected to the at least two packaging interfaces on the packaging substrate; and a third internal data interface, which is connected to all other memory components of the multiple homogeneous memory components in the dual-port stack; and a fourth memory component among the multiple homogeneous memory components comprises: a fourth external data interface, which is not connected to the at least two packaging interfaces on the packaging substrate; and a fourth internal data interface, which is connected to all other memory components of the multiple homogeneous memory components in the dual-port stack.

[0370] In some embodiments, the device also includes: a memory module substrate, wherein the packaging substrate is arranged on a first side of the memory module substrate; a second packaging substrate, comprising at least two additional packaging interfaces, wherein the second packaging substrate is arranged on a second side of the memory module substrate; and a second dual-port stack, comprising a second plurality of homogeneous memory components stacked on the second packaging substrate, wherein: a third memory component of the second plurality of homogeneous memory components includes: a third external data interface, the third external data interface is connected to a third packaging interface among the at least two additional packaging interfaces on the second packaging substrate; and a third internal data interface, the third internal data interface is connected to all other memory components of the second plurality of homogeneous memory components in the second dual-port stack; and a fourth memory component of the second plurality of homogeneous memory components includes: a fourth external data interface, the fourth external data interface is connected to a fourth packaging interface of the at least two additional packaging interfaces on the second packaging substrate; and a fourth internal data interface, the fourth internal data interface is connected to all other memory components of the second plurality of homogeneous memory components in the second dual-port stack.

[0371] In some embodiments, the first memory component and the second memory component each include steering logic to enable a bypass path through the dual port stack.

[0372] In some embodiments, the first memory component is located at a first side of the dual-port stack arranged on a first surface of the packaging substrate, and wherein the second memory component is located at a second side of the dual-port stack arranged farthest from the first surface of the packaging substrate.

[0373] In some embodiments, the second external data interface is connected to the second packaging interface on the packaging substrate via a wire bonding interconnect.

[0374] In some embodiments, the second external data interface is connected to the second packaging interface on the packaging substrate through the plurality of homogeneous memory components of the dual-port stack via the first memory component connected using through silicon vias (TSVs).

[0375] In some embodiments, wherein the first internal data interface and the second internal data interface are not coupled to the packaging substrate, wherein the first external data interface and the second external data interface are coupled to the packaging substrate, and wherein access to any one of the plurality of homogeneous memory components in the dual-port stack is performed through at least one of the first packaging interface or the second packaging interface, wherein the dual-port stack is operable to pass data from the first packaging interface to the second packaging interface through the first internal data interface and the second internal data interface, and wherein the dual-port stack is operable to pass data from the second packaging interface to the first packaging interface through the second internal data interface and the first internal data interface.

[0376] According to the eleventh aspect of the present disclosure, a memory module is provided, comprising: a module substrate; a first packaging substrate, arranged on a first side of the module substrate, wherein the first packaging substrate comprises a first packaging interface and a second packaging interface; a first memory component, arranged on the first packaging substrate, wherein the first memory component comprises: a first external data interface, the first external data interface is connected to the first packaging interface on the first packaging substrate; and a first internal data interface, the first internal data interface is connected to at least a second memory component; and a second memory component, the second memory component is stacked on the first memory component, wherein the second memory component comprises: a second external data interface, the second external data interface is connected to the second packaging interface on the first packaging substrate; and a second internal data interface, the second internal data interface is connected to at least the first memory component, and wherein the first memory component and the second memory component are isomorphic memory components.

[0377] In some embodiments, the second external data interface is connected to the second packaging interface on the first packaging substrate via wire bonding interconnects.

[0378] In some embodiments, the memory module also includes: a second packaging substrate, which is arranged on the second side of the module substrate, wherein the second packaging substrate includes a third packaging interface and a fourth packaging interface; a third memory component, which is arranged on the second packaging substrate, wherein the third memory component includes: a third external data interface, which is connected to the third packaging interface on the second packaging substrate; and a third internal data interface, which is connected to at least a fourth memory component; and the fourth memory component, which is stacked on the third memory component, wherein the fourth memory component includes: a fourth external data interface, which is connected to the fourth packaging interface on the second packaging substrate; and a fourth internal data interface, which is connected to at least the first memory component, and wherein the third memory component and the fourth memory component are isomorphic memory components.

[0379] In some embodiments, the second external data interface is connected to the second packaging interface on the first packaging substrate via a first wire bonding interconnect, and wherein the fourth external data interface is connected to the fourth packaging interface on the second packaging substrate via a second wire bonding interconnect.

[0380] In the above description, many details are set forth. However, it will be apparent to those of ordinary skill in the art who benefit from this disclosure that embodiments of the present invention may be implemented without these specific details. In some cases, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring the description.

[0381] Some portions of the detailed description are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the art of data processing to most effectively convey the substance of their work to those skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Typically, although not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. At times, it has proven convenient, primarily for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0382] It should be remembered, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless expressly stated otherwise, it is apparent from the above discussion that throughout the specification, discussions using terms such as "encrypt," "decrypt," "store," "provide," "derive," "obtain," "receive," "authenticate," "delete," "execute," "request," "communicate," etc. refer to the actions and processes of a computing system or similar electronic computing device that manipulates and transforms data represented as physical (e.g., electronic) quantities within the computing system's registers and memories into other data similarly represented as physical quantities within the computing system's memories or registers or other such information storage, transmission, or display devices.

[0383] The words "example" or "exemplary" are used herein to mean used as an example, instance or illustration. Any aspect or design described herein as "example" or "exemplary" is not necessarily to be interpreted as being preferred or advantageous over other aspects or designs. Of course, the use of the words "example" or "exemplary" is intended to present concepts in a specific way. As used in this disclosure, the term "or" is intended to represent an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, "X includes A or B" is intended to refer to any natural inclusive arrangement. That is, if X includes A; X includes B; or X includes A and B, then in any of the above cases "X includes A or B" is satisfied. In addition, the quantifiers "a" and "an" used in this disclosure and the appended claims should generally be interpreted as meaning "one or more", unless otherwise specified or clearly specified as a singular form from the context. In addition, the use of the terms "embodiment" or "one embodiment" or "implementation" or "one implementation" is not intended to refer to the same embodiment or implementation throughout the text unless so described.

[0384] The embodiments described herein may also relate to a device for performing the operations herein. The device may be specially constructed for the desired purpose, or may include a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a non-temporary computer-readable storage medium, such as but not limited to any type of disk including a floppy disk, an optical disk, a CD-ROM, and a magneto-optical disk, a read-only memory (ROM), a random access memory (RAM), an EPROM, an EEPROM, a magnetic or optical card, a flash memory, or any type of medium suitable for storing electronic instructions. The term "computer-readable storage medium" should be deemed to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) storing one or more sets of instructions. The term "computer-readable medium" should also be deemed to include any medium capable of storing, encoding, or carrying a set of instructions for machine execution, and causing the machine to execute any one or more methods of the existing embodiments. Therefore, the term "computer-readable storage medium" should be deemed to include, but not limited to, solid-state memory, optical media, magnetic media, any medium capable of storing a set of instructions for execution by a machine, and causing the machine to execute any one or more methods of the present embodiment.

[0385] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems can be used with programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the required method steps. The structures required for various these systems will appear from the following description. In addition, the present embodiment is not described with reference to any particular programming language. It should be understood that various programming languages ​​can be used to implement the teachings of the embodiments as described herein.

[0386] The above description proposes many specific details, such as examples of specific systems, components, methods, etc., in order to provide a good understanding of multiple embodiments of the present invention. However, it will be apparent to those skilled in the art that at least some embodiments of the present invention may be practiced without these specific details. In other cases, well-known components or methods will not be described in detail, or presented in a simple block diagram format, to avoid unnecessarily obscuring the present invention. Therefore, the specific details proposed above are merely exemplary. Specific implementations may vary according to these exemplary details and are still considered to be within the scope of the present invention.

[0387] The above description includes specific terms and reference numerals to provide a thorough understanding of the present invention. In some cases, terms and symbols may mean specific details that are not required for implementing the present invention. For example, any one of a specific number of bits, signal path width, signal transmission or operating frequency, component circuits or devices, etc. may be different from those described in the above-mentioned alternative embodiments. In addition, the interconnection between the circuit elements or circuit blocks shown or described as multi-conductor signal links may alternatively be single-conductor signal links, and the single-conductor signal links may alternatively be multi-conductor signal links. The signals and signal paths shown or described as single-ended may also be differential, and vice versa. Similarly, in alternative embodiments, the signals described or depicted as having a high-state effective or low-state effective logic level may have opposite logic levels. Metal oxide semiconductor (MOS) technology, bipolar technology, or any other technology that can implement logic and analog circuits can be used to implement component circuits in integrated circuit devices. With regard to terminology, when a signal is driven to a low or high logic state (or charged to a high logic state or discharged to a low logic state), the signal is referred to as "assertion" to indicate a specific condition. Conversely, a signal is said to be "deasserted" to indicate that the signal is driven (or charged or discharged) to a state other than the asserted state (including a high or low logic state, or a floating state that may occur when the signal driving circuit transitions to a high impedance condition, such as an open drain or open collector condition). When a signal driving circuit asserts (or deasserts if explicitly stated or indicated by context) a signal on a signal line between the signal driving circuit and the signal receiving circuit, the signal driving circuit is said to "output" the signal to the signal receiving circuit. When the signal is asserted on the signal line, the signal line is said to be "activated" and when the signal is deasserted, the signal line is "deactivated." In addition, a prefix symbol " / " appended to a signal name indicates that the signal is an active low signal (i.e., the asserted state is a logic low state). A line on a signal name (e.g., ) is also used to indicate an active low signal. The term "coupled" is used herein to express direct connection as well as connection through one or more intermediate circuits or structures. Integrated circuit device "programming" may include, for example, but not limited to, loading control values ​​into registers or other storage circuits within the device in response to host instructions, and thereby controlling the operating aspects of the device, establishing the device configuration or controlling the operating aspects of the device through a one-time programming operation (e.g., blowing fuses within the configuration circuit during device manufacturing), and / or connecting one or more selected pins or other contact structures of the device to a reference voltage line (referred to as strapping) to establish a specific device configuration or operating aspects of the device. The term "exemplary" is used to indicate an example, rather than a preference or requirement. Although the present invention has been described with reference to specific embodiments of the present invention, it will be apparent that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present invention. For example, the features or aspects of any embodiment may be applied in combination with any other embodiment, at least where practicable, or in place of corresponding features or aspects thereof. Therefore, the specification and drawings are to be regarded as illustrative rather than restrictive.

[0388] It should be understood that the above description is intended to be illustrative rather than restrictive. Upon reading and understanding the above description, many other embodiments will be apparent to those skilled in the art. Therefore, the scope of the present invention should be determined with reference to the appended claims and the full scope of equivalents to which these claims are assigned.

[0389] Although the present invention has been described with reference to specific embodiments thereof, it will be apparent that various modifications and variations may be made thereto without departing from the broader spirit and scope of the present invention. For example, the features or aspects of any embodiment may be applied in combination with any other embodiment, at least where practicable, or in place of corresponding features or aspects thereof. Accordingly, the description and drawings are to be regarded as illustrative rather than restrictive.

Claims

1. A dynamic random access memory (DRAM) component comprising: a collection of memory cells; a first data link set; a second data link set; a third data link set; a first receiver coupled to the first set of data links; a first transmitter coupled to the first set of data links; a second receiver coupled to the second set of data links; a second transmitter coupled to the second set of data links; a first multiplexer having an output coupled to the first transmitter; a second multiplexer having an output coupled to the second transmitter; a third multiplexer; a fourth multiplexer having an output coupled to an input of the first multiplexer and an input of the second multiplexer; a fifth multiplexer having an output coupled to the set of memory cells; as well as a sixth multiplexer having an output coupled to the third set of data links, wherein the first receiver is coupled to the input of the second multiplexer and to the input of the third multiplexer, wherein the second receiver is coupled to the input of the first multiplexer and to the input of the third multiplexer, wherein the output of the third multiplexer is coupled to the input of the fifth multiplexer and to the input of the sixth multiplexer, wherein the third set of data links is coupled to the input of the fifth multiplexer and to the input of the fourth multiplexer, and wherein the set of memory cells is coupled to the input of the fourth multiplexer and to the input of the sixth multiplexer.

2. The DRAM component of claim 1, wherein the third set of data lines is a set of through silicon via (TSV) links.

3. The DRAM component of claim 1 further comprising a set of command address (CA) links.

4. The DRAM component of claim 1, wherein the set of memory cells is organized into a plurality of memory bank groups.

5. A memory module, comprising: Printed circuit boards, including: a first set of data lines, a second set of data lines, and a third set of data lines; and a first set of pins and a second set of pins, the first set of pins being coupled to the first set of data lines and the second set of pins being coupled to the second set of data lines; a first dynamic random access memory (DRAM) component located at a first location on the printed circuit board, wherein the first DRAM component includes a first data interface coupled to the first set of data lines and a second data interface coupled to the third set of data lines; and A second DRAM component is located at a second location on the printed circuit board, wherein the second DRAM component includes a first data interface coupled to the third set of data lines and a second data interface coupled to the second data lines.

6. The memory module of claim 5, further comprising a register clock driver (RCD) component, and wherein the printed circuit board comprises: a first set of command and address (CA) lines and a second set of command and address (CA) lines; as well as A fourth set of pins is coupled to the first set of CA lines, wherein the second set of CA lines is coupled between the RCD and the first location and between the RCD and the second location.

7. A memory module according to claim 5, wherein the first DRAM component is part of a first DRAM stack at the first location and the second DRAM component is part of a second DRAM stack at the second location, wherein the first DRAM stack includes a main DRAM component and a plurality of auxiliary DRAM components, and wherein the second DRAM stack includes a main DRAM component and a plurality of auxiliary DRAM components.

8. The memory module according to claim 7, further comprising: a third DRAM stack located at a third location on the printed circuit board; as well as A fourth DRAM stack located at a fourth location on the printed circuit board, wherein the first DRAM stack, the second DRAM stack, the third DRAM stack and the fourth DRAM stack are connected in a chain between the first pin set and the second pin set, wherein the third DRAM stack includes a third DRAM component, the third DRAM component has a first data interface and a second data interface, the first data interface is coupled to a first subset of the third data line set, and the second data interface is coupled to a second subset of the third data line set, wherein the fourth DRAM stack includes a fourth DRAM component, the fourth DRAM component has a first data interface and a second data interface, the first data interface is coupled to a third subset of the third data line set, and the second data interface is coupled to a fourth subset of the third data line set.

9. The memory module of claim 8, further comprising a register clock driver (RCD) component, and wherein the printed circuit board comprises: a first set of command and address (CA) lines and a second set of command and address (CA) lines; as well as A fourth set of pins is coupled to the first set of CA lines, wherein the second set of CA lines is coupled between the RCD and the first location and between the RCD and the second location.

10. The memory module of claim 5, wherein the first DRAM component comprises: a collection of memory cells; a first data link set; a second data link set; a third data link set; a first receiver coupled to the first set of data links; a first transmitter coupled to the first set of data links; a second receiver coupled to the second set of data links; a second transmitter coupled to the second set of data links; a first multiplexer having an output coupled to the first transmitter; a second multiplexer having an output coupled to the second transmitter; a third multiplexer; a fourth multiplexer having an output coupled to an input of the first multiplexer and an input of the second multiplexer; a fifth multiplexer having an output coupled to the set of memory cells; as well as a sixth multiplexer having an output coupled to the third set of data links, wherein the first receiver is coupled to the input of the second multiplexer and to the input of the third multiplexer, wherein the second receiver is coupled to the input of the first multiplexer and to the input of the third multiplexer, wherein the output of the third multiplexer is coupled to the input of the fifth multiplexer and to the input of the sixth multiplexer, wherein the third set of data links is coupled to the input of the fifth multiplexer and to the input of the fourth multiplexer, wherein the set of memory cells is coupled to the input of the fourth multiplexer and to the input of the sixth multiplexer.

11. The memory module of claim 5, wherein the first data interface is arranged into a first nibble and the second data interface is arranged into a second nibble, the first nibble and the second nibble each comprising a corresponding timing link.

12. The memory module of claim 5, wherein during a write operation, the first data interface is configured to receive data and the second data interface is configured to retransmit the data.

13. The memory module of claim 5, wherein during a read operation, the second data interface is configured to receive data and the first data interface is configured to retransmit the data.

14. The memory module of claim 5, wherein the first DRAM component comprises: A set of memory cells is organized into a first memory bank group and a second memory bank group, wherein the first data interface is configured to access at least one of the first memory bank group or the second memory bank group.

15. A memory module, comprising: Module interface; At least two groups of stacked memory components, wherein each stack of memory components comprises two data interfaces connected using a point-to-point topology in a linear chain, wherein a first stack in a first group of the at least two groups of stacked memory components comprises: a first data interface coupled to the module interface; and a second data interface coupled to a second stack in a second group of the at least two groups of stacked memory components; and A command and address (CA) interface is connected on a shared bus, wherein a first access slot at the module interface of the first group is offset in time from a second access slot at the module interface of the second group.

16. The memory module of claim 15, wherein an offset between the first access slot and the second access slot is controlled by a memory controller coupled to the memory module as a pipeline of slot accesses.

17. The memory module of claim 16 , wherein the CA interface comprises a remanent clock driver (RCD) component coupled to the memory controller via a primary CA link, coupled to the first group using a first secondary CA link, and coupled to the second group using a second secondary CA link, wherein the RCD component is operable to receive a first command or a second command from the memory controller on the primary CA link, wherein the at least two groups of stacked memory components are programmed with a first delay in response to the first command and are programmed with a second delay in response to the second command, and wherein the first delay is less than the second delay.

18. The memory module of claim 16 , wherein the CA interface comprises a remanent clock driver (RCD) component coupled to the memory controller via a primary CA link, coupled to the first group using a first secondary CA link, and coupled to the second group using a second secondary CA link, wherein the RCD component is operable to receive a read command or a delayed read command from the memory controller on the primary CA link, wherein the at least two groups of stacked memory components are programmed with a first delay in response to the read command and are programmed with a second delay in response to the delayed read command, and wherein the first delay is less than the second delay.

19. A memory module according to claim 15, wherein the first group of the at least two groups of stacked memory components includes the first stack and the third stack, wherein the second group of the at least two groups of stacked memory components includes the second stack and the fourth stack, and wherein the third access slot at the module interface of the first group is offset in time from the fourth access slot at the module interface of the second group.

20. The memory module of claim 19, wherein: The second stack in the first group comprises: a first data interface coupled to the first stack in the first group; and a second data interface coupled to the third stack in the first group; and The third stack in the first group comprises: a first data interface coupled to the second stack in the second group; and A second data interface is coupled to the fourth stack in the second group.

21. A memory module according to claim 20, wherein first data from the first stack is passed to the module interface at the first access slot in a first cycle, wherein second data from the second stack is passed to the first stack in the first cycle, wherein third data from the third stack is passed to the second stack in the first cycle, and wherein fourth data from the fourth stack is passed to the third stack in the first cycle.

22. A memory module according to claim 21, wherein the second data is passed to the module interface at the second access slot in a second cycle, wherein the third data is passed from the second stack to the first stack in the second cycle, and wherein the fourth data is passed from the third stack to the second stack in the second cycle.

23. The memory module of claim 22, wherein the third data is transferred to the module interface at a third access slot in a third cycle, wherein the fourth data is transferred from the second stack to the first stack in the third cycle.

24. The memory module of claim 23, wherein the fourth data is transferred to the module interface at a fourth access slot in a fourth cycle.

25. The memory module of claim 15 , wherein the first of the at least two groups of stacked memory components includes only the first stack, wherein the second of the at least two groups of stacked memory components includes only the second stack, wherein the CA interface includes a register clock driver (RCD) component, the RCD component being coupled to a memory controller via a primary CA link, coupled to the first stack using a first secondary CA link, and coupled to the second stack using a second secondary CA link.

26. A memory module according to claim 25, wherein first data from the first stack is passed to the module interface at the first access slot in a first cycle, wherein second data from the second stack is passed to the first stack in the first cycle, and wherein the second data is passed to the module interface at the second access slot in a second cycle.

27. The memory module of claim 15, wherein the module interface is arranged into a first nibble, the first nibble comprising a corresponding timing link.

28. A memory module comprising: Printed circuit boards, including: a first set of data lines, a second set of data lines, and a third set of data lines; and a first set of pins and a second set of pins, the first set of pins being coupled to the first set of data lines; a first dynamic random access memory (DRAM) component stack located at a first site on the printed circuit board, wherein the first DRAM component stack includes a first data interface coupled to the first set of data lines and a second data interface coupled to the second set of data lines; a second DRAM component stack located at a second location on the printed circuit board, wherein the second DRAM component stack includes a first data interface coupled to the second set of data lines and a second data interface coupled to the third set of data lines; a third DRAM component stack located at a third site on the printed circuit board, wherein the third DRAM component stack includes a first data interface coupled to the third set of data lines and a second data interface coupled to the fourth set of data lines; and A fourth DRAM component stack is located at a fourth location on the printed circuit board, wherein the fourth DRAM component stack includes a first data interface coupled to the fourth set of data lines.

29. The memory module of claim 28, further comprising a register clock driver (RCD) component disposed on the printed circuit board, and wherein the printed circuit board comprises: a first set, a second set, and a third set of command and address (CA) line sets; as well as a third pin set, the third pin set being coupled to the first CA line set, wherein the first CA line set is coupled to the RCD component, wherein the second CA line set is coupled between the RCD component and the first location and between the RCD component and the third location, and wherein the third CA line set is coupled between the RCD component and the second location and between the RCD component and the fourth location.

30. The memory module of claim 28, wherein a first DRAM component of the first DRAM component stack comprises: a collection of memory cells; a first data link set; a second data link set; a third data link set; a first receiver coupled to the first set of data links; a first transmitter coupled to the first set of data links; a second receiver coupled to the second set of data links; a second transmitter coupled to the second set of data links; a first multiplexer having an output coupled to the first transmitter; a second multiplexer having an output coupled to the second transmitter; a third multiplexer; a fourth multiplexer having an output coupled to an input of the first multiplexer and an input of the second multiplexer; a fifth multiplexer having an output coupled to the set of memory cells; as well as a sixth multiplexer having an output coupled to the third set of data links, wherein the first receiver is coupled to the input of the second multiplexer and to the input of the third multiplexer, wherein the second receiver is coupled to the input of the first multiplexer and to the input of the third multiplexer, wherein the output of the third multiplexer is coupled to the input of the fifth multiplexer and to the input of the sixth multiplexer, wherein the third data link set is coupled to the input of the fifth multiplexer and to the input of the fourth multiplexer, wherein the set of memory cells is coupled to the input of the fourth multiplexer and to the input of the sixth multiplexer.

31. A system comprising: motherboard substrate; A memory controller is arranged on the motherboard substrate; a memory module disposed on the motherboard substrate and coupled to the memory controller; The memory module comprises: Module interface; At least two groups of stacked memory components, wherein each stacked memory component comprises two data interfaces connected using a point-to-point topology in a linear chain, wherein a first stack in a first group of the at least two groups of stacked memory components comprises: a first data interface coupled to the module interface; and a second data interface coupled to a second stack in a second group of the at least two groups of stacked memory components; and A command and address (CA) interface is connected on a shared bus, wherein a first access slot at said module interface of said first group is offset in time from a second access slot at said module interface of said second group.

32. The system of claim 31, wherein the memory controller is operable to control an offset between the first access slot and the second access slot as a pipeline of slot accesses.

33. The system of claim 31 , wherein the at least two groups of stacked memory components are programmed with a first delay in response to a first command from the memory controller and are programmed with a second delay in response to a second command from the memory controller, and wherein the first delay is less than the second delay.

34. The system of claim 31 , wherein the first stack of the first group is programmed with a first delay, and wherein the second stack of the second group is programmed with a second delay, wherein the first delay and the second delay are the same.

35. The system of claim 32, wherein the CA interface includes a register clock driver (RCD) component coupled to the memory controller via a primary CA link, coupled to the first group using a first secondary CA link, and coupled to the second group using a second secondary CA link.

36. A memory package comprising: A packaging substrate, comprising at least two data interfaces; as well as A memory component stack is stacked on the packaging substrate, wherein the memory components of the stack are homogeneous, wherein each of the memory components comprises: an external data interface connected to a subset of said memory components of said stack; as well as an internal data interface connected to all of the memory components of the stack, and The external data interfaces of at least two of the memory components are coupled to the at least two data interfaces on the packaging substrate.

37. The memory package of claim 36, wherein each of the memory components comprises a single set of primary and secondary interfaces that includes only the external data interface and the internal data interface.

38. The memory package of claim 36, wherein each of the memory components comprises boot logic for enabling a bypass path through the memory component stack.

39. The memory package of claim 36, wherein the memory component stack comprises: a top-most memory component, wherein the external data interface of the top-most memory component is coupled to a first data interface of the at least two data interfaces on the packaging substrate; as well as A bottom-most memory component is arranged closer to the packaging substrate than the top-most memory component, wherein the external data interface of the bottom-most memory component is coupled to a second data interface of the at least two data interfaces on the packaging substrate.

40. The memory package of claim 39, wherein access to any of the memory components in the stack is through at least one of the first data interface or the second data interface.

41. The memory package of claim 39, wherein the memory component stack is operable to transfer data from the first data interface to the second data interface through the internal data interface, and to transfer data from the second data interface to the first data interface through the internal data interface.

42. The memory package of claim 39, wherein the internal data interface is not coupled to the package substrate.

43. The memory package of claim 39, wherein the external interface of a first memory component of the memory component stack is coupled to the package substrate, and wherein the external interface of a second memory component of the memory component stack is not coupled to the package substrate.

44. An apparatus comprising: A packaging substrate, comprising at least two packaging interfaces; as well as A dual-port stack comprising a plurality of homogeneous memory components stacked on the packaging substrate, wherein: A first memory component of the plurality of homogeneous memory components comprises: a first external data interface connected to a first packaging interface of the at least two packaging interfaces on the packaging substrate; and a first internal data interface connected to all other memory components of the plurality of homogeneous memory components in the dual-port stack; and A second memory component of the plurality of homogeneous memory components comprises: a second external data interface connected to a second packaging interface of the at least two packaging interfaces on the packaging substrate; and A second internal data interface is provided, the second internal data interface being connected to all other memory components of the plurality of homogeneous memory components in the dual port stack.

45. The apparatus of claim 44, wherein: A third memory component of the plurality of homogeneous memory components comprises: a third external data interface, the third external data interface not connected to the at least two packaging interfaces on the packaging substrate; and a third internal data interface connected to all other memory components of the plurality of homogeneous memory components in the dual-port stack; and A fourth memory component of the plurality of homogeneous memory components comprises: a fourth external data interface, the fourth external data interface not connected to the at least two packaging interfaces on the packaging substrate; and A fourth internal data interface is connected to all other memory components of the plurality of homogeneous memory components in the dual port stack.

46. ​​The apparatus of claim 44, further comprising: a memory module substrate, wherein the packaging substrate is disposed on a first side of the memory module substrate; a second packaging substrate comprising at least two additional packaging interfaces, wherein the second packaging substrate is disposed on a second side of the memory module substrate; as well as a second dual-port stack comprising a second plurality of homogeneous memory components stacked on the second packaging substrate, wherein: A third memory component of the second plurality of homogeneous memory components comprises: a third external data interface connected to a third packaging interface of the at least two additional packaging interfaces on the second packaging substrate; and a third internal data interface connected to all other memory components of the second plurality of homogeneous memory components in the second dual-port stack; and A fourth memory component of the second plurality of homogeneous memory components comprises: a fourth external data interface connected to a fourth packaging interface of the at least two additional packaging interfaces on the second packaging substrate; and A fourth internal data interface connected to all other memory components of the second plurality of homogeneous memory components in the second dual-port stack.

47. The apparatus of claim 44, wherein the first memory component and the second memory component each include directing logic to enable a bypass path through the dual port stack.

48. A device according to claim 44, wherein the first memory component is located at a first side of the dual-port stack arranged on the first surface of the packaging substrate, and wherein the second memory component is located at a second side of the dual-port stack arranged farthest from the first surface of the packaging substrate.

49. The apparatus of claim 48, wherein the second external data interface is connected to the second packaging interface on the packaging substrate via a wire bonding interconnect.

50. The apparatus of claim 44, wherein the second external data interface is connected to the second packaging interface on the packaging substrate through the plurality of homogeneous memory components of the dual-port stack via the first memory component connected using through silicon vias (TSVs).

51. The apparatus of claim 44, wherein the first internal data interface and the second internal data interface are not coupled to the packaging substrate, wherein the first external data interface and the second external data interface are coupled to the packaging substrate, and wherein access to any one of the plurality of homogeneous memory components in the dual-port stack is performed through at least one of the first packaging interface or the second packaging interface, wherein the dual-port stack is operable to pass data from the first packaging interface to the second packaging interface through the first internal data interface and the second internal data interface, and wherein the dual-port stack is operable to pass data from the second packaging interface to the first packaging interface through the second internal data interface and the first internal data interface.

52. A memory module comprising: Module substrate; A first packaging substrate is arranged on a first side of the module substrate, wherein the first packaging substrate comprises a first packaging interface and a second packaging interface; A first memory component is arranged on the first packaging substrate, wherein the first memory component comprises: a first external data interface connected to the first packaging interface on the first packaging substrate; and a first internal data interface connected to at least a second memory component; and a second memory component, the second memory component being stacked on the first memory component, wherein the second memory component comprises: a second external data interface connected to the second packaging interface on the first packaging substrate; and A second internal data interface connected to at least the first memory component, and wherein the first memory component and the second memory component are homogeneous memory components.

53. The memory module of claim 52, wherein the second external data interface is connected to the second packaging interface on the first packaging substrate via a wire bonding interconnect.

54. The memory module of claim 52, further comprising: A second packaging substrate is arranged on the second side of the module substrate, wherein the second packaging substrate includes a third packaging interface and a fourth packaging interface; A third memory component is arranged on the second packaging substrate, wherein the third memory component comprises: a third external data interface, the third external data interface connected to the third packaging interface on the second packaging substrate; and a third internal data interface connected to at least a fourth memory component; and The fourth memory component is stacked on the third memory component, wherein the fourth memory component comprises: a fourth external data interface connected to the fourth packaging interface on the second packaging substrate; and A fourth internal data interface connected to at least the first memory component, and wherein the third memory component and the fourth memory component are homogeneous memory components.

55. A memory module according to claim 54, wherein the second external data interface is connected to the second packaging interface on the first packaging substrate via a first wire bonding interconnect, and wherein the fourth external data interface is connected to the fourth packaging interface on the second packaging substrate via a second wire bonding interconnect.

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