Computer system based on wafer stack architecture and memory test method

Abstract

The invention discloses a memory testing method, which is suitable for a computer system based on a wafer stacking framework. The computer system is a stereoscopic wafer product formed by a memory crystal layer, a logic circuit layer and a substrate. When a memory test is performed, a memory device in a memory crystal layer is divided into a plurality of memory sub-blocks. First, the same data table is established in at least two memory sub-blocks. Providing a plurality of different initial values prepared in advance, simultaneously performing proof-of-work operation on the at least two memory sub-blocks, and performing multiple times of read-write on the data tables of the at least two memory sub-blocks to generate a plurality of operation results corresponding to each initial value; the judgment module obtains a plurality of operation results from the operation module and compares the operation results with corresponding known solutions, so that the error rate of the sub-blocks of the tested memory can be counted.

Description

Technical Field

[0001] The present application relates to a method for testing a memory device, and more particularly to a method for testing a memory in a computer system implemented by wafer stacking technology. Background Art

[0002] In this era, the application of artificial intelligence and blockchain has become a new business opportunity. Blockchain can be widely used in smart contracts, digital identities, shared economy and other applications.

[0003] However, some blockchain platforms often change the blockchain algorithm for various security considerations or vulnerability fixes. In addition to increasing the difficulty of calculations, they often deliberately make special designs to reduce the computing efficiency of specific application chips, such as increasing the requirements for memory throughput or the capacity of storage devices.

[0004] Therefore, for blockchain server developers, they must also change the hardware architecture to adapt to the high standard requirements for memory throughput. Therefore, a new hardware architecture for blockchain servers needs to be developed. In addition, the memory control method and memory test method suitable for the new hardware architecture need to have corresponding improvement mechanisms. Summary of the invention

[0005] Traditional memory testing methods require a dedicated test module to be configured inside the chip in order to test the memory. In a computer system based on a wafer stacking architecture, testing all memory units may take a huge amount of time. Therefore, the present application embodiment proposes a computer system based on a wafer stacking architecture and a memory testing method thereof, which utilizes the native algorithm in the computer system with different initial values ​​and known solutions, and quickly determines the availability of the memory device based on the calculation results of the initial values ​​and the known solutions, thereby achieving the purpose of improving test efficiency.

[0006] In order to achieve the above-mentioned purpose, the present application proposes a memory testing method, which is applicable to a computer system based on a wafer stacking architecture. The so-called wafer stacking architecture is a wafer stack formed by a memory crystal layer, a logic circuit layer and a substrate using WoW (Wafer on Wafer) technology. The memory crystal layer includes at least one memory device. The logic circuit layer is connected to the at least one memory device through a plurality of connection pads, including firmware, a computing module connecting the firmware and the at least one memory device, and a judgment module connecting the computing module.

[0007] When performing a memory test, the at least one memory device is basically divided into a plurality of memory sub-blocks for testing. First, the same data table is established in at least two of the plurality of memory sub-blocks. Then, a plurality of different initial values ​​prepared in advance and a known solution corresponding to each initial value are provided. Each initial value is a value required by the computing module for performing a proof-of-work operation. The proof-of-work operation can read and write the data table of the at least two memory sub-blocks multiple times to generate a plurality of operation results corresponding to each initial value. After the judgment module obtains the plurality of operation results from the computing module and compares them with the corresponding known solutions, the error rate of the tested memory sub-block can be statistically calculated.

[0008] In a further embodiment, the judgment module compares the error rate of the memory sub-block with a critical value to determine whether the availability of the memory sub-block is available or unavailable. Afterwards, the judgment module records the number of the tested memory sub-block in the firmware according to the determination result of the availability.

[0009] In a specific embodiment, the workload proof operation can be an Ethereum hash algorithm (Ethash). The data table is a directed acyclic graph (DAG).

[0010] In order to completely test the memory cells in each memory sub-block, a directed acyclic graph having a size consistent with the memory sub-block may be generated in the memory sub-block through program-controlled configuration of the computing module.

[0011] In a further embodiment, the pre-prepared initial value and the corresponding known solution may be pre-stored in the firmware at the factory, or may be a value inputted from the outside. When testing, the judgment module obtains the known solution from the firmware or the outside, and compares it with the test result.

[0012] In order to achieve the above objectives, the present application also proposes an embodiment of the computer system based on the wafer stacking architecture.

[0013] In summary, the computer system and memory testing method proposed in the embodiments of the present application are suitable for computer systems with wafer stacking architecture. The native algorithm in the computing module is used with different initial values ​​and known solutions to execute the test program on more than two memory sub-blocks at the same time to determine the availability of the memory sub-blocks based on the computing results of the computing module. This method does not require the design of additional test logic in the computer system, effectively simplifies the complexity of the computer system, and by testing multiple memory sub-blocks at the same time, the test efficiency of the memory device is also exponentially improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0015] Figure 1 It is a schematic diagram of the three-dimensional wafer product architecture according to an embodiment of the present application.

[0016] Figure 2 It is a schematic diagram of a computer system architecture according to an embodiment of the present application.

[0017] Figure 3 It is a schematic diagram of the computing module architecture according to an embodiment of the present application.

[0018] Figure 4 is a flow chart of a memory testing method according to an embodiment of the present application.

[0019] Figure 5 is a flow chart of a memory sub-block testing method according to an embodiment of the present application. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0021] Figure 1 1 is a schematic diagram of a wafer stacking structure of a three-dimensional wafer product 100 according to an embodiment of the present application. The three-dimensional wafer product 100 is stacked layer by layer by at least one memory crystal layer 110, a logic circuit layer 120, and a substrate 130. A plurality of memory devices 112 are arranged in the memory crystal layer 110. The memory device 112 can be a memory module composed of memory particles, such as a dynamic random access memory (DRAM). The logic circuit layer 120 is a wafer layer in which a plurality of logic circuits 122 are arranged. A plurality of logic circuits 122 is a general term for various chip modules, such as, but not limited to, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), memory controllers or processors. In addition to providing basic support, the bottom substrate 130 also provides additional wiring space. A plurality of connection pads 102 or 104 are arranged between each layer to provide a signal channel. The three-dimensional wafer product 100 of this embodiment is a semi-finished product of a computer system 200, and after cutting, a plurality of independently operating computer systems 200 can be produced. Figure 1Although only one substrate 130 is shown, it is not limited to this in the physical design, and multiple substrates 130 may be arranged in parallel. In one embodiment, each computer system 200 may include a plurality of memory devices 112 and a plurality of logic circuits 122, and have the same three-dimensional wafer structure. In other words, the memory devices 112 and logic circuits 122 included in each computer system 200 are preliminarily arranged in the memory crystal layer 110 and the logic circuit layer 120, and then a three-dimensional structure is made in the form of wafer stacking. In the three-dimensional structure, the circuit wires between the chip groups do not need to occupy extra area, and the connection pads 102 and 104 can be directly used as the path for signal transmission, so that the performance problem of data transmission is effectively solved to realize the computer system 200 of the present application.

[0022] exist Figure 1 In the wafer stacking architecture, since the number of transmission lines is no longer limited by the planar design, a large number of dedicated wiring can be used to solve the performance problem of data transmission. The spacing between the memory crystal layer 110 and the logic circuit layer 120 becomes smaller, so more interfaces can be laid out in the same area. The bandwidth is obtained by multiplying the number of interfaces by the frequency formula of the channel, so more interfaces can get higher bandwidth. Thanks to wafer stacking technology, applications that require a large amount of memory access, such as machine learning, artificial intelligence or blockchain applications, can achieve exponential performance improvements.

[0023] Figure 2 The computer system 200 of the embodiment of the present application is composed of Figure 1 The computer system 200 may include one or more memory devices 210 cut from the memory crystal layer 110, and multiple chips cut from the logic circuit layer 120, such as firmware 202, computing module 204 and judgment module 206. The computing module 204 may include the function of a memory controller, through Figure 1 The plurality of connection pads 102 shown are connected to the memory device 210. For example, the memory device 210 may include a plurality of memory arrays (BANK), each memory array including a plurality of memory cells (not shown). Each memory cell is used to store a bit of data 0 or 1. Each row or column of memory cells may be connected to the computing module 204 through a corresponding plurality of connection pads 102. The internal circuit of the memory already has known standard specifications, so the detailed implementation will not be repeated.

[0024] Generally speaking, a common memory test method is to build the memory test logic into the chip. For example, when the computing module 204 receives a command to execute a test, it will automatically test the memory device. This method is called a built-in self-test module (Build-In-Self-Test; BIST). However, as the number of memory devices gradually increases, the time required to execute a complete BIST (including the time to execute the test and the time required to read the results) will also increase, and this has a huge impact on the wafer stacking architecture.

[0025] In the embodiment proposed in the present application, the memory block in the memory device 210 is first divided into a plurality of memory sub-blocks 212, and then the computing module 204 executes the native function of the computing module 204 on at least two memory sub-blocks 212 at the same time, so that the data error rate of all memory sub-blocks 212 can be quickly estimated. In this embodiment, the native function of the computing module 204 can be a proof-of-work algorithm. In this embodiment, if the data error rate of a memory sub-block 212 is greater than a critical value, the memory sub-block 212 is marked as an unavailable block. Conversely, if the data error rate of the memory sub-block 212 is less than the critical value, the memory sub-block 212 is marked as an available block. After the memory test is completed, the information of the available blocks can be stored in the firmware 202 to facilitate subsequent applications of the computer system 200.

[0026] Please refer to Figure 3 In this embodiment, the computing module 204 may further define a plurality of sub-computing modules 2041, and each sub-computing module 2041 may individually perform the native function of the computing module 204 on different memory sub-blocks 212 to quickly infer the data error rates of the plurality of memory sub-blocks 212. In one embodiment, the number of sub-computing modules 2041 may be the same as or different from the number of memory sub-blocks 212, and the present application is not limited thereto.

[0027] The above-mentioned proof-of-work algorithm is a block-solving algorithm based on a hash function. Input any initial value, and after the hash function, a corresponding result will be obtained. As long as the initial value changes by one bit, it will cause an avalanche effect, so it is almost impossible to reverse it. Therefore, by looking for calculation results with specified characteristics, allowing users to perform a large number of exhaustive calculations, proof of work can be achieved. Common proof-of-work algorithms include SHA-256, Ethash, Scrypt, Equihash, CryptoNode or algorithms based on Memory Hard Function. The following only takes Ethash as an example, and the detailed operation details of other algorithms will not be repeated.

[0028] Ethereum Hash (Ethash) is a proof-of-work algorithm modified from the Dagger-Hashimoto algorithm. The main principle is to increase the load on the memory by a large number of random table lookups to counteract the acceleration effect of the application-specific integrated chip ASIC. Ethash uses a data table with an initial value of 1GB and a pseudo-random number table (cache) with an initial value of 16MB. Every time an interval of 30,000 blocks is passed, the data table and pseudo-random number table will be recalculated. This interval of 30,000 blocks is called an epoch. The content generated by each epoch will increase, so 1GB and 16MB are just basic values. The computer system of the embodiment of the present application will store the entire data table and pseudo-random number table. When the computer system performs a proof-of-work operation on a block, it first fills a random number (nonce) into the block header, and continuously looks up the table in the form of SHA-3 to seek the mixed value MIX to calculate the solution of the block.

[0029] The data table used by the Ethereum hash algorithm during operation is called a directed acyclic graph (DAG). When the sub-operation module 2041 performs the proof-of-work algorithm, it will randomly read 64 data from the DAG, and each piece of data is 128 bytes. The sub-operation module 2041 will first randomly select an initial value, and then randomly read a piece of data from the DAG. After the sub-operation module 2041 combines the initial value with the piece of data read from the DAG, it can be converted into an intermediate product through the hash function SHA-3. Then, the sub-operation module 2041 randomly reads a piece of data from the DAG again, mixes it with the intermediate product and executes the next hash function SHA-3. After repeating this 64 times, the sub-operation module 2041 can obtain the proof of work of the corresponding memory sub-block 212.

[0030] The following will be matched Figure 2 and Figure 3The memory test method of the present application is described. In the present embodiment, when performing the memory test, the memory device 210 is basically divided into a plurality of memory sub-blocks 212, and each of the memory sub-blocks 212 is tested separately. First, the same data table is established in a plurality of memory sub-blocks 212, and the plurality of memory sub-blocks 212 are, for example, at least two memory sub-blocks 212. In one embodiment, the same data table can be established for all memory sub-blocks 212, and the present application is not limited thereto. Then, the plurality of sub-operation modules 2041 in the operation module 204 simultaneously execute the test program on the plurality of memory sub-blocks 212. That is, one sub-operation module 2041 executes the test program on one memory sub-block 212 with the data table established, and at the same time, the plurality of sub-operation modules 2041 individually execute the test program on the plurality of memory sub-blocks 212. The test program provides each sub-operation module 2041 with a plurality of different initial values ​​#N prepared in advance, and a known solution #A corresponding to each initial value #N. Each initial value #N is a value required by the sub-operation module 2041 for performing a proof-of-work operation. In one embodiment, the sub-operation module 2041 may also use an externally input hash value #H as an initial value. In each proof-of-work operation, the sub-operation module 2041 may read and write the data table in the memory sub-block 212 multiple times to generate a plurality of operation results corresponding to each initial value #N. After the judgment module 206 obtains the plurality of operation results from the sub-operation module 2041 and compares them with the corresponding known solution #A, it can count the error rate of the tested memory sub-block 212.

[0031] After the judgment module 206 calculates the error rate of the memory sub-block 212, it compares it with a critical value #T to determine whether the availability of the memory sub-block 212 is available or unavailable. Afterwards, the judgment module 206 records the number #R of the available or unavailable memory sub-block 212 in the firmware 202. For example, in some applications, the critical value #T only needs to be 80%. In more stringent applications, the critical value #T may require 99% or 99.999%.

[0032] In this embodiment, by establishing the same data table for the tested memory sub-blocks 212, the memory testing method of the present application can use only the initial value #N and the corresponding known solution #A corresponding to the data table to determine the availability of the tested memory sub-block 212, thereby effectively reducing the complexity of the memory testing method. At the same time, by testing a plurality of memory sub-blocks 212 at the same time, the overall test time of the memory device is further reduced, thereby achieving the purpose of improving the test efficiency.

[0033] The workload proof operation mentioned in this embodiment can be an Ethereum hash algorithm. The data table is the aforementioned directed acyclic graph DAG. In order to allow the memory cells in each memory sub-block 212 to be fully tested, a directed acyclic graph DAG with a size consistent with the memory sub-block 212 can be generated in the memory sub-block 212 through the program control configuration of the computing module 204.

[0034] Furthermore, the pre-prepared initial value #N and the corresponding known solution #A may be pre-stored in the firmware 202 at the factory, or values ​​inputted from the outside in real time.

[0035] In the embodiment of the computer system 200 of the present application, the initial size of the directed acyclic graph DAG may be 1 GB. However, the size of the directed acyclic graph DAG increases as the number of blocks on the blockchain increases. In other words, the size of the directed acyclic graph DAG is not always a fixed value, and can be increased or decreased as needed in actual applications.

[0036] Assuming that the total size of the memory device in the computer system 200 is 4GB, we can divide the memory device into 8192 memory sub-blocks 212, and each memory sub-block 212 has the same size of 512 kilobytes (KB). At the same time, the size of the directed acyclic graph DAG in the Ethash algorithm is also configured to be 512KB. In this way, running the Ethash algorithm once to obtain a proof of work step is equivalent to randomly reading 64*128bytes=8KB of data from a memory sub-block 212 of size 512KB. In a further approach, the segmentation size of each memory sub-block 212 can be flexibly adjusted. For example, if a memory sub-block 212 is found to have a high error rate after testing, it can be cut into smaller memory sub-blocks and tested separately to reduce the range of unusable sub-blocks and increase available capacity.

[0037] In this embodiment, multiple sets of initial values ​​of known results can be prepared in advance as test samples. When the sub-operation module 2041 of the operation module 204 uses a memory sub-block 212 to obtain an operation result, the operation result can be compared with the known result. If the two are the same, it means that the 8KB of data randomly read this time are all correct. In this embodiment, different initial values ​​can be reused to enable the sub-operation module 2041 to perform multiple operations on the same memory sub-block 212 to increase the number of memory cells accessed in the memory sub-block 212. It can be understood that since a directed acyclic graph DAG is stored in the memory sub-block 212, after multiple test operations are performed on the same memory sub-block 212 using more than a certain number of different initial values, it can be confirmed that all memory cells in the memory sub-block 212 are tested. Similarly, the above process can also be applied to 8192 areas in the memory device. After testing all available areas in the memory sub-block 212, the memory device can be used for subsequent calculations and applications.

[0038] Figure 4 The memory test method described in the embodiment of the present application includes steps S100 and S200. In step S100, a data table is established in at least two memory sub-blocks. In this step, the data table is a directed acyclic graph DAG, and the data tables in at least two memory sub-blocks 212 are the same. In one embodiment, the same data table can be established for all memory sub-blocks 212 in the memory device 210, and the present application is not limited to this. In step S200, the memory sub-blocks for which the data table is established are tested simultaneously. In this step, the plurality of sub-operation modules 2041 of the operation module 204 can simultaneously perform a test program on the memory sub-blocks 212 for which the data table has been established and the corresponding memory sub-blocks. That is, a plurality of memory sub-blocks 212 can execute the test program at the same time, so the test time of the memory device can be greatly reduced, thereby achieving the purpose of improving the test efficiency.

[0039] Furthermore, step S200 further includes steps S210 to S260, such as Figure 5 shown.

[0040] In step S210, the computer system 200 starts to perform a memory test. The sub-operation module 2041 tests one of the memory sub-blocks 212 in the memory device 210, and sequentially uses a plurality of different pre-prepared starting values ​​to perform a proof-of-work operation on the memory sub-block 212. In step S220, the result of each proof-of-work operation is compared with the corresponding known solution to determine whether the operation result is correct, and a plurality of correct and incorrect records of the operation results are stored. In step S230, it is determined whether the workload operation of all initial values ​​is completed. If so, step S240 is continued. If there are still unused initial values, step S210 is repeated.

[0041] In step S240, the data error rate of the memory sub-block 212 is calculated. Since the correct and error records of multiple operation results have been obtained in steps S210 to S230, the data error rate of the memory sub-block 212 can be counted. In step S250, the determination module 206 can mark the memory sub-block 212 as available or unavailable according to the data error rate.

[0042] In step S260, the determination module 206 stores the marking information of the memory sub-block 212 determined to be available or unavailable in the firmware. It is to be understood that the above steps are only exemplary, and the execution order can be reasonably adjusted. The memory test method can be performed when the computer system 200 is turned on, or when the computer system 200 is in an idle state. The memory test method can also be triggered only when the user requests it.

[0043] In summary, the embodiments of the present application provide a memory testing method and a computer system suitable for a wafer stacking architecture. By utilizing the native algorithm in the computing module 204 with different initial values ​​and known solutions, the availability of the memory device can be directly determined based on the computing results of the computing module 204, without the need to design additional test logic in the computer system 200. At the same time, the same data table is established for the tested memory sub-block 212. The memory testing method of the present application can only use the initial value #N and the corresponding known solution #A corresponding to the data table to determine the availability of the tested memory sub-block 212, effectively reducing the complexity of the memory testing method. In addition, the computer system of the present application is defined with multiple sub-computing modules 2041, so that multiple memory sub-blocks 212 can be tested at the same time, which greatly reduces the overall test time of the memory device and achieves the purpose of improving the test efficiency.

[0044] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0045] The embodiments of the present application are described above in conjunction with the drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, those skilled in the art to which the present invention belongs can make many forms without departing from the scope protected by the purpose of the present application and the scope of the patent application, all of which are protected by the present application.

Claims

1. A memory testing method, applied in a computer system; The computer system comprises at least one memory device, firmware, a computing module connected to the firmware and the at least one memory device, and a judgment module connected to the computing module; characterized in that: The memory testing method comprises: dividing the at least one memory device into a plurality of memory sub-blocks; Creating a same data table in at least two memory sub-blocks among the plurality of memory sub-blocks; and Performing a test procedure on the at least two memory sub-blocks simultaneously to determine availability of the at least two memory sub-blocks; The test procedure includes: Provide multiple different initial values ​​and the known solutions corresponding to each initial value; The computing module performs multiple proof-of-work operations on the memory sub-blocks, and each proof-of-work operation performs multiple reading and writing of the data table according to an initial value among multiple different initial values ​​to generate multiple computing results corresponding to each initial value; as well as The determination module obtains a plurality of the operation results from the operation module and compares the results with corresponding known solutions to calculate the error rate of the memory sub-block.

2. The memory testing method according to claim 1, wherein: Further including: The determination module compares the error rate of the memory sub-block with a critical value to determine the availability of the memory sub-block.

3. The memory testing method according to claim 2, wherein: Further including: The determination module records the serial number of the memory sub-block in the firmware according to the determination result of the availability.

4. The memory testing method according to claim 1, wherein: The proof-of-work operation is a block solving algorithm based on a hash function; and The data table is a directed acyclic graph.

5. The memory testing method according to claim 4, wherein: The size of the directed acyclic graph is consistent with the size of the memory sub-block; and The computer system is based on a wafer stacking architecture, and includes a memory crystal layer, a logic circuit layer and at least one substrate stacked into a three-dimensional structure.

6. A computer system based on a wafer stacking architecture, characterized in that: Include: at least one memory device; firmware; A computing module, connected to the firmware and the at least one memory device, to test the at least one memory device; as well as A judgment module is connected to the computing module; wherein: When the computing module divides the at least one memory device into a plurality of memory sub-blocks, when the computing module tests at least two of the plurality of memory sub-blocks, the same data table is established in the at least two memory sub-blocks, and a plurality of initial values ​​are sequentially used to perform a proof-of-work operation on the at least two memory sub-blocks, so that the data table in the at least two memory sub-blocks is read and written multiple times to generate a plurality of operation results corresponding to the plurality of initial values, wherein each initial value corresponds to a known solution; as well as The determination module obtains a plurality of the operation results from the operation module and compares the results with corresponding known solutions to calculate the error rates of the at least two memory sub-blocks.

7. The computer system based on wafer stacking architecture as claimed in claim 6, wherein: The operation module is defined with a plurality of sub-operation modules, and each sub-operation module sequentially uses the plurality of initial values ​​to perform the proof-of-work operation on a memory sub-block.

8. The computer system based on wafer stacking architecture as claimed in claim 6, wherein: The determination module compares the error rates of the at least two memory sub-blocks with a threshold value to determine the availability of the at least two memory sub-blocks.

9. The computer system based on wafer stacking architecture as claimed in claim 6, wherein: The proof-of-work operation is a block solving algorithm based on a hash function; and The data table is a directed acyclic graph.

10. The computer system based on wafer stacking architecture as claimed in claim 6, wherein: It further comprises a memory crystal layer, a logic circuit layer and at least one substrate stacked into a three-dimensional structure; wherein: The logic circuit layer is connected to the at least one memory device and the substrate through a plurality of connection pads; The firmware, the computing module, and the determination module are configured in the logic circuit layer; and The at least one memory device is disposed in the memory crystal layer.

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