Electronic device and method of manufacturing same

Abstract

An electronic device and a method of manufacturing the electronic device. In one example, an electronic device includes: a first substrate including a first dielectric structure and a first conductive structure; a first interconnect structure over an inward side of the first substrate and coupled with the first conductive structure; a first encapsulant over the inward side of the first substrate and contacting a lateral side of the first interconnect structure; a second substrate over the first encapsulant and including a second dielectric structure and a second conductive structure, where the second conductive structure is coupled with the first interconnect structure; and a first electronic component coupled to the outward side of the first substrate. The first electronic component is coupled with the second conductive structure via the first interconnect structure and the first conductive structure. Other examples and related methods are also disclosed herein.

Description

Technical Field

[0001] The present disclosure relates generally to electronic devices, and more particularly to electronic devices and methods of manufacturing electronic devices. Background Art

[0002] Existing electronic packages and methods of forming electronic packages are inadequate, for example resulting in excessive cost, reduced reliability, relatively low performance, or excessive package size. Other limitations and disadvantages of conventional and traditional methods will be apparent to those skilled in the art by comparing such methods with the present disclosure and referring to the drawings. Summary of the invention

[0003] One aspect of the present invention is an electronic device, comprising: a first substrate, which includes a first dielectric structure and a first conductive structure; a first interconnect structure, which is above the inner side of the first substrate and coupled to the first conductive structure; a first encapsulant, which is above the inner side of the first substrate and contacts the lateral side of the first interconnect structure; a second substrate, which is above the first encapsulant and includes a second dielectric structure and a second conductive structure, wherein the second conductive structure is coupled to the first interconnect structure; and a first electronic component, which is coupled to the outer side of the first substrate; wherein the first electronic component is coupled to the second conductive structure via the first interconnect structure and the first conductive structure.

[0004] The electronic device according to an aspect of the present invention comprises: a second encapsulant, which is above the outer side of the second substrate and covers the second conductive structure; wherein the second encapsulant comprises a first material and the second dielectric structure comprises a second material different from the first material.

[0005] In the electronic device according to an aspect of the present invention, the second conductive structure includes an antenna directional pattern.

[0006] In the electronic device according to an aspect of the present invention, the first interconnect structure includes: an interconnect encapsulant; and a metal interconnect confined by the interconnect encapsulant.

[0007] The electronic device according to an aspect of the present invention comprises: a second encapsulant coupled to the outward side of the first substrate and contacting a lateral side of the first electronic component.

[0008] The electronic device according to an aspect of the present invention includes a cover coupled to the outer side of the second enclosure.

[0009] The electronic device according to an aspect of the present invention comprises: a thermal interface material between the first electronic component and the cover; wherein: the first electronic component comprises a metal layer on the back side of the first electronic component; and the metal layer is coupled to the thermal interface material.

[0010] In the electronic device according to an aspect of the present invention, the first substrate includes a first redistribution layer substrate; and the second substrate includes a second redistribution layer substrate.

[0011] Another aspect of the present invention is an electronic device, comprising: a first substrate, which includes a first dielectric structure and a first conductive structure; a first interconnect structure, which is above the top side of the first substrate and coupled to the first conductive structure; a first encapsulant, which is above the first substrate and contacts the lateral side of the first interconnect structure; a second substrate, which is above the first encapsulant and includes a second dielectric structure and a second conductive structure, wherein the second conductive structure is coupled to the first interconnect structure; a first electronic component, which is above the top side of the second substrate and coupled to the second conductive structure; a second electronic component, which is coupled to the second conductive structure; and a second encapsulant, which is above the top side of the second substrate and contacts the lateral side of the first electronic component.

[0012] In an electronic device according to another aspect of the present invention, the second electronic component includes a decoupling capacitor.

[0013] In the electronic device according to another aspect of the present invention, the second electronic component is coupled to the bottom side of the second substrate; and the second electronic component is in the first package and at least partially within the footprint of the first electronic component.

[0014] In the electronic device according to another aspect of the present invention, the second electronic component is coupled to the top side of the second substrate; and the second electronic component is in the second package.

[0015] According to another aspect of the present invention, the electronic device comprises: a third electronic component coupled to the second conductive structure; wherein the second electronic component and the third electronic component are on opposite sides of the second substrate.

[0016] In the electronic device according to another aspect of the present invention, the first interconnect structure includes: an interconnect encapsulation; and a metal interconnection confined by the interconnect encapsulation.

[0017] In an electronic device according to another aspect of the present invention, the first substrate includes a first redistribution layer substrate; and the second substrate includes a second redistribution layer substrate.

[0018] Another aspect of the present invention is a method for manufacturing an electronic device, comprising: providing a first interconnect structure; providing a first encapsulant contacting a lateral side of the first interconnect structure; providing a first substrate coupled to a first side of the first encapsulant, wherein the first substrate includes a first dielectric structure and a first conductive structure, and wherein the first conductive structure is coupled to the first interconnect structure; providing a second substrate coupled to a second side of the first encapsulant, wherein the second substrate includes a second dielectric structure and a second conductive structure, and wherein the second conductive structure is coupled to the first interconnect structure; and providing a first electronic component coupled to the first substrate; wherein the first electronic component is coupled to the second conductive structure via the first interconnect structure and the first conductive structure.

[0019] According to another aspect of the present invention, the method includes: providing a second encapsulant coupled to the second substrate and covering the second conductive structure.

[0020] In the method according to another aspect of the present invention, the second conductive structure includes an antenna directional pattern.

[0021] In a method according to another aspect of the present invention, the first interconnect structure includes: an interconnect encapsulation; and a metal interconnection confined by the interconnect encapsulation.

[0022] According to yet another aspect of the invention, the method includes providing a second encapsulant coupled to the first substrate and contacting a lateral side of the first electronic component. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A cross-sectional view of an example electronic device is shown.

[0024] FIG. 2A to FIG. 2F A cross-sectional view illustrating an example method for manufacturing an example electronic device.

[0025] Figure 3 A cross-sectional view of an example electronic device is shown.

[0026] Figure 4 A cross-sectional view of an example electronic device is shown.

[0027] Figure 5 A cross-sectional view of an example electronic device is shown.

[0028] FIG. 6A to FIG. 6G A cross-sectional view illustrating an example method for manufacturing an example electronic device. DETAILED DESCRIPTION

[0029] The following discussion provides various examples of electronic devices and methods of making electronic devices. Such examples are non-limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "example" and "for example" are non-limiting.

[0030] Each figure illustrates a general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the present disclosure. In addition, the elements in the drawings are not necessarily drawn to scale. For example, the size of some elements in the various figures may be enlarged relative to other elements to help improve the understanding of the examples discussed in the present disclosure. The same reference numerals in different figures may represent the same elements.

[0031] The term "or" means any one or more of the items in the list connected by "or". As an example, "x or y" means any one of the three-element set {(x), (y), (x, y)}. As another example, "x, y or z" means any one of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}.

[0032] The terms "comprises / comprising" and "includes / including" are "open" terms and specify the presence of stated features but do not exclude the presence or addition of one or more other features. The terms "first," "second," etc. may be used herein to describe various elements, and these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, for example, a first element discussed in the present disclosure may be referred to as a second element without departing from the teachings of the present disclosure.

[0033] Unless otherwise specified, the term "coupled" may be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly coupled through one or more other elements. For example, if element A is coupled to element B, element A may be in direct contact with element B or indirectly coupled to element B through an intervening element C. Similarly, the terms "on" or "over" may be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly coupled through one or more other elements.

[0034] In one example, an electronic device includes: a first substrate including a first dielectric structure and a first conductive structure; a first interconnect structure over an inward side of the first substrate and coupled to the first conductive structure; a first encapsulant over an inward side of the first substrate and contacting a lateral side of the first interconnect structure; a second substrate over the first encapsulant and including a second dielectric structure and a second conductive structure, wherein the second conductive structure is coupled to the first interconnect structure; and a first electronic component coupled to an outward side of the first substrate. The first electronic component is coupled to the second conductive structure via the first interconnect structure and the first conductive structure.

[0035] In another example, an electronic device includes: a first substrate including a first dielectric structure and a first conductive structure; a first interconnect structure above the top side of the first substrate and coupled to the first conductive structure; a first encapsulant above the first substrate and contacting a lateral side of the first interconnect structure; a second substrate above the first encapsulant and including a second dielectric structure and a second conductive structure, wherein the second conductive structure is coupled to the first interconnect structure; a first electronic component above the top side of the second substrate and coupled to the second conductive structure; a second electronic component coupled to the second conductive structure; and a second encapsulant above the top side of the second substrate and contacting a lateral side of the first electronic component.

[0036] In another example, a method for manufacturing an electronic device includes: providing a first interconnect structure; providing a first encapsulant, the first encapsulant contacting a lateral side of the first interconnect structure; providing a first substrate, the first substrate coupled to a first side of the first encapsulant, wherein the first substrate includes a first dielectric structure and a first conductive structure, and wherein the first conductive structure is coupled to the first interconnect structure; providing a second substrate, the second substrate coupled to a second side of the first encapsulant, wherein the second substrate includes a second dielectric structure and a second conductive structure, and wherein the second conductive structure is coupled to the first interconnect structure; and providing a first electronic component, the first electronic component coupled to the first substrate. The first electronic component is coupled to the second conductive structure via the first interconnect structure and the first conductive structure.

[0037] Other examples are included in the present disclosure. Such examples can be found in the drawings, claims, or description of the present disclosure.

[0038] Figure 1 A cross-sectional view of an example electronic device 100 is shown. Figure 1 In the example shown in , the electronic device 100 may include substrates 110 and 160 , an electronic component 120 , an underfill 130 , an interconnect structure 140 , and encapsulants 150 and 170 .

[0039] Substrate 110 may include dielectric structure 111 and conductive structure 112. Conductive structure 112 may include inward terminal 112a and outward terminal 112b. Substrate 160 may include dielectric structure 161 and conductive structure 162. Conductive structure 162 may include inward terminal 162a and outward terminal 162b. In some examples, electronic device 100 may include a port or connector 180 coupled to conductive structure 111 of substrate 110. Connector 180 may be used to couple electronic device 100 to another electronic device, for example, via an interconnect, a cable, or a printed circuit board (PCB), which may include a flexible PCB in some examples. In some examples, connector 180 may be omitted.

[0040] The electronic component 120 may include a component interconnect 121. The interconnect structure 140 may include a metal interconnect 141 and an encapsulant 142. The interconnect structure 140 may be above the inner side of the substrate 110 and may be coupled with the conductive structure 112. The encapsulants 150 and 170 may include an encapsulant material. In some examples, the encapsulant 142 may be referred to as an interconnect encapsulant 142, and the metal interconnect 141 may be bounded by the interconnect encapsulant 142. The encapsulant 150 may be above the inner side of the substrate 110 and may contact or cover the lateral side of the interconnect structure 140. The substrate 160 may be above the encapsulant 150. The conductive structure 162 may be coupled with the interconnect structure 140. The electronic component 120 may be coupled with the outer side of the substrate 110. The electronic component 120 may be coupled with the conductive structure 162 via the interconnect structure 140 and the conductive structure 112. The encapsulant 170 may be over the outwardly facing side of the substrate 160 and may cover or protect the conductive structure 162 .

[0041] FIG. 2A to FIG. 2F A cross-sectional view of an example method for manufacturing an example electronic device 100 is shown. Figure 2A The electronic device 100 is shown in an early stage of manufacture. Figure 2A In the example shown in , the interconnect structure 140 may be disposed on one side of the carrier 10. In some examples, the interconnect structure 140 may include or be referred to as a copper pillar cube (CCC), a copper (Cu) pillar, a Cu pillar, a copper core solder ball (CCB), a solder ball, or a wire. For example, the interconnect structure 140 may be applied by electrolytic plating, electroless plating, sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or ball drop. In some examples, the interconnect structure 140 may be made of copper, gold, silver, palladium, or nickel.

[0042] When the interconnect structure 140 is a CCC, the interconnect structure 140 may include one or more metal interconnects 141 and an encapsulant 142 covering the sidewalls of such one or more metal interconnects 141. In some examples, the CCC may include one or more rows of metal interconnects 141. The metal interconnects 141 may pass between one outer side and another outer side of the encapsulant 142. One side of the metal interconnect 141 and one side of the encapsulant 142 may be coplanar, and the other side of the metal interconnect 141 and the other side of the encapsulant 142 may be coplanar. In some examples, the encapsulant 142 may include an epoxy molding compound, a resin, a filler-reinforced polymer, a B-stage pressing film, or a gel.

[0043] In some examples, the interconnect structure 140 may be picked up by a pick-and-place device and placed and glued to one side of the carrier 10. The side 140b of the interconnect structure 140 may be bonded to one side of the carrier 10. The interconnect structure 140 may be attached to the carrier 10 to have a plurality of rows or columns. By placing and bonding the CCCs, process efficiency may be enhanced, for example, compared to the case where the interconnect structure 140 is provided by plating or deposition. The height of the interconnect structure 140 may range from approximately 1 micrometer (μm) to approximately 300 μm.

[0044] The carrier 10 may be a substantially planar plate. In some examples, the carrier 10 may include or be referred to as a plate, a single plate, a wafer, a panel, or a strip. For example, the carrier 10 may be made of steel, stainless steel, aluminum, copper, ceramic, glass, or a wafer. In some examples, the thickness of the carrier 10 may range from approximately 300 μm to approximately 2000 μm, and the width of the carrier 10 may range from approximately 100 millimeters (mm) to approximately 300 mm. The carrier 10 is used to integrally handle the components in the process of providing the substrate 110, the interconnect structure 140, and the encapsulation 150.

[0045] The carrier 10 may include a temporary bonding layer disposed on one side. The interconnection structure 140 may be disposed on one side of the temporary bonding layer of the carrier 10 to be bonded and fixed. The temporary bonding layer may be formed on one side of the carrier 10 by coating methods such as spin coating, blade coating, casting, brushing, spraying, slit type extrusion coating, curtain coating, inclined plate coating or blade coating, printing methods such as screen printing, pad printing, gravure printing, elastic printing or lithography, inkjet printing methods, intermediate technologies between coating and printing, or by the direct attachment of adhesive film or adhesive tape. In some instances, the temporary bonding layer may be referred to as a temporary adhesive film, a temporary adhesive tape or a temporary adhesive coating. For example, the temporary bonding layer may be a thermal release tape or film or an optical release tape or film, and the bonding strength may be weakened or removed due to heat or light. In some instances, the temporary bonding layer may have an adhesive force weakened or removed due to physical or chemical external forces. The temporary bonding layer may allow the carrier 10 to be separated from the interconnect structure 140 and the encapsulant 150 before providing the substrate 160 .

[0046] Figure 2B The electronic device 100 is shown in a later stage of manufacturing. Figure 2B In the example shown in FIG. 1 , the encapsulant 150 may be provided to cover one side of the carrier 10 , the side 140 a of the interconnection structure 140 , or the sidewall of the interconnection structure 140 .

[0047] In some examples, the encapsulant 150 may include or be referred to as a body or a molding. For example, the encapsulant 150 may include an epoxy molding compound, a resin, a filler-reinforced polymer, a B-stage pressed film, or a gel. For example, the encapsulant 150 may be formed by compression molding, transfer molding, liquid body molding, vacuum lamination, paste printing, or film-assisted molding.

[0048] The side 150a of the encapsulant 150 may be removed to expose the side 140a of the interconnect structure 140. In some examples, the side 150a of the encapsulant 150 may be removed by grinding. In some examples, when the side 150a of the encapsulant 150 is removed, the side 140a of the interconnect structure 140 may also be removed. The side 150a of the encapsulant 150 may be coplanar or substantially coplanar with the side 140a of the interconnect structure 140. The thickness of the encapsulant 150 and the height of the interconnect structure 140 may be similar. The encapsulant 150 may contact a side of the carrier 10 and a sidewall of the interconnect structure 140. In some examples, the thickness of the encapsulant 150 and the interconnect structure 140 may range from approximately 10 μm to approximately 1200 μm.

[0049] Figure 2C The electronic device 100 is shown in a later stage of manufacturing. Figure 2CIn the example shown in FIG. 1 , the substrate 110 may be disposed on the side 150 a of the encapsulant 150 and the side 140 a of the interconnect structure 140 . The substrate 110 may include a dielectric structure 111 and a conductive structure 112 .

[0050] Inward terminal 112a may be disposed on side 150a of encapsulation 150 and side 140a of interconnection structure 140. Inward terminal 112a may be disposed to have a plurality of patterns on side 150a of encapsulation 150 and side 140a of interconnection structure 140. Inward terminal 112a may contact or electrically couple with side 140a of interconnection structure 140. Inward terminal 112a may include or be referred to as conductor, conductive material, pad, pad or under bump metal (UBM). In some examples, inward terminal 112a may include copper, gold, silver or nickel. In some examples, inward terminal 112a may be provided by plating. For example, after providing a metal seed layer to cover side 150a of encapsulation 150 and side 140a of interconnection structure 140 and providing a mask pattern to cover the outside of the seed layer, inward terminal 112a may be provided by plating to have a pattern by using the seed layer as a seed. For example, the mask pattern may use a photoresistor. The mask pattern may be removed after forming the inward terminal 112a. In some examples, the thickness of the inward terminal 112a may range from approximately 1 μm to approximately 20 μm.

[0051] The dielectric structure 111 may be disposed on the inward terminal 112a, the side 150a of the encapsulant 150, and the side 140a of the interconnection structure 140. The dielectric structure 111 may be provided to cover the side of the inward terminal 112a, the encapsulant 150, and the interconnection structure 140, and then an opening exposing the inward terminal 112a may be provided. For example, a mask pattern may be formed on the side of the dielectric structure 111, and then the exposed dielectric structure 111 may be removed by etching to form an opening. In some examples, the opening may include or be referred to as an orifice or hole. In some examples, the dielectric structure 111 may include or be referred to as a dielectric layer, a coreless layer, or a fillerless layer. For example, the dielectric structure 111 may include an electrically insulating material, such as polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), resin, or ajinomoto deposited film (ABF). In some examples, dielectric structure 111 can be formed by spin coating, spray coating, dip coating, or bar coating. In some examples, the thickness of dielectric structure 111 can range from approximately 5 μm to approximately 50 μm.

[0052] Conductive structure 112 may be disposed on one side of dielectric structure 111 and above inward terminal 112a. Conductive structure 112 may be configured to have a plurality of patterns that may be electrically coupled to inward terminal 112a. In some instances, conductive structure 112 may include or be referred to as a conductive layer, a trace, a pad, a TVS, a TGS, a via, a redistribution layer (RDL), a wiring pattern, or a circuit pattern. In some instances, conductive structure 112 may include copper, gold, silver, or nickel. In some instances, conductive structure 112 may have corresponding elements, features, materials, or manufacturing methods similar to inward terminal 112a described previously. Inward terminal 112a may be part of conductive structure 112.

[0053] The dielectric structure 111 may have one or more layers. When the dielectric structure 111 has a plurality of layers, the conductive structures 112 may be alternately stacked. The conductive structure 112 located on the outer side of the dielectric structure 112a may include or be referred to as an outward terminal 112b.

[0054] Although the completed substrate 110 is shown as including two layers of dielectric structure 111 and three layers of conductive structure 112, the number of layers for either structure may be less than or more than those stated. One or more layers or elements of conductive structure 112 may be interlaced with dielectric structure 111. Inward terminals 112a and outward terminals 112b may be disposed inside and outside of substrate 110 to be spaced apart from each other in row or column directions. In some examples, the overall thickness of substrate 110 may range from approximately 5 μm to approximately 50 μm.

[0055] In some examples, substrate 110 may be a redistribution layer ("RDL") substrate. The RDL substrate may include one or more conductive redistribution layers and one or more dielectric layers, and may (a) be formed layer by layer above an electronic device to which the RDL substrate is to be coupled, or (b) may be formed layer by layer above a carrier, and may be completely or at least partially removed after the electronic device and the RDL substrate are coupled together. The RDL substrate may be manufactured layer by layer as a wafer-level substrate on a circular wafer using a wafer-level process, or may be manufactured layer by layer as a panel-level substrate on a rectangular or square panel carrier using a panel-level process. The RDL substrate may be formed using an additive lamination process, and may include one or more dielectric layers alternately stacked with one or more conductive layers, and define corresponding conductive redistribution patterns or traces, which are configured to collectively (a) fan the electrical traces out of the footprint of the electronic device, or (b) fan the electrical traces into the footprint of the electronic device. The conductive pattern may be formed using a plating process such as an electroplating process or an electroless plating process. The conductive pattern may include a conductive material such as copper or other plateable metal. The location of the conductive pattern may be produced using a photopatterning process such as a photolithography process and a photoresist material for forming a photolithography mask. The dielectric layer of the RDL substrate may be patterned using a photopatterning process and may include a photolithography mask through which light is exposed to photopattern desired features such as through holes in the dielectric layer. The dielectric layer may be made of a photodefinable organic dielectric material such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). Such dielectric materials may be spin-coated or otherwise applied in liquid form rather than attached in the form of a preformed film. In order to permit the desired photodefinable features to be properly formed, such photodefinable dielectric materials may omit structural reinforcements, or may be filler-free, without strands, woven fabrics, or other particles, and may interfere with light from the photopatterning process. In some examples, such filler-free properties of filler-free dielectric materials may result in a reduced thickness of the resulting dielectric layer. Although the photo-definable dielectric material described above may be an organic material, in some instances, the dielectric material of the RDL substrate may include one or more inorganic dielectric layers. Some examples of one or more inorganic dielectric layers may include silicon nitride (Si3N4), silicon oxide (SiO2), or silicon oxynitride (SiON). One or more inorganic dielectric layers may be formed not by using a photo-definable organic dielectric material but by growing an inorganic dielectric layer using an oxidation or nitridation process. Such inorganic dielectric layers may be filler-free without strands, woven fabrics, or other different inorganic particles. In some instances, the RDL substrate may omit a permanent core structure or carrier, such as a dielectric material including bismaleimide triazine (BT) or FR4, and these types of RDL substrates may include or be referred to as coreless substrates. Other substrates in the present disclosure may also include an RDL substrate.

[0056] In some examples, substrate 110 may be a preformed substrate. The preformed substrate may be manufactured before being attached to an electronic device, and may include a dielectric layer between corresponding conductive layers. The conductive layer may include copper and may be formed using an electroplating process. The dielectric layer may be a relatively thick non-photodefinable layer that may be attached in the form of a preformed film rather than in the form of a liquid, and may include a resin having fillers such as strands, woven fabrics or other inorganic particles for rigidity or structural support. Since the dielectric layer is non-photodefinable, features such as through holes or openings may be formed by using drilling or lasers. In some examples, the dielectric layer may include a prepreg material or an Ajinomoto stacked film (ABF). The preformed substrate may include a permanent core structure or carrier, such as a dielectric material including bismaleimide triazine (BT) or FR4, and the dielectric layer and the conductive layer may be formed on the permanent core structure. In other examples, the preformed substrate may be a coreless substrate omitting a permanent core structure, and the dielectric layer and the conductive layer may be formed on a sacrificial carrier that is removed after the dielectric layer and the conductive layer are formed and before being attached to an electronic device. The preformed substrate may be referred to as a printed circuit board (PCB) or a laminated substrate. Such a preformed substrate may be formed by a semi-additive process or a modified semi-additive process. Other substrates in the present disclosure may also include a preformed substrate.

[0057] Figure 2D The electronic device 100 is shown in a later stage of manufacturing. Figure 2D In the example shown in , the substrate 160 may be disposed on the side 150 b of the encapsulant 150 and the side 140 b of the interconnect structure 140 .

[0058] Before providing the substrate 160, the carrier 10 may be separated from the side 150b of the encapsulant 150 and the side 140b of the interconnection structure 140. In some examples, after providing heat, light, a chemical solution, or a physical external force to remove or reduce the adhesive force of the temporary bonding layer inserted between the carrier 10 and the encapsulant 150 and between the carrier 10 and the interconnection structure 140, the carrier 10 may be separated from the side 150b of the encapsulant 150 and the side 140b of the interconnection structure 140. The temporary bonding layer of the carrier 10 may be separated from the encapsulant 150 and the interconnection structure 140 in a state in which the temporary bonding layer is attached to the carrier 10. The carrier 10 may be removed, and the side 150b of the encapsulant 150 and the side 140b of the interconnection structure 140 may be exposed.

[0059] Figure 2D The electronic device 100 shown in FIG. Figure 2C, and the substrate 110 may be positioned below the encapsulant 150 and the interconnect structure 140. The electronic device 100 may be flipped so that the sides 150a and 150b of the encapsulant 150 become inverted relative to each other, and the sides 140a and 140b of the interconnect structure 140 similarly become inverted relative to each other.

[0060] Substrate 160 may include dielectric structure 161 and conductive structure 162. Conductive structure 162 may include inward terminal 162a and outward terminal 162b. In some examples, substrate 160 may include an RDL substrate. In other examples, substrate 160 may include a preformed substrate.

[0061] The inward terminal 162a may be disposed on the side 150b of the encapsulant 150 and the side 140b of the interconnect structure 140. The inward terminal 162a may be disposed to have a pattern on the side 150b of the encapsulant 150 and the side 140b of the interconnect structure 140. The inward terminal 162a may have corresponding elements, features, materials, or manufacturing methods similar to those of the inward terminal 112a.

[0062] The dielectric structure 161 may be disposed on the inward terminals 162a, the side 150b of the encapsulant 150, and the side 140b of the interconnect structure 140. The dielectric structure 161 may have corresponding elements, features, materials, or manufacturing methods similar to the dielectric structure 161.

[0063] A conductive structure 162 may be provided to cover the outside of the dielectric structure 161 and the inward terminal 162a. The conductive structure 162 may be configured to have a plurality of patterns, wherein the pattern may be electrically coupled to the interconnect structure 140 through the inward terminal 162a. In a certain example, the conductive structure 162 may have corresponding elements, features, materials, or manufacturing methods similar to the inward terminal 162a described above. The conductive structure 162 located on the outside of the dielectric structure 161 may include an outward terminal 162b. The outward terminal 162b of the conductive structure 162 may include or be referred to as an antenna directional pattern. In some examples, the antenna directional pattern 162b may include or be referred to as a dipole antenna, a monopole antenna, a patch antenna, a loop antenna, a beam antenna, a dual antenna, a folded antenna, a diamond antenna, or a half-wave antenna. Since the antenna directional pattern 162b is provided by RDL, fine size adjustment can be achieved and distance control between the antenna directional patterns 162b can be achieved.

[0064] Although the completed substrate 160 is shown as including a single layer of dielectric structure 161 and two layers of conductive structure 162, the number of layers of either structure may be less than or greater than those stated. One or more layers or elements of conductive structure 162 may be interlaced with dielectric structure 161. Inward terminals 162a and outward terminals 162b may be disposed inside and outside of substrate 160 to be spaced apart from each other in row or column directions. In some examples, the overall thickness of substrate 160 may range from approximately 5 μm to approximately 50 μm.

[0065] Figure 2E The electronic device 100 is shown in a later stage of manufacturing. Figure 2E In the example shown in , an encapsulant 170 may be provided to cover the outside of the substrate 160. An encapsulant 170 may be provided to cover the dielectric structure 161 and the outward terminal 162b of the substrate 160. Encapsulant 170 may have corresponding elements, features, materials, or manufacturing methods similar to encapsulant 150. In some examples, encapsulant 170 may include a first material, and dielectric structure 161 may include a second material different from the first material. Encapsulant 170 may protect the external terminal 162b from the external environment. In some examples, the thickness of encapsulant 170 may range from approximately 5μm to approximately 15μm.

[0066] Figure 2F The electronic device 100 is shown in a later stage of manufacturing. Figure 2F In the example shown in , the electronic component 120 may be disposed outside the substrate 110. The electronic component 120 may contact and electrically couple with the outward terminal 112b of the substrate 110. In some examples, one side of the electronic component 120 may include or be referred to as an inactive side, and the opposite side of the electronic component 120 may include or be referred to as an active side. The electronic component 120 may include a component interconnect 121 on the active side of the electronic component 120. The component interconnect 121 may be disposed on the active side of the electronic component 120 so as to be spaced apart from each other in the row or column direction. The component interconnect 121 may include or be referred to as a bump, a pad, or a pillar. The component interconnect 121 may be an input / output terminal of the electronic component 120. In some examples, the component interconnect 121 may be applied on the active side of the electronic component 120 by electroplating, electroless plating, sputtering, PVD, CVD, MOCVD, ALD, LPCVD, or PECVD. For example, after providing a photoresist pattern that exposes the bonding pads of the electronic component 120, the component interconnect 121 may be provided to contact the exposed bonding pads. In some examples, the thickness of the component interconnect 121 may range from approximately 1 μm to approximately 35 μm, and the width and spacing may range from approximately 10 μm to approximately 50 μm.

[0067] In some examples, the pick-and-place equipment may pick up the electronic component 120 or the connector 180 and place it outside the substrate 110. In such examples, the substrate 110 of the electronic device 100 may be located on the side 150a of the encapsulation 150. The component interconnect 121 of the electronic component 120 may be located on the outside of the outward terminal 112b of the first board 110. Subsequently, the component interconnect 121 of the electronic component 120 may be contacted and bonded to the outward terminal 112b by a reflow or thermal compression bonding process. In some examples, the electronic component 120 may include or be referred to as a bare die, a chip, or a package. Similarly, the connector 180 may be coupled to the conductive structure 112. The electronic component 120 or the connector 180 may be electrically coupled to the antenna directional pattern 162b of the substrate 160 through the conductive structure 112 of the substrate 110 and the interconnect structure 140.

[0068] The bottom filler 130 may be positioned between the electronic component 120 and the substrate 110. The bottom filler 130 may contact the active side of the electronic component 120 and the outer side of the substrate 110. The bottom filler 130 may contact the component interconnect 121 of the electronic component 120. The bottom filler 130 may include or be referred to as a dielectric layer or a non-conductive paste, and may not contain an inorganic filler. In some examples, the bottom filler 130 may include or be referred to as a capillary bottom filler (CUF), a non-conductive paste (NCP), a non-conductive film (NCF), an anisotropic conductive film (ACF) or an anisotropic conductive paste (ACP). In some examples, when the bottom filler 130 includes a molded bottom filler (MUF), the electronic component 120 may be covered by an encapsulant, and the bottom filler 130 may be considered as a part of the encapsulant. In some examples, the bottom filler 130 may be cured after being positioned between the electronic component 120 and the substrate 110. In some examples, after providing underfill 130 to cover the inside of substrate 110, component interconnects 121 of electronic component 120 may pass through underfill 130 and be coupled with outward terminals 112b. Underfill 130 may prevent electronic component 120 from being separated from substrate 110 due to physical or chemical influences.

[0069] Although the electronic component 120 is shown as having a face-down or flip chip configuration, the electronic component 120 may have a face-up or wire bonding configuration. For example, the electronic component 120 may include an inactive side on one side and may include an active side on the opposite side. The electronic component 120 may be bonded to the substrate 110. In the electronic component 120, the component terminals may be located at the active side. The component terminals of the electronic component 120 may be electrically coupled to the outward terminals 112b of the substrate 110 through component interconnects 121. The component interconnects 121 may include or be referred to as conductive wires. For example, the conductive wires may be bonded to the outward terminals 112b of the substrate 110 by using gold wires, copper wires, or aluminum wires through wire bonding equipment. In some examples, the overall thickness of the electronic component 120 may range from approximately 20 μm to approximately 50 μm, and the area may range from approximately 0.5 millimeters (mm)×0.5 mm to approximately 70 mm×70 mm.

[0070] In some examples, a singulation process for separating into individual electronic components 100 by sawing substrates 110 and 160 and encapsulants 150 and 170 may be performed. Electronic device 100 may include substrates 110 and 160, electronic component 120, bottom filler 130, interconnect structure 140, and encapsulants 150 and 170. Since electronic device 100 may be provided by RDL in substrate 160, fine size adjustment may be achieved and distance control between patterns may be facilitated. By including encapsulant 170, electronic device 100 may protect antenna directional pattern 162b from external environment.

[0071] Figure 3 A cross-sectional view of an example electronic device 200 is shown. Figure 3 In the example shown, the electronic device 200 may include a substrate 110 , a substrate 160 , an electronic component 120 , an underfill 130 , an interconnect structure 140 , an encapsulant 150 , an encapsulant 170 , and an encapsulant 280 .

[0072] The electronic device 200 may be similar to the electronic device 100. For example, with respect to the substrate 110, the substrate 160, the electronic component 120, the underfill 130, the interconnect structure 140, the encapsulant 150, and the encapsulant 170, the electronic device 200 may be similar to the electronic device 100. Figure 4 The electronic device 200 may include an encapsulant 280. The encapsulant 280 may be coupled with an outer side of the substrate 110 and may contact a lateral side of the electronic component 120.

[0073] Encapsulant 280 may be provided to cover the outside of electronic component 120, the lateral sides of electronic component 120, bottom fill 130, or substrate 110. Encapsulant 280 may contact the outside of substrate 110, the sidewalls and inactive sides of electronic component 120, and the sidewalls of bottom fill 130. Encapsulant 280 may protect electronic component 120 from external elements. Encapsulant 280 may have corresponding elements, features, materials, or manufacturing methods similar to encapsulant 150. In some examples, the outside of encapsulant 280 may be removed to expose the inactive side of electronic component 120. In some examples, the thickness of encapsulant 280 may range from approximately 100 μm to approximately 1200 μm.

[0074] In some examples, electronic device 200 may include a port or connector 180 coupled to conductive structure 112 of substrate 110. Connector 180 may be used to couple electronic device 200 to another electronic device, for example, via an interconnect, a cable, or a printed circuit board (PCB), which in some examples may include a flexible PCB. Figure 3 In the example shown in , the encapsulant 280 does not cover the portion of the substrate 110 where the connector 180 is coupled to the substrate 110 and is not covered by the encapsulant 280. In some examples, the connector 180 may be omitted. In such examples, the encapsulant 280 may extend to the lateral sides of the substrate 110.

[0075] Figure 4 A cross-sectional view of an example electronic device 300 is shown. Figure 4 In the example shown in , the electronic device 300 may include a substrate 110 , a substrate 160 , an electronic component 120 , an underfill 130 , an interconnect structure 140 , an encapsulant 150 , an encapsulant 170 , an encapsulant 380 , and a cover 390 .

[0076] The electronic device 300 may be similar to the electronic device 100. For example, the electronic device 300 may be similar to the electronic device 100 with respect to the substrate 110, the substrate 160, the electronic component 120, the underfill 130, the interconnect structure 140, the encapsulant 150, and the encapsulant 170. The electronic device 300 may include an encapsulant 380 and a cover 390. In some examples, the cover 390 may be coupled to the outer side of the encapsulant 380.

[0077] Encapsulant 380 may be provided to cover the exterior of electronic component 120, bottom fill 130, and substrate 110. Encapsulant 380 may contact the exterior of substrate 110, the sidewalls of electronic component 120, and the sidewalls of bottom fill 130. The exterior of encapsulant 380 may be removed to expose the inactive side of electronic component 120. Encapsulant 380 may protect electronic component 120 from external elements. Encapsulant 380 may have corresponding elements, features, materials, or manufacturing methods similar to encapsulant 150. In some examples, the thickness of encapsulant 380 may range from approximately 100 μm to approximately 1200 μm.

[0078] The cover 390 may be an approximately rectangular plate. The cover 390 may be made of a metal having high thermal conductivity and high radiation. In some examples, the cover 390 may include aluminum or copper. In some examples, the cover 390 may include or be referred to as a shield, a heat sink, a heat sink or a cover. In some examples, the cover 390 may easily release the heat generated from the electronic component 120 and prevent the inflow of electromagnetic waves. In some examples, a thermal interface material (TIM) 391 may be inserted between the inside of the cover 390 and the non-active side of the electronic component 120. TIM 391 may include a thermally conductive material, such as a metal material such as solder or solder paste. Examples of such thermal interface materials include metal alloy materials, such as gallium, gallium alloys (e.g., alloys with indium, tin and zinc), silver alloys, tin-silver, indium and indium alloys. The thermal interface material 391 may more easily deliver the heat generated from the electronic component 120 to the cover 390. In some examples, the electronic component 120 may include a metal layer 129 in contact with the non-active side. Metal layer 329 may be interposed between the inactive side of electronic component 120 and TIM 391. In some examples, metal layer 329 may be coupled with TIM 329. Metal layer 329 may include or be referred to as a backside metallization (BSM) plating, a conductive film, or a conductive film. For example, metal layer 329 may be disposed on the inactive side of electronic component 120 by electroplating, electroless plating, sputtering, or PVD. In some examples, metal layer 329 may be made of gold (Au) or silver (Ag). In some examples, the thickness of metal layer 329 may range from approximately 0.3 μm to approximately 3 μm.

[0079] In some examples, electronic device 300 may include a port or connector 180 coupled to conductive structure 112 of substrate 110. Connector 180 may be used to couple electronic device 300 to another electronic device, for example, via an interconnect, a cable, or a printed circuit board (PCB), which may include a flexible PCB in some examples. Figure 4In the example shown in FIG. 1 , the encapsulant 380, the cover 390, and the TIM 391 do not cover the portion of the substrate 110 where the connector 180 is coupled to the substrate 110 and is not covered by the encapsulant 380, the cover 390, and the TIM 391. In some examples, the connector 180 may be omitted. In such examples, the encapsulant 380, the cover 390, and the TIM 391 may extend to the lateral sides of the substrate 110.

[0080] Figure 5 A cross-sectional view of an example electronic device 400 is shown. Figure 5 In the example shown in , electronic device 400 may include substrate 410 , substrate 460 , electronic component 420 , electronic component 420 a , electronic component 420 b , underfill 430 , interconnect structure 140 , encapsulant 150 , encapsulant 470 , and external interconnect 480 .

[0081] Electronic device 400 may be similar to electronic device 100. For example, electronic device 400 may be similar to electronic device 100 with respect to interconnect structure 140 and encapsulant 150. Electronic device 400 may include substrate 410, substrate 460, electronic component 420, electronic component 420a, electronic component 420b, underfill 430, encapsulant 470, and external interconnect 480. Although electronic device 400 is shown in one particular orientation with substrate 410 oriented or facing the top, there may be instances where electronic device 400 may be oriented or mounted in another orientation with substrate 410 oriented or facing the bottom.

[0082] Substrate 410 may include dielectric structure 411 and conductive structure 412. Conductive structure 412 may include inward terminal 412a, outward terminal 412c, or antenna directional pattern 412b. Substrate 460 may include dielectric structure 461 and conductive structure 462. Conductive structure 462 may include inward terminal 462a and outward terminal 462b. Electronic component 420, electronic component 420a, and electronic component 420b may include component interconnect 421, component interconnect 421a, and component interconnect 421b. Electronic component 420 may be at the outward side of substrate 460 and may be coupled with conductive structure 462. One or more interconnect structures 140 may be between the inward side of substrate 410 and the inward side of substrate 460 and may be coupled with conductive structure 412 and conductive structure 462. Encapsulant 150 may contact the lateral side of interconnect structure 140. In some examples, electronic component 420a may be coupled with conductive structure 462 of substrate 460. Encapsulant 470 may be above the outward side of substrate 460 and may contact the lateral side of electronic component 420. Electronic component 420a may be coupled to the outward side of substrate 460 and may be in encapsulant 470. One or more interconnect structures 140 may be coupled to conductive structure 462 at the outward side of substrate 460. One or more of such interconnect structures 140 may extend to couple with external interconnect 480 or with TIM 391 or lid 390. In some examples, electronic component 420b may be coupled to the inward side of substrate 460 and may be in encapsulant 150. In some examples, electronic component 420b may be coupled to conductive structure 462. In some examples, electronic component 420b may be at least partially or completely within the footprint of electronic component 420 or the footprint of adjacent electronic component 420. In some examples, electronic component 420a and electronic component 420b may be on opposite sides of substrate 460.

[0083] In some examples, the encapsulant 170 may be over the outward side of the substrate 410 or may at least partially cover the lateral sides of the external interconnect 480. In some examples, the external interconnect 480 at one side of the electronic device 400, such as on or adjacent to the substrate 410, may be omitted. In some examples, the external interconnect 480 at the opposite side of the electronic device 400, such as on or adjacent to the encapsulant 470, may be omitted. In some examples, the cover 390 or TIM 391 may extend to cover the entire outward side of the encapsulant 470, or may extend from a lateral edge, such as the left edge, of the encapsulant 470 to an opposite lateral edge, such as the right edge, to provide heat dissipation, such as via the TIM 391, or to provide electromagnetic shielding through the cover 390. In some examples, the cover 390 may optionally be coupled with the metal interconnects 141 of one or more interconnect structures 140, such as for shielding. In some examples, the TIM 391 may be omitted, and in some examples, the cover 390 may be omitted.

[0084] In some examples, electronic device 400 may include a port or connector 180 coupled to conductive structure 112 of substrate 110. Connector 180 may be used to couple electronic device 400 to another electronic device, for example, via an interconnect, a cable, or a printed circuit board (PCB), which may include a flexible PCB in some examples. Figure 5 , the encapsulant 470, the cover 390, and the TIM 391 do not cover the portion of the substrate 460 adjacent to where the connector 180 is coupled, so that the connector 180 or the adjacent portion of the substrate 460 remains uncovered by the encapsulant 470, the cover 390, and the TIM 391. In some examples, the connector 180 may be omitted. In such examples, the encapsulant 470 may extend to the lateral sides of the substrate 460.

[0085] FIG. 6A to FIG. 6G A cross-sectional view illustrating an example method for manufacturing an example electronic device. Fig. 6A The electronic device 400 is shown in an early stage of manufacture. Fig. 6A In the example shown in FIG. 1 , the interconnection structure 140 and the electronic component 420 b may be disposed on the carrier 10. The carrier 10 and the interconnection structure 140 may have a similar structure to that of the reference Figure 2A Corresponding elements, features, materials or manufacturing methods of the carrier 10 and the interconnect structure 140 in the manufacture of the electronic device 100 are described.

[0086] The electronic component 420b may include or be referred to as a passive component. In some examples, the electronic component 420b may include or be referred to as a decoupling capacitor. The electronic component 420b may include a component interconnect 421b coupled to the carrier 10. The electronic component 420b may include one or more than two electronic components. The component interconnect 421b of the electronic component 420b may be adhered and fixed to the carrier 10. For example, the electronic component 420b may be picked up by a pick-and-place device to be placed and bonded to the carrier 10. The electronic component 420b may be attached to the carrier 10 to be spaced apart from the interconnect structure 140. In some examples, the height of the electronic component 420b may be less than the height of the interconnect structure 140. The electronic component 420b may be installed between the interconnect structures 140 to prevent an increase in the size of the electronic device 400 from occurring during stacking. In some examples, the height of the electronic component 420b may range from approximately 50 μm to approximately 120 μm.

[0087] Figure 6B The electronic device 400 is shown in a later stage of manufacturing. Figure 6BIn the example shown in FIG. 1 , an encapsulant 150 may be provided to cover the carrier 10, the interconnection structure 140, and the electronic component 420 b. The encapsulant 150 may be in contact with the sidewalls of the carrier 10, the interconnection structure 140, and the sidewalls of the electronic component 420 b. The side 140 a of the interconnection structure 140 may be exposed from the encapsulant 150. The encapsulant 150 may have a shape similar to that of the reference 10. Figure 2B The corresponding elements, features, materials or manufacturing methods of the encapsulant 150 described.

[0088] Figure 6C The electronic device 400 is shown in a later stage of manufacturing. Figure 6C In the example shown in , the substrate 410 may be disposed on the side 150 a of the encapsulant 150 and the side 140 a of the interconnect structure 140 .

[0089] Substrate 410 may include dielectric structure 411 and conductive structure 412. Conductive structure 412 may include inward terminal 412a and outward terminal 412c. Substrate 410 may have a structure similar to reference Figure 2C The corresponding elements, features, materials or manufacturing methods of the described substrate 110. In some examples, the substrate 410 may include an RDL substrate. In other examples, the substrate 410 may include a preformed substrate.

[0090] Fig.6D The electronic device 400 is shown in a later stage of manufacturing. Fig.6D In the example shown in FIG. 4 , the substrate 460 may be disposed on the side 150 b of the encapsulant 150 , on the side 140 b of the interconnect structure 140 , and on the electronic component 420 b .

[0091] Before providing the substrate 460, the carrier 10 may be separated from the side 150b of the encapsulant 150, the side 140b of the interconnect structure 140, and the component interconnects 421b of the electronic component 420b. The separation of the carrier 10 may include steps similar to those described in reference 4. Figure 2D In some examples, substrate 460 may include an RDL substrate. In other examples, substrate 460 may include a preformed substrate.

[0092] Fig.6D The electronic device 400 shown in FIG. 4 can be flipped so that the substrate 410 can be positioned below the encapsulant 150, the electronic component 420b, and the interconnect structure 140. The substrate 460 can include a dielectric structure 461 and a conductive structure 462. The conductive structure 462 can include an inward terminal 462a and an outward terminal 462b. The substrate 460 can have a similar structure to that of the reference Figure 2D The interconnect structure 140 and the component interconnect 421 b of the electronic component 420 b may be coupled to the internal terminal 462 a of the substrate 460 .

[0093] Fig. 6E The electronic device 400 is shown in a later stage of manufacturing. Fig. 6E 4, electronic component 420 and electronic component 420a may be disposed on substrate 460. Electronic component 420 and electronic component 420a may be coupled to outward terminal 462b of substrate 460. Electronic component 420 and electronic component 420a may be located adjacent to each other on substrate 460. Electronic component 420 may have corresponding elements, features, materials, or manufacturing methods similar to electronic component 120. Electronic component 420a may have corresponding elements, features, materials, or manufacturing methods similar to electronic component 420b.

[0094] Electronic component 420 may be located above electronic component 420b at an opposite side of substrate 460. Because electronic component 420b may be located within or overlap the footprint of electronic component 420, or within or overlap the footprint of an electronic component adjacent to electronic component 420, the area size of electronic device 400 may be reduced.

[0095] Electronic component 420 may be coupled to electronic component 420a and electronic component 420b via conductive structure 462 of substrate 460. In some examples, when electronic component 420a and electronic component 420b are decoupling capacitors, noise removal may be enhanced by mounting them more closely adjacent to electronic component 420. When power lines and ground lines are disposed within substrate 460, electronic component 420, electronic component 420a, and electronic component 420b may have low loop inductance. Electronic component 420, electronic component 420a, and electronic component 420b may be coupled to substrate 410 via interconnect structure 140. Similar to the description regarding Figure 2F Connector 180 is provided and coupled to conductive structure 462 in a similar manner as described.

[0096] Fig. 6F The electronic device 400 is shown in a later stage of manufacturing. Fig. 6FIn the example shown in FIG. 4 , an encapsulant 470 may be provided to cover the outside of the electronic components 420 and 420a and the substrate 460. The encapsulant 470 may contact the outer side and sidewall of the electronic component 420 and the outer side and sidewall of the electronic component 420a. The encapsulant 470 may cover the dielectric structure 461 and the outward terminal 462b of the substrate 460. In some examples, the encapsulant 470 may have corresponding elements, features, materials, or manufacturing methods similar to the encapsulant 150 of the electronic device 100 or the encapsulant 280 of the electronic device 200. In some examples, the encapsulant 470 may expose the outer side of the electronic component 420 or its corresponding metal layer 329. In some examples, similar to the structure of the encapsulant 380 of the electronic device 300, the TIM 391 or the cover 390 may be disposed on the encapsulant 470 or the metal layer 329. In some examples, the thickness of the encapsulant 470 can range from approximately 10 μm to approximately 1200 μm. In some examples, the interconnect structure 140 can be in the encapsulant 470 .

[0097] Figure 6G The electronic device 400 is shown in a later stage of manufacturing. Figure 6GIn the example shown in , an external interconnect 480 may be provided. In some examples, the external interconnect 480 may be coupled to the metal interconnect 141 of the interconnect structure 140 adjacent to the encapsulant 470. In some examples, the external interconnect 480 may be coupled to the external terminal 412c of the substrate 410. In some examples, the external interconnect 480 may be coupled to the electronic component 420, the electronic component 420a, or the electronic component 420b through the substrate 410, the interconnect structure 140, and the substrate 460. In some examples, the external interconnect 480 may include tin (Sn), silver (Ag), lead (Pb), copper (Cu), Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, or Sn-Ag-Cu. For example, after forming a conductive material including solder on the outward terminal 412c or the interconnect structure 140 by a ball drop method, an external interconnect 480 may be formed by a reflow process. The external interconnect 480 may include or be referred to as a conductive ball such as a solder ball, a conductive pillar such as a copper pillar, or a conductive pillar having a solder cap disposed on a copper pillar. In some instances, the external interconnects 480 may be arranged in a ball grid array or a pad grid array outside the substrate 410. In some instances, the size of the external interconnects 480 may range from approximately 25 μm to approximately 300 μm. In some instances, the external interconnects 480 may be referred to as external input / output terminals of the electronic device 400. It should be noted that in some instances, some or all of the external interconnects 480 may be omitted at either or both sides of the electronic device 400. In some examples, a singulation process for separating into individual electronic components 400 by sawing the substrates 410 and 460 and the encapsulants 150 and 470 may be performed.

[0098] The present disclosure includes references to certain examples. However, it will be appreciated by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present disclosure. In addition, modifications may be made to the disclosed examples without departing from the scope of the present disclosure. Therefore, it is intended that the present disclosure is not limited to the disclosed examples, but that the present disclosure will include all examples within the scope of the appended claims.

Claims

1. An electronic device, characterized in that: include: a first substrate comprising a first dielectric structure and a first conductive structure; a first interconnect structure over an inwardly facing side of the first substrate and coupled to the first conductive structure; a first encapsulant over the inwardly facing side of the first substrate and contacting a lateral side of the first interconnect structure; a second substrate over the first encapsulant and comprising a second dielectric structure and a second conductive structure, wherein the second conductive structure is coupled to the first interconnect structure; and a first electronic component coupled to an outwardly facing side of the first substrate; The first electronic component is coupled to the second conductive structure via the first interconnect structure and the first conductive structure.

2. The electronic device according to claim 1, characterized in that: include: a second encapsulant over the outward side of the second substrate and covering the second conductive structure; The second encapsulant includes a first material and the second dielectric structure includes a second material different from the first material.

3. The electronic device according to claim 1, wherein: The second conductive structure includes an antenna directional pattern.

4. The electronic device according to claim 1, characterized in that: The first interconnect structure comprises: interconnecting the encapsulant; and A metal interconnect is bounded by the interconnect encapsulation.

5. The electronic device according to claim 1, characterized in that: include: A second encapsulant is coupled to the outwardly facing side of the first substrate and contacts a lateral side of the first electronic component.

6. The electronic device according to claim 5, characterized in that: include: A cover is coupled to the outward side of the second enclosure.

7. The electronic device according to claim 6, characterized in that: include: a thermal interface material between the first electronic component and the cover; in: The first electronic component includes a metal layer on a back side of the first electronic component; and The metal layer is coupled to the thermal interface material.

8. The electronic device according to claim 1, characterized in that: The first substrate comprises a first redistribution layer substrate; and The second substrate includes a second redistribution layer substrate.

9. An electronic device, characterized in that: include: a first substrate comprising a first dielectric structure and a first conductive structure; a first interconnect structure over a top side of the first substrate and coupled to the first conductive structure; a first encapsulant over the first substrate and contacting a lateral side of the first interconnect structure; a second substrate over the first encapsulant and comprising a second dielectric structure and a second conductive structure, wherein the second conductive structure is coupled to the first interconnect structure; a first electronic component over the top side of the second substrate and coupled to the second conductive structure; a second electronic component coupled to the second conductive structure; as well as A second encapsulant is over the top side of the second substrate and contacts lateral sides of the first electronic component.

10. The electronic device according to claim 9, characterized in that: The second electronic component includes a decoupling capacitor.

11. The electronic device according to claim 9, characterized in that: The second electronic component is coupled to a bottom side of the second substrate; and The second electronic component is in the first enclosure and at least partially within a footprint of the first electronic component.

12. The electronic device according to claim 9, characterized in that: The second electronic component is coupled to the top side of the second substrate; and The second electronic component is in the second enclosure.

13. The electronic device according to claim 9, characterized in that: include: a third electronic component coupled to the second conductive structure; The second electronic component and the third electronic component are on opposite sides of the second substrate.

14. The electronic device according to claim 9, characterized in that: The first interconnect structure comprises: interconnecting the encapsulant; and A metal interconnect is bounded by the interconnect encapsulation.

15. The electronic device according to claim 9, characterized in that: The first substrate comprises a first redistribution layer substrate; and The second substrate includes a second redistribution layer substrate.

16. A method for manufacturing an electronic device, characterized in that: include: providing a first interconnect structure; providing a first encapsulant contacting a lateral side of the first interconnect structure; providing a first substrate coupled to a first side of the first encapsulant, wherein the first substrate comprises a first dielectric structure and a first conductive structure, and wherein the first conductive structure is coupled to the first interconnect structure; providing a second substrate coupled to a second side of the first encapsulant, wherein the second substrate comprises a second dielectric structure and a second conductive structure, and wherein the second conductive structure is coupled to the first interconnect structure; and providing a first electronic component coupled to the first substrate; The first electronic component is coupled to the second conductive structure via the first interconnect structure and the first conductive structure.

17. The method according to claim 16, characterized in that include: A second encapsulant coupled to the second substrate and covering the second conductive structure is provided.

18. The method according to claim 16, characterized in that: The second conductive structure includes an antenna directional pattern.

19. The method according to claim 16, characterized in that The first interconnect structure comprises: interconnecting the encapsulant; and A metal interconnect is bounded by the interconnect encapsulation.

20. The method according to claim 16, characterized in that include: A second encapsulant is provided coupled to the first substrate and contacting lateral sides of the first electronic component.

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