A test structure and preparation method thereof

Abstract

The present invention discloses a test structure and a preparation method thereof, wherein the test structure comprises a trench capacitor and a test layer, wherein the trench capacitor comprises a lower plate, a capacitor dielectric layer and an upper plate arranged in sequence from bottom to top, wherein the trench capacitor comprises at least two trench regions, wherein the test layer is connected to the lower plate of the trench capacitor, wherein the test layer comprises test units arranged in one-to-one correspondence with the trench regions of the trench capacitor, wherein the test units are arranged separately, and wherein the test units respectively lead out ports of a four-terminal test method. According to the test structure and the preparation method thereof provided by the present invention, by forming a test path for a four-terminal test method through the lower plate of the trench capacitor between the separately arranged test units, the contact resistance of the lower plate of the trench capacitor in the trench region is monitored, thereby helping engineers to more quickly and accurately discover the causes of trench capacitor failure and facilitate corresponding improvements.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a test structure and a preparation method thereof. Background Art

[0002] CMOS image sensors (CIS) have been used in many fields such as machine vision, automobiles, analytical instruments, and absorption imaging. With the continuous development of sensing technology, wide dynamic range (WDR) has become the main direction for improving CIS performance. In the current WDR technology, lateral overflow integrated capacitor technology (LOFIC) can accumulate overflow electrons from PD and FD capacitors and read out signals with different sensitivities in a single exposure, which is a research hotspot of WDR technology. Wide dynamic range CIS can improve the maximum signal-to-noise ratio and signal-to-noise ratio of the signal switching point by introducing lateral overflow integrated trench capacitors (trench LOFIC). Among them, the lateral overflow integrated trench capacitor (trench LOFIC) has a trench metal-insulator-metal (MIM) capacitor.

[0003] There are many technical difficulties in the process development of trench MIM capacitors, including the resistance monitoring of the upper and lower plates. Resistance monitoring can help engineers find the causes of trench MIM capacitor failure more quickly and accurately, thereby accurately positioning and improving the corresponding process technology. Summary of the invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0005] The present invention provides a test structure, characterized in that it includes:

[0006] A trench capacitor, wherein the trench capacitor comprises a lower plate, a capacitor dielectric layer and an upper plate arranged in sequence from bottom to top, and the trench capacitor comprises at least two trench regions;

[0007] A test layer, the test layer is connected to the lower plate of the trench capacitor, the test layer includes test units arranged in one-to-one correspondence with the trench regions of the trench capacitor, and the test units are arranged separately;

[0008] Wherein, the test units respectively lead out ports of a four-terminal test method.

[0009] Exemplarily, the test structure is used to test the contact resistance of the lower plate of the trench capacitor in the trench region.

[0010] Exemplarily, a test path is formed between the separated test units via the lower plate of the trench capacitor.

[0011] Exemplarily, the ports of the four-terminal test method include two loading terminals and two sensing terminals, the two loading terminals are respectively led out by different test units, and the two sensing terminals are respectively led out by different test units.

[0012] Exemplarily, the test layer includes a first test unit and a second test unit arranged corresponding to the trench areas at both ends of the trench capacitor, and the first test unit and the second test unit lead out a first current sensing terminal and a first voltage loading terminal, respectively. The test layer also includes a third test unit arranged corresponding to the trench area in the middle of the trench capacitor, and the two ends of the third test unit lead out a second current sensing terminal and a second voltage loading terminal, respectively.

[0013] Exemplarily, the first current sensing terminal and the first voltage loading terminal extend along a first direction, the second current sensing terminal and the second voltage loading terminal extend along a second direction, and the first direction intersects with the second direction.

[0014] Exemplarily, the trench capacitor includes a metal-insulator-metal capacitor, the upper plate and the lower plate are formed of a metal material, and the dielectric layer is formed of a high dielectric constant dielectric material.

[0015] Exemplarily, the test structure further includes a top metal layer and a metal plug, wherein the top metal layer is connected to an upper plate of the trench capacitor via the metal plug.

[0016] The present invention also provides a method for preparing a test structure, comprising:

[0017] Forming a test layer and patterning the test layer to form at least two test units, wherein the at least two test units are not connected to each other and the test units respectively lead out ports of a four-terminal test method;

[0018] forming a dielectric layer on the test layer, and etching the dielectric layer to form a groove above each of the test units until a surface of the test unit is exposed;

[0019] A lower plate, a capacitor dielectric layer and an upper plate covering the dielectric layer and the trench are sequentially formed to form a trench capacitor.

[0020] Exemplarily, after patterning the test layer, the method further includes:

[0021] Filling an isolation material between the test units to form separate test units;

[0022] The test unit and the isolation material are planarized.

[0023] According to the test structure and preparation method thereof provided by the present invention, a one-to-one corresponding test unit is arranged under each trench area of ​​the trench capacitor, and the test units are arranged separately, and ports for the four-terminal test method are respectively led out from the test units, so that a test path for the four-terminal test method is formed between the test units via the lower electrode plate of the trench capacitor, thereby realizing the monitoring of the contact resistance of the lower electrode plate of the trench capacitor in the trench area, helping engineers to find the cause of the failure of the trench capacitor more quickly and accurately, and facilitating corresponding improvements. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The following drawings of the present invention are used to understand the present invention as part of the present invention. The embodiments of the present invention are shown in the drawings and the description thereof is used to explain the principle of the present invention.

[0025] In the attached figure:

[0026] Figure 1 is a flow chart of a method for preparing a test structure according to an embodiment of the present invention;

[0027] Figure 2A-2E It is a cross-sectional schematic diagram of a structure obtained by sequentially implementing the method for preparing a test structure according to an embodiment of the present invention;

[0028] Figure 2F FIG. 4 is a schematic cross-sectional diagram of a test structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present invention. However, it is apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features well known in the art are not described.

[0030] It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0031] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0032] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0033] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0034] In order to fully understand the present invention, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution proposed by the present invention. The preferred embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other implementations.

[0035] Currently, in a trench MIM capacitor, test ports are usually led out from the upper plate and the lower plate of the trench MIM capacitor, respectively. However, it becomes difficult to monitor the contact resistance Rc of the lower plate at the trench.

[0036] In view of the above problems, the present invention provides a method for preparing a test structure, such as Figure 1 As shown, including:

[0037] Step S110: forming a test layer and patterning the test layer to form at least two test units, wherein the at least two test units are not connected to each other and the test units respectively lead out ports of a four-terminal test method;

[0038] Step S120: forming a dielectric layer on the test layer, and etching the dielectric layer to form a groove above each of the test units until the surface of the test unit is exposed;

[0039] Step S130: sequentially forming a lower plate, a capacitor dielectric layer and an upper plate covering the dielectric layer and the trench to form a trench capacitor.

[0040] In order to fully understand the present invention, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by the present invention. The preferred embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other implementations.

[0041] Below, reference FIG. 2A to FIG. 2E The preparation method of the test structure of the present invention is described in detail, wherein: FIG. 2A to FIG. 2E The cross-sectional schematic diagram shows a test structure obtained by sequentially implementing the method for preparing the test structure according to the embodiment of the present invention.

[0042] Exemplarily, the method for preparing the test structure of the present invention comprises the following steps:

[0043] First, step S110 is performed to form a test layer 201, and the test layer 201 is obtained. Figure 2A The structure shown in FIG. 1 is patterned to form at least two test units, wherein the at least two test units are not connected to each other, and the test unit 201 is patterned to form at least two test units. Figure 2B In the structure shown, the test units respectively lead out ports for the four-terminal test method.

[0044] In one embodiment, the test layer 201 is formed on a semiconductor substrate (not shown). The semiconductor substrate may be a silicon substrate, or at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including a multilayer structure composed of these semiconductor materials, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or double-side polished silicon wafers (DSP), or ceramic substrates such as alumina, quartz or glass substrates, etc.

[0045] In one embodiment, Figure 2A As shown, the test layer 201 is formed of metal materials, including but not limited to copper-manganese alloy (Cu-Mn). The test layer 201 can be formed by a low-pressure chemical vapor deposition (LPCVD) formed by a chemical vapor deposition (CVD) method, a physical vapor deposition (PVD) method, or an atomic layer deposition (ALD) method, laser ablation deposition (LAD), and selective epitaxial growth (SEG), and the present invention does not limit this.

[0046] In one embodiment, patterning the test layer 201 includes: forming a hard mask layer (not shown) on the test layer 201, the hard mask layer including but not limited to a silicon oxide layer, a silicon nitride layer or an ONO structure, and then forming a patterned photoresist layer on the hard mask layer, and etching the hard mask layer using the photoresist layer as a mask to form a patterned hard mask layer. Next, using the patterned hard mask layer as a mask, etching the test layer 201 so that the test layer 201 forms a plurality of test units, and the formed test units are not connected to each other. Figure 2B In the example shown, three test units are formed: a first test unit 201a, a second test unit 201b and a third test unit 201c, wherein the first test unit 201a leads to a test port, which is a first current sensing terminal (IH), the second test unit 201b leads to a test port, which is a first voltage loading terminal (VH), and the third test unit 201c leads to two test ports, which are a second current sensing terminal (IL) and a second voltage loading terminal (VL).

[0047] In one embodiment, Figure 2B As shown, after patterning the test layer 201, the step of filling the test units with an isolation material 202 to form separate test units is also included. The isolation material 202 may be made of oxide, such as SiO 2. The method for forming the isolation material 202 can adopt any existing technology familiar to those skilled in the art, preferably chemical vapor deposition (CVD), such as low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD). By filling the isolation material between the test units to form separated test units, it is possible to avoid the direct formation of electrical connection paths between the test units, and the test path must be formed through the lower plate of the trench capacitor formed in the subsequent steps.

[0048] In one embodiment, after the unconnected test units are separated from each other by the isolation material 202, a step of planarizing the test layer 201 and the isolation material 202 is also included to make the surface of the isolation material 202 flush with the surface of the test layer 201. The planarization method may be chemical mechanical polishing (CMP).

[0049] Next, step S120 is performed to form a dielectric layer 204 on the test layer 201, and the dielectric layer 204 is etched to form a groove 205 above each of the test units until the surface of the test unit is exposed, thereby obtaining Figure 2C The structure shown.

[0050] In one embodiment, before forming the dielectric layer 204, a step of forming a diffusion barrier layer 203 on the test layer 201 and the isolation material 202 is also included. The diffusion barrier layer 203 includes but is not limited to a nitrogen-doped silicon carbide (NDC) layer. The dielectric layer 204 includes but is not limited to a tetraethoxysilane (TEOS) layer. The method for forming the diffusion barrier layer 203 and the dielectric layer 204 can adopt any existing technology familiar to those skilled in the art, preferably a chemical vapor deposition method (CVD).

[0051] In one embodiment, etching the dielectric layer 204 to form a groove 205 above each of the test units includes: forming a hard mask layer (not shown) on the dielectric layer 204, then forming a patterned photoresist layer on the hard mask layer, and etching the hard mask layer using the photoresist layer as a mask to form a patterned hard mask layer. Next, using the patterned hard mask layer as a mask, etching the dielectric layer 204 and the diffusion barrier layer 203 until the surface of the test layer 201 is exposed. Etching the dielectric layer 204 and the diffusion barrier layer 203 can be performed using any existing technology familiar to those skilled in the art, preferably dry etching. Dry etching processes include, but are not limited to, reactive ion etching (RIE), ion beam etching, plasma etching, and laser ablation. A single etching method or any combination of these methods can be used.

[0052] Next, step S130 is performed to sequentially form a lower plate 206a, a capacitor dielectric layer 206b and an upper plate 206c covering the dielectric layer 204 and the trench 205 to form a trench capacitor 206. Figure 2D The structure shown.

[0053] In one embodiment, before forming the trench capacitor, a step of forming an adhesion layer (not shown) covering the dielectric layer 204 and the trench 205 is also included. The adhesion layer includes but is not limited to Ti, Cr and TiW.

[0054] In one embodiment, the lower plate 206a and the upper plate 206c may be made of the same material or different materials. The lower plate 206a and the upper plate 206c may be made of metal materials, such as copper (Cu), titanium (Ti), etc., or titanium nitride (TiN), etc., which is not limited in this application. The lower plate 206a and the upper plate 206c may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc., which will not be described in detail here.

[0055] In one embodiment, the capacitor dielectric layer 206b may include conventional dielectric materials such as oxides, nitrides, and oxynitrides of silicon having a dielectric constant from about 4 to about 20 (measured in a vacuum). Alternatively, the capacitor dielectric layer 206b may include a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant electrolyte materials may include, but are not limited to, hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs). The formation method of the capacitor dielectric layer 206b may be any prior art familiar to those skilled in the art, preferably chemical vapor deposition (CVD), such as low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD), and plasma enhanced chemical vapor deposition (PECVD).

[0056] In one embodiment, the trench capacitor formed by the above steps is a metal-insulator-metal (MIM) capacitor, but this is not restrictive. Any trench capacitor whose contact resistance (Rc) of the lower plate in the trench area can be tested by the test structure provided in the present application is suitable for the present application.

[0057] In one embodiment, after forming the trench capacitor, the step further includes forming a dielectric layer covering the upper plate of the trench capacitor, and forming a metal plug and a top metal layer in the dielectric layer covering the upper plate, wherein the top metal layer is connected to the upper plate 206c of the trench capacitor via the metal plug, forming a Figure 2E The structure shown.

[0058] The key steps of the method for preparing the test structure of the present invention have been introduced so far. For the complete device preparation, multiple other process steps may be required, which will not be described one by one here.

[0059] It is worth mentioning that the order of the above steps is only an example. Under the premise of no conflict, the order of the above steps can also be swapped or performed alternately.

[0060] The present invention also provides a test structure, such as Figure 2E and 2F As shown, including:

[0061] A trench capacitor 206, wherein the trench capacitor 206 comprises a lower plate 206a, a capacitor dielectric layer 206b and an upper plate 206c arranged in sequence from bottom to top, and the trench capacitor 206 comprises at least two trench regions;

[0062] A test layer 201, wherein the test layer 201 is connected to the lower plate 206a of the trench capacitor, and the test layer 201 includes test units arranged in one-to-one correspondence with the trench regions of the trench capacitor 206, and the test units are arranged separately;

[0063] Wherein, the test units respectively lead out ports of a four-terminal test method.

[0064] In one embodiment, the test structure further includes a top metal layer and a metal plug, wherein the top metal layer is connected to the upper plate of the trench capacitor via the metal plug.

[0065] Exemplarily, the test structure is used to test the contact resistance of the lower plate of the trench capacitor in the trench region. The ports of the four-terminal test method include two loading terminals and two sensing terminals, the two loading terminals are respectively led out by different test units, and the two sensing terminals are respectively led out by different test units. The separated test units form a test path via the lower plate of the trench capacitor.

[0066] In one embodiment, Figure 2E and 2FAs shown, the test layer 201 forms three test units: a first test unit 201a, a second test unit 201b and a third test unit 201c. The first test unit 201a and the second test unit 201b are respectively arranged corresponding to the trench regions at both ends of the trench capacitor 206, and the third test unit 201c is arranged corresponding to the trench region in the middle of the trench capacitor 206. The first test unit 201a leads to a test port, which is a first current sensing terminal (IH), the second test unit 201b leads to a test port, which is a first voltage loading terminal (VH), and the third test unit 201c leads to two test ports, which are a second current sensing terminal (IL) and a second voltage loading terminal (VL).

[0067] In one embodiment, the four terminals of the four-terminal test method are arranged in a "cross" or "X" shape. Figure 2F , the first current sensing terminal (IH) and the first voltage loading terminal (VH) extend along the first direction, the second current sensing terminal (IL) and the second voltage loading terminal (VL) extend along the second direction, the first direction intersects the second direction, and preferably, the first direction is perpendicular to the second direction. Among them, the multiple trench regions of the trench capacitor are arranged along the first direction, and each capacitor in the trench capacitor extends along the second direction. The first current sensing terminal (IH) and the first voltage loading terminal (VH) are located outside the trench capacitor in the first direction, and the second current sensing terminal (IL) and the second voltage loading terminal (VL) are located outside the trench capacitor in the second direction.

[0068] In one embodiment, the trench capacitor includes a metal-insulator-metal (MIM) capacitor, the upper plate and the lower plate are formed of a metal material, and the dielectric layer is formed of a high dielectric constant dielectric material. Through the test structure provided by the present invention, the contact resistance (Rc) of the lower plate of the trench capacitor at the trench area can be tested. Specifically, a voltage Vf is applied to the first voltage loading terminal (VH) and the second voltage loading terminal (VL), and a current Is is tested at the first current sensing terminal (IH) and the second current sensing terminal (IL). The test path formed between the first test unit 201a and the third test unit 201c is shown as curve ①, and the test path formed between the second test unit 201b and the third test unit 201c is shown as curve ②.

[0069] According to the test structure and preparation method thereof provided by the present invention, a one-to-one corresponding test unit is arranged under each trench area of ​​the trench capacitor, and the test units are arranged separately, and ports for the four-terminal test method are respectively led out from the test units, so that a test path for the four-terminal test method is formed between the test units via the lower electrode plate of the trench capacitor, thereby realizing the monitoring of the contact resistance of the lower electrode plate of the trench capacitor in the trench area, helping engineers to find the cause of the failure of the trench capacitor more quickly and accurately, and facilitating corresponding improvements.

[0070] The present invention has been described by the above embodiments, but it should be understood that the above embodiments are only for the purpose of example and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, it can be understood by those skilled in the art that the present invention is not limited to the above embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the scope of the protection claimed by the present invention. The protection scope of the present invention is defined by the attached claims and their equivalents.

Claims

1. A test structure, characterized in that: include: A trench capacitor, wherein the trench capacitor comprises a lower plate, a capacitor dielectric layer and an upper plate arranged in sequence from bottom to top, and the trench capacitor comprises at least two trench regions; A test layer, the test layer is connected to the lower plate of the trench capacitor, the test layer includes test units arranged in one-to-one correspondence with the trench regions of the trench capacitor, and the test units are arranged separately; The test units lead out ports of the four-terminal test method respectively; the ports of the four-terminal test method include two loading terminals and two sensing terminals, the two loading terminals are led out by different test units respectively, and the two sensing terminals are led out by different test units respectively; The test structure is used to test the contact resistance of the lower plate of the trench capacitor in the trench area; The separated test units form a test path through the lower plate of the trench capacitor.

2. The test structure according to claim 1, characterized in that The test layer includes a first test unit and a second test unit which are arranged corresponding to the trench areas at both ends of the trench capacitor, and the first test unit and the second test unit lead out a first current sensing end and a first voltage loading end respectively. The test layer also includes a third test unit which is arranged corresponding to the trench area in the middle of the trench capacitor, and the two ends of the third test unit lead out a second current sensing end and a second voltage loading end respectively.

3. The test structure according to claim 2, characterized in that: The first current sensing end and the first voltage loading end extend along a first direction, the second current sensing end and the second voltage loading end extend along a second direction, and the first direction intersects with the second direction.

4. The test structure according to claim 1, characterized in that: The trench capacitor comprises a metal-insulator-metal capacitor, the upper plate and the lower plate are formed of metal material, and the dielectric layer is formed of a high dielectric constant dielectric material.

5. The test structure according to claim 1, characterized in that: The invention also includes a top metal layer and a metal plug, wherein the top metal layer is connected to the upper plate of the trench capacitor via the metal plug.

6. A method for preparing a test structure, characterized in that: include: Forming a test layer and patterning the test layer to form at least two test units, the at least two test units are not connected to each other, and the test units respectively lead out ports of a four-terminal test method; the ports of the four-terminal test method include two loading terminals and two sensing terminals, the two loading terminals are respectively led out by different test units, and the two sensing terminals are respectively led out by different test units; forming a dielectric layer on the test layer, and etching the dielectric layer to form a groove above each of the test units until a surface of the test unit is exposed; Sequentially forming a lower plate, a capacitor dielectric layer and an upper plate covering the dielectric layer and the trench to form a trench capacitor; Wherein, the test structure is used to test the contact resistance of the lower plate of the trench capacitor in the trench area; A test path is formed between the unconnected test units via the lower electrode plate of the trench capacitor.

7. The preparation method according to claim 6, characterized in that: After patterning the test layer, the method further comprises: Filling an isolation material between the test units to form separate test units; The test unit and the isolation material are planarized.

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