Semiconductor device structure

Abstract

The embodiment of the invention provides a semiconductor device structure. Protection against electrostatic discharge (ESD) events is provided by forming a discharge guide point (LPoD) structure on a semiconductor die or a composite die. The LPoD structure may include an upper protruding portion on the ESD path metal structure, an intermediate metal material portion, a solder material portion that is higher than a normal solder material portion that does not provide ESD protection, or an elongated metal strip structure. The LPoD structure may be used in an anisotropic etch process to form a via cavity, a bonding process using solder material portions, a bonding process using metal-to-metal bonding, and / or a solder ball attachment process.

Description

Technical Field

[0001] An embodiment of the present application relates to a semiconductor device structure. Background Art

[0002] Electrostatic discharge (ESD) events can damage semiconductor dies and semiconductor packages during and after manufacturing. ESD events can cause immediate device failure, yield loss, shortened device life, and potential reliability risks, and can have a detrimental impact on device reliability and manufacturing yield. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a semiconductor device structure is provided, comprising: a semiconductor device located on a semiconductor substrate; an electrostatic discharge (ESD) path metal structure buried in a cover dielectric layer, wherein the electrostatic discharge path metal structure includes a first top surface segment located in a first horizontal plane, and also includes an upper protrusion protruding above the first horizontal plane; a first metal bonding pad having a flat bottom surface in contact with the first top surface segment; and a second metal bonding pad in contact with the top surface of the upper protrusion.

[0004] According to another aspect of an embodiment of the present application, a semiconductor device structure is provided, including: a molded plastic die frame laterally surrounding a first semiconductor die and a second semiconductor die; a first passivation level metal structure overlying the first semiconductor die; a second passivation level metal structure overlying the second semiconductor die; an electrostatic discharge (ESD) path metal structure overlying the first semiconductor die, the molded plastic die frame, and the second semiconductor die, wherein the electrostatic discharge path metal structure includes a first top surface segment located in a first horizontal plane, the first horizontal plane includes a top surface of one of the first passivation level metal structures and a top surface of one of the second passivation level metal structures, and the electrostatic discharge path metal structure also includes an upper protrusion protruding above the first horizontal plane; a first metal bonding pad having a flat bottom surface in contact with the first top surface segment; and a second metal bonding pad in contact with the top surface of the upper protrusion.

[0005] According to another aspect of an embodiment of the present application, a semiconductor device structure is provided, comprising: a first semiconductor die, comprising a first semiconductor substrate, a first semiconductor device located on the first semiconductor substrate, a first dielectric material layer in which a first metal interconnect structure is buried, and a first metal bonding pad, wherein the first metal bonding pad comprises a first type first metal bonding pad and a second type first metal bonding pad; a second semiconductor die, comprising a second semiconductor substrate, a second semiconductor device located on the second semiconductor substrate, a second dielectric material layer in which a second metal interconnect structure is buried, and a second metal bonding pad, wherein the second metal bonding pad comprises a first type second metal bonding pad directly bonded to the first type first metal bonding pad and a second type second metal bonding pad that does not contact any first metal bonding pad; and intermediate metal material portions, wherein each intermediate metal material portion contacts a corresponding one of the second type first metal bonding pads and a corresponding one of the second type second metal bonding pads. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a vertical cross-sectional view of a first embodiment structure including a semiconductor die according to a first embodiment of the present disclosure.

[0008] FIG. 2A to FIG. 2F According to the first embodiment of the present disclosure, during the formation of the guiding point of the discharge structure Figure 1 Continuous vertical cross-sectional views of region M of the structure of the first embodiment.

[0009] Figure 3 FIG. 4 is a top view of a region of the structure of the first embodiment after forming a discharge structure and a guide point of a passivation level metal structure according to the first embodiment of the present disclosure.

[0010] 4A to 4F According to the first embodiment of the present disclosure Figure 1 1 and 2 are sequential vertical cross-sectional views of a region M of the structure of the first embodiment during formation of a pad and attachment of a solder material portion.

[0011] Figure 5 is a vertical cross-sectional view of a semiconductor die after being cut according to the first embodiment structure of the first embodiment of the present disclosure.

[0012] FIG. 6A to FIG. 6Iare sequential vertical cross-sectional views of regions of an alternative configuration of the first embodiment structure during formation of guide points and pads of the discharge structure and attachment of solder material portions according to the first embodiment of the present disclosure.

[0013] FIG. 7A to FIG. 7D 2 are continuous vertical cross-sectional views of the structure of the second embodiment during pilot point formation of the discharge structure according to the second embodiment of the present disclosure.

[0014] Fig. 8A According to the second embodiment of the present disclosure Fig.7D A top view of a region of the structure of the second embodiment.

[0015] Figure 8B is a top view of a region of an alternative configuration of a second embodiment structure according to a second embodiment of the present disclosure.

[0016] 9A to 9D are sequential vertical cross-sectional views of the second embodiment structure of a fan-out package according to the second embodiment of the present disclosure during dicing and attachment to an interposer.

[0017] FIG. 10A to FIG. 10F are sequential vertical cross-sectional views of a third embodiment structure during formation of a bonded assembly of two semiconductor dies according to a third embodiment of the present disclosure.

[0018] FIG. 11A to FIG. 11D are sequential vertical cross-sectional views of a fourth embodiment structure during formation of a bonded assembly of two semiconductor dies according to a fourth embodiment of the present disclosure.

[0019] FIG. 12A to FIG. 12E are sequential vertical cross-sectional views of a fifth embodiment structure during formation of a bonded assembly of two semiconductor dies according to a fifth embodiment of the present disclosure.

[0020] Fig.13 is a top view of a sixth embodiment structure including a wafer or a reconstituted wafer according to the sixth embodiment of the present disclosure.

[0021] FIG. 14A to FIG. 14J yes Fig.13 Enlarged views of various configurations of the structure of the sixth embodiment.

[0022] Fig.15A FIG. 4 is a top view of a seventh embodiment structure of a wafer or a reconstructed wafer according to a seventh embodiment of the present disclosure.

[0023] Fig. 15B yes Fig.15A An enlarged view of a unit area in the structure of the seventh embodiment.

[0024] Fig. 15C The area along which the first configuration of the seventh embodiment is arranged Fig. 15BVertical cross-sectional view of the vertical plane C-C'.

[0025] Fig.15D The area along which the first configuration of the seventh embodiment is arranged Fig. 15B Vertical cross-sectional view of the vertical plane D-D'.

[0026] Fig.15E The area along which the second configuration of the seventh embodiment is arranged Fig. 15B Vertical cross-sectional view of the vertical plane C-C'.

[0027] Fig.15F The area along which the second configuration of the seventh embodiment is arranged Fig. 15B Vertical cross-sectional view of the vertical plane D-D'.

[0028] Figure 15G yes Fig.15A An enlarged view of the unit area in the third configuration of the structure of the seventh embodiment.

[0029] Fig.15H The third configuration area of ​​the seventh embodiment is along Figure 15G Vertical cross-sectional view of the vertical plane H-H'.

[0030] Fig.15I The third configuration area of ​​the seventh embodiment is along Figure 15G A vertical cross-sectional view of a vertical plane I-I'.

[0031] Fig.15J yes Fig.15H Magnified view of area J.

[0032] Figure 15K yes Fig.15I Magnified view of area K.

[0033] Figure 15L yes Fig.15I Detailed view of the .

[0034] FIG. 16A to FIG. 16E is a sequential vertical cross-sectional view of the structure of the eighth embodiment, wherein FIG. 15A to FIG. 15G The seventh exemplary structure is processed to attach a solder material portion.

[0035] Fig.17 is a schematic circuit diagram of a combined electrostatic discharge circuit during various pilot point operations of the discharge structure of various embodiments of the present disclosure.

[0036] Fig.18 is a first flow chart illustrating steps of forming a device structure according to an embodiment of the present disclosure.

[0037] Fig.19is a second flow chart illustrating steps of forming a device structure according to an embodiment of the present disclosure.

[0038] Fig. 20 is a third flow chart illustrating steps of forming a device structure according to an embodiment of the present disclosure.

[0039] Fig.21 is a fourth flow chart illustrating steps of forming a device structure according to an embodiment of the present disclosure.

[0040] Fig. 22 is a fifth flow chart illustrating steps of forming a device structure according to an embodiment of the present disclosure.

[0041] Fig.23 is a sixth flow chart illustrating steps of forming a device structure according to an embodiment of the present disclosure.

[0042] Fig.24 is a seventh flow chart illustrating steps of forming a device structure according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0044] In addition, for ease of description, spacing relationship terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figure. In addition to the orientation shown in the figure, the spacing relationship terms are intended to include different orientations of the device in use or operating processes. The device can be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing relationship descriptors used in this article can be interpreted accordingly. Unless otherwise explicitly stated, each element with the same element number is assumed to have the same material composition and have a thickness within the same thickness range.

[0045] Reference Figure 1, shows a first embodiment structure according to the first embodiment of the present disclosure, which includes a semiconductor die 700. The semiconductor die 700 shown may be one of a plurality of semiconductor dies 700 formed on a semiconductor substrate 110, which may be a commercially available semiconductor wafer. In this embodiment, a two-dimensional array of semiconductor dies 700 may be formed on the semiconductor substrate 110, such that each semiconductor die 700 may include a corresponding portion of the semiconductor substrate 100. The semiconductor die 700 may be a logic die, a memory die, or any other type of semiconductor die known in the art. Typically, a semiconductor device 120 may be formed on a top surface of the semiconductor substrate 110. For simplicity, the details of the semiconductor device are not depicted, but any known semiconductor device 120 may be formed in the identified area.

[0046] The semiconductor device 120 may include any type of semiconductor device known in the art, and may include, for example, a field effect transistor. In one embodiment, the field effect transistor may include a die-to-die input / output (I / O) switch that can withstand an electrostatic discharge (ESD) event. According to one aspect of the present disclosure, an electrostatic discharge (ESD) protection circuit 122 may be formed in each semiconductor die 700. Generally, any type of ESD protection device known in the art may be used for the ESD protection circuit 122. In addition, a well-laid out metal interconnect structure network (such as Figure 15L 1) can be electrically connected to ESD protection circuit 122, or in some cases, can replace ESD protection circuit 112. Thus, ESD protection circuit 122 can include any type of ESD protection circuit, can be replaced by a network of metal interconnect structures that are electrically shorted to the semiconductor substrate, or can be electrically connected to a network of metal interconnect structures. In one embodiment, ESD protection circuit 122 can include at least one diode, such as a plurality of diodes interconnected to each other, to provide sufficient charge handling capability when subjected to an ESD event.

[0047] The metal interconnect structure 140 is embedded in the dielectric material layer 150, which can be formed on the semiconductor device 120 and the ESD protection circuit 122. The metal interconnect structure 140 may include metal lines, metal via structures, integrated metal lines and via structures, metal bonding pads, etc. For simplicity, the details of the metal interconnect structure 40 embedded in the dielectric material layer 150 are not shown. The dielectric material layer 150 may include an interlayer dielectric (ILD) material, such as silicon oxide, silicon nitride, dielectric metal oxide, porous or non-porous organic silicate glass, etc. Generally, the dielectric material layer 150 may include a non-polymer material. The total number of layers of metal lines in the metal interconnect structure 140 may be in the range of 1 to 20, such as 2 to 12, but more layers may also be used. The metal bonding pad structure 158 may be formed on the top surface of the dielectric material layer 150. In some embodiments, at least one of the metal bonding pad structures 158 may be electrically connected to the metal interconnect structure 140 formed over the semiconductor substrate 110 and the semiconductor device 120 .

[0048] FIG. 2A to FIG. 2F is the guiding point formation period of the discharge structure according to the first embodiment of the present disclosure Figure 1 Continuous vertical cross-sectional views of region M of the structure of the first embodiment.

[0049] Reference Figure 1 and Figure 2A , a metal bonding pad structure 158 can be formed at the topmost layer of the dielectric material layer 150. For example, a via opening can be formed through the topmost dielectric material 150 selected from the dielectric material layer 150, so that the top surface of the topmost metal interconnect structure 140 is physically exposed below the via opening. In some embodiments, the topmost metal interconnect structure 140 may include a copper pad. The first passivation level metal can be deposited in the via opening and above the top surface of the topmost dielectric material layer 150, and can be patterned by performing a photolithography patterning process and an etching process (such as an anisotropic etching process). The patterned portion of the first passivation level metal includes a metal bonding pad structure 158. The metal bonding pad structure 158 may include aluminum, copper, an aluminum-based alloy, a copper-based alloy, etc.

[0050] Subsets of the metal interconnect structures 140 may be interconnected to each other to provide a conductive path between a subset of the metal bonding pad structures 158 and the ESD protection circuit 122. The conductive path may be used as a current path during an electrostatic discharge event, referred to herein as a discharge current path DCP. In some embodiments, the discharge current path DCP may be electrically connected to a node of the semiconductor device 120 that needs to be protected from an electrostatic discharge event. Such a semiconductor device 120 may include an input / output transistor, i.e., a field effect transistor, which is configured to receive an input / output signal into or send from the semiconductor die 700 to the semiconductor die 800.

[0051] Reference Figure 2B , a first passivation dielectric layer 161 can be deposited over the topmost dielectric material layer 150 and the metal bonding pad structure 158. The first passivation dielectric layer 161 includes a diffusion barrier dielectric material, such as silicon nitride or silicon carbonitride. The thickness of the first passivation dielectric layer 161 can be in the range of 100nm to 500nm, but lesser or greater thicknesses can also be used. An opening can be formed in the metal bonding pad structure 158, for example, by applying and patterning a photoresist layer (not shown), and transferring the opening pattern in the photoresist layer through the first passivation dielectric layer 161 using an etching process. The photoresist layer can then be removed, for example, by ashing.

[0052] Reference Figure 2C , a second passivation dielectric layer 163 may be formed over the first passivation dielectric layer 161. In one embodiment, the second passivation dielectric layer 163 may include a polymer-based (e.g., polyimide) passivation dielectric layer. The thickness of the second passivation dielectric layer 163 (measured in a region laterally spaced apart from the metal bonding pad structure 158) may be in the range of 1 micron to 10 microns, for example 2 microns to 6 microns, but smaller or larger thicknesses may also be used. The second passivation dielectric layer 163 may be patterned to form an opening therethrough so that the top surface of the metal bonding pad structure 158 is exposed to the environment below the opening in the second passivation dielectric layer 163. The environment may be an atmospheric environment or a low oxygen environment.

[0053] Reference Figure 2D , a metal seed layer 164 may be formed over the second passivation dielectric layer 163. The metal seed layer 164 includes at least one metal material, which may be used as an adhesion promoter material, a diffusion barrier material, and / or a metal seed material for a subsequent electroplating process. For example, the metal seed layer 164 may include a stack of a titanium layer and a copper seed layer, which may be deposited by physical vapor deposition. The thickness of the titanium layer may be in the range of 5nm to 100nm, and the thickness of the copper seed layer may also be in the range of 50nm to 500nm. However, the titanium layer and the copper seed may use smaller and larger thicknesses, respectively.

[0054] A first photoresist layer 165 can be deposited over the metal seed layer 164 and can be photolithographically patterned to form openings in areas where metal structures are subsequently to be formed. The thickness of the first photoresist layer 165 can be in the range of 2 microns to 20 microns, but lesser or greater thicknesses can also be used. Typically, the opening area in the first photoresist layer 165 includes the area of ​​the metal bonding pad structure 158 and the area where the metal bonding pad will be subsequently formed. In one embodiment, a subset of the openings in the first photoresist layer 165 can be formed with a low pattern factor.

[0055] As used herein, pattern factor refers to the local ratio of the area of ​​a pattern to the total local area. For each pattern having a minimum lateral dimension (commonly referred to as "critical dimension CD"), the local ratio of the pattern area to the total local area can be calculated by selecting a circle with a radius of 10 times the minimum lateral dimension for the local area. In other words, for an opening pattern having a minimum lateral dimension (such as minimum width), the pattern factor can be calculated by drawing a circle with a radius of 10 times the minimum lateral dimension, calculating the total area of ​​the openings within the circle, and dividing the total area of ​​the openings by the area of ​​the circle.

[0056] Reference Figure 2E , an electroplating process may be performed to electroplate copper or a copper-containing alloy in the opening region in the first photoresist layer 165. The copper-based metal portion 166 may be formed in the opening region in the first photoresist layer 165 by the electroplating process. According to one aspect of the present disclosure, process parameters of the electroplating process may be selected so that a deposition rate of the copper-based material of the copper-based metal portion 166 depends on a pattern factor of the opening in the first photoresist layer 165.

[0057] For example, the electroplating process can be performed under the following conditions, the supply of copper atoms in the electroplating path is insufficient to provide conformal growth of the copper-based metal, but a higher deposition rate is induced in the area of ​​the low pattern factor of the opening in the first photoresist layer 165, and a lower deposition rate is induced in the area of ​​the high pattern factor of the opening in the first photoresist layer 165. In this embodiment, the copper-based metal portion 166 can have a uniform thickness in the first area with a normal pattern factor, and can have a gradient thickness (i.e., a varying thickness) in the second area with a low pattern factor. The uniform thickness is also referred to as the normal thickness, and the first area is also referred to as the normal height area NHR. The gradient thickness is a varying thickness greater than the normal thickness, and the second area is also referred to as the extended height area EHR. The uniform thickness can be in the range of 1 micron to 10 microns, but smaller or larger thicknesses can also be used.

[0058] In one embodiment, at least one first copper-based metal portion 166 selected from the copper-based metal portions 166 includes at least one uniform thickness region (i.e., at least one normal height region NHR) and a gradually changing thickness region (i.e., an extended height region EHR). In this embodiment, the gradually changing thickness region of each such first copper-based metal portion 166 may be formed with at least one inclined top surface, each top surface having an inclination angle relative to a horizontal plane in the range of 0.1 to 10 degrees, for example, 0.3 to 5 degrees and / or 0.5 to 3 degrees. Each region of the copper-based metal portion 166 located above a horizontal plane including a flat horizontal top surface of a region having a uniform thickness of the copper-based metal portion 166 is referred to herein as an upper protruding portion 166P. In one embodiment, the first copper-based metal portion 166 may be electrically connected to the ESD protection circuit 122 via a discharge current path DCP. At least a second copper-based metal portion 166 selected from the copper-based metal portions 166 may have a uniform thickness and may therefore be composed of a single uniform thickness region (i.e., a normal height region NHR).

[0059] Typically, a first copper-based metal portion 166 including a corresponding upper protruding portion 166P and a second copper-based metal portion consisting of a corresponding normal height region NHR can be simultaneously formed using a single deposition process that provides a deposition rate that depends on a pattern factor. In one embodiment, the single deposition process may include an electroplating process that electroplates copper or a copper-containing alloy that includes copper at an atomic concentration of 98% or more. Typically, the first surface metal density in the area including the copper-based metal portion 166 (including the corresponding upper protruding portion 166P) is at least 3 times smaller than the second surface metal density in the area of ​​the additional copper-based metal portion consisting of the corresponding normal height region NHR. In an illustrative example, the first surface metal density can be in the range of 0.002 to 0.15; the second surface metal density can be in the range of 0.20 to 0.60, for example 0.35 to 0.50.

[0060] Reference Figure 2F , the first photoresist layer 165 may be removed, for example, by ashing. Subsequently, an isotropic etching process, such as a wet etching process, may be performed to remove the unmasked portions of the metal seed layer 164. Physically exposed surface portions of the copper-based metal portion 166 may be incidentally removed during the isotropic etching.

[0061] Each remaining continuous combination of the metal seed layer 164 and the first copper-based metal portion 166 including the corresponding upper protruding portion 166P is referred to herein as an electrostatic discharge (ESD) path metal structure 168. Each remaining continuous combination of the metal seed layer 164 and the second copper-based metal portion 166 consisting of the corresponding normal height region NHR is referred to herein as a passivation level metal structure 167. Generally, a passivation level metal structure 167 and at least one electrostatic discharge (ESD) path metal structure 168 may be formed. Each ESD path metal structure 168 includes a first top surface segment TSS1 located within a first horizontal plane HP1, which first horizontal plane HP1 contains the top surface of one, a plurality of and / or each passivation level metal structure 167. In addition, each ESD path metal structure 168 includes an upper protruding portion 166P protruding above the first horizontal plane HP1. In one embodiment, the entire passivation level metal structure 167 may be formed below the first horizontal plane HP1 or within the first horizontal plane HP1.

[0062] The passivation level metal structure 167 and the ESD path metal structure 168 may include respective via portions contacting respective underlying metal bonding pad structures 158. The uniform thickness UT of the horizontally extending portion of the passivation level metal structure 167 and the ESD path metal structure 168 outside the via portion area and outside the upper protrusion 166P area may be in the range of 1 micron to 8 microns, although lesser or greater thicknesses may also be used. The height of the upper protrusion 166P may be in the range of 10% to 80% of the uniform thickness UT and may be in the range of 400nm to 4 microns (e.g., 800nm ​​to 2 microns).

[0063] Common Reference Figure 1 and FIG. 2A to FIG. 2F , an electrostatic discharge (ESD) protection circuit 122 on the semiconductor substrate 110 and a metal interconnect structure 140 embedded in the dielectric material layer 150 may be formed over the semiconductor substrate 110. An ESD path metal structure 168 may be formed over the metal interconnect structure 140 and may be electrically connected to the ESD protection circuit 122 through a subset of the metal interconnect structure 140. In one embodiment, the passivation level metal structure 167 and the electrostatic discharge (ESD) path metal structure 168 are formed simultaneously using a single deposition process that provides a pattern factor-dependent deposition rate. In one embodiment, the passivation level metal structure 167 and the ESD path metal structure 168 are formed by performing at least one electroplating process.

[0064] The ESD path metal structure 168 includes a first top surface segment TSS1 located within a first horizontal plane HP1, which includes the top surface of one, multiple and / or each passivation level metal structure 167. In one embodiment, the upper protrusion 166P may be formed with at least one inclined top surface, each top surface having an inclination angle in the range of 0.1 degrees to 10 degrees relative to the first horizontal plane HP1. In one embodiment, the first surface metal density at the level of the passivation level metal structure 167 and the ESD path metal structure 168 in the area including the upper protrusion 166P of the ESD path metal structure 168 is at least 3 times less than the second surface metal density at the level of the passivation level metal structure 167 and the ESD path metal structure 168 in the area of ​​the passivation level metal structure 167.

[0065] Figure 3 1 is a top view of a region of the first embodiment structure after forming a discharge structure and a guide point of a passivation level metal structure 167 according to the first embodiment of the present disclosure. In this example, the entire passivation level metal structure 167 may be formed within the normal height region NHR, and the upper protruding portion 166P of the ESD path metal structure 168 may be formed in the extended height region EHR.

[0066] 4A to 4F During the formation of the metal bonding pad 178 and the attachment of the solder material portion 188 according to the first embodiment of the present disclosure Figure 1 Continuous vertical cross-sectional views of region M of the structure of the first embodiment.

[0067] Reference Figure 4A , a cap dielectric material such as polyimide may be deposited on the passivation level metal structure 167 and the ESD path metal structure 168 to form a cap dielectric layer 173. The thickness of the cap dielectric layer 173 may be in the range of 2 microns to 6 microns when measured above the horizontally extending portions of the passivation level metal structure 167 and the ESD path metal structure 168, but lesser or greater thicknesses may also be used. The cap dielectric layer 173 may be patterned to form a through-hole opening (179A, 179B) extending therethrough above the areas of the passivation level metal structure 167 and the ESD path metal structure 168. The through-hole opening (179A, 179B) may be formed through the cap dielectric layer 173 by performing an etching process. In some embodiments, the etching process may include an anisotropic etching process, such as a reactive ion etching process using a reactive ion plasma. Therefore, when a subset of the metal structures in the semiconductor die 700 is physically exposed to the plasma of the reactive ion etching process, a transient discharge from the plasma to the subset of the metal structures in the semiconductor die 700 may occur. Alternatively, the etching process may employ an alternative etching process known in the art.

[0068] According to one aspect of the present disclosure, the via openings (179A, 179B) include a first via opening 179A formed on a horizontally extending portion of the passivation level metal structure 167 and the ESD path metal structure 168 having a uniform thickness UT, and a second via opening 179B formed on the upper protruding portion 166P. The upper protruding portion 166P protrudes above the first horizontal plane HP1, and the anisotropic etching process that forms the first via opening 179A and the second via opening 179B etches the material of the capping dielectric layer 173 at the same etching rate. Therefore, during the anisotropic etching process, before the first top surface segment TSS1 of the ESD path metal structure 168 is exposed below the first via opening 179A, the surface of the upper protruding portion 166P is physically exposed below the second via opening 179B.

[0069] Figure 4A This corresponds to a time point during the anisotropic etching process at which the surface of the upper protrusion 166P is physically exposed below the second via opening 179B, while the first top surface segment TSS1 of the ESD path metal structure 168 is still covered by the material of the cap dielectric layer 173. When the surface of the upper protrusion 166P is physically exposed to the plasma environment in the anisotropic etching process chamber, a discharge current path (DCP) may occur from the plasma through the ESD path metal structure 168 and the discharge current path (DCP; e.g., Figure 1 ) into the ESD protection circuit 122 (as shown Figure 1 168) to protect the semiconductor device 120 electrically connected to the ESD path metal structure 168 from the transient surge of charge in the ESD path metal structure 168. Therefore, the upper protruding portion 166P of the ESD path metal structure 168 serves as a discharge guiding point (LPoD) structure, which is exposed to the plasma during the anisotropic etching process before other metal structures in the semiconductor die 700 are exposed, thereby serving as a connection point for the discharge path in the semiconductor die 700 at the moment of exposure to the plasma.

[0070] Reference Figure 4B, the anisotropic etching process can continue until the first via opening 179A extends vertically to the corresponding underlying portions of the passivation level metal structure 167 and the ESD path metal structure 168. After the anisotropic etching process, the surfaces of the passivation level metal structure 167 and the ESD path metal structure 168 can be physically exposed below the first via opening 179A and the second via opening 179B. Each via opening (179A, 179B) can have at least one tapered sidewall extending from the top surface of the cap dielectric layer 173 to the top surface of one of the passivation level metal structure 167 and the ESD path metal structure 168. The tapered angle of the tapered sidewall measured from the vertical direction can be in the range of 5 degrees to 60 degrees, for example 10 degrees to 45 degrees, but smaller or larger tapered angles can also be used. The lateral dimension of the bottom of each via opening (179A, 179B) (e.g., the diameter or width of the physically exposed surface of a corresponding one of the passivation level metal structure 167 and the ESD path metal structure 168) can be in the range of 30 microns to 50 microns, although smaller or larger lateral dimensions may also be used.

[0071] The cover dielectric layer 173 may have a flat top surface located within the second horizontal plane HP2. The thickness of the cover dielectric layer 173 may be in the range of 2 microns to 6 microns as measured between the second horizontal plane HP2 and the first horizontal plane HP1 including the first top surface segment TSS1, although smaller or larger thicknesses may also be used. The height of the upper protrusion 166P may be in the range of 400 nm to 4 microns. The ratio of the height of the upper protrusion 166P to the thickness of the cover dielectric layer 173 may be in the range of 0.2 to 0.8, although smaller or larger ratios may also be used.

[0072] Reference Figure 4C , a metal seed layer 174 may be formed over the cap dielectric layer 173. The metal seed layer 174 includes at least one metal material, which may be used as an adhesion promoter material, a diffusion barrier material, and / or a metal seed material for a subsequent electroplating process. For example, the metal seed layer 174 may include a stack of a titanium layer and a copper seed layer, which may be deposited by physical vapor deposition. The thickness of the titanium layer may be in the range of 5nm to 100nm, and the thickness of the copper seed layer may also be in the range of 50nm to 500nm. However, the titanium layer and the copper seed may use smaller and larger thicknesses, respectively.

[0073] A second photoresist layer 175 may be deposited over the metal seed layer 174 and may be photolithographically patterned to form openings in areas where metal bonding pads are subsequently to be formed. The thickness of the second photoresist layer 175 may be in the range of 2 microns to 20 microns, but smaller or larger thicknesses may also be used. The area for forming the metal bonding pads corresponds to the area of ​​the through-hole openings (179A, 179B) through the cover dielectric layer 173. The lateral dimensions of each opening in the second photoresist layer 175 (e.g., in embodiments where each opening has a rectangular or rounded rectangular shape, it may be a width) may be in the range of 50 microns to 80 microns, but smaller or larger lateral dimensions may also be used.

[0074] Reference Figure 4D , metal may be deposited within the opening in the second photoresist layer 175. For example, an electroplating process may be performed to electroplate copper or a copper-containing alloy within the opening region in the second photoresist layer 175. The pad-level metal portion 176 may be formed within the opening region in the second photoresist layer 175 by the electroplating process.

[0075] Reference Figure 4E , for example, the second photoresist layer 175 can be removed by ashing. Subsequently, an isotropic etching process, such as a wet etching process, can be performed to remove the unmasked portion of the metal seed layer 174. During the isotropic etching process, the physically exposed surface portion of the pad level metal portion 176 can be removed incidentally. Each remaining continuous combination of the metal seed layer 164 and the pad level metal portion 176 constitutes a metal bonding pad 178. Although the present disclosure is described using an embodiment in which the metal bonding pad 178 includes copper, embodiments in which the metal bonding pad 178 includes an aluminum-based metal material or other alternative metal material are explicitly considered herein. Typically, the metal bonding pad 178 is formed on the passivation level metal structure 167 and the ESD path metal structure 168. Each metal bonding pad 178 may include a corresponding through-hole portion and a corresponding pad portion.

[0076] According to one aspect of the present disclosure, a first metal bonding pad 178A may be formed directly in each first via opening 179A on the first top surface segment TSS1 of a corresponding one of the ESD path metal structures 168, and a second metal bonding pad 178B may be formed directly in each second via opening 179B on the top surface of the upper protrusion 166P of a corresponding one of the ESD path metal structures 168. The flat top surface of the cap dielectric layer 173 may be formed in a second horizontal plane HP2 overlying the first horizontal plane HP1. In one embodiment, each of the first metal bonding pad 178A and the second metal bonding pad 179B may be formed with a corresponding planar portion overlying the second horizontal plane HP2 and a corresponding via portion located below the second horizontal plane HP2 and extending vertically through the cap dielectric layer 173. Typically, the via portion of each first metal bonding pad 178A has a larger vertical extent than the via portion of each second metal bonding pad 1789B.

[0077] Reference Figure 4F , solder material portions 188, such as solder balls, may be attached to metal bonding pads 178. For example, first solder material portions 188A may be attached to each first metal bonding pad 178A, and second solder material portions 188B may be attached to each second metal bonding pad 178B. Subsequently, the semiconductor wafer including the two-dimensional array of semiconductor dies 700 may be singulated along the dicing lanes to separate the semiconductor dies 700.

[0078] Figure 5 1 is a vertical cross-sectional view of a semiconductor die 700 after dicing according to the first embodiment of the present disclosure. The combination of the first passivation dielectric layer 161 , the second passivation dielectric layer 163 and the capping dielectric layer 173 is denoted as a bonding level dielectric layer 170 .

[0079] FIG. 6A to FIG. 6I 1 are sequential vertical cross-sectional views of regions of an alternative configuration of the first embodiment structure during formation of guiding points and metal bonding pads of the discharge structure and attachment of solder material portions 188 according to the first embodiment of the present disclosure.

[0080] Reference Fig. 6A , in the Figure 2E An alternative configuration of the first embodiment structure is shown at a processing step corresponding to the processing step of . In this embodiment, the electroplating process that forms the copper-based metal portion 166 may or may not conformally deposit the copper-based material. Each copper-based metal portion 166 includes a flat top surface that may be completely located in a horizontal plane, or may include a vertical protrusion that protrudes above a horizontal plane including a horizontal top surface segment of the corresponding copper-based metal portion 166. The first photoresist layer 165 can then be removed, for example, by ashing.

[0081] Reference Figure 6B , an additional photoresist layer 169 (which may be referred to as a second photoresist layer in the present application) may be applied to the metal seed layer 164 and the copper-based metal portion 166, and may be photolithographically patterned to form openings therein. Each opening in the additional photoresist layer 169 may have an area that is completely within the area of ​​the copper-based metal portion 166 below. An additional electroplating process may be performed to form an upper protrusion 166P within each opening in the additional photoresist layer 169. Each upper protrusion 166P may have a corresponding planar top surface segment. The height of each upper protrusion 166P may be in the range of 400nm to 4 microns, for example 800nm ​​to 2 microns, but smaller or larger heights may also be used.

[0082] Reference Figure 6C , the additional photoresist layer 169 may be removed, for example, by ashing. Subsequently, an isotropic etching process, such as a wet etching process, may be performed to remove the unmasked portion of the metal seed layer 164. Physically exposed surface portions of the copper-based metal portion 166 may be incidentally removed during the isotropic etching process.

[0083] Each remaining continuous combination of the metal seed layer 164 and the first copper-based metal portion 166 including the corresponding upper protrusion 166P is referred to herein as an electrostatic discharge (ESD) path metal structure 168. Each remaining continuous combination of the metal seed layer 164 and the second copper-based metal portion 166 not including any upper protrusion 166P is referred to herein as a passivation level metal structure 167. Generally, a passivation level metal structure 167 and at least one electrostatic discharge (ESD) path metal structure 168 can be formed. Each ESD path metal structure 168 includes a first top surface segment TSS1 located within a first horizontal plane HP1, which first horizontal plane HP1 contains the top surface of one, a plurality of and / or each passivation level metal structure 167. In addition, each ESD path metal structure 168 includes an upper protrusion 166P protruding above the first horizontal plane HP1. In one embodiment, the entire passivation level metal structure 167 can be formed below the first horizontal plane HP1 or within the first horizontal plane HP1.

[0084] The passivation level metal structure 167 and the ESD path metal structure 168 may include respective via portions contacting respective underlying metal bonding pad structures 158. The uniform thickness UT of the horizontally extending portions of the passivation level metal structure 167 and the ESD path metal structure 168 outside the via portion area and outside the upper protrusion 166P area may be in the range of 1 micron to 8 microns, although lesser or greater thicknesses may also be used. The height of the upper protrusion 166P may be in the range of 10% to 80% of the uniform thickness UT, and may be in the range of 400nm to 4 microns (e.g., 800nm ​​to 2 microns).

[0085] Typically, the passivation level metal structure 167 and the ESD path metal structure 168 can be formed by performing at least one electroplating process. In one embodiment, the ESD path metal structure 168 can be formed by two electroplating processes using two electroplating mask layers. In one embodiment, each upper protrusion 166P can be formed with a flat top surface segment and at least one vertical surface segment having a bottom periphery within the first horizontal plane HP1. In one embodiment, at least one uniform thickness region of the passivation level metal structure 167 and the ESD path metal structure 168 that does not overlap with the upper protrusion 166P is formed by a first metal deposition process (such as a first electroplating process), and the upper protrusion 166P is formed by a second metal deposition process (such as a second electroplating process) performed after the first metal deposition process.

[0086] Reference Fig.6D , you can execute the reference Figure 4A The processing steps described are to form the cap dielectric layer 173, and to form via openings (179A, 179B) extending vertically through the cap dielectric layer 173. According to one aspect of the present invention, the via openings (179A, 179B) include a first via opening 179A formed on a horizontally extending portion of the passivation level metal structure 167 and the ESD path metal structure 168 having a uniform thickness UT, and a second via opening 179B formed on the upper protruding portion 166P. The upper protruding portion 166P protrudes above the first horizontal plane HP1, and the anisotropic etching process that forms the first via opening 179A and the second via opening 179B etches the material of the cap dielectric layer 173 at the same etching rate. Therefore, during the anisotropic etching process, the surface of the upper protruding portion 166P is physically exposed under the second via opening 179B before the first top surface segment TSS1 of the ESD path metal structure 168 is exposed under the first via opening 179A.

[0087] Fig.6DThis corresponds to a time point during the anisotropic etching process at which the surface of the upper protrusion 166P is physically exposed below the second via opening 179B, while the first top surface segment TSS1 of the ESD path metal structure 168 is still covered by the material of the cap dielectric layer 173. When the surface of the upper protrusion 166P is physically exposed to the plasma environment in the anisotropic etching process chamber, a discharge current path (DCP) may occur from the plasma through the ESD path metal structure 168 and the discharge current path (DCP; e.g., Figure 1 ) into the ESD protection circuit 122 (as shown Figure 1 168) to protect the semiconductor device 120 electrically connected to the ESD path metal structure 168 from the transient surge of charge in the ESD path metal structure 168. Therefore, the upper protruding portion 166P of the ESD path metal structure 168 serves as a discharge guiding point (LPoD) structure, which is exposed to the plasma during the anisotropic etching process before other metal structures in the semiconductor die 700 are exposed, thereby serving as a connection point for the discharge path in the semiconductor die 700 at the moment of exposure to the plasma.

[0088] Reference Fig. 6E , the anisotropic etching process can continue until the first via opening 179A extends vertically to the corresponding lower portions of the passivation level metal structure 167 and the ESD path metal structure 168. After the anisotropic etching process, the surfaces of the passivation level metal structure 167 and the ESD path metal structure 168 can be physically exposed below the first via opening 179A and the second via opening 179B. Each via opening (179A, 179B) can have at least one tapered sidewall extending from the top surface of the cap dielectric layer 173 to the top surface of one of the passivation level metal structure 167 and the ESD path metal structure 168. The tapered angle of the tapered sidewall measured from the vertical direction can be in the range of 5 degrees to 60 degrees, for example 10 degrees to 45 degrees, but smaller or larger tapered angles can also be used. The lateral dimension of the bottom of each via opening (179A, 179B) (e.g., the diameter or width of the physically exposed surface of a corresponding one of the passivation level metal structure 167 and the ESD path metal structure 168) can be in the range of 30 microns to 50 microns, although smaller or larger lateral dimensions may also be used.

[0089] The cover dielectric layer 173 may have a flat top surface located within the second horizontal plane HP2. The thickness of the cover dielectric layer 173 may be in the range of 2 microns to 6 microns as measured between the second horizontal plane HP2 and the first horizontal plane HP1 including the first top surface segment TSS1, although smaller or larger thicknesses may also be used. The height of the upper protrusion 166P may be in the range of 400 nm to 4 microns. The ratio of the height of the upper protrusion 166P to the thickness of the cover dielectric layer 173 may be in the range of 0.2 to 0.8, although smaller or larger ratios may also be used.

[0090] Reference Fig. 6F , a metal seed layer 174 may be formed over the cap dielectric layer 173. The metal seed layer 174 includes at least one metal material, which may be used as an adhesion promoter material, a diffusion barrier material, and / or a metal seed material for a subsequent electroplating process. For example, the metal seed layer 174 may include a stack of a titanium layer and a copper seed layer, which may be deposited by physical vapor deposition. The thickness of the titanium layer may be in the range of 5nm to 100nm, and the thickness of the copper seed layer may also be in the range of 50nm to 500nm. However, the titanium layer and the copper seed may use smaller and larger thicknesses, respectively.

[0091] A second photoresist layer 175 may be deposited over the metal seed layer 174 and may be photolithographically patterned to form openings in areas where metal bonding pads are subsequently to be formed. The thickness of the second photoresist layer 175 may be in the range of 2 microns to 20 microns, but smaller or larger thicknesses may also be used. The area for forming the metal bonding pads corresponds to the area of ​​the through-hole openings (179A, 179B) through the cover dielectric layer 173. The lateral dimensions of each opening in the second photoresist layer 175 (e.g., in embodiments where each opening has a rectangular or rounded rectangular shape, it may be a width) may be in the range of 50 microns to 80 microns, but smaller or larger lateral dimensions may also be used.

[0092] Reference Figure 6G , metal may be deposited within the opening in the second photoresist layer 175. For example, an electroplating process may be performed to electroplate copper or a copper-containing alloy within the opening region in the second photoresist layer 175. The pad-level metal portion 176 may be formed within the opening region in the second photoresist layer 175 by the electroplating process.

[0093] Reference Figure 6H, for example, the second photoresist layer 175 can be removed by ashing. Subsequently, an isotropic etching process, such as a wet etching process, can be performed to remove the unmasked portion of the metal seed layer 174. During the isotropic etching process, the physically exposed surface portion of the pad level metal portion 176 can be removed incidentally. Each remaining continuous combination of the metal seed layer 164 and the pad level metal portion 176 constitutes a metal bonding pad 178. Although the present disclosure is described using an embodiment in which the metal bonding pad 178 includes copper, embodiments in which the metal bonding pad 178 includes an aluminum-based metal material or other alternative metal material are explicitly considered herein. Typically, the metal bonding pad 178 is formed on the passivation level metal structure 167 and the ESD path metal structure 168. Each metal bonding pad 178 may include a corresponding through-hole portion and a corresponding pad portion.

[0094] According to one aspect of the present disclosure, a first metal bonding pad 178A may be formed directly in each first via opening 179A on the first top surface segment TSS1 of a corresponding one of the ESD path metal structures 168, and a second metal bonding pad 178B may be formed directly in each second via opening 179B on the top surface of the upper protrusion 166P of an appropriate one of the ESD path metal structures 168. The flat top surface of the cap dielectric layer 173 may be formed in a second horizontal plane HP2 covering the first horizontal plane HP1. In one embodiment, each of the first metal bonding pad 178A and the second metal bonding pad 178B may be formed with a corresponding planar portion covering the second horizontal plane HP2 and a corresponding via portion located below the second horizontal plane HP2 and extending vertically through the cap dielectric layer 173. Typically, the via portion of each first metal bonding pad 178A has a larger vertical extent than the via portion of each second metal bonding pad 178B.

[0095] Reference Fig.6I , solder material portions 188, such as solder balls, may be attached to metal bonding pads 178. For example, a first solder material portion 188A may be attached to each first metal bonding pad 178A, and a second solder material portion 188B may be attached to each second metal bonding pad 178B.

[0096] Subsequently, the semiconductor wafer including the two-dimensional array of semiconductor dies 700 may be diced along dicing streets to separate the semiconductor dies 700 .

[0097] Common Reference Figure 4F , Figure 5 and Fig.6IAccording to a first embodiment of the present disclosure, a device structure is provided, which includes: a semiconductor device 120 located on a semiconductor substrate 110; a passivation level metal structure 167 and an electrostatic discharge (ESD) path metal structure 168 embedded in a cover dielectric layer 173, wherein the ESD path metal structure 166 includes a first top surface segment TSS1 located in a first horizontal plane HP1, the first horizontal plane HP1 includes a top surface of one of the passivation level metal structures 167, and also includes an upper protrusion 166P protruding above the first horizontal plane HP1; a first metal bonding pad 178A, which has a flat bottom surface contacting the first top surface segment TSS1; and a second metal bonding pad 178B contacting the top surface of the upper protrusion 166P.

[0098] In one embodiment, the device structure further includes: a first solder material portion 188A in contact with the first metal bonding pad 178A; and a second solder material portion 188B in contact with the second metal bonding pad 178B. In one embodiment, the upper protrusion 166P has at least one inclined top surface, and the inclination angle of each top surface relative to the first horizontal plane HP1 is in the range of 0.1 degrees to 10 degrees. In one embodiment, the first surface metal density at the level of the passivation level metal structure 167 and the electrostatic discharge (ESD) path metal structure 168 in the area of ​​the upper protrusion 166P including the ESD path metal structure 168 is less than the second surface metal density at the level of the passivation level metal structure 167 and the electrostatic discharge (ESD) path metal structure 168 in the area of ​​the passivation level metal structure 167 by at least 3 times. In another embodiment, the upper protrusion 166P includes a planar top surface segment and at least one vertical surface segment, the vertical surface segment having a bottom periphery in the first horizontal plane HP1.

[0099] In one embodiment, the upper protruding portion 166P of the ESD path metal structure 168 has the same material composition as a portion of the passivation level metal structure 167 below the first horizontal plane HP1. In one embodiment, the upper protruding portion 166P of the ESD path metal structure 168 includes at least 98 atomic percent copper.

[0100] In one embodiment, a second horizontal plane HP2 including a flat top surface of cover dielectric layer 173 is located above first horizontal plane HP1; and each of first metal bonding pad 178A and second metal bonding pad 178B includes a corresponding planar portion covering second horizontal plane HP2 and a corresponding via portion located below second horizontal plane HP2 and extending vertically through cover dielectric layer 173. In one embodiment, the via portion of first metal bonding pad 178A has a greater vertical extent than the via portion of second metal bonding pad 178B.

[0101] In one embodiment, the device structure also includes: an electrostatic discharge (ESD) protection circuit 122 located on the semiconductor substrate 110; and a metal interconnect structure 140 embedded in a dielectric material layer 150 located between the semiconductor substrate 110 and a cover dielectric layer 173, wherein an ESD path metal structure 168 is electrically connected to the ESD protection circuit 122 through a subset of the metal interconnect structure 140.

[0102] FIG. 7A to FIG. 7D 2 are sequential vertical cross-sectional views of the structure of the second embodiment during pilot point formation of the discharge structure according to the second embodiment of the present disclosure.

[0103] Reference Fig. 7A , the second embodiment structure includes a carrier substrate 210, which may be a carrier wafer, upon which a reconstructed wafer including a two-dimensional array of repeating units may subsequently be formed, each repeating unit including a corresponding composite die. Fig. 7A The area shown in corresponds to the unit area of ​​a single repeating unit in which a single composite die is subsequently formed. Fig. 7A The structure shown can be repeated in two horizontal directions to provide a two-dimensional periodic array of repeating units. The shown portion of the carrier substrate 210 is the portion of the carrier substrate 210 that is located within the region of a single repeating unit. The carrier substrate 210 can be any type of carrier substrate for forming a reconstructed wafer thereon. For example, the carrier substrate 210 can include a silicon wafer, a glass wafer, a sapphire wafer, or any other recyclable wafer.

[0104] The adhesive layer 211 may be applied to the top surface of the carrier substrate 210. At least one semiconductor die 700 may be attached to the adhesive layer 211 within each unit region, so that a two-dimensional periodic array of at least one semiconductor die 700 may be attached to the carrier substrate 210. In one embodiment, each group of at least one semiconductor die 700 is disposed within a corresponding unit region and may include at least two semiconductor die 700, including a first semiconductor die 700 and a second semiconductor die 700. The first semiconductor die 700 and the second semiconductor die 700 may be disposed on the carrier substrate 210 with a gap therebetween. Each semiconductor die 700 may be attached to the adhesive layer 211 within each unit region, so that a two-dimensional periodic array of at least one semiconductor die 700 may be attached to the carrier substrate 210. Figure 2B The processing steps described above (i.e., by depositing and patterning the first passivation dielectric layer 161) and by depositing the second passivation dielectric layer 163 thereon) are performed to form a passivation layer. Figure 1 The semiconductor die 700 shown is derived. Subsequently, at least two semiconductor dies 700 may be attached to the carrier substrate 210 in each unit area.

[0105] Typically, the first semiconductor die 700 and the second semiconductor die 700 may be attached to the carrier substrate 210. The first semiconductor die 700 includes a first semiconductor substrate 110 and a first electrostatic discharge (ESD) protection circuit 122 electrically connected to the first semiconductor substrate 100. The second semiconductor die 700 includes a second semiconductor substrate 110 and a second electrostatic discharge (ESD) protection circuit 122 electrically connected to the second semiconductor substrate 110. Figure 1 As shown, a discharge current path DCP may be provided in each semiconductor die 700 .

[0106] Reference Figure 7B , the molding compound material may be applied to the gap between the adjacent pairs of semiconductor dies 700. A planarization process (e.g., chemical mechanical polishing (CMP)) and a curing process may be performed to form a molding compound matrix 220M. The molding compound matrix 220M laterally surrounds and embeds each semiconductor die 700. The combination of the molding compound matrix 220M and the semiconductor die 700 constitutes a reconstructed wafer, which may have the same lateral extent as the carrier substrate 210. In one embodiment, the top surface of the second passivation dielectric layer 163 of the semiconductor die 700 may be coplanar with the top surface of the molding compound matrix 220M. Each portion of the molding compound matrix 220M located in the corresponding unit area constitutes a molding compound die frame, which laterally surrounds a corresponding group of at least one semiconductor die 700 in the corresponding unit area.

[0107] Reference Figure 7C Through a combination of photolithography processing steps and anisotropic etching processes, a via opening may be formed through the second passivation dielectric layer 163. A top surface of the metal bonding pad structure 158 may be physically exposed through the second passivation dielectric layer 163 below the via opening.

[0108] Reference Fig.7D , you can execute the reference Figure 2D-2F Processing steps described or referenced Figure 2D , Figure 2E and FIG. 6A to FIG. 6CThe process described above is to form patterned metal structures (167, 168). The patterned metal structures (167, 168) in each unit area include a first passivation level metal structure 167 formed on the first semiconductor die 700, a second passivation level metal structure 167 formed on the second semiconductor die 700, and at least one electrostatic discharge (ESD) path metal structure 168 formed on the top surface of the molding compound die frame (which is a part of the molding compound matrix 220M located in the unit area) and electrically connected to the first ESD protection circuit 122 in the first semiconductor die 700, and can be electrically connected to the second ESD protection circuit 122 in the second semiconductor die 700. In one embodiment, the at least one ESD path metal structure 168 extends through the molding compound matrix and is formed on the top surface of the first semiconductor die 700 and the top surface of the second semiconductor die 700.

[0109] In general, each ESD path metal structure 168 in the second embodiment structure may have any of the features described with reference to the first embodiment structure, but a possible modification is that at least one ESD path metal structure 168 may be formed above and directly on the molding compound matrix 220M. In one embodiment, the ESD path metal structure 168 in the second embodiment structure may include a first top surface segment TSS1 located within a first horizontal plane HP1, the first horizontal plane HP1 including a top surface of one of the first passivation level metal structures 167 and a top surface of one of the second passivation level metal structures 167, and also including an upper protruding portion 166P protruding above the first horizontal plane HP1. In general, the first passivation level metal structure 167 and the ESD path metal structure 168 are formed by performing at least one electroplating process.

[0110] Fig. 8A According to the second embodiment of the present disclosure Fig.7D A top view of a region of the structure of the second embodiment. Fig.7D and Fig. 8A In a plan view, at least one upper protrusion 166P has an area overlap with the molding compound mold frame 220. The molding compound die frame 220 is a portion of the molding compound matrix 220M, which is located in a unit area of ​​a two-dimensional periodic array consisting of at least two semiconductor dies 700. The molding compound die frame 220 at least laterally surrounds the first semiconductor die 700 and the second semiconductor die 700.

[0111] exist Fig. 8AIn the illustrated configuration, the upper protrusion 166P may be formed with a flat top surface segment and at least one vertical surface segment having a bottom edge within the first horizontal plane HP1. In one embodiment, the uniform thickness regions of the first passivation level metal structure 167 and the ESD path metal structure 168 that do not overlap with the upper protrusion 166P are formed by a first metal deposition process; the upper protrusion 166P is formed by a second metal deposition process performed after the first metal deposition process.

[0112] Figure 8B is a top view of an area of ​​an alternative configuration of a second embodiment structure according to a second embodiment of the present disclosure. Fig.7D and Figure 8B , in a plan view, at least one upper protrusion 166P has an area overlap with the molded material frame 220. Typically, the first passivation level metal structure 167 and each ESD path metal structure 168 are formed by performing at least one electroplating process. In one embodiment, the first passivation level metal structure 167 and each electrostatic discharge (ESD) path metal structure 168 are simultaneously formed using a single deposition process that provides a pattern factor-dependent deposition rate.

[0113] In one embodiment, the upper protrusion 166P is formed with at least one inclined top surface, each of which has an inclination angle with respect to the first horizontal plane HP1 in the range of 0.1 to 10 degrees. In one embodiment, the first-plane metal density at the level of the patterned metal structure (167, 168) in the region of the upper protrusion 166P including the ESD path metal structure 168 is at least 3 times less than the second-area metal density at the level of the patterned metal structure (167, 168) in the region of the passivation level metal structure 167.

[0114] Common Reference Fig.7D , Fig. 8A and Figure 8BIn one embodiment, the first semiconductor die 700 includes a first semiconductor device 120 located on a first semiconductor substrate 110 and a first metal interconnect structure 140 embedded in a first dielectric material layer 150; the first semiconductor device 120 includes a first field effect transistor; the ESD path metal structure 168 is electrically connected to a node of one of the first field effect transistors through a subset of the first metal interconnect structure 140 in the first semiconductor die 700. In one embodiment, the second semiconductor die 700 includes a second semiconductor device 120 located on a second semiconductor substrate 110 and a second metal interconnect structure 140 embedded in a second dielectric material layer 150; the second semiconductor device 120 includes a second field effect transistor; and the ESD path metal structure 168 is electrically connected to a node of one of the second field effect transistors through a subset of the second metal interconnect structure 140 in the second semiconductor die 700.

[0115] 9A to 9C are sequential vertical cross-sectional views of the second embodiment structure of a fan-out package according to the second embodiment of the present disclosure during dicing and attachment to an interposer.

[0116] Reference Fig. 9A , you can execute the reference 4A to 4F Processing steps described or referenced Figure 6D-Figure 6I The processing steps are described to form the capping dielectric layer 173 and the metal bonding pad 178, and to attach the solder material portion 188 to the metal bonding pad 176. The capping dielectric layer 173 can be formed on the patterned metal structures (167, 168) such that a flat top surface of the capping dielectric layer 173 is formed in a second horizontal plane HP2 overlying the first horizontal plane HP1.

[0117] The metal bonding pads 178 include a first metal bonding pad 178A and a second metal bonding pad 178B. Each of the first metal bonding pad 178A and the second metal bonding pad 1789B is formed with a corresponding plane portion overlying the second horizontal plane HP2 and a corresponding through-hole portion located below the second horizontal plane HP2 and extending vertically through the cover dielectric layer 173. Each first metal bonding pad 178A can be formed on a horizontal top surface of a corresponding patterned metal structure (167, 168) located within the first horizontal plane HP1, and the second metal bonding pad 178B can be formed on a horizontal or non-horizontal surface of a corresponding upper protrusion 166P located above the first horizontal plane HP1. Therefore, the through-hole portion of each first metal bonding pad 178A has a larger vertical range than the through-hole portion of the second metal bonding pad 178B.

[0118] In one embodiment, a first metal bonding pad 178A and a second metal bonding pad 1789B may be formed over and directly on the ESD path metal structure 168. The first metal bonding pad 178A has a flat bottom surface that contacts the first top surface segment TSS1; the second metal bonding pad 178B contacts the top surface of the upper protrusion 166P. In some embodiments, the first metal bonding pad 178A has an area overlap with the molded material die frame 220 in a plan view; and the second metal bonding pad 178B is completely located within the area of ​​the first semiconductor die 700 in a plan view. Subsequently, the solder material portion 188 may be attached to the metal bonding pad 178.

[0119] Reference Fig. 9B , for example, by decomposing the adhesive layer 211, the carrier substrate 210 can be separated from the reconstructed wafer (700, 220M). An appropriate cleaning process can be performed to remove the residue of the adhesive layer 211. Subsequently, the reconstructed wafer (700, 220M) can be cut along the cutting streets to form a plurality of fan-out packages 720, one of which is Fig. 9B Each fan-out package 720 may be a composite semiconductor die including a plurality of semiconductor dies 700 and a molding compound die frame 220 , which is a cut portion of a molding compound matrix 220M.

[0120] Reference Fig. 9C , an interposer 800 including an interposer pad 878 may be provided. The interposer 800 may include an organic interposer, a ceramic interposer, or any other type of interposer known in the art. The fan-out package 720 may be bonded to the interposer 800 via the solder material portion 188 .

[0121] Fig. 9C The second embodiment structure shown includes a device structure, which includes: a molded plastic die frame 220 laterally surrounding a first semiconductor die 700 and a second semiconductor die 700; a first passivation level metal structure 167 overlying the first semiconductor die 700; a second passivation level metal structure 167 overlying the second semiconductor die 700; an electrostatic discharge (ESD) path metal structure 168 overlying the first semiconductor die 700, the molded plastic die frame 220, and the second semiconductor die 700, wherein the ESD path metal structure Structure 168 includes a first top surface segment TSS1 located in a first horizontal plane HP1, which includes a top surface of one of the first passivation level metal structures 167 and a bottom surface of one of the second passivation level metal structures 167, and also includes an upper protrusion 166P protruding above the first horizontal plane HP1; a first metal bonding pad 178A having a flat bottom surface contacting the first top surface segment TSS1; and a second metal bonding pad 178B contacting the top surface of the upper protrusion 166P.

[0122] In one embodiment, the device structure further includes: a first solder material portion 188A in contact with the first metal bonding pad 178A; and a second solder material portion 188B in contact with the second metal bonding pad 178B. In one embodiment, the first metal bonding pad 178A has an area overlap with the molded material die frame 220 in a plan view; and the second metal bonding pad 178B is completely located within the area of ​​the first semiconductor die 700 in a plan view. In one embodiment, the upper protrusion 166P has an area overlap with the molded material die frame 220 in a plan view.

[0123] In one embodiment, the upper protrusion 166P has at least one inclined top surface, each of which has an inclination angle with respect to the first horizontal plane HP1 in the range of 0.1 to 10 degrees. In one embodiment, the device structure includes a cap dielectric layer 173 embedding the first passivation level metal structure 167, the second passivation level metal structure 167, and the ESD path metal structure 168, wherein the first surface metal density at the level of the first passivation level metal structure 167 and the second passivation level metal structure 167 in the region of the upper protrusion 166P including the ESD path metal junction 168 is less than the second surface metal density at the level of the first passivation level metal structure 167 and the second passivation level metal structure 167 in the region of the first passivation level metal structure 167 by at least 3 times.

[0124] In one embodiment, the upper protrusion 166P includes a flat top surface segment and at least one vertical surface segment having a bottom periphery in the first horizontal plane HP1.

[0125] In one embodiment, the upper protrusion 166P of the ESD path metal structure 168 has the same material composition as a portion of the first passivation level metal structure 167 below the first horizontal plane HP1. In one embodiment, the upper protrusion 166P of the ESD path metal structure 168 includes at least 98 atomic percent copper.

[0126] In one embodiment, a second horizontal plane HP2 including a planar top surface of cover dielectric layer 173 is located above first horizontal plane HP1; and each of first metal bonding pad 178A and second metal bonding pad 178B includes a respective planar portion overlying second horizontal plane HP2 and a respective via portion located below second horizontal plane HP2 and extending vertically through cover dielectric layer 173. In one embodiment, the via portion of first metal bonding pad 178A has a greater vertical extent than the via portion of second metal bonding pad 1789B.

[0127] In one embodiment, the first semiconductor die 700 includes: a first semiconductor device 120 located on a first semiconductor substrate 110; a first metal interconnect structure 140 embedded in a first dielectric material layer 150 located between the first semiconductor substrate 110 and a cap dielectric layer 173, wherein an ESD path metal structure 168 is electrically connected to an ESD protection circuit 122 through a subset of the first metal interconnect structure 140. In one embodiment, the first semiconductor device 120 includes a first field effect transistor; and the ESD path metal structure 168 is electrically connected to a node of one of the first field effect transistors through a subset of the first metal interconnect structure 140.

[0128] FIG. 10A to FIG. 10F 7 are sequential vertical cross-sectional views of the third embodiment structure during formation of a bonded assembly of two semiconductor dies 700 according to the third embodiment of the present disclosure.

[0129] Reference Fig. 10A , providing a first semiconductor die 300, which may be formed by omitting the formation of the metal bonding pad structure 158 and by forming a first metal bonding pad 358 configured for metal-to-metal bonding. Figure 1 The first semiconductor die 700 shown is derived from. Metal-to-metal bonding refers to direct bonding between two metal surfaces using any intermediate solder. In this embodiment, a subset of grain boundaries between a first metal in a first metal bonding pad and a second metal in a second metal bonding pad crosses an initial boundary between the first metal bonding pad and the second metal bonding pad, such that the second metal is bonded to the first metal through the grain boundaries. A typical example of metal-to-metal bonding is copper-to-copper bonding.

[0130] In one embodiment, each first metal bonding pad 358 may have a lateral length in the range of 2 microns to 10 microns and a lateral width in the range of 2 μm to 10 μm. In some embodiments, first metal bonding pads 358 may be arranged in a two-dimensional periodic array having a first pitch along a first horizontal direction and a second pitch along a second horizontal direction. The first pitch and the second pitch may be in the range of 25 microns to 120 microns, although smaller or larger pitches may also be used.

[0131] In one embodiment, the first semiconductor die 300 includes a first semiconductor substrate 310, a first semiconductor device 120 located on the first semiconductor substrate 320, and a first dielectric material layer 350 and a first metal bonding pad 358 in which a first metal interconnect structure 340 is buried. The first semiconductor die 300 may include a first electrostatic discharge (ESD) protection circuit 122 located on the first semiconductor substrate 310. In one embodiment, the first metal bonding pad 358 includes a first type first metal bonding pad 358A that is not electrically connected to the first ESD protection circuit 122 and a second type first metal bonding pad 358B that is electrically connected to the first ESD protection circuit 122. In this embodiment, the first type first metal bonding pad 358A is electrically isolated from the first ESD protection circuit 122. Therefore, a discharge current path DCP is provided between each second type first metal bonding pad 358B and the first ESD protection circuit 122.

[0132] exist Fig. 10A In the illustrated processing steps, the first type first metal bonding pad 358A and the second type first metal bonding pad 358B may have the same first uniform thickness, referred to herein as the first thickness. In one embodiment, the first thickness may be in the range of 1 micron to 10 microns, such as 2 microns to 6 microns. The top surfaces of the first type first metal bonding pad 358A and the second type first metal bonding pad 358B may be located in a horizontal plane including the physically exposed top surface of the first dielectric material layer 350.

[0133] Reference Fig. 10B , a photoresist layer (not shown) may be applied on the first dielectric material layer 350 and may be photolithographically patterned to cover the first type first metal bonding pad 358A and not cover the second type first metal bonding pad 358B. A selective etching process may be performed that selectively etches the metal material of the second type first metal bonding pad 358B to vertically recess the physically exposed horizontal surface of the second type first metal bonding pad 358B. For example, if the metal bonding pad 358 includes copper, the selective etching process may include a wet etching process that selectively etches copper to the dielectric material of the dielectric material layer 350.

[0134] Typically, the top surface of the second type first metal bonding pad 358B is vertically recessed relative to the top surface of the first type first metal bonding pad 358A. The vertical recessed distance of the top surface of the second type first metal bonding pad 358B can be in the range of 20% to 80% of the first thickness (i.e., the thickness of the first type first metal bonding pad 358A). The photoresist layer can then be removed, for example, by ashing. Each first type first metal bonding pad 358A has a first thickness, and each second type first metal bonding pad 358B has a second thickness less than the first thickness. The second thickness can be in the range of 20% to 80% of the first thickness.

[0135] Reference Fig. 10C A patterned mask layer (not shown) may be formed on the metal bonding pad 358 and the first dielectric material layer 350. The patterned mask layer includes an opening above the second type first metal bonding pad 358B. The area of ​​each opening in the patterned mask layer may be smaller than the area of ​​the corresponding underlying second type first metal bonding pad 358B.

[0136] A metal material having a Young's modulus lower than that of the material of the second type first metal bonding pad 358 may be deposited in the opening in the patterned mask layer. The metal material may include solder or non-solder metal materials such as lead, aluminum, tin, zinc, bismuth, cadmium, etc. Each deposited portion of the metal material may be formed into a pillar structure having an area smaller than that of the corresponding underlying second type first metal bonding pad 358B, referred to herein as an intermediate metal material portion 389.

[0137] According to one aspect of the present disclosure, the intermediate metal material portions 389 protrude above a horizontal plane including a physically exposed horizontal plane of the first dielectric material layer 350. Each intermediate metal material portion 389 includes Fig. 10B The volume of each intermediate metal material portion 389 may be smaller than the volume of the corresponding cavity. When the intermediate metal material portion 389 is attached to the second type first metal bonding pad 358B, the top surface of the intermediate metal material portion 389 protrudes above the horizontal plane including the top surface of the first type first metal bonding pad 358A.

[0138] In one embodiment, intermediate metal material portion 389 is formed by forming a mask layer on first type first metal bonding pad 358A and second type first metal bonding pad 358B, forming an opening through the mask layer in an area covering second type first metal bonding pad 358B, and depositing metal in the opening. Intermediate metal material portion 389 can be attached to second type first metal bonding pad 358B without covering the surface of first type first metal bonding pad 358A with any metal material.

[0139] Reference Fig. 10D , providing a second semiconductor die 400, which may be formed by omitting the formation of the metal bonding pad structure 158 and by forming a second metal bonding pad 488 configured for metal-to-metal bonding. Figure 1 The second semiconductor die 700 is shown derived therefrom. The pattern of the second metal bond pads 488 can be a mirror image pattern of the first metal bond pads 358 .

[0140] In one embodiment, the second semiconductor die 400 includes a second semiconductor substrate 410, a second semiconductor device 120 located on the second semiconductor substrate 410, and a second dielectric material layer 450 and a second metal bonding pad 488 in which a second metal interconnect structure 440 is buried. The second semiconductor die 400 may include a second electrostatic discharge (ESD) protection circuit 122 located on the second semiconductor substrate 410. In one embodiment, the second metal bonding pad 488 includes a first type second metal bonding pad 488A that is not electrically connected to the second ESD protection circuit 122 and a second type second metal bonding pad 488B that is electrically connected to the second electrostatic discharge protection circuit 122. In this embodiment, the first type second metal bonding pad 488A is electrically isolated from the second ESD protection circuit 122. Therefore, a discharge current path DCP is provided between each second type second metal bonding pad 488B and the second ESD protection circuit 122.

[0141] The second metal bonding pad 488 may have the same second uniform thickness, referred to herein as the third thickness. In one embodiment, the third thickness may be in the range of 1 micron to 10 microns, for example 2 microns to 6 microns. The physically exposed planar horizontal surface of the second metal bonding pad 488 may be located within a horizontal plane including the physically exposed top surface of the second dielectric material layer 450. The second metal bonding pad 488 includes a second metal material, which may be bonded to the first metal material of the first metal bonding pad 358. In one embodiment, the second metal bonding pad 488 and the first metal bonding pad 358 may include copper. Typically, the Young's modulus of the material of the intermediate metal material portion 389 is less than the elastic modulus of the material of the second metal bonding pad 488.

[0142] The second semiconductor die 400 may be positioned such that the second metal bonding pads 488 face the first metal bonding pads 358. When the second semiconductor die 400 is aligned with the first semiconductor die 300, the second type second metal bonding pads 488B may face the intermediate metal material portion 389.

[0143] Reference Fig. 10E, during the initial steps of the bonding process, the vertical spacing between the second semiconductor die 400 and the first semiconductor die 300 can be gradually reduced. The distance between each intermediate metal material portion 389 and the corresponding overlying second type second metal bonding pad 488B can be reduced until the intermediate metal material portion 389 contacts the second type second metal bonding pad 488B. Before the intermediate metal material portion 389 contacts the second type second metal bonding pad 488B, an electrostatic discharge (ESD) event may occur immediately. Therefore, the intermediate metal material portion 389 serves as a discharge guide point (LPoD) structure in the third embodiment structure.

[0144] In one embodiment, one, a plurality of, and / or each intermediate metal material portion 389 may be electrically connected to first ESD protection circuit 122 in first semiconductor die 300 through a corresponding one of second type first metal bonding pads 358B and a subset of first metal interconnect structures 340. When one, a plurality of, and / or each second type second metal bonding pad 488B is in contact with intermediate metal material portion 389, second type second metal bonding pad 488B may be electrically connected to first ESD protection circuit 122 through intermediate metal material portion 389.

[0145] In one embodiment, the second semiconductor die 400 includes a second electrostatic discharge (ESD) protection circuit 122 located on the second semiconductor substrate 410. One, a plurality of and / or each second type second metal bonding pad 488B may be electrically connected to the second ESD protection circuit 122 through a subset of the second metal interconnect structure 440. During an ESD event occurring at the moment of electrical contact between the intermediate metal material portion 389 and the second type second metal bonding pad 488B, a transient electrostatic discharge current may flow between the first ESD protection circuit 122 located on the first semiconductor substrate 310 and the second ESD protection circuit 112 located on the second semiconductor substrate 420.

[0146] Reference Fig.10F , the distance between the horizontal plane including the physically exposed planar horizontal surface of the first dielectric material layer 350 and the physically exposed planar horizontal surface including the second dielectric material layer 450 can gradually decrease to zero. As described above, the Young's modulus of the intermediate metal material portion 389 is less than the Young's modulus of the metal material of the second metal bonding pad 488 and the first metal bonding pad 358. Therefore, the intermediate metal material portion 389 is deformed during this processing step and is completely contained in Fig. 10B The volume of the recessed cavity formed during the processing step.

[0147] The annealing process may be performed at an elevated temperature while the first semiconductor die 300 and the second semiconductor die 400 are pressed against each other. The first type second metal bonding pad 488A may be bonded to the first type first metal bonding pad 358A by metal-to-metal bonding (e.g., copper-to-copper bonding), with the intermediate metal material portion 389 interposed between the second type second metal bonding pad 488B and the mating pair of the second type first metal bonding pad 358B. Typically, the first type second metal bonding pad 488A is bonded to the first type first metal bonding pad 358A by metal-to-metal bonding.

[0148] In addition, the surface of the second dielectric material layer 450 can be bonded to the surface of the first dielectric material layer 350 by dielectric-to-dielectric bonding, so that the second semiconductor die 400 is bonded to the first semiconductor die 300 by hybrid bonding. The elevated temperature can be in the range of 200 degrees Celsius to 400 degrees Celsius, but lower and higher temperatures can also be used. The duration of the annealing process at high temperature can be in the range of 30 minutes to 240 minutes, but shorter or longer durations can also be used.

[0149] In one embodiment, intermediate metal material portions 389 may be deformed so that the thickness of the metal material portion of each intermediate metal material portion 389 is equal to the difference between the first thickness and the second thickness after first type second metal bonding pad 488A is bonded to first type first metal bonding pad 358A. In one embodiment, each intermediate metal material portion 389 may have a respective horizontal surface section that is located within a horizontal plane including the bonding surface of first type first metal bonding pad 358A after first type second metal bonding pad 488A is bonded to first type first metal bonding pad 358A.

[0150] In one embodiment, each of first type second metal bonding pad 488A and second type second metal bonding pad 488B has a respective horizontal surface located within a horizontal plane including a bonding interface between first dielectric material layer 350 and second dielectric material layer 450. In one embodiment, after first type second metal bonding pad 488A is bonded to first type first metal bonding pad 358A, a cavity free of any solid phase material and liquid phase material may be formed around one, a plurality of and / or each intermediate metal material portion 389. The cavity is laterally surrounded by first dielectric material layer 350.

[0151] Fig. 10EThe structure of the third embodiment shown includes a device structure, which includes: a first semiconductor die 300, which includes a first semiconductor substrate 310, a first semiconductor device 120 located on the first semiconductor substrate 310, and a first dielectric material layer 350 and a first metal bonding pad 358 buried in a first metal interconnect structure 340, wherein the first metal bonding pad 358 includes a first type first metal bonding pad 358A and a second type first metal bonding pad 358B; a second semiconductor die 400, which includes a second semiconductor substrate 410, a first semiconductor device 120 located on the first semiconductor substrate 410, and a first dielectric material layer 350 and a first metal bonding pad 358 buried in the first metal interconnect structure 340, wherein the first metal bonding pad 358 includes a first type first metal bonding pad 358A and a second type first metal bonding pad 358B. A second semiconductor device 420 on the substrate, and a second dielectric material layer 450 and a second metal bonding pad 488 embedded in the second metal interconnect structure 440, wherein the second metal bonding pad 488 includes a first type second metal bonding pad 488A directly bonded to the first type first metal bonding pad 358A and a second type second metal bonding pad 488B that does not contact any first metal bonding pad 358; wherein each intermediate metal material portion 389 is respectively in contact with a corresponding one of the second type first metal bonding pad 358B and the second type second metal bonding pad 488B.

[0152] In one embodiment, each first type first metal bonding pad 358A has a first thickness; and each second type first metal bonding pad 358B has a second thickness less than the first thickness. In one embodiment, each second metal bonding pad 488 has a uniform thickness. In one embodiment, the metal material portion thickness of each intermediate metal material portion 389 is equal to the difference between the first thickness and the second thickness.

[0153] In one embodiment, each intermediate metal material portion 389 has a respective horizontal surface segment that lies within a horizontal plane including the bonding surface of first type first metal bonding pad 358A. In one embodiment, each of first type second metal bonding pad 488A and second type second metal bonding pad 488B has a respective horizontal surface that lies within a horizontal plane.

[0154] In one embodiment, second dielectric material layer 450 is bonded to first dielectric material layer 350 by dielectric-to-dielectric bonding. In one embodiment, first type second metal bonding pad 488A is bonded to first type first metal bonding pad 358A by metal-to-metal bonding, wherein a subset of grain boundaries between a first metal in first type first metal bonding pad 358A and a second metal in first type second metal bonding pad 488A pass through a horizontal plane including a horizontal interface between first dielectric material layer 350 and second dielectric material segment 450.

[0155] In one embodiment, the Young's modulus of the material of intermediate metal material portion 389 is less than a first Young's modulus of the first metal in first metal bond pad 358 and less than a second Young's modulus of the second metal in second metal bond pad 488 .

[0156] In one embodiment, the cavity free of any solid phase material and liquid phase material is laterally surrounded by one of the intermediate metal material portions 389 and laterally surrounded by the first dielectric material layer 350 .

[0157] In one embodiment, first semiconductor die 300 includes first electrostatic discharge (ESD) protection circuit 122 on first semiconductor substrate 310, wherein one of second type first metal bonding pads 358B is electrically connected to first ESD protection circuit 122 through a subset of first metal interconnect structures 340. In one embodiment, second semiconductor die 400 includes second electrostatic discharge (ESD) protection circuit 122 on second semiconductor substrate 410, wherein one of second type first metal bonding pads 358B is electrically connected to second ESD protection circuit 122 through a subset of second metal interconnect structures 440. In one embodiment, first type first metal bonding pad 358A is electrically isolated from first ESD protection circuit 122.

[0158] FIG. 11A to FIG. 11D 7 are sequential vertical cross-sectional views of a fourth embodiment structure during formation of a bonded assembly of two semiconductor dies 700 according to a fourth embodiment of the present disclosure.

[0159] Reference Fig.11A , providing a first semiconductor die 300, which can be replaced by forming a first metal bonding pad 368 instead of the first metal bonding pad 358. Fig. 10A The first metal bonding pad 358 used in the fourth embodiment structure includes a solder bonding pad, i.e., a bonding pad configured to be bonded to other pads through a solder material portion (e.g., a solder ball). In this embodiment, the first metal bonding pad 368 in the first semiconductor die 300 of the fourth embodiment structure may include a C4 bonding pad or a micro-bump structure (also referred to as a C2 bump structure).

[0160] The first semiconductor die 300 includes a first semiconductor substrate 310, a first semiconductor device 120 located on the first semiconductor substrate 320, a first dielectric material layer 350 in which a first metal interconnect structure 340 is buried, and a first metal bonding pad 368. The first metal bonding pad 368 includes a first type first metal bonding pad 368A and a second type first metal bonding pad 368B. In one embodiment, the first semiconductor die 300 includes a first electrostatic discharge (ESD) protection circuit 122 located on the first semiconductor substrate 310. In one embodiment, one, a plurality of and / or each second type first metal bonding pad 368B may be electrically connected to the first ESD protection circuit 122 in the first semiconductor die 300 through a subset of the first metal interconnect structure 340. In one embodiment, the first semiconductor device 120 includes a first field effect transistor having an electrical node electrically connected to one of the second type first metal bonding pads 368B. In one embodiment, the first type first metal bonding pad 368A is electrically isolated from the first ESD protection circuit 122.

[0161] The first solder material portion 188A may be attached to a corresponding one of the first type first metal bonding pads 368A. Each first solder material portion 188A may have a first height. In addition, the second solder material portion 188B may be attached to a corresponding one of the second type first metal bonding pads 368B. Each second solder material portion 188B may have a second height greater than the first height. In an illustrative example, the first height may be in the range of 20 microns to 60 microns, for example, 30 microns to 50 microns. The second height may be in the range of 25 microns to 100 microns, for example, 40 microns to 70 microns. The difference between the second height and the first height may be in the range of 5 microns to 40 microns, for example, 10 microns to 30 microns.

[0162] In one embodiment, the volume of each first solder material portion 188A may be in the range of 80% to 120% of the first reference volume, such as 90% to 110% and / or 98% to 102%. In one embodiment, the volume of each second solder material portion 188B may be in the range of 80% to 120% of the second reference volume, such as 90% to 110% and / or 98% to 102%. Wherein, the ratio of the second reference volume to the first reference volume is in the range of 1.5 to 4, such as 2 to 3. When the first solder material portion 188A and the second solder material portion 188B are attached to the first metal bonding pad 368, the interface between the first metal bonding pad 368, the first solder material portion 188B and the second solder material portion 188B may be formed within the first horizontal plane HP1.

[0163] Reference Fig. 11B, a structure including interconnections may be provided, which may include a second semiconductor die 400. The second semiconductor die 400 of the fourth embodiment structure may be formed by replacing the second metal bonding pad 488 with the second metal bonding pad 468, thereby Fig. 10D The second metal bonding pad 468 used in the structure of the fourth embodiment includes a solder bonding pad, i.e., a bonding pad configured to bond to other pads through a solder material portion (e.g., a solder ball). In this embodiment, the second metal bonding pad 468 in the second semiconductor die 400 of the structure of the fourth embodiment may include a C4 bonding pad or a micro-bump structure (also referred to as a C2 bump structure).

[0164] The pattern of the second metal bonding pads 468 may be a mirror image pattern of the pattern of the first metal bonding pads 368. The second metal bonding pads 468 may include a first type second metal bonding pad 468A and a second type second metal bonding pad 464B.

[0165] In one embodiment, the interconnect-containing structure includes a second semiconductor die 400, which includes: a second semiconductor substrate 410; a second semiconductor device 420 located on the second semiconductor substrate 410; and a second dielectric material layer 450 in which a second metal interconnect structure 440 is buried. In one embodiment, the second semiconductor die 400 includes an electrostatic discharge (ESD) protection circuit 122 located on the second semiconductor substrate 410. One, a plurality of and / or each second type first metal bonding pad 368B can be electrically connected to the second ESD protection circuit 122 through a subset of the second metal interconnect structure 440. The first type second metal bonding pad 468A can be electrically isolated from the ESD protection circuit 122 in the second semiconductor die 400. The second semiconductor die 400 can be positioned so that the second metal bonding pad 468 faces the first metal bonding pad 368.

[0166] Reference Fig. 11C , during the initial steps of the bonding process, the vertical spacing between the second semiconductor die 400 and the first semiconductor die 300 can be gradually reduced. The distance between each second solder material portion 188B and the corresponding lower second type second metal bonding pad 468B can be reduced until the second solder material portion 188B contacts the second type second metal bonding pad 468B. An electrostatic discharge (ESD) event may occur immediately before the second solder material portion 188B contacts the second type second metal bonding pad 468B. Therefore, the second solder material portion 188B serves as a discharge guide point (LPoD) structure in the fourth embodiment structure.

[0167] In one embodiment, one, a plurality of, and / or each second solder material portion 188B may be electrically connected to the first ESD protection circuit 122 in the first semiconductor die 300 through a corresponding one of the second type first metal bonding pads 368B and a subset of the first metal interconnect structures 340. When one, a plurality of, and / or each of the second type second metal bonding pads 468B are in contact with the second solder material portion 188B, they may be electrically connected to the first ESD protection circuit 122 in the first semiconductor die 300 through the second solder material portion 188B.

[0168] In one embodiment, the second semiconductor die 400 includes a second electrostatic discharge (ESD) protection circuit 122 located on the second semiconductor substrate 410. One, a plurality of and / or each second type second metal bonding pad 468B may be electrically connected to the second ESD protection circuit 122 through a subset of the second metal interconnect structure 440. During an ESD event occurring at the moment of electrical contact between the second solder material portion 188B and the second type second metal bonding pad 468B, a transient electrostatic discharge current may flow between the first ESD protection circuit 122 located on the first semiconductor substrate 310 and the second ESD protection circuit 112 located on the second semiconductor substrate 420.

[0169] Typically, during the bonding process, the second solder material portion 188B contacts the second type second metal bonding pad 488B before the first solder material portion 188A contacts the first type second metal bonding pad 488A. In one embodiment, the second solder material portion 188B contacts the second type second metal bonding pad 488B when the second solder material portion 188B is at or above the reflow temperature of the solder material of the second solder material portion 188B, so that the second solder component 188B does not crack when contacting the second type second metal bonding pad 468B, but reflows and deforms.

[0170] Reference Fig.11D , the vertical distance between the first semiconductor die 300 and the second semiconductor die 400 can be gradually reduced until the first type solder material portion 188A contacts the first type first metal bonding pad 368A and is bonded to the first type first metal bonding pad 368A. The temperature of the solder material portion 188 can be controlled to induce a solder bond between each pair of the first metal bonding pad 368 and the second metal bonding pad 468. Typically, the first type second metal bonding pad 468A is bonded to the first type first metal bonding pad 368A by solder bonding.

[0171] Typically, a bonding process may be performed in which first solder material portion 188A is bonded to a corresponding one of first type second metal bonding pads 488A and second solder material portion 188B is bonded to a corresponding one of second type second metal bonding pads 488B. In one embodiment, during the bonding process, all horizontal interfaces between first solder material portion 188A and first type second metal bonding pad 488A are formed within second horizontal plane HP2; and during the bonding process, all horizontal interfaces between second solder material portion 188B and second type second metal bonding pad 488B are formed within second horizontal plane HP2.

[0172] In one embodiment, first solder material portion 188A is bonded to first type second metal bonding pad 488A such that first solder material portion 1888A does not contact the sidewalls of first type first metal bonding pad 368A nor the sidewalls of first type second metal bonding pad 488A. In one embodiment, second solder material portion 188B is bonded to second type second metal bonding pad 488B such that second solder material portion 188B contacts the sidewalls of second type first metal bonding pad 368B and contacts the sidewalls of second type second metal bonding pad 488B.

[0173] Fig.11D The fourth embodiment structure shown includes a device structure, which includes: a first semiconductor die 300, which includes a first semiconductor substrate 310, a first semiconductor device 120 located on the first semiconductor substrate 310, and a first dielectric material layer 350 and a first metal bonding pad 368 buried in a first metal interconnect structure 340, wherein the first metal bonding pad 368 includes a first type first metal bonding pad 368A and a second type first metal bonding pad 368B; a structure including an interconnect (e.g., a second semiconductor die 400), which includes a second metal interconnect structure 440 and a second metal bonding pad 488 buried in the second metal bonding pad 488, wherein the second metal bonding pad 488 includes a first type first metal bonding pad 368A and a second type first metal bonding pad 368B. A type second metal bonding pad 488A and a second type second metal bonding pad 488B; a first solder material portion 188A bonded to a corresponding one of the first type first metal bonding pad 368A and the first type second metal bonding pad 488A and having a volume in the range of 80% to 120% of the first reference volume; and a second solder material portion 188B bonded to a corresponding one of the second type first metal bonding pad 368B and the second type second metal bonding pad 488B and having a volume in the range of 80% to 120% of the second reference volume, wherein a ratio of the second reference volume to the first reference volume is in the range of 1.5 to 4.

[0174] In one embodiment, a first vertical spacing between a corresponding one of first type first metal bonding pad 368A and first type second metal bonding pad 488A is the same as a second vertical spacing between a corresponding one of second type first metal bonding pad 368B and second type second metal bonding pad 488B.

[0175] In one embodiment, all horizontal interfaces between first solder material portions 188A and first type first metal bonding pads 368A are located within first horizontal plane HP1; and all horizontal interfaces between second solder material portions 188B and second type first metal bonding pads 368B are located within first horizontal plane HP1. In one embodiment, all horizontal interfaces between first solder material portions 188A and first type second metal bonding pads 488A are located within second horizontal plane HP2; and all horizontal interfaces between second solder material portions 188B and second type second metal bonding pads 488B are located within second horizontal plane HP2.

[0176] In one embodiment, each of the first type first metal bonding pad 368A and the second type first metal bonding pad 368B has the same area. In one embodiment, the first semiconductor die 300 includes a first electrostatic discharge (ESD) protection circuit 122 located on the first semiconductor substrate 310, wherein one of the second type first metal bonding pads 368B is electrically connected to the first ESD protection circuit 122 through a subset of the first metal interconnect structure 340. In one embodiment, the first semiconductor device 120 includes a first field effect transistor having an electrical node that is electrically connected to one of the second type first metal bonding pads 368B. In one embodiment, the first type first metal bonding pad 368A is electrically isolated from the first ESD protection circuit 122.

[0177] In one embodiment, the first solder material portion 188A does not contact the side walls of the first type first metal bonding pad 368A, nor does it contact the side walls of the first type second metal bonding pad 488A; the second solder material portion 188B contacts the side walls of the second type first metal bonding pad 368B and the side walls of the second type second metal bonding pad 488B.

[0178] In one embodiment, the interconnect-containing structure includes a second semiconductor die 400, which includes: a second semiconductor substrate 410; a second semiconductor device 420 located on the second semiconductor substrate 410; and a second dielectric material layer 450 in which a second metal interconnect structure 440 is buried. In one embodiment, the second semiconductor die 400 includes an electrostatic discharge (ESD) protection circuit 122 located on the second semiconductor substrate 410, wherein one of the second type first metal bonding pads 368B is electrically connected to the second ESD protection circuit 122 through a subset of the second metal interconnect structure 440.

[0179] FIG. 12A to FIG. 12E 3 are sequential vertical cross-sectional views of a fifth embodiment structure during formation of a bonded assembly of two semiconductor dies 300 according to a fifth embodiment of the present disclosure.

[0180] Reference Fig. 12A , providing a first semiconductor die 300A and a structure including interconnects. The first semiconductor die 300A can be connected to the reference Fig.11A The first semiconductor chip 300 is described the same.

[0181] The first semiconductor die 300A includes a first semiconductor substrate 310, a first semiconductor device 120 located on the first semiconductor substrate 320, a first dielectric material layer 350 in which a first metal interconnect structure 340 is buried, and a first metal bonding pad 368. The first metal bonding pad 368 includes a first type first metal bonding pad 368A and a second type first metal bonding pad 368B. In one embodiment, the first semiconductor die 300A includes a first electrostatic discharge (ESD) protection circuit 122 located on the first semiconductor substrate 310. In one embodiment, one, a plurality of and / or each second type first metal bonding pad 368B may be electrically connected to the first ESD protection circuit 122 in the first semiconductor die 300A through a subset of the first metal interconnect structure 340. In one embodiment, the first semiconductor device 120 includes a first field effect transistor having an electrical node electrically connected to one of the second type first metal bonding pads 368B. In one embodiment, the first type first metal bonding pad 368A is electrically isolated from the first ESD protection circuit 122.

[0182] The first solder material portion 188A may be attached to a corresponding one of the first type first metal bonding pads 368A. Each first solder material portion 188A may have a first height. In addition, the second solder material portion 188B may be attached to a corresponding one of the second type first metal bonding pads 368B. Each second solder material portion 188B may have a second height greater than the first height. Typically, the height and volume of the first solder material portion 188A and the second solder material portion 188B may be the same as described with reference to the first semiconductor die 300 of the fourth embodiment structure. Typically, when the first solder material portion 188A and the second solder material portion 188B are attached to the first metal bonding pad 368, the interface between the first metal bonding pad 368, the first solder material portion 188A and the second solder material portion 188B is formed within the first horizontal plane HP1.

[0183] In one embodiment, the first semiconductor die 300A includes a first electrostatic discharge (ESD) protection circuit 122 located on the first semiconductor substrate 310. One, a plurality of and / or each second type first metal bonding pad 368B can be electrically connected to the first ESD protection circuit 122 through a subset of the first metal interconnect structure 340. In one embodiment, the first semiconductor device 120 includes a first field effect transistor having an electrical node that is electrically connected to one of the second type first metal bonding pads 368B. In one embodiment, the first type first metal bonding pad 368A can be electrically isolated from the first ESD protection circuit 122.

[0184] The structure containing the interconnect may be an interposer 800, which may include an organic interposer, a ceramic interposer, or any other type of interposer known in the art. In one embodiment, the interposer 800 includes a redistribution wiring interconnect 840 embedded in a redistribution dielectric layer 850 including a polymer material. In one embodiment, the interposer 800 includes an interposer metal bonding pad 878. The interposer metal bonding pad 878 includes a first type interposer metal bonding pad 878A and a second type interposer metal bonding pad 878B. In general, an interconnect containing structure (e.g., an interposer 800) is provided that embeds a second metal interconnect structure (e.g., a redistribution wiring interconnect 840) and includes a second metal bonding pad (e.g., an interposer metal bonding pad 878). The second metal bonding pad 878 includes a first type second metal bonding pad (e.g., a first type interposer metal bonding pad 878A) and a second type second metal bonding pad (e.g., a second type interposer metal bonding pad 878B).

[0185] In one embodiment, the interposer 800 includes substrate-side metal bonding pads 868 on opposite sides of the interposer metal bonding pads 878. The interposer metal bonding pads 878 can be configured to bond with at least two semiconductor dies including the first semiconductor die 300A. In this embodiment, a first subset of the interposer metal bonding pads 878 can have a mirror image pattern of the first metal bonding pads 368 of the first semiconductor die 300A. The first semiconductor die 300A can be aligned to the first subset of the interposer metal bonding pads 878 of the interposer 800.

[0186] Reference Fig. 12B , a first bonding process may be performed. The first solder material portion 188A is bonded to a corresponding one of the first type second metal bonding pads (e.g., the first type interposer bonding pad 878A), and the second solder material portion 188B is bonded to a corresponding one of the second type second metal bonding pads (e.g., the second type interposer bonding pad 878B). Typically, during the bonding process, before the first solder material portion 188A contacts the first type interposer metal bonding pad (e.g., the first type interposer bonding pad 878A), the second solder material portion 188B contacts the second type interposer metal bonding pad (e.g., the second type interposer metal bonding pad 878B). When the second solder material portion 188B is at or above the reflow temperature of the solder of the second solder material portion 188B, the second solder material portion 188B contacts the second type interposer metal bonding pad (e.g., the second type interposer metal bonding pad 878B).

[0187] During the initial step of the first bonding process, the vertical spacing between the first semiconductor die 300A and the interposer 800 can be gradually reduced. The distance between each second solder material portion 188B and the corresponding lower second type interposer metal bonding pad 878B can be reduced until the second solder material portion 188B contacts the second type interposer metal bonding pad 878B. An electrostatic discharge (ESD) event may occur immediately before the second solder material portion 188B contacts the second type interposer metal bonding pad 878B. Therefore, the second solder material portion 188B serves as a discharge guide point (LPoD) structure in the fifth embodiment structure.

[0188] Reference Fig. 12C, while the solder material portions 188 are maintained at the reflow temperature, the vertical distance between the first semiconductor die 300A and the interposer 800 can be further reduced. Each first type first metal bonding pad 368A can be bonded to a corresponding first type interposer bonding pad 878A through a corresponding first solder material portion 188A, and each second type first metal bonding pad 368B can be bonded to a corresponding second type interposer pad 878B through a corresponding second solder material portion 188B.

[0189] In one embodiment, during the bonding process, all horizontal interfaces between the first solder material portions 188A and the first type interposer metal bonding pads 878A are formed within the second horizontal plane HP2; and during the bonding process, all horizontal interfaces between the second solder material portions 188B and the second type interposer metal bonding pads 878B are formed within the second horizontal plane HP2. In one embodiment, the difference between the volume of each first solder material portion 188A and the volume of each second solder material portion 188B may result in different bonding configurations of the first solder material portions 188A and the second solder portions 188B. In one embodiment, after the bonding process is performed, the first solder material portions 188A do not contact the sidewalls of the first type first metal bonding pads 368A nor the sidewalls of the first type interposer metal bonding pads 878A; after the bonding process is performed, the second solder material portions 188B contact the sidewalls of the second type first metal bonding pads 368B and the sidewalls of the second type interposer metal bonding pads 878B.

[0190] refer to Fig.12D , a second semiconductor die 300B can be provided, which includes a second semiconductor substrate 310, a second semiconductor device 320 located on the second semiconductor substrate 310, a second dielectric material layer 350 (which may be referred to as an additional dielectric material in the present application) with a buried second metal interconnect structure (which may be referred to as an additional metal interconnect structure in the present application), and a second metal bonding pad 368 (which may also be referred to as an additional metal bonding pad or a third metal bonding pad in the present application).

[0191] In one embodiment, second semiconductor die 300B includes electrostatic discharge (ESD) protection circuit 122 on second semiconductor substrate 310. In one embodiment, one, more, and / or each second type second metal bonding pad 878B is electrically connected to ESD protection circuit 122 through a subset of second metal interconnect structures 340.

[0192] The second metal bonding pads 368 of the second semiconductor die 300B include a first type second metal bonding pad 368A and a second type second metal bonding pad 368B. The additional first solder material portion 188A may be attached to a corresponding one of the first type second metal bonding pads 368A of the second semiconductor die 300B; and the additional second solder material portion 188B may be attached to a corresponding one of the second type second metal bonding pads 878B of the second semiconductor die 300B. A second bonding process (which may also be referred to as an additional bonding process) may be performed, in which the additional first solder material portion 188A is bonded to a corresponding additional pad of the first type interposer metal bonding pad 878A, and the additional second solder material portion 188B is bonded to a corresponding additional pad of the second type interposer metal bonding pad 878B.

[0193] During the initial steps of the second bonding process, the vertical spacing between the second semiconductor die 300B and the interposer 800 can be gradually reduced. The distance between each additional second solder material portion 188B and the corresponding lower second type interposer metal bonding pad 878B can be reduced until the additional third solder material portion 188B contacts the additional second type interposer metal bonding pad 878B. An electrostatic discharge (ESD) event can occur immediately before the additional second solder material portion 188B contacts the additional second type interposer metal bonding pad 878B. Therefore, the additional second solder material portion 188B serves as a discharge guide point (LPoD) structure in the fifth embodiment structure.

[0194] Reference Fig.12E , while maintaining the additional solder material portion 188 at the reflow temperature, the vertical distance between the second semiconductor die 300B and the interposer 800 can be further reduced. Each first type first metal bonding pad 368A of the second semiconductor die 300B can be bonded to a corresponding additional first type interposer bonding pad 878A through a corresponding additional first solder material portion 188A, and each second type first metal bonding pad 368B in the second semiconductor die 300B can be bonded to a corresponding additional second type interposer metal bonding pad 878B through a corresponding additional second solder material portion 188B.

[0195] According to one aspect of the present disclosure, the second semiconductor die 300B can be attached to the interposer 800 such that at least one electrical connection is provided between the second semiconductor die 300B and the first semiconductor die 300. In one embodiment, a first conductive path is formed between the first semiconductor die 300A and the second semiconductor die 300B through a first subset of the redistribution wiring interconnects 840 and through a pair of first type interposer metal bonding pads 878A selected from the first type interposer metal bonding pads 878A. In one embodiment, a second conductive path is formed between the first semiconductor die 300A and the second semiconductor die 300B through a second subset of the redistribution wiring interconnects 840 and through a pair of second type interposer metal bonding pads 878B selected from the second type interposer metal bonding pads 878B.

[0196] In one embodiment, the interposer 800 includes a substrate-side metal bonding pad 868 located on an opposite side of the interposer metal bonding pad 878. In one embodiment, a third conductive path is provided within the interposer 800. The third conductive path includes one of the first type interposer metal bonding pads 878A, a third subset of the redistribution wiring interconnects, and one of the substrate-side metal bonding pads. In one embodiment, the third conductive path is electrically isolated from the first conductive path and the second conductive path.

[0197] See also Fig.12E , the fifth embodiment structure includes a device structure, which includes: a first semiconductor die 300A, which includes a first semiconductor substrate 310, a first semiconductor device 120 located on the first semiconductor substrate 320, and a first dielectric material layer 350 and a first metal bonding pad 368 in which a first metal interconnect structure 340 is buried, wherein the first metal bonding pad 368 includes a first type first metal pad 368A and a second type first metal bonding pad 368B; an interposer 800, which includes a redistribution wiring interconnect 840 embedded in a redistribution dielectric layer 850, the redistribution dielectric layer 850 includes a polymer material, and further includes an interposer metal bonding pad 878, wherein the interposer metal bonding pad 878 78 includes a first type interposer metal bonding pad 878A and a second type interposer metal bonding pad 878B; a first solder material portion 188A joined to a corresponding one of the first type first metal bonding pad 368A and the first type interposer metal bonding pad 878A, and having a volume in the range of 80% to 120% of the first reference volume; and a second solder material portion 188B joined to a corresponding one of the second type first metal bonding pad 368B and the second type interposer metal bonding pad 878B, and having a volume in the range of 80% to 120% of the second reference volume, wherein a ratio of the second reference volume to the first reference volume is in the range of 1.5 to 3.

[0198] In one embodiment, a first vertical spacing between a corresponding one of the first type first metal bonding pads 368A and a corresponding one of the first type interposer metal bonding pads 878A is the same as a second vertical spacing between a corresponding one of the second type first metal bonding pads 368B and a corresponding one of the second type interposer metal bonding pads 878B.

[0199] In one embodiment, all horizontal interfaces between first solder material portions 188A and first type first metal bonding pads 368A are located within first horizontal plane HP1; and all horizontal interfaces between second solder material portions 188B and second type first metal bonding pads 368B are located within first horizontal plane HP1. In one embodiment, all horizontal interfaces between first solder material portions 188A and first type interposer metal bonding pads 878A are located within second horizontal plane HP2; and all horizontal interfaces between second solder material portions 188B and second type interposer metal bonding pads 878B are located within second horizontal plane HP2.

[0200] In one embodiment, the first semiconductor die 300A includes a first electrostatic discharge (ESD) protection circuit 122 on the first semiconductor substrate 310, wherein one of the second type first metal bonding pads 368B is electrically connected to the first ESD protection circuit 122 through a subset of the first metal interconnect structure 340. In one embodiment, the first semiconductor device 120 includes a first field effect transistor having an electrical node electrically connected to one of the second type first metal bonding pads 368B. In one embodiment, the first type first metal bonding pad 368A is electrically isolated from the first ESD protection circuit 122.

[0201] In one embodiment, each of the first type first metal bonding pad 368A and the second type first metal bonding pad 368B has the same area. In one embodiment, the first solder material portion 188A does not contact the sidewalls of the first type first metal bonding pad 368A nor the sidewalls of the first type interposer metal bonding pad 878A; the second solder material portion 188B contacts the sidewalls of the second type first metal bonding pad 368B and the sidewalls of the second type interposer metal bonding pad 878B.

[0202] In one embodiment, the device structure further includes: a second semiconductor die 300B, which includes a second semiconductor substrate 310, a second semiconductor device 320 located on the second semiconductor substrate 310, a second dielectric material layer 350 in which a second metal interconnect structure (such as a redistribution wiring interconnect 840) is buried, and a second metal bonding pad 878, wherein the second metal bonding pad 878 includes a first type second metal pad 878A and a second type second metal bonding pad 878B; an additional first solder material portion 188A, which is bonded to a corresponding one of the first type second metal bonding pads 878A and another one of the first type interposer metal bonding pads, and has a volume within a range of 80% to 120% of the first reference volume; and an additional second solder material portion 188B, which is bonded to a corresponding one of the second type second metal bonding pads 878B and a corresponding additional one of the second type interposer metal bonding pads, and has a volume within a range of 80% to 120% of the second reference volume.

[0203] In one embodiment, a first conductive path extends between the first semiconductor die 300A and the second semiconductor die 400B through a first subset of the redistribution wiring interconnects 840 and through a pair of first type interposer metal bonding pads 878A selected from the first type interposer metal bonding pads 878A; and a second conductive path extends between the first semiconductor die 300A and the second semiconductor die 400B through a second subset of the redistribution wiring interconnects 840 and a pair of second type interposer metal bonding pads 878B selected from the second type interposer metal bonding pads 878B.

[0204] In one embodiment, the interposer 800 includes a substrate-side metal bonding pad 868 located on an opposite side of the interposer metal bonding pad 878; a third conductive path is provided within the interposer 800, wherein the third conductive path includes the first type interposer metal bonding pad 878A, a third subset of the redistribution wiring interconnects, and one of the substrate-side metal bonding pads; and the third conductive path is electrically isolated from the first conductive path and the second conductive path.

[0205] In one embodiment, the second semiconductor die 300B includes an electrostatic discharge (ESD) protection circuit 122 located on the second semiconductor substrate 310, wherein one of the second type second metal bonding pads 878B is electrically connected to the ESD protection circuit 122 through a subset of the second metal interconnect structure (e.g., a redistribution wiring interconnect 840).

[0206] Common Reference Fig.11D and Fig.12EAccording to various embodiments of the present disclosure, a device structure is provided, which includes: a first semiconductor die (300 or 300A), which includes a first semiconductor substrate 310, a first semiconductor device 120 located on the first semiconductor substrate 320, and a first dielectric material layer 350 and a first metal bonding pad 368 in which a first metal interconnect structure 340 is buried, wherein the first metal bonding pad 368 includes a first type first metal bonding pad 368A and a second type first metal bonding pad 368B; a structure containing an interconnect (e.g., a second semiconductor die 400 or an interposer 800), which includes a second metal interconnect structure (e.g., a redistribution wiring interconnect 840 or a second metal wiring structure 440 in the second semiconductor die 400) and includes a second metal bonding pad (which may include an interposer metal bonding pad 878 or a second metal bonding pad 878 in the second semiconductor die 400) a second metal bonding pad 468), wherein the second metal bonding pad (878 or 468) includes a first type second metal bonding pad (878A or 468A) and a second type second metal bonding pad (878B or 468B); a first solder material portion 188A is bonded to a corresponding one of the first type first metal bonding pad 368A and the first type second metal bonding pad (878A or 468A) and has a volume in the range of 80% to 120% of the first reference volume; and a second solder material portion 188B, which is bonded to a corresponding one of the second type first metal bonding pad 368B and the second type second metal bonding pad (878B or 468B) and has a volume in the range of 80% to 120% of the second reference volume, wherein the ratio of the second reference volume to the first reference volume is in the range of 1.5 to 3.

[0207] In one embodiment, a first vertical spacing between the first type first metal bonding pad 368A and a corresponding one of the first type second metal bonding pads (878A or 468A) is the same as a second vertical spacing between the second type first metal bonding pad 368B and a corresponding one of the second type second metal bonding pads (878B or 468B).

[0208] In one embodiment, all horizontal interfaces between first solder material portions 188A and first type first metal bonding pads 368A are located within first horizontal plane HP1; and all horizontal interfaces between second solder material portions 188B and second type first metal bonding pads 368B are located within first horizontal plane HP1. In one embodiment, all horizontal interfaces between first solder material portions 188A and first type second metal bonding pads (878A or 468A) are located within second horizontal plane HP2; and all horizontal interfaces between second solder material portions 188B and second type second metal bonding pads (878B or 468B) are located within second horizontal plane HP2.

[0209] In one embodiment, the first semiconductor die (300 or 300A) includes a first electrostatic discharge (ESD) protection circuit 122 located on a first semiconductor substrate 310, wherein one of the second type first metal bonding pads 368B is electrically connected to the first ESD protection circuit 122 through a subset of the first metal interconnect structure 340. In one embodiment, the first semiconductor device 120 includes a first field effect transistor having an electrical node electrically connected to one of the second type first metal bonding pads 368B. In one embodiment, the first type first metal bonding pad 368A is electrically isolated from the first ESD protection circuit 122.

[0210] In one embodiment, each of first type first metal bonding pad 368A and second type first metal bonding pad 368B has the same area. In one embodiment, first solder material portion 188A does not contact the sidewall of first type first metal bonding pad 368A, nor does it contact the sidewall of first type second metal bonding pad (878A or 468A); second solder material portion 188B contacts the sidewall of second type first metal bonding pad 368B and the sidewall of second type second metal bonding pad (878B or 468B).

[0211] In one embodiment, the interconnect-containing structure includes an interposer 800; and the second metal interconnect structure includes a redistribution wiring interconnect 840 embedded within a redistribution dielectric layer 850 including a polymer material.

[0212] In one embodiment, the interconnect-containing structure includes a second semiconductor die 300B, which includes: a second semiconductor substrate 310; a second semiconductor device 320 located on the second semiconductor substrate 310; and an additional dielectric material layer 350 in which an additional metal interconnect structure 340 is buried. In one embodiment, the second semiconductor die 300B includes an electrostatic discharge (ESD) protection circuit 122 located on the second semiconductor substrate 310. One, a plurality of, and / or each second type first metal bonding pad 368B is electrically connected to the second ESD protection circuit 122 through a subset of the additional metal interconnect structure 340.

[0213] Fig.13 is a top view of a sixth embodiment structure including a wafer or a reconstructed wafer according to the sixth embodiment of the present disclosure. The sixth embodiment structure includes a two-dimensional periodic array of semiconductor die (700, 720, 300, 400) located on a substrate (110, 210). Each semiconductor die (700, 720, 300, 400) can be located within a corresponding unit area UA. The two-dimensional periodic array of semiconductor die (700, 720, 300, 400) can be arranged at a first pitch p1 along a first horizontal direction hd1 and at a second pitch p2 along a second horizontal direction hd2. In general, the features described with reference to the sixth embodiment structure can be applied to each of the previously described embodiments of the present disclosure.

[0214] The substrate (110, 210) may include a semiconductor substrate 110 or a carrier substrate 210. If the semiconductor substrate 110 is used, the semiconductor die within each unit area UA may include a semiconductor die (700, 300, 400) including a corresponding portion of the semiconductor substrate 110, which may be any semiconductor substrate (110, 310, 410) of the above-mentioned semiconductor die. In an embodiment using the carrier substrate 210, the semiconductor die may be the above-mentioned fan-out package 720.

[0215] FIG. 14A to FIG. 14J yes Fig.13 1 and 10. In general, each unit area UA includes a semiconductor die (700, 720, 300, 400) and an area not occupied by the semiconductor die (700, 720, 300, 400) (i.e., a non-die area). In an embodiment where the substrate includes a semiconductor substrate 110, the non-die area includes a cutout area (in FIG. 14A to FIG. 14G In embodiments where the substrate includes a carrier substrate 210, the non-die region includes a region of the molding compound die frame 220 that is a portion of the molding compound matrix 220M located within a corresponding unit area UA.

[0216] According to one aspect of the present invention, at least one discharge guiding point (LPoD) structure (166P, 389, 188B) may be provided in each unit area UA. The at least one LPoD structure (166P, 389, and 188B) may include any of the aforementioned LPoD structures. The at least one LPoD structure (166P, 389, 188B) may be disposed in the region of each semiconductor die (700, 720, 300, 400), and / or may be disposed in a corresponding non-die region, which may be a cutout region (i.e., a region of the cutout structure) or a region of the molding compound die frame 220 (which is a part of the molding compound matrix 220M). In general, the at least one LPoD structure (166P, 389, 188B) may be formed on or near a subset of the metal bonding pads (178, 358, 368, 468).

[0217] Reference Fig.14A , showing a first configuration of the unit area UA. In the first configuration, the LPoD structure (166P, 389, 188B) is formed in the area of ​​the semiconductor die (700, 720, 300, 400) and the area of ​​the notch structure or the molding compound matrix 220M.

[0218] Reference Fig. 14B , showing a second configuration of the unit area UA. In the second configuration, the LPoD structure (166P, 389, 188B) is formed only in the region of the notch structure or the molding compound matrix 220M.

[0219] Reference Fig. 14C , showing a third configuration of the unit area UA. In the third configuration, the LPoD structure (166P, 389, 188B) is formed only in the region of the semiconductor die (700, 720, 300, 400).

[0220] Reference Fig.14D , showing a fourth configuration of the unit area UA. In the fourth configuration, the semiconductor die (700, 720, 300, 400) may be a relatively large semiconductor die, such as an artificial intelligence (AI) semiconductor die. Within the region of the semiconductor die (700, 720, 300, 400), a plurality of metal bonding pad arrays (178, 358, 368, 468) may be provided. In the fourth configuration, the LPoD structure (166P, 389, 188B) is formed in the region of the semiconductor die (700, 720, 300, 400) and in the region of the cutout structure or the molding compound matrix 220M. The LPoD structure (166P, 389, 188B) is formed between adjacent metal bonding pad arrays (178, 358, 368, 468).

[0221] Reference Fig.14E, showing a fifth configuration of the unit area UA. In the fifth configuration, the semiconductor die (700, 720, 300, 400) may be a relatively large semiconductor die, such as an artificial intelligence (AI) semiconductor die. A plurality of metal bonding pad arrays (178, 358, 368, 468) may be provided within the region of the semiconductor die (700, 720, 300, 400). In the fifth configuration, the LPoD structure (166P, 389, 188B) is formed in the region of the semiconductor die (700, 720, 300, 400) and the region of the cutout structure or the molding compound matrix 220M, but is not formed between adjacent metal bonding pad arrays (178, 358, 368, 468).

[0222] Reference Fig.14F , showing a sixth configuration of the unit area UA. In the sixth configuration, the semiconductor die (700, 720, 300, 400) may be a relatively large semiconductor die, such as an artificial intelligence (AI) semiconductor die. A plurality of metal bonding pad arrays (178, 358, 368, 468) may be provided within the region of the semiconductor die (700, 720, 300, 400). In the sixth configuration, the LPoD structure (166P, 389, 188B) is formed in the region of the semiconductor die (700, 720, 300, 400), but is not formed in the region of the notch structure or the molding compound matrix 220M. The LPoD structure (166P, 389, 188B) may be formed between adjacent metal bonding pad arrays (178, 358, 368, 468).

[0223] Reference Figure 14G , showing the seventh configuration of the unit area UA. In the seventh configuration, the semiconductor die (700, 720, 300, 400) may be a relatively large semiconductor die, such as an artificial intelligence (AI) semiconductor die. A plurality of metal bonding pad arrays (178, 358, 368, 468) may be provided within the region of the semiconductor die (700, 720, 300, 400). In the seventh configuration, the LPoD structure (166P, 389, 188B) is formed in the region of the semiconductor die (700, 720, 300, 400), but is not formed in the region of the cutout structure or the molding compound matrix 220M. The LPoD structure (166P, 389, 188B) does not exist between adjacent metal bonding pad arrays (178, 358, 368, 468).

[0224] Reference Fig.14H, showing an eighth configuration of the unit area UA. In the eighth configuration, the LPoD structure (166P, 389, 188B) is formed in the area of ​​the semiconductor die 700 and the area of ​​the molding compound matrix 220M. The unit area UA may be the same as the area of ​​the fan-out package 720.

[0225] Reference Fig.14I , shows a ninth configuration of the unit area UA. In the ninth configuration, the LPoD structure (166P, 389, 188B) is formed in the area of ​​the molding compound matrix 220M, but not in the area of ​​the semiconductor die 700. The unit area UA may be the same as the area of ​​the fan-out package 720.

[0226] Reference Fig.14J , shows a tenth configuration of the unit area UA. In the tenth configuration, the LPoD structure (166P, 389, 188B) is formed in the area of ​​the semiconductor die 700, but not in the area of ​​the molding compound matrix 220M. The unit area UA may be the same as the area of ​​the fan-out package 720.

[0227] Common Reference Figures 1 to 9D , Fig.13 and FIG. 14A to FIG. 14J According to various embodiments of the present disclosure, a method for forming a device structure is provided. The method includes: forming a two-dimensional unit structure array on a substrate (110, 210), wherein each unit structure includes at least one semiconductor die (700, 720, 300, 400), wherein the semiconductor device (120, 320, 420) is contained, a metal interconnect structure (140, 340, 440) embedded in a dielectric material layer (150, 350, 450), and a cap dielectric layer 173 overlying the dielectric material layer (150, 350, 450); and forming a passivation level metal structure 167 and a first electrostatic discharge (ESD) path metal structure 168 in each unit structure, wherein each first ESD path metal structure 168 includes a first top surface segment TSS1 located in a first horizontal plane HP1, the first horizontal plane HP1 including a top surface of one of the passivation level metal structures 167, and also including an upper protrusion 166P protruding above the first horizontal plane HP1.

[0228] In one embodiment, the method further includes: forming a cap dielectric layer 173 on the passivation level metal structure 167 and the first ESD path metal structure 168 in each unit structure; and forming a through-hole opening (179A, 179B) through the cap dielectric layer 173 by performing an etching process, wherein the upper protruding portion 166P of each first ESD path metal structure 168 is physically exposed before the passivation level metal structure 167 is physically exposed. In one embodiment, the method further includes forming a first metal bonding pad 178A and a second metal bonding pad 1789B on each first ESD path metal structure 168, wherein: the first metal pad 178A has a flat bottom surface in contact with the first top surface segment TSS1; and the second metal bonding pad 178B in contact with the top surface of the upper protruding portion 166P. In one embodiment, the method further includes: attaching a first solder material portion 188A to the first metal bonding pad 178A; and attaching a second solder material portion 188B to the second metal bonding pad 178B.

[0229] In one embodiment, each unit structure includes a single semiconductor die (700, 720, 300, 400) and a notch structure 701; and the substrate includes a semiconductor wafer. In one embodiment, within each unit structure, a first ESD path metal structure 168 is formed in the notch structure 701. In one embodiment, each unit structure includes a second ESD path metal structure 168 formed in a single semiconductor die (700, 720, 300, 400). In one embodiment, within each unit structure, a first ESD path metal structure 168 is formed in a single semiconductor die (700, 720, 300, 400).

[0230] In one embodiment, each unit structure includes a molded plastic die frame 220 that laterally surrounds at least one semiconductor die (700, 720, 300, 400). In one embodiment, within each unit structure, a first ESD path metal structure 168 is formed over the molded plastic die frame 220. In one embodiment, each unit structure includes a second ESD path metal structure 168 formed in at least one semiconductor die (700, 720, 300, 400). In one embodiment, within each unit structure, a first ESD path metal structure 168 is formed in at least one semiconductor die (700, 720, 300, 400). In one embodiment, at least one semiconductor die (700, 720, 300, 400) includes a plurality of semiconductor chips (700, 720, 300, 400), each semiconductor chip being laterally surrounded by the molded plastic die frame 220.

[0231] In one embodiment, the upper protrusion 166P of each first ESD path metal structure 168 is formed with at least one inclined top surface, and the inclination angle of each top surface relative to the first horizontal plane HP1 is in the range of 0.1 degrees to 10 degrees. In one embodiment, in the area including the upper protrusion 166P of the ESD path metal structure 168, the first surface metal density at the level of the passivation level metal structure 167 and the first electrostatic discharge (ESD) path metal structure 166 is less than the second surface metal density at the level of the passivation level metal structure 167 and the first electrostatic discharge (ESD) path metal in the area of ​​the passivation level metal structure 167 by at least 3 times.

[0232] In one embodiment, the upper protruding portion 166P of each first ESD path metal structure 168 is formed with a flat top surface section and at least one vertical surface section having a bottom periphery within the first horizontal plane HP1 .

[0233] In one embodiment, the upper protruding portion 166P of the ESD path metal structure 168 of each first ESD path metal structure 168 has the same material composition as a portion of the passivation level metal structure 167 below the first horizontal plane HP1. In one embodiment, the upper protruding portion 166P of the ESD path metal structure 168 of each first ESD path metal structure 168 includes copper at a percentage of at least 98 atomic percent.

[0234] In one embodiment, the method includes forming a capping dielectric layer 173 on the passivation level metal structure 167 and the first ESD path metal structure 168 in each unit structure, wherein a second horizontal plane HP2 including a flat top surface of the capping dielectric film 173 is located above the first horizontal plane HP1. In one embodiment, the method includes forming a first metal bonding pad 178A and a second metal bonding pad 178B, wherein each of the first metal bonding pads includes a corresponding planar portion covering the second horizontal plane HP2 and a corresponding via portion located below the second horizontal plane HP2 and extending vertically through the capping dielectric layer 173. In one embodiment, the via portion of the first metal bonding pad 178A has a larger vertical extent than the via portion of the second metal bonding pad 178B.

[0235] In one embodiment, at least one semiconductor die (700, 720, 300, 400) in each unit structure includes: an electrostatic discharge (ESD) protection circuit 122 located on a semiconductor material portion; and a metal interconnect structure (140, 340, 440) embedded in a dielectric material layer (150, 350, 450) located between a semiconductor substrate (110, 210) and a cover dielectric layer 173, wherein a first ESD path metal structure 168 is electrically connected to the ESD protection circuit 122 through a subset of the metal interconnect structure.

[0236] Common Reference Figures 1 to 9D , Fig.13 and FIG. 14A to FIG. 14J According to various embodiments of the present disclosure, a device structure is provided. The device structure includes a two-dimensional array of unit structures located on a substrate (110, 210). Each unit structure includes at least one semiconductor die (700, 720, 300, 400), which includes a semiconductor device (120, 320, 420), a metal interconnect structure (140, 340, 440) embedded in a dielectric material layer (150, 350, 450), and at least one semiconductor die (700, 720, 300, 400) located in a cover dielectric layer 173 above the dielectric material layer (150, 350, 450). A passivation level metal structure 167 is embedded in the cover dielectric layer 173, which is located in at least one semiconductor die (700, 720, 300, 400) in each unit structure. A first electrostatic discharge (ESD) path metal structure 168 is embedded in the cover dielectric layer 173 in each unit structure. The first ESD path metal structure 168 includes a first top surface segment TSS1 located within a first horizontal plane HP1 that includes a top surface of one of the passivation level metal structures 167 , and also includes an upper protruding portion 166P protruding above the first horizontal plane HP1 .

[0237] In one embodiment, each unit structure includes: a first metal bonding pad 178A having a flat bottom surface in contact with the first top surface segment TSS1; and a second metal bonding pad 178B in contact with the top surface of the upper protrusion 166P. In one embodiment, the device structure further includes: a first solder material portion 188A in contact with the first metal bonding pad 178A; and a second solder material portion 188B in contact with the second metal bonding pad 178B.

[0238] In one embodiment, each unit structure includes a single semiconductor die (700, 720, 300, 400) and a notch structure 701; and the substrate includes a semiconductor wafer. In one embodiment, within each unit structure, a first ESD path metal structure 168 is located in the notch structure 701. In one embodiment, each unit structure includes a second ESD path metal structure 168 located in a single semiconductor die (700, 720, 300, 400). In one embodiment, within each unit structure, a first ESD path metal structure 168 is located in a single semiconductor die (700, 720, 300, 400).

[0239] In one embodiment, each unit structure includes a molded plastic die frame 220 that laterally surrounds at least one semiconductor die (700, 720, 300, 400). In one embodiment, within each unit structure, a first ESD path metal structure 168 is located above the molded plastic die frame 220. In one embodiment, each unit structure includes a second ESD path metal structure 168 located in at least one semiconductor die (700, 720, 300, 400). In one embodiment, within each unit structure, a first ESD path metal structure 168 is located in at least one semiconductor die (700, 720, 300, 400). In one embodiment, the at least one semiconductor die (700, 720, 300, 400) includes a plurality of semiconductor chips (700, 720, 300, 400), each semiconductor chip being laterally surrounded by the molded plastic die frame 220.

[0240] In one embodiment, the upper protrusion 166P has at least one inclined top surface, and the inclination angle of each top surface relative to the first horizontal plane HP1 is in the range of 0.1 degrees to 10 degrees. In one embodiment, the first surface metal density at the level of the passivation level metal structure 167 and the first ESD path metal structure 168 in the area of ​​the upper protrusion 166P including the first ESD path metal structure 168 is less than the second surface metal density at the level of the passivation level metal structure 167 and the first ESD path metal structure 168 in the area of ​​the passivation level metal structure 167 by at least 3 times.

[0241] In one embodiment, the upper protrusion 166P includes a flat top surface segment and at least one vertical surface segment having a bottom periphery in the first horizontal plane HP1.

[0242] In one embodiment, the upper protruding portion 166P of the ESD path metal structure 168 has the same material composition as a portion of the passivation level metal structure 167 below the first horizontal plane HP1. In one embodiment, the upper protruding portion 166P of the ESD path metal structure 168 includes at least 98 atomic percent copper.

[0243] In one embodiment, a second horizontal plane HP2 including a flat top surface of cover dielectric layer 173 is located above first horizontal plane HP1; and each of first metal bonding pad 178A and second metal bonding pad 178B includes a corresponding planar portion covering second horizontal plane HP2 and a corresponding via portion located below second horizontal plane HP2 and extending vertically through cover dielectric layer 173. In one embodiment, the via portion of first metal bonding pad 178A has a greater vertical extent than the via portion of second metal bonding pad 178B.

[0244] In one embodiment, at least one semiconductor die (700, 720, 300, 400) in each unit structure includes: an electrostatic discharge (ESD) protection circuit 122 located on a semiconductor material portion; and a metal interconnect structure (140, 340, 440) embedded in a dielectric material layer (150, 350, 450) located between a semiconductor substrate (110, 210) 110 and a cover dielectric layer 173, wherein a first ESD path metal structure 168 is electrically connected to the ESD protection circuit 122 through a subset of the metal interconnect structure.

[0245] FIG. 15A to FIG. 15L are various views of the structure of the seventh embodiment. Fig.15A FIG. 4 is a top view of a structure of a seventh embodiment including a wafer or a reconstituted wafer according to a seventh embodiment of the present disclosure. Fig. 15B yes Fig.15A An enlarged view of a unit area in the structure of the seventh embodiment. Fig. 15C The area along which the first configuration of the seventh embodiment is arranged Fig. 15B Vertical cross-sectional view of the vertical plane C-C'. Fig.15D The area along which the first configuration of the seventh embodiment is arranged Fig. 15B Vertical cross-sectional view of the vertical plane D-D'. Fig.15E The area along which the second configuration of the seventh embodiment is arranged Fig. 15B Vertical cross-sectional view of the vertical plane C-C'. Fig.15F The area along which the second configuration of the seventh embodiment is arranged Fig. 15B Vertical cross-sectional view of the vertical plane D-D'.

[0246] Common Reference FIG. 15A to FIG. 15F , FIG. 15A to FIG. 15GThe first and second configurations of the seventh embodiment structure shown may be obtained by forming an elongated metal strip structure 198 outside the area of ​​the semiconductor die (700, 720, 300, 400). Fig.13 and FIG. 14A to FIG. 14J In any of the foregoing embodiments in which metal bonding pad 178 is formed, elongated metal strip structure 198 may be formed simultaneously with the formation of metal bonding pad 178. Therefore, the horizontally extending portion of elongated metal strip structure 198 may have the same thickness and the same material composition as the horizontally extending portion of metal bonding pad 178. In general, in the structure of the seventh embodiment, the discharge guiding point (LPoD) structure (166P, 389, 188B) used in the structure of the sixth embodiment is optional and may therefore be present or may be omitted.

[0247] FIG. 15A to FIG. 15D The first configuration of the seventh embodiment structure shown corresponds to an embodiment in which the substrate includes a semiconductor substrate 110, each semiconductor die includes a corresponding portion of the semiconductor substrate 100 (before the semiconductor substrate 110 is cut), and a notch structure 701 is formed in the notch area within each unit area UA. In this embodiment, the elongated metal strip structure 198 is formed as an element of the notch structure 701 on the bonding level dielectric layer 170, and the bonding level dielectric layer 170 may include a stack of the first passivation dielectric layer 161, the second passivation dielectric layer 163, and the cap dielectric layer 173 as described above. The metal connection structure 178C provides an electrical connection between the elongated metal strip structure 198 and the ESD protection circuit 122, for example, through a discharge current path that may be provided between one of the metal bonding pads 178 and the ESD protection line circuit 122. The metal connection structure 178C may be provided at the level of the elongated metal strip structure 198, the level of the ESD path metal structure 168, the level of the metal bonding pad structure 158, and / or the level of the metal interconnect structure 140.

[0248] Fig.15A , Fig. 15B , Fig.15F and Figure 15GThe second configuration of the seventh embodiment structure shown corresponds to an embodiment in which the substrate includes a carrier substrate 210, and the semiconductor die 700 is bonded to the carrier substrate 210 by the bonding layer 211. In this embodiment, the elongated metal strip structure 198 is formed on the molding compound matrix 220M, which laterally surrounds the plurality of semiconductor dies 700 in the two-dimensional semiconductor die array 700. The metal connection structure 178C provides an electrical connection between the elongated metal strip structure 198 and the ESD protection circuit 122, for example, through a discharge current path that may be provided between one of the metal bonding pads 178 and the ESD protection circuit 122. The metal connection structure 178C may be provided at the level of the elongated metal strip structure 198 and the metal bonding pad 178.

[0249] Figure 15G yes Fig.15A An enlarged view of the unit area in the third configuration of the structure of the seventh embodiment. Fig.15H The third configuration area of ​​the seventh embodiment is along Figure 15G Vertical cross-sectional view of the vertical plane H-H'. Fig.15I The third configuration area of ​​the seventh embodiment is along Figure 15G A vertical cross-sectional view of a vertical plane I-I'. Fig.15J yes Fig.15H Magnified view of area J. Figure 15K yes Fig.15I Magnified view of area K. Figure 15L yes Fig.15I Detailed view of the .

[0250] The third configuration of the seventh embodiment structure can be derived from the first configuration of the seventh embodiment structure by forming an ESD protection circuit 122' (which can be referred to as an additional ESD protection circuit or a second ESD protection circuit) in the notch structure 701 (i.e., outside the semiconductor die 700). A metal interconnect structure 140' (which can be referred to as an additional metal interconnect structure or a second metal interconnect structure) can be formed in the dielectric material layer 150, and an additional metal connection structure (which can include an additional ESD path metal structure 168' and an additional metal bonding pad structure 158') can be formed in the bonding level dielectric layer 170. The elongated metal strip structure 198 can be electrically connected to the ESD protection circuit 122' in the notch structure 701 through the metal interconnect structure 140' and the additional metal connection structure (158', 168'). Therefore, there is no need to form the metal connection structure 178C used in the first configuration of the seventh embodiment structure. In some embodiments, as Figure 15L As shown, the metal interconnect structure 140' may be arranged as a row of vertical interconnect pathways extending vertically from the ESD protection circuit 122' to the additional metal connection structures (158', 168').

[0251] Common Reference Figures 1 to 6I , Fig.15A and FIG. 15H to FIG. 15L According to various embodiments of the present disclosure, a method for forming a device structure is provided. The method includes: forming a two-dimensional unit structure array located on a substrate (which may be a semiconductor substrate 110, such as a semiconductor wafer), wherein each unit structure in the two-dimensional unit structure array includes a semiconductor die 700 and a notch structure 701, wherein the semiconductor die 700 includes a semiconductor device 120, a first metal interconnect structure 140 embedded in a first portion of a dielectric material layer 150, and wherein the notch structure 701 includes an electrostatic discharge (ESD) protection circuit 122, a second metal interconnect structure 140' embedded in a second portion of the dielectric material layer 150; and in each A patterned metal structure (178, 198) is formed on each unit structure, wherein the patterned metal structure (178, 198) includes a group of metal bonding pads 178, which are electrically connected to the semiconductor device 120 through the first metal interconnect structure 140 in the semiconductor tube core 700 in each unit structure, and also includes a first elongated metal strip structure 198, whose top surface is located in a horizontal plane including the top surface of the metal bonding pad 176, and is electrically connected to the ESD protection circuit 122 of each unit structure through the second metal interconnect structure 140' of each unit structure.

[0252] In one embodiment, the two-dimensional array of unit structures has a first pitch p1 along a first horizontal direction hd1; and the first elongated metal strip structure 198 extends laterally along the first horizontal direction hd1 by at least half of the first pitch p1. In one embodiment, the cutout structure 701 includes a second elongated metal strip structure 198, whose top surface is located in a horizontal plane and is electrically connected to the ESD protection circuit 122 through an additional second metal interconnect structure 140'. In one embodiment, the two-dimensional array of unit structures has a second pitch p2 along a second horizontal direction hd2; and the second elongated metal strip structure 198 extends laterally along the second horizontal direction hd2 by at least half of the second pitch p2.

[0253] In one embodiment, the method further includes forming a capping dielectric layer 173 on the two-dimensional array of unit structures; and forming a via opening through the capping dielectric layer 173, wherein each of the metal bonding pads 178 and the first elongated metal strip structure 198 includes a respective via portion extending vertically through the corresponding via opening in the capping dielectric layer 173. In one embodiment, each metal bonding pad 178 includes a respective plate portion overlying the capping dielectric layer 173; and the first elongated metal strip structure 198 includes a line portion overlying the capping dielectric layer 173.

[0254] FIG. 16A to FIG. 16E are sequential vertical cross-sectional views of the structure of the eighth embodiment according to the eighth embodiment of the present disclosure, wherein FIG. 15A to FIG. 15G The seventh exemplary structure is processed to attach solder material portion 188 .

[0255] Reference Fig.16A , a solder ball attachment device is provided, which includes a chuck 620 configured to mount a wafer or a reconstructed wafer thereon, a frame 610 attached to the periphery of the chuck 620 and serving as a lateral cladding frame, and a template support structure 630 configured to structurally support a conductive template subsequently placed thereon. A wafer including a two-dimensional array of unit structures and a substrate (110, 210) can be mounted on the chuck 620. Generally, a wafer or a reconstructed wafer of any configuration including the seventh embodiment structure can be placed on the top surface of the chuck 620. Although the present disclosure is described using embodiments in which a wafer of the first configuration or the third configuration including the seventh embodiment structure is used, embodiments using a reconstructed wafer of the second configuration including the seventh embodiment structure are explicitly contemplated herein.

[0256] Reference Fig. 16B , a conductive template 640 including an array of openings can be disposed on the two-dimensional array of unit structures. The pattern of openings in the conductive template 640 matches the pattern of metal bonding pads 178 on the wafer. The conductive template 640 can be aligned with the wafer so that the openings in the conductive template 640 are aligned with the corresponding underlying metal bonding pads 178, and each elongated metal strip structure 198 is located outside the opening area of ​​the conductive template 640.

[0257] Each opening in the conductive template 640 can have the same size and the same shape (e.g., circular). The size of the opening in the conductive template 640 is determined by the size of the solder ball to be attached to the metal bonding pad 178 on the wafer. The opening in the conductive template 640 is large enough to pass a single solder ball while preventing multiple solder balls from passing through. In addition, the thickness of the conductive template 640 is selected to prevent two or more solder balls from piling up in a single opening. In an illustrative example, the metal bonding pad 178 can be configured to bond with a solder ball having a diameter in the range of 20 microns to 80 microns. In this embodiment, the diameter of each opening in the conductive template 640 can be in the range of 101% to 150% of the diameter of the solder ball to be used subsequently. In addition, the thickness of the conductive template 640 can be in the range of 50% to 100% of the diameter of the solder ball to be used subsequently.

[0258] refer to Fig. 16C, the vertical distance between the conductive template 640 and the two-dimensional unit structure array can be reduced so that the elongated metal strip structure 198 contacts the bottom surface of the conductive template 640, while the group of metal bonding pads 178 does not contact the conductive template 640. Before the elongated metal strip structure 198 contacts the bottom surface of the conductive template 640, an electrostatic discharge (ESD) event may occur immediately, and electrostatic charge may flow between the conductive template 640 and the elongated metal strip structure 198. The discharge can be directed to the ESD protection circuit (122 or 122') described with reference to the structure of the seventh embodiment. Therefore, in the structures of the seventh and eighth embodiments, the elongated metal strip structure 198 serves as a discharge guiding point (LPoD) structure.

[0259] Reference Fig.16D , the vertical distance between the conductive template 640 and the two-dimensional array of unit structures can be reduced to zero, and the elongated metal strip structure 198 contacts the bottom surface of the conductive template 640. The metal bonding pad 178 is aligned with the opening in the conductive template 640. In one embodiment, the metal bonding pad 178 does not contact the conductive template 640.

[0260] Reference Fig.16E , solder balls 188 can pass through the openings in the conductive template 640, for example, by spreading the solder balls 188 on the conductive template 640 and sweeping the solder balls 188 with a roller 650 including at least one rotating brush 652. A single solder ball 188 falls into each opening in the conductive template 640 and lands on a corresponding one of the metal bonding pads 178. Excess solder balls 188 can be removed from above the conductive template 640. Subsequently, the solder balls 188 can be attached to each set of metal bonding pads 178 within the corresponding semiconductor die 700 by reflowing the solder balls 188. In general, the solder balls 188 can be attached to the metal bonding pads 178 of the semiconductor die 700 in the two-dimensional unit structure array without attaching the solder balls 188 to the elongated metal strip structures 198.

[0261] Common Reference Figures 1 to 6I , Fig.15A , FIG. 15H to FIG. 15L and FIG. 16A to FIG. 16EAccording to various embodiments of the present disclosure, a device structure is provided, which includes a two-dimensional array of unit structures located on a substrate. Each unit structure includes a semiconductor die 700 and a notch structure 701. The semiconductor die 700 includes a semiconductor device 120, a first metal interconnect structure 140 embedded in a first portion of a dielectric material layer 150, and a metal bonding pad 178 electrically connected to the semiconductor device 120 through the first metal interconnect structure 140. The notch structure 701 includes an electrostatic discharge (ESD) protection circuit 122, a second metal interconnect structure 140' embedded in a second portion of the dielectric material layer 150, and a first elongated metal strip structure 198, the top surface of which is located in a horizontal plane including the top surface of the metal bonding pad 178, and is electrically connected to the ESD protection circuit 122 through the second metal interconnect structure 140'.

[0262] In one embodiment, the two-dimensional array of unit structures has a first pitch p1 along a first horizontal direction hd1; and the first elongated metal strip structure 198 extends laterally along the first horizontal direction hd1 by at least half of the first pitch p1. In one embodiment, the cutout structure 701 includes a second elongated metal strip structure 198, whose top surface is located in a horizontal plane and is electrically connected to the ESD protection circuit 122 through an additional second metal interconnect structure 140'. In one embodiment, the two-dimensional array of unit structures has a second pitch p2 along a second horizontal direction hd2; and the second elongated metal strip structure 198 extends laterally along the second horizontal direction hd2 by at least half of the second pitch p2.

[0263] In one embodiment, the device structure includes solder balls 188 bonded to metal bond pads 178 of semiconductor die 700 in a two-dimensional array of unit structures, wherein first elongated metal strip structures 198 are not in contact with the material of solder balls 188 .

[0264] In one embodiment, cover dielectric layer 173 extends continuously through the two-dimensional array of unit structures; and each of metal bond pads 178 and first elongated metal strip structures 198 includes a respective via portion extending vertically through a corresponding via opening in cover dielectric layer 173. In one embodiment, each metal bond pad 178 includes a respective plate portion overlying cover dielectric layer 173; and first elongated metal strip structures 198 include a line portion overlying cover dielectric layer 173.

[0265] Fig.17Schematic circuit diagram of a combined electrostatic discharge circuit during various pilot point operations of the discharge structure of various embodiments of the present disclosure. Generally, a first semiconductor die (700, 300, 400) including a first semiconductor device 120 and a first ESD protection circuit 122 and a second semiconductor die including a second semiconductor device 120 and a second ESD protection circuit 112 can be provided. Each ESD protection circuit 122 may include any ESD protection circuit element known in the art, such as at least one diode. The first semiconductor device 120 and the second semiconductor device 120 may include any semiconductor device known in the art, and may include device components that are sensitive to ESD events, such as a die-to-die input / output driver. The electrostatic charge on the first semiconductor die (700, 300, 400) and the second semiconductor die is represented by a capacitor.

[0266] A discharge pilot point (LPoD) structure is provided between a first semiconductor die (700, 300, 400) and a second semiconductor die (700, 300, 400). The LPoD structure may be any of the above-described LPoDs and may be a part of the first semiconductor die (700, 300, 400), may be the second semiconductor die (700, 300, 400), or may be an external component that is not part of the first semiconductor die (700, 300, 400) or the second semiconductor die (700, 300, 400). During bonding of the second semiconductor die (700, 300, 400), the LPoD structure induces an electrical connection between an electrical node of the first semiconductor die (700, 300, 400) and an electrical node of the second semiconductor die (700, 300, 400), and induces an electrostatic discharge event. A discharge current flows through the LPoD structure. The electrical connection between the electrical nodes of the semiconductor device 120 that needs to be protected from the ESD event only occurs after the ESD event. Therefore, through the LPoD structure of the present disclosure, the semiconductor devices 120 in the first semiconductor die (700, 300, 400) and the second semiconductor die (700, 300, 400) can be protected from the ESD event.

[0267] Fig.18 is a first flow chart illustrating steps of forming a device structure according to an embodiment of the present disclosure.

[0268] Refer to step 1810 and Figure 1 , a semiconductor device 120 may be formed on a semiconductor substrate 110 .

[0269] Refer to step 1820 and FIG. 2A to FIG. 2F , Figure 3 and FIG. 6A to FIG. 6C, a passivation level metal structure 167 and an electrostatic discharge (ESD) path metal structure 168 may be formed. The ESD path metal structure 168 includes a first top surface segment TSS1 located within a first horizontal plane HP1, which includes a top surface of one of the passivation level metal structures 167, and also includes an upper protrusion 166P protruding above the first horizontal plane HP-1.

[0270] Refer to step 1830 and Figure 4A and Fig.6D , a capping dielectric layer 173 may be formed on the passivation level metal structure 167 and the electrostatic discharge (ESD) path metal structure 168 .

[0271] Refer to step 1840 and Figure 4A , Figure 4B , Fig.6D and Fig. 6E By performing an etching process, the first via opening 179A and the second via opening 79B may be formed through the capping dielectric layer 173. Before the first top surface segment TSS1 is exposed below the first via opening 179A, the surface of the upper protrusion 166P is physically exposed below the second via opening 79B.

[0272] Fig.19 is a second flow chart illustrating steps for forming a device structure according to an embodiment of the present disclosure.

[0273] Refer to step 1910 and Fig. 7A , the first semiconductor die 700 and the second semiconductor die 600 may be attached to the carrier substrate 210. The first semiconductor die 700 includes a first semiconductor substrate 110 and a first electrostatic discharge (ESD) protection circuit 122 electrically connected to the first semiconductor substrate 110.

[0274] Refer to step 1920 and Figure 7B , a molding compound matrix 220M may be formed around the first semiconductor die 700 and the second semiconductor die 600 .

[0275] Refer to steps 1930 and Figure 7C , Fig.7D , Fig. 8A and Figure 8B , a patterned metal structure (167, 168) can be formed, which includes a first passivation level metal structure 167 formed on the first semiconductor die 700, a second passivation level metal structure 167 formed on the second semiconductor die 700, and an electrostatic discharge (ESD) path metal structure 168 formed on the top surface of the molded material die frame 220 and electrically connected to the first ESD protection circuit 122.

[0276] Fig. 20is a third flow chart illustrating steps for forming a device structure according to an embodiment of the present disclosure.

[0277] Refer to Step 2010 and Fig. 10A and Fig. 10B , providing a first semiconductor die 300, which includes a first semiconductor substrate 310, a first semiconductor device 120 located on the first semiconductor substrate 310, and a first dielectric material layer 350 and a first metal bonding pad 358 in which a first metal interconnect structure 340 is buried, wherein the first metal pad 358 includes a first type first metal bonding pad 358A and a second type first metal bonding pad 358B.

[0278] Refer to steps 2020 and Fig. 10C , the intermediate metal material portion 389 can be attached to the second type first metal bonding pad 358B without covering the surface of the first type first metal bonding pad 358A with any metal material.

[0279] Refer to steps 2030 and Fig. 10D , providing a second semiconductor die 400, which includes a second semiconductor substrate 410, a second semiconductor device 420 located on the second semiconductor substrate 410, a second dielectric material layer 450 in which a second metal interconnect structure 440 is buried, and a second metal bonding pad 488, wherein the second metal bonding pad 488 includes a first type second metal bonding pad 488A and a second type second metal bonding pad 488B.

[0280] Refer to steps 2040 and Fig. 10E and Fig.10F , first type second metal bonding pad 488A may be bonded to first type first metal bonding pad 358A, while intermediate metal material portion 389 is disposed between a mating pair of second type second metal bonding pad 488B and second type first metal bonding pad 358B.

[0281] Fig.21 is a fourth flow chart illustrating steps of forming a device structure according to an embodiment of the present disclosure.

[0282] Refer to step 2110 and Fig.11A and Fig. 12A , providing a first semiconductor die 300, which includes a first semiconductor substrate 310, a first semiconductor device 120 located on the first semiconductor substrate 310, and a first dielectric material layer 350 and a first metal bonding pad 368 in which a first metal interconnect structure 340 is buried, wherein the first metal bonding pad 368 includes a first type first metal bonding pad 368A and a second type first metal bonding pad 368B.

[0283] Refer to step 2120 and Fig. 11B and Fig. 12A , providing a structure including an interconnect (e.g., a second semiconductor die 400 or an interposer 800), which embeds a second metal interconnect structure (e.g., a first metal interconnect structure 440 or a redistribution wiring interconnect 840) and includes a second metal bonding pad (e.g., a first metal bonding pad 488 or an interposer metal bonding pad 878). The second metal bonding pad (488 or 878) includes a first type second metal bonding pad (488A or 878A) and a second type second metal bonding pad (488B or 878B).

[0284] Refer to step 2130 and Fig.11A and Fig. 12A , attaching the first solder material portion 188A to a corresponding one of the first type first metal bonding pads 368A, wherein the first solder material portion 1888 has a first height.

[0285] Refer to step 2140 and Fig.11A and Fig. 12A , attaching the second solder material portion 188B to a corresponding one of the second type first metal bonding pads 368B, wherein the second solder material portion 188B has a second height greater than the first height.

[0286] Refer to step 2150 and Fig. 11C , Fig.11D , Fig. 12B and Fig. 12C , performing a bonding process wherein the first solder material portion 188A is bonded to a corresponding one of the first type second metal bonding pads (488A or 878A), and the second solder material portion 188B is bonded to an appropriate one of the second type second metal bonding pads (488B or 878B).

[0287] Fig. 22 is a fifth flow chart illustrating steps of forming a device structure according to an embodiment of the present disclosure.

[0288] Refer to step 2210 and Fig. 12A , a first semiconductor die 300 is provided, which includes a first semiconductor substrate 310, a first semiconductor device 120 located on the first semiconductor substrate 310, and a first dielectric material layer 350 and a first metal bonding pad 368 embedded with a first metal interconnect structure 340. The first metal bonding pad 368 includes a first type first metal bonding pad 368A and a second type first metal bonding pad 368B.

[0289] Refer to step 2220 and Fig. 12A, an interposer 800 is provided, which includes a redistribution wiring interconnect 840 embedded in a redistribution dielectric layer 850, the dielectric layer including a polymer material, and also includes an interposer metal bonding pad 878. The interposer metal bonding pad 878 includes a first type interposer metal bonding pad 878A and a second type interposer material pad 878B.

[0290] Refer to step 2230 and Fig. 12A , attaching the first solder material portion 188A to a corresponding one of the first type first metal bond pads 368A. The first solder material portion 188A has a first height.

[0291] Refer to steps 2240 and Fig. 12A , attaching the second solder material portion 188B to a corresponding one of the second type first metal bond pads 368B. The second solder material portion 188B has a second height that is greater than the first height.

[0292] Refer to step 2250 and Fig. 12B and Fig. 12C , a bonding process is performed in which the first solder material portion 188A is bonded to a corresponding one of the first type interposer metal bonding pads 878A, and the second solder material portion 188B is bonded to a corresponding one of the second type interposer metal bonding pads.

[0293] Fig.23 is a sixth flow chart illustrating steps of forming a device structure according to an embodiment of the present disclosure.

[0294] Refer to step 2310 and Figure 1 , Fig. 7A , Figure 7B , Fig.13 and FIG. 14A to FIG. 14G A two-dimensional array of unit structures can be formed on a substrate (110, 210). Each unit structure includes at least one semiconductor die (700, 720, 300, 400), which contains a semiconductor device (120, 320, 420), a metal interconnect structure (140, 340, 440) embedded in a dielectric material layer (150, 350, 450), and a cap dielectric layer 173 located above the dielectric material layer (150, 350, 450).

[0295] Refer to step 2320 and FIG. 2A to FIG. 2F , Figure 3 , FIG. 6A to FIG. 6C , Figure 7C , Fig.7D , Fig. 8A , Figure 8B , Fig.13 and FIG. 14A to FIG. 14G, a passivation level metal structure 167 and a first electrostatic discharge (ESD) path metal structure 168 may be formed in each unit structure. Each first ESD path metal structure 168 includes a first top surface segment TSS1 located within a first horizontal plane HP1 that includes a top surface of one of the passivation level metal structures 167, and also includes an upper protrusion 166P protruding above the first horizontal plane HP1.

[0296] Fig.24 is a seventh flow chart illustrating steps of forming a device structure according to an embodiment of the present disclosure.

[0297] Refer to step 2410 and Figure 1 , Fig. 7A , Figure 7B , Fig.13 , FIG. 14A to FIG. 14G , Fig.15A and Figure 15G to Figure 15L , a two-dimensional unit structure array located on a substrate can be formed. Each unit structure in the two-dimensional unit structure array includes a semiconductor die 700 and a notch structure 701. The semiconductor die 700 includes a semiconductor device 120, a first metal interconnect structure 140 embedded in a first portion of a dielectric material layer 150, wherein the notch structure 701 includes an electrostatic discharge (ESD) protection circuit 122, and a second metal interconnect structure 140' embedded in a second portion of the dielectric material layer 150.

[0298] Refer to step 2420 and FIG. 2A to FIG. 2F , Figure 3 , FIG. 6A to FIG. 6C , Figure 7C , Fig.7D , Fig. 8A , Figure 8B , Fig.13 , FIG. 14A to FIG. 14G , Fig.15A and Figure 15G to Figure 15L , a patterned metal structure (168, 198) may be formed on each of the unit structures. The patterned metal structure (168, 198) includes a set of metal bonding pads 178, which are electrically connected to the semiconductor device 120 through the first metal interconnect structure 140 in the semiconductor die 700 in each of the unit structures, and also includes a first elongated metal strip structure 198, whose top surface is located in a horizontal plane including the top surface of the metal bonding pads 178' and is electrically connected to the ESD protection circuit 122 of each unit structure through the second metal interconnect structure 140' of each unit structure.

[0299] Various embodiments of the present disclosure may be used to provide and utilize discharge pilot point (LPoD) structures at the interconnect level, die level, and / or wafer level. Various LPoD structures may be formed on a semiconductor wafer (serving as semiconductor substrate 110) or on a carrier substrate 210 supporting a reconstructed wafer. The LPoD structure may include an upper protrusion on an ESD path metal structure, an intermediate metal material portion, a solder material portion having a height greater than a normal solder material portion that does not provide ESD protection, or an elongated metal strip structure. The LPoD structure may be used in an anisotropic etching process for forming a through-hole cavity, a bonding process using a solder material portion, a bonding process using metal-to-metal bonding, and / or a solder ball attachment process.

[0300] According to one aspect of an embodiment of the present application, a semiconductor device structure is provided, comprising: a semiconductor device located on a semiconductor substrate; an electrostatic discharge (ESD) path metal structure buried in a cover dielectric layer, wherein the electrostatic discharge path metal structure comprises a first top surface segment located within a first horizontal plane, and further comprises an upper protrusion protruding above the first horizontal plane; a first metal bonding pad having a flat bottom surface in contact with the first top surface segment; and a second metal bonding pad in contact with the top surface of the upper protrusion.

[0301] In some embodiments, the semiconductor device structure further includes: a first solder material portion contacting the first metal bonding pad; and a second solder material portion contacting the second metal bonding pad.

[0302] In some embodiments, the upper protruding portion has at least one inclined top surface, each top surface having an inclined angle relative to the first horizontal plane.

[0303] In some embodiments, the semiconductor device structure also includes a passivation level metal structure located at the same level as the electrostatic discharge path metal structure, wherein a top surface of one of the passivation level metal structures is located within a first horizontal plane, and wherein a first surface metal density at the level of the passivation level metal structure and the electrostatic discharge path metal structure within an area including an upper protruding portion of the electrostatic discharge path metal structure is at least 3 times smaller than a second surface metal density at the level of the passivation level metal structure and the electrostatic discharge path metal structure within an area of ​​the passivation level metal structure.

[0304] In some embodiments, the upper protruding portion of the electrostatic discharge path metal structure has the same material composition as a portion of one of the passivation level metal structures located below the first horizontal plane.

[0305] In some embodiments, the upper projection includes a planar top surface segment and at least one vertical surface segment having a bottom periphery in a first horizontal plane.

[0306] In some embodiments, the upper raised portion of the electrostatic discharge path metal structure includes at least 98 atomic percent copper.

[0307] In some embodiments, a second horizontal plane including a flat top surface of a cover dielectric layer is located above the first horizontal plane; and each of the first metal bonding pad and the second metal bonding pad includes a corresponding flat portion overlying the second horizontal plane and a corresponding through-hole portion underlying the second horizontal plane and extending vertically through the cover dielectric layer.

[0308] In some embodiments, the via portion of the first metal bond pad has a greater vertical extent than the via portion of the second metal bond pad.

[0309] In some embodiments, the semiconductor device structure also includes: an electrostatic discharge (ESD) protection circuit located on the semiconductor substrate; and a metal interconnect structure buried in a dielectric material layer between the semiconductor substrate and a cover dielectric layer, wherein the electrostatic discharge path metal structure is electrically connected to the electrostatic discharge protection circuit through a subset of the metal interconnect structure.

[0310] According to another aspect of an embodiment of the present application, a semiconductor device structure is provided, which includes: a molded plastic die frame laterally surrounding a first semiconductor die and a second semiconductor die; a first passivation level metal structure overlying the first semiconductor die; a second passivation level metal structure overlying the second semiconductor die; an electrostatic discharge (ESD) path metal structure overlying the first semiconductor die, the molded plastic die frame, and the second semiconductor die, wherein the electrostatic discharge path metal structure includes a first top surface segment located in a first horizontal plane, the first horizontal plane includes a top surface of one of the first passivation level metal structures and a top surface of one of the second passivation level metal structures, and the electrostatic discharge path metal structure also includes an upper protrusion protruding above the first horizontal plane; a first metal bonding pad having a flat bottom surface in contact with the first top surface segment; and a second metal bonding pad in contact with the top surface of the upper protrusion.

[0311] In some embodiments, the semiconductor device structure further includes: a first solder material portion contacting the first metal bonding pad; and a second solder material portion contacting the second metal bonding pad.

[0312] In some embodiments, the first metal bond pad has an area overlap with the molding compound die frame in plan view; and the second metal bond pad is completely within the area of ​​the first semiconductor die in plan view.

[0313] In some embodiments, the upper projection has an area overlap with the molding compound die frame in plan view.

[0314] In some embodiments, the semiconductor device structure also includes a capping dielectric layer in which a first passivation level metal structure, a second passivation level metal structure, and an electrostatic discharge path metal structure are buried, wherein a first surface metal density at the level of the first passivation level metal structure and the second passivation level metal structure in an area including an upper protruding portion of the electrostatic discharge path metal structure is at least 3 times smaller than a second surface metal density at the level of the first passivation level metal structure and the second passivation level metal structure in an area of ​​the first passivation level metal structure.

[0315] According to another aspect of an embodiment of the present application, a semiconductor device structure is provided, comprising: a first semiconductor die, comprising a first semiconductor substrate, a first semiconductor device located on the first semiconductor substrate, a first dielectric material layer in which a first metal interconnect structure is buried, and a first metal bonding pad, wherein the first metal bonding pad comprises a first type first metal bonding pad and a second type first metal bonding pad; a second semiconductor die, comprising a second semiconductor substrate, a second semiconductor device located on the second semiconductor substrate, a second dielectric material layer in which a second metal interconnect structure is buried, and a second metal bonding pad, wherein the second metal bonding pad comprises a first type second metal bonding pad directly bonded to the first type first metal bonding pad and a second type second metal bonding pad that does not contact any first metal bonding pad; and intermediate metal material portions, wherein each intermediate metal material portion contacts a corresponding one of the second type first metal bonding pads and a corresponding one of the second type second metal bonding pads.

[0316] In some embodiments, each first type first metallic bonding pad has a first thickness; and each second type first metallic bonding pad has a second thickness that is less than the first thickness.

[0317] In some embodiments, each second metal bonding pad has a uniform thickness throughout.

[0318] In some embodiments, the metal material portion thickness of each intermediate metal material portion is equal to a difference between the first thickness and the second thickness.

[0319] In some embodiments, each intermediate metal material portion has a corresponding horizontal surface segment that lies within a horizontal plane of the bonding surface including the first type first metal bonding pad.

[0320] The above outlines the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Unless otherwise explicitly disclosed herein, each embodiment described using the word "including" also inherently discloses other embodiments, where "including" is replaced by "substantially consisting of" or "consisting of" ... Whenever two or more elements are listed as alternatives in the same paragraph or in different paragraphs, a Markush group including two or more lists of elements is also implicitly disclosed. Whenever the auxiliary verb "may" is used in the present disclosure to describe the formation of an element or the execution of a processing step, embodiments in which such elements or such processing steps are not performed are also explicitly considered, provided that the resulting device or apparatus can provide equivalent results. Therefore, the auxiliary verb "may" applied to the formation of an element or the execution of a processing step should also be interpreted as "may" or "may or may not", as long as the formation of such an element or processing step can provide the same result or equivalent result, and the equivalent result includes slightly better results and slightly worse results. It should be understood by those skilled in the art that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device structure, comprising: A semiconductor device is located on a semiconductor substrate; an electrostatic discharge path metal structure buried in the cover dielectric layer, wherein the electrostatic discharge path metal structure includes a first top surface segment located in a first horizontal plane and further includes an upper protrusion protruding above the first horizontal plane; a first metal bonding pad having a planar bottom surface in contact with the first top surface segment; and A second metal bonding pad contacts a top surface of the upper protruding portion.

2. The semiconductor device structure according to claim 1, further comprising: a first solder material portion in contact with the first metal bond pad; as well as A second solder material portion contacts the second metal bond pad.

3. The semiconductor device structure according to claim 1, wherein: The upper protruding portion has at least one inclined top surface, and each of the top surfaces has an inclined angle relative to the first horizontal plane.

4. The semiconductor device structure according to claim 1, further comprising a passivation level metal structure located at the same level as the electrostatic discharge path metal structure, wherein: The top surface of one of the passivation level metal structures is located in the first horizontal plane, and wherein the first surface metal density at the level of the passivation level metal structure and the electrostatic discharge path metal structure in the area including the upper protrusion of the electrostatic discharge path metal structure is at least 3 times smaller than the second surface metal density at the level of the passivation level metal structure and the electrostatic discharge path metal structure in the area of ​​the passivation level metal structure.

5. The semiconductor device structure according to claim 1, wherein: a second horizontal plane including a planar top surface of the cap dielectric layer located above the first horizontal plane; as well as Each of the first metal bonding pad and the second metal bonding pad includes a corresponding planar portion overlying the second horizontal plane and a corresponding via portion underlying the second horizontal plane and extending vertically through the capping dielectric layer.

6. The semiconductor device structure according to claim 1, further comprising: An electrostatic discharge protection circuit, located on the semiconductor substrate; as well as a metal interconnect structure embedded in a dielectric material layer between the semiconductor substrate and the cap dielectric layer, The electrostatic discharge path metal structure is electrically connected to the electrostatic discharge protection circuit through a subset of the metal interconnect structure.

7. A semiconductor device structure, comprising: a molding compound die frame laterally surrounding the first semiconductor die and the second semiconductor die; a first passivation level metal structure overlying the first semiconductor die; a second passivation level metal structure overlying the second semiconductor die; an electrostatic discharge path metal structure overlying the first semiconductor die, the molded material die frame, and the second semiconductor die, wherein the electrostatic discharge path metal structure includes a first top surface segment located within a first horizontal plane, the first horizontal plane including a top surface of one of the first passivation level metal structures and a top surface of one of the second passivation level metal structures, and the electrostatic discharge path metal structure also includes an upper protrusion protruding above the first horizontal plane; a first metal bonding pad having a planar bottom surface in contact with the first top surface segment; and A second metal bonding pad contacts the top surface of the upper protruding portion.

8. The semiconductor device structure according to claim 7, wherein: In plan view, the first metal bond pad has an area overlap with the molded compound die frame; as well as In plan view, the second metal bond pad is located entirely within the area of ​​the first semiconductor die.

9. The semiconductor device structure according to claim 7, wherein: In a plan view, the upper projection has an area overlap with the molding compound die frame.

10. A semiconductor device structure, comprising: A first semiconductor die, comprising a first semiconductor substrate, a first semiconductor device located on the first semiconductor substrate, a first dielectric material layer in which a first metal interconnect structure is buried, and a first metal bonding pad, wherein the first metal bonding pad comprises a first type first metal bonding pad and a second type first metal bonding pad; a second semiconductor die, comprising a second semiconductor substrate, a second semiconductor device located on the second semiconductor substrate, a second dielectric material layer in which a second metal interconnect structure is buried, and a second metal bonding pad, wherein the second metal bonding pad comprises a first type second metal bonding pad directly bonded to the first type first metal bonding pad and a second type second metal bonding pad not contacting any of the first metal bonding pads; and Intermediate metallic material portions, wherein each of the intermediate metallic material portions is in contact with a respective one of the second type first metallic bonding pads and a respective one of the second type second metallic bonding pads.

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