Semiconductor module device

Abstract

A semiconductor module apparatus is disclosed that includes a first substrate having a first plurality of semiconductor bodies disposed thereon, a second substrate having a second plurality of semiconductor bodies disposed thereon, and a third substrate having a third plurality of semiconductor bodies disposed thereon. The first, second, and third plurality of semiconductor bodies together form a semiconductor device including a first node configured to be operably coupled to a first potential and a second node configured to be operably coupled to a second potential different from the first potential. The layout of the third substrate is equal to that of the second substrate. The first substrate is configured to be connected to the first and second nodes, and each of the second and third substrates is configured to be connected to the third node.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor module arrangement, and more particularly to a semiconductor module arrangement including a plurality of separate substrates. Background Art

[0002] The power semiconductor module device generally includes at least one semiconductor substrate arranged in a housing. A semiconductor device including a plurality of controllable semiconductor elements (e.g., IGBT, MOSFET, HEMT, etc.) is arranged on each substrate in at least one substrate. Each substrate generally includes a substrate layer (e.g., a ceramic layer), a first metallization layer deposited on a first side of the substrate layer, and optionally, each substrate further includes a second metallization layer deposited on a second side of the substrate layer. The controllable semiconductor elements are mounted on, for example, the first metallization layer. The second metallization layer can be optionally attached to a substrate or a heat sink. The layout of the semiconductor device should be selected to minimize the size of at least one substrate required, while preventing uneven distribution of current density, electrical loss, and thermal stress.

[0003] Therefore, power semiconductor modules are generally required to prevent uneven distribution of current density, electrical losses and thermal stress. Summary of the invention

[0004] The semiconductor module device includes a first substrate on which a first plurality of semiconductor bodies are arranged, a second substrate on which a second plurality of semiconductor bodies are arranged, and a third substrate on which a third plurality of semiconductor bodies are arranged. The first plurality of semiconductor bodies, the second plurality of semiconductor bodies, and the third plurality of semiconductor bodies together form a semiconductor device, which includes a first node configured to be operably coupled to a first potential and a second node configured to be operably coupled to a second potential different from the first potential. The layout of the third substrate on which the third plurality of semiconductor bodies are arranged is equal to the layout of the second substrate on which the second plurality of semiconductor bodies are arranged. The first substrate is configured to be connected to a first node and a second node, and each of the second substrate and the third substrate is configured to be connected to a third node. A first current path extending between the first node and the third node via the first substrate and the second substrate provides a voltage and current transfer characteristic equivalent to a second current path extending between the first node and the third node via the first substrate and the third substrate, and a third current path extending between the second node and the third node via the first substrate and the second substrate provides a voltage and current transfer characteristic equivalent to a fourth current path extending between the second node and the third node via the first substrate and the third substrate.

[0005] A semiconductor module arrangement comprises a first semiconductor module arrangement and an identical second semiconductor module arrangement, wherein the first semiconductor module arrangement and the second semiconductor module arrangement are arranged adjacent to one another in a plane and symmetrically with respect to an axis of symmetry.

[0006] The present invention can be better understood with reference to the following drawings and descriptions. The components in the drawings are not necessarily drawn to scale, but emphasis is placed on illustrating the principles of the present invention. In the drawings, similar reference numerals represent corresponding parts throughout the different views. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a cross-sectional view of a semiconductor module device.

[0008] Figure 2 is a schematic top view of a semiconductor module arrangement according to an embodiment of the present disclosure.

[0009] Figure 3 is a schematic top view of a semiconductor module arrangement according to another embodiment of the present disclosure.

[0010] Figure 4 is a top view of a semiconductor module device according to another embodiment of the present disclosure.

[0011] Figure 5 is a circuit diagram of a semiconductor device according to one example.

[0012] Figure 6 is a top view of a symmetrical arrangement of a semiconductor module arrangement according to yet another embodiment of the present disclosure.

[0013] Figure 7 is a top view of a second substrate of a semiconductor module arrangement according to an embodiment of the present disclosure.

[0014] Figure 8 is a top view of a heat sink having a plurality of semiconductor module devices arranged thereon according to an embodiment of the present disclosure.

[0015] Fig. 9 is a top view of a heat sink having a plurality of semiconductor module devices arranged thereon according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] In the following detailed description, reference is made to the accompanying drawings. The accompanying drawings show specific examples in which the present invention can be practiced. It should be understood that the features and principles described with respect to the various examples can be combined with each other unless otherwise specifically noted. And in the claims, the names of certain elements as "first element", "second element", "third element", etc. should not be understood as enumeration. On the contrary, such names are only used to address different "elements". That is, for example, the presence of a "third element" does not require the presence of a "first element" and a "second element". The wire as described herein can be a single conductive element, or include at least two separate conductive elements connected in series and / or in parallel. The wire can include metal and / or semiconductor material and can be permanently conductive (i.e., non-switchable). The wire can have a resistivity that is independent of the direction of the current flowing through the wire. The semiconductor body as described herein can be made of (doped) semiconductor material and can be a semiconductor chip or included in a semiconductor chip. The semiconductor body has an electrically connected disk and includes at least one semiconductor element having an electrode. The disk is electrically connected to the electrode including the disk as an electrode, and vice versa.

[0017] Reference Figure 1 , schematically shows a cross-sectional view of a power semiconductor module device 100. The power semiconductor module device 100 includes a housing 7 and a substrate 10. The substrate 10 includes a dielectric insulation layer 11, a structured first metallization layer 111 attached to the dielectric insulation layer 11, and a (structured) second metallization layer 112 attached to the dielectric insulation layer 11. The dielectric insulation layer 11 is arranged between the first metallization layer 111 and the second metallization layer 112.

[0018] Each of the first metallization layer 111 and the second metallization layer 112 may be composed of or include one of the following materials: copper; copper alloy; aluminum; aluminum alloy; any other metal or alloy that remains solid during operation of the power semiconductor module device. The substrate 10 may be a ceramic substrate, i.e., a substrate in which the dielectric insulating layer 11 is a ceramic, such as a thin ceramic layer. The ceramic may be composed of or include one of the following materials: aluminum oxide; aluminum nitride; zirconium oxide; silicon nitride; boron nitride; or any other dielectric ceramic. For example, the dielectric insulating layer 11 may be composed of or include one of the following materials: Al2O3, AlN, SiC, BeO, or Si3N4. For example, the substrate 10 may be, for example, a direct copper bonding (DCB) substrate, a direct aluminum bonding (DAB) substrate, or an active metal brazing (AMB) substrate. In addition, the substrate 10 may be an insulated metal substrate (IMS). For example, an insulated metal substrate typically includes a dielectric insulating layer 11 containing a (filled) material such as an epoxy resin or a polyimide. For example, the material of the dielectric insulating layer 11 may be filled with ceramic particles. Such particles may include, for example, SiO2, Al2O3, AlN or BN, and may have a diameter between about 1 μm and about 50 μm. The substrate 10 may also be a conventional printed circuit board (PCB) having a non-ceramic dielectric insulating layer 11. For example, the non-ceramic dielectric insulating layer 11 may be composed of or include a cured resin.

[0019] The substrate 10 is arranged in the housing 7. Figure 1 In the example shown, the substrate 10 is arranged on a base plate 12 forming a ground surface of the housing 7, while the housing 7 itself only includes side walls and a cover. However, this is only an example. The housing 7 may also further include a ground surface, and the substrate 10 and the base plate 12 are arranged inside the housing 7. In some power semiconductor module devices 100, more than one substrate 10 is arranged on a single base plate 12 or on a ground surface of the housing 7. The substrate 10 itself may also form a ground surface of the housing 7.

[0020] One or more semiconductor bodies 20 may be arranged on at least one substrate 10. Each of the semiconductor bodies 20 arranged on the at least one substrate 10 may include a diode, an IGBT (insulated gate bipolar transistor), a MOSFET (metal oxide semiconductor field effect transistor), a JFET (junction field effect transistor), a HEMT (high electron mobility transistor) and / or any other suitable semiconductor element.

[0021] One or more semiconductor bodies 20 may form a semiconductor device on the substrate 10. Figure 1 In FIG. 2 , only two semiconductor bodies 20 are shown by way of example. Figure 1The second metallization layer 112 of the substrate 10 is a continuous layer. Figure 1 In the example shown, the first metallization layer 111 is a structured layer. "Structured layer" means that the first metallization layer 111 is not a continuous layer, but includes recesses between different parts of the layer. Figure 1 Schematically showing such a recess. In this example, the first metallization layer 111 includes three different parts. However, this is only an example. Any other number of parts is possible. Different semiconductor bodies 20 can be mounted to the same part or different parts of the first metallization layer 111. Different parts of the first metallization layer 111 may not have an electrical connection, or may be electrically connected to one or more other parts using an electrical connection element 3 such as a bonding wire or a bonding tape. For example, to name just a few examples, the electrical connection element 3 may also include a connecting plate, a conductive track or a connecting clip. One or more semiconductor bodies 20 may be electrically connected and mechanically connected to the substrate 10 via a conductive connection layer 30. For example, such a conductive connection layer 30 may be a solder layer, a conductive adhesive layer or a sintered metal powder layer, such as a sintered silver powder layer. According to other examples, the second metallization layer 112 may also be a structured layer. The second metallization layer 112 may also be completely omitted.

[0022] The substrate 10 may also be implemented as a multilayer substrate (not specifically described) having more than one dielectric insulating layer 11 and at least one metallization layer (which may be referred to as a "buried metallization layer") arranged between two corresponding dielectric insulating layers. For example, by providing an additional dielectric insulating layer between the second metallization layer 112 and the substrate 12, in this sense, the second metallization layer 112 will become a buried metallization layer. As described with respect to the first metallization layer 111, at least one buried metallization layer may also be structured. Electrical contact with the corresponding buried metallization layer (between different metallization layers of the multilayer substrate) may be established by one or more so-called "through holes", which are conductive connections extending through the dielectric insulating layer arranged adjacent to the corresponding buried metallization layer and reaching another metallization layer, which may be the first buried metallization layer, the second buried metallization layer or another buried metallization layer. The corresponding buried metallization layer or at least a portion of the buried metallization layer may be used to transmit current or signals. For example, the corresponding buried metallization layer can be used to connect different nodes and / or circuit elements arranged on the substrate in a manner similar to a bonding wire. In other words, the connecting element 3 can also be formed by a portion of the buried metallization layer (a portion of the additional metallization layer) of the multilayer substrate contacted by the corresponding through hole or can include a portion of the buried metallization layer (a portion of the additional metallization layer) of the multilayer substrate contacted by the corresponding through hole. Therefore, the multilayer substrate can be used to replace some or all surface connection elements and / or can be used to achieve a higher interconnection complexity between circuit nodes.

[0023] Figure 1 The power semiconductor module device 100 shown also includes a terminal element 40. The terminal element 40 is electrically connected to the first metallization layer 111 and provides an electrical connection between the interior and the exterior of the housing 7. The terminal element 40 can be electrically connected to the first metallization layer 111 using the first end 41, while the second end 42 of each of the terminal elements 40 protrudes from the housing 7. The terminal element 40 can be electrically contacted from the outside at its corresponding second end 42. A first portion of the terminal element 40 can extend through the interior of the housing 7 in a vertical direction y. The vertical direction y is a direction perpendicular to the top surface of the substrate 10, wherein the top surface of the substrate 10 is a surface on which at least one semiconductor body 20 is mounted. However, Figure 1 The terminal elements 40 shown are only examples. The terminal elements 40 can be implemented in any other way and can be arranged at any position within the housing 7. For example, one or more terminal elements 40 can be arranged close to or adjacent to the side wall of the housing 7. The terminal elements 40 can also protrude through the side wall of the housing 7 instead of through the cover. The first end 41 of the terminal element 40 can be connected in any suitable way (for example, by means of a welded joint or by means of a conductive connecting layer ( Figure 1 The first end 41 of the terminal element 40 may also be electrically coupled to the substrate 10 via one or more electrical connections 3.

[0024] The power semiconductor module device 100 may further include a sealant 5. For example, the sealant 5 may be composed of or include silicone gel, or may be a rigid molding compound. The sealant 5 may at least partially fill the interior of the housing 7, thereby covering the components and electrical connections arranged on the substrate 10. The terminal element 40 may be partially embedded in the sealant 5. However, at least the second end 42 of the terminal element 40 is not covered by the sealant 5, and protrudes from the sealant 5 through the housing 7 to the outside of the housing 7. The sealant 5 is configured to protect the components and electrical connections of the power semiconductor module device 100, in particular the components on the substrate 10 arranged inside the housing 7 from certain environmental conditions and mechanical damage.

[0025] The layout of the semiconductor device (e.g., different parts of the first metallization layer 111, the semiconductor body 20, the electrical connections 3, the terminal elements 40, etc.) can generally be selected to minimize the required size of each of the at least one substrate, while also minimizing the uneven distribution of current density, electrical losses and thermal stresses. Symmetry with respect to gate drive and parasitic inductances can be very important for achieving excellent performance of the semiconductor module device. In semiconductor module devices including more than one substrate 10, considerations regarding symmetry and thermal distribution are generally crucial.

[0026] The semiconductor module arrangement according to the embodiments of the present disclosure provides highly symmetrical current flow, low parasitic inductance, while providing satisfactory thermal performance (heat distribution). Figure 2 The semiconductor module device according to the embodiment of the present disclosure includes a first substrate 101 on which a first plurality of semiconductor bodies 20 are arranged, a second substrate 101 on which a second plurality of semiconductor bodies 20 are arranged, 21 , and a third substrate 10 on which a third plurality of semiconductor bodies 20 are arranged 22 The first plurality of semiconductor bodies, the second plurality of semiconductor bodies and the third plurality of semiconductor bodies 20 together form a semiconductor device including a first node ND1 configured to be operably coupled to a first potential and a second node ND2 configured to be operably coupled to a second potential different from the first potential. A third substrate 10 having the third plurality of semiconductor bodies 20 arranged thereon 22 The layout is equal to the second substrate 10 on which the second plurality of semiconductor bodies 20 are arranged. 21 The third substrate 10 22 The layout is equal to the second substrate 10 21 The layout of the second substrate 10 generally means that, for example, the arrangement, size, shape, material, etc. of different parts of the first metallization layer 111, the semiconductor body 20, the electrical connection 3, the terminal element 40 and any other elements arranged on the respective substrate are substantially the same (substantially identical). 21 can be easily formed by the third substrate 10 22 The replacement and vice versa do not affect the electrical characteristics and functions of the semiconductor module arrangement.

[0027] According to some embodiments of the present disclosure, the first substrate 101 and the second substrate 10 21 and the third substrate 10 22 The first substrate 101 is arranged adjacent to each other in a plane, wherein the first substrate 101 is arranged on the second substrate 10 21 The third substrate 10 22This means, for example, that the three substrates are arranged at substantially the same level or height in a vertical direction perpendicular to the plane in which the three substrates are arranged. Therefore, it may be convenient to use a heat sink with a flat contact surface to cool the substrates. The substrates may also be arranged on a back plate 12, which may have a flat surface.

[0028] The terms "equal", "same" or "equivalent" as used herein should be understood such that the relevant properties of the different entities are very similar. It can also be said that the different entities can be designed such that the relevant properties are exactly the same, but slight deviations may occur based on manufacturing tolerances. Manufacturing tolerances may vary between different applications and between different manufacturing processes used to produce the different entities.

[0029] The first substrate 101 is configured to be connected to the first node ND1 and the second node ND2, and the second substrate 10 21 and the third substrate 10 22 Each of the first and second substrates 101 and 102 is configured to be connected to the third node ND3. 21 The first current path 80 extending between the first node ND1 and the third node ND3 11 Provided via the first substrate 101 and the third substrate 10 22 The second current path 80 extending between the first node ND1 and the third node ND3 12 Equivalent voltage and current transmission characteristics, and via the first substrate 101 and the second substrate 10 21 The third current path 80 extending between the second node ND2 and the third node ND3 13 Provided via the first substrate 101 and the third substrate 10 22 The fourth current path 80 extending between the second node ND2 and the third node ND3 14 Equivalent voltage and current transfer characteristics.

[0030] That is, for example, the first current path 80 11 and the second current path 80 12 The first current path 80 may exhibit at least one of substantially equal or equal ohmic behavior, substantially equal or equal inductive behavior, and substantially equal or equal capacitive behavior. 11 The sum of the impedances of the different components (the first current path 80 11 The total impedance of the second current path 80 12 The sum of the impedances of the different components (second current path 80 12 The same applies to the third current path 80. 13 and the fourth current path 8014 The elements of the current path are, for example, the semiconductor body 20 , corresponding parts of the first metallization layer 111 , and connecting elements that together form the corresponding current path.

[0031] According to one embodiment of the present disclosure, the semiconductor bodies 20 of the first plurality of semiconductor bodies 20 may be slow switching semiconductor bodies, and the semiconductor bodies 20 of the second plurality of semiconductor bodies 20 and the semiconductor bodies 20 of the third plurality of semiconductor bodies 20 may be fast switching semiconductor bodies. A fast switching semiconductor body is generally a semiconductor body that can perform a switching operation (e.g., from a conducting state / on state to a non-conducting state / off state, and vice versa) at a certain speed (e.g., faster than a defined threshold speed). A slow switching semiconductor body is generally a semiconductor body that can perform a switching operation (e.g., from a conducting state / on state to a non-conducting state / off state, and vice versa) at a speed slower than a defined threshold speed. According to an example, a semiconductor body 20 that switches at a high switching frequency (higher than a defined threshold frequency) during operation may be implemented as a fast switching device. For example, any other semiconductor body 20 that switches at a low switching frequency (lower than a defined threshold frequency), such as a grid frequency, during operation may be implemented as a slow switching device. Typically, during operation, each semiconductor body 20 generates switching losses as well as conduction losses. According to an example, a semiconductor body generating more switching losses than conduction losses during operation may be implemented as a fast switching device.For example, any other semiconductor body 20 generating more conduction losses than switching losses during operation may be implemented as a slow switching device.

[0032] By using the second substrate 10 21 and the third substrate 10 22 The fast switching semiconductor body 20 is arranged on the first substrate 101, and the slow switching semiconductor body 20 is arranged on the second substrate 10 21 and the third substrate 10 22 Therefore, during operation of the semiconductor module device, the second substrate 10 21 and the third substrate 10 22 The second substrate 101 is heated more than the first substrate 101 and thus forms the hottest part of the semiconductor module arrangement. 21 The third substrate 10 22 The first substrate 101 on which the slow switching semiconductor body 20 is arranged is arranged between the substrates 101 and the substrates 102, 103 and 104, 105, 106 and 107, 108, 109 and 110, 111 and 112, 113 and 114, 115 and 116, 117 and 118, 119 and 120 Figure 8 and Fig. 9 A further detailed description is given.

[0033] According to an embodiment of the present disclosure, the substrate material and / or substrate thickness for the first substrate, the second substrate, and the third substrate may be equal or different. For example, the substrate material for the first substrate that can carry the slow switching semiconductor body 20 may have a lower thermal conductivity than the substrate material for the second substrate and the third substrate that can carry the fast switching semiconductor body. Similarly, the substrate thickness between the first substrate and the second substrate and the third substrate may be different. Thinner substrates and materials with lower thermal conductivity may be cheaper and / or easier to handle, and therefore the overall cost of the semiconductor module device may be reduced in this case.

[0034] According to another embodiment of the present disclosure, the first substrate, the second substrate and the third substrate may be integrated in a structured multilayer substrate, such as an insulated metal substrate, wherein each of the first substrate, the second substrate and the third substrate is provided as a region of the structured multilayer substrate.

[0035] The semiconductor device formed by the first plurality of semiconductor bodies, the second plurality of semiconductor bodies and the third plurality of semiconductor bodies 20 may include an input stage IPS and an output stage OPS. The input stage IPS may be formed by the first plurality of semiconductor bodies 20. The output stage OPS includes a first output sub-stage OPS1 and a second output sub-stage OPS2. The second plurality of semiconductor bodies 20 may form a first output sub-stage OPS1, and the third plurality of semiconductor bodies 20 may form an equivalent second output sub-stage OPS2. The first output sub-stage OPS1 and the second output sub-stage OPS2 may operate in parallel or individually. This will be described below with the aid of Figure 5 Further detailed explanation is given.

[0036] Figure 5 is a circuit diagram of a semiconductor device according to one example. Figure 5 The semiconductor device may include an ANPC (Active Neutral Point Clamped) topology and may be operated in the ANPC topology. Figure 5 The semiconductor device in the embodiment includes a first node ND1 (e.g., a first supply node DC+) configured to be operably connected to a first potential. The semiconductor device also includes a second node ND2 (e.g., a second supply node DC-) configured to be operably connected to a second potential. The fourth node NP is configured to be operably connected to a third potential. When the semiconductor device is used as intended, the first potential is positive relative to the third potential, and the second potential is negative relative to the third potential.

[0037] The device also includes a first controllable semiconductor element T1 and a second controllable semiconductor element T2. Each of the first controllable semiconductor element T1 and the second controllable semiconductor element T2 includes a control electrode G1, G2 and a controllable load path between a first load electrode and a second load electrode. The first controllable semiconductor element T1 and the second controllable semiconductor element T2 are connected to each other so that their respective load paths form a series connection between a first node ND1 and a fourth node NP. The device also includes a third controllable semiconductor element T3 and a fourth controllable semiconductor element T4. Each of the third controllable semiconductor element T3 and the fourth controllable semiconductor element T4 includes a control electrode G3, G4 and a controllable load path between a first load electrode and a second load electrode. The third controllable semiconductor element T3 and the fourth controllable semiconductor element T4 are connected to each other so that their respective load paths form a series connection between a fourth node NP and a second node ND2. The first controllable semiconductor element T1 and the second controllable semiconductor element T2 are connected to each other via a first common node P, and the third controllable semiconductor element T3 and the fourth controllable semiconductor element T4 are connected to each other via a second common node N.

[0038] The device further includes: a fifth controllable semiconductor element T51 having a controllable load path between a control electrode G51 and two load electrodes, the load path being operatively connected between the first common node P and a third node ND3 (e.g., an output node OUT); and a sixth controllable semiconductor element T61 having a controllable load path between a control electrode G61 and two load electrodes, the load path being operatively connected between the third node ND3 and a second common node N. The fifth controllable semiconductor element T51 and the sixth controllable semiconductor element T61 are connected to each other so that their respective load paths form a series connection between the first common node P and the second common node N.

[0039] The device also includes a seventh controllable semiconductor element T52 and an eighth controllable semiconductor element T62, the seventh controllable semiconductor element T52 having a controllable load path between the control electrode G52 and the two load electrodes, and the eighth controllable semiconductor element T62 having a controllable load path between the control electrode G62 and the two load electrodes. The seventh controllable semiconductor element T52 and the eighth controllable semiconductor element T62 are connected to each other so that their respective load paths form a series connection between the first common node P and the second common node N. The seventh controllable semiconductor element T52 and the eighth controllable semiconductor element T62 are connected to each other via a third node ND3.

[0040] Each of the controllable semiconductor elements T1, T2, T3, T4, T51, T61, T52, T62 may include an intrinsic freewheeling element, such as a body diode, which is electrically connected between the first load electrode and the second load electrode of the corresponding controllable semiconductor element T1, T2, T3, T4, T51, T61, T52, T62 ( Figure 5 The semiconductor device further includes a first freewheeling element F1, a second freewheeling element F2, a third freewheeling element F3, a fourth freewheeling element F4, a fifth freewheeling element F51, a sixth freewheeling element F61, a seventh freewheeling element F52, and an eighth freewheeling element F62. Each of the first freewheeling element F1, the second freewheeling element F2, the third freewheeling element F3, the fourth freewheeling element F4, the fifth freewheeling element F51, the sixth freewheeling element F61, the seventh freewheeling element F52, and the eighth freewheeling element F62 includes a first electrode (e.g., an anode) and a second electrode (e.g., a cathode). Each of the first freewheeling element F1, the second freewheeling element F2, the third freewheeling element F3, the fourth freewheeling element F4, the fifth freewheeling element F51, the sixth freewheeling element F61, the seventh freewheeling element F52 and the eighth freewheeling element F62 can be connected in parallel to one of the controllable semiconductor elements T1, T2, T3, T4, T51, T61, T52, T62.

[0041] For example, the first freewheeling element F1 can be connected to the first node ND1 through its second electrode and to the first common node P through its first electrode, so that it is connected between the first node ND1 and the first common node P, and is connected in parallel with the load path of the first controllable semiconductor element T1. The second freewheeling element F2 can be connected to the first common node P through its second electrode and to the fourth node NP through its first electrode, so that it is connected between the first common node P and the fourth node NP, and is connected in parallel with the load path of the second controllable semiconductor element T2. The third freewheeling element F3 can be connected to the fourth node NP through its second electrode and to the second common node N through its first electrode, so that it is connected between the fourth node NP and the second common node N, and is connected in parallel with the load path of the third controllable semiconductor element T3. The fourth freewheeling element F4 can be connected to the second common node N through its second electrode and to the second node ND2 through its first electrode, so that it is connected between the second common node N and the second node ND2, and is connected in parallel with the load path of the fourth controllable semiconductor element T4. The fifth freewheeling element F51 can be connected to the first common node P through its second electrode and to the third node ND3 through its first electrode, so that it is connected between the first common node P and the third node ND3 and in parallel with the fifth controllable semiconductor element T51. The sixth freewheeling element F61 can be connected to the third node ND3 through its second electrode and to the second common node N through its first electrode, so that it is connected between the third node ND3 and the second common node N and in parallel with the sixth controllable semiconductor element T61. The seventh freewheeling element F52 can be connected to the first common node P through its second electrode and to the third node ND3 through its first electrode, so that it is connected between the first common node P and the third node ND3 and in parallel with the seventh controllable semiconductor element T52. The eighth freewheeling element F62 can be connected to the third node ND3 through its second electrode and to the second common node N through its first electrode, so that it is connected between the third node ND3 and the second common node N and in parallel with the eighth controllable semiconductor element T62.

[0042] Figure 5Each of the first controllable semiconductor element T1, the second controllable semiconductor element T2, the third controllable semiconductor element T3, the fourth controllable semiconductor element T4, the fifth controllable semiconductor element T51, the sixth controllable semiconductor element T61, the seventh controllable semiconductor element T52 and the eighth controllable semiconductor element T62 of the semiconductor device of the present invention can be implemented by means of one or more semiconductor bodies 20 of the semiconductor module device. In particular, the first plurality of semiconductor bodies 20 may include at least one semiconductor body 20 forming the first controllable semiconductor element T1, at least one semiconductor body 20 forming the second controllable semiconductor element T2, at least one semiconductor body 20 forming the third controllable semiconductor element T3 and at least one semiconductor body 20 forming the fourth controllable semiconductor element T4. For example, the first controllable semiconductor element T1, the second controllable semiconductor element T2, the third controllable semiconductor element T3 and the fourth controllable semiconductor element T4 may form an input stage IPS of the semiconductor device arranged on the first substrate 101.

[0043] The second plurality of semiconductor bodies 20 may include at least one semiconductor body 20 forming a fifth controllable semiconductor element T51 and at least one semiconductor body 20 forming a sixth controllable semiconductor element T61, and the third plurality of semiconductor bodies 20 may include at least one semiconductor body 20 forming a seventh controllable semiconductor element T52 and at least one semiconductor body 20 forming an eighth controllable semiconductor element T62. That is, the second plurality of semiconductor bodies 20 and the third plurality of semiconductor bodies 20 may each form a half-bridge device. The fifth controllable semiconductor element T51, the sixth controllable semiconductor element T61, the seventh controllable semiconductor element T52, and the eighth controllable semiconductor element T62 may form an output stage OPS of the semiconductor device, wherein the fifth controllable semiconductor element T51 and the sixth controllable semiconductor element T61 form a first output sub-stage OPS1, and the seventh controllable semiconductor element T52 and the eighth controllable semiconductor element T62 form a second output sub-stage OPS2. The first output sub-stage OPS1 and the second output sub-stage OPS2 may operate in parallel or individually. This is because the semiconductor bodies 20 forming the controllable semiconductor elements T51 , T61 of the first output sub-stage OPS1 are arranged on the second substrate 10 21 The semiconductor elements 20 forming the controllable semiconductor elements T52 and T62 of the second output sub-stage OPS2 are arranged on the third substrate 10. 22 By placing the second substrate 10 21 and the third substrate 10 22 Both are connected to the third node ND3, and the first output sub-stage OPS1 and the second output sub-stage OPS2 can operate in parallel. 21 and the third substrate 10 22If only one of the first and second output sub-stages OPS1 and OPS2 is connected to the third node ND3, the first and second output sub-stages OPS1 and OPS2 may be independently operated.

[0044] When the second substrate 10 21 and the third substrate 10 22 When both are coupled to the third node ND3, the current will flow through the first substrate 101 and the second substrate 10 21 The first current path 80 flows equally between the first node ND1 and the third node ND3. 11 ), and through the first substrate 101 and the third substrate 10 22 The second current path 80 flows equally between the first node ND1 and the third node ND3. 12 ). Similarly, the current will flow through the first substrate 101 and the second substrate 10 21 The current flows equally between the second node ND2 and the third node ND3 (third current path 80 13 ), and through the first substrate 101 and the third substrate 10 22 The fourth current path 80 flows equally between the second node ND2 and the third node ND3. 14 ). For example, if the third substrate 10 22 is not coupled to the third node ND3, the second current path 80 12 and the fourth current path 80 14 is invalid (no current will flow through the corresponding current path). 21 is not connected to the third node ND3, the same applies to the first current path 80 11 and the third current path 80 13 .

[0045] As described above, the third substrate 10 on which the third plurality of semiconductor bodies 20 are arranged 22 The layout is equal to the second substrate 10 on which the second plurality of semiconductor bodies 20 are arranged. 21 Now refer to Figure 3 According to one embodiment of the present disclosure, at least a second plurality of semiconductor bodies 20 may be symmetrically arranged on the second substrate 10 about a second symmetry axis S2. 21 The third plurality of semiconductor bodies 20 may be symmetrically arranged on the third substrate 10 about the third symmetry axis S3. 22 However, it is also possible that the second substrate 10 21 and the third substrate 10 22 The entire layout of the substrate 10 is symmetrical about the second symmetry axis S2 and the third symmetry axis S3. 21 , 10 22Any other elements of the first metallization layer 111 (for example, different parts of the first metallization layer 111, the electrical connection 3, the terminal element 40, etc.) may also be arranged symmetrically about the second symmetry axis S2 and the third symmetry axis S3, respectively. Additionally or alternatively, at least the first plurality of semiconductor bodies 20 may be arranged symmetrically about the first symmetry axis S1 on the first substrate 101. However, it is also possible that the entire layout of the first substrate 101 is symmetrical about the first symmetry axis S1. That is, any other elements of the first substrate 101 (for example, different parts of the first metallization layer 111, the electrical connection 3, the terminal element 40, etc.) may also be arranged symmetrically about the first symmetry axis S1. For example, when the layout of the first substrate 101 is implemented accordingly, the relevant stray inductances in the semiconductor device (for example, the stray inductances between the first node ND1 and the fourth node NP and between the second node ND2 and the fourth node NP) may be very low.

[0046] Now refer to Figure 4 , schematically shows a top view of a semiconductor module device 100 according to an embodiment of the present disclosure. For example, the first metallization layer 111 of the first substrate 101 may include at least five different parts. One or more semiconductor bodies forming the first controllable semiconductor element T1 may be arranged on a first part of the first metallization layer 111 of the first substrate 101 and electrically coupled to the first part. Similarly, one or more semiconductor elements forming the first freewheeling element F1 may be arranged on the first part and electrically coupled to the first part. The first part may form a first node ND1 or may be connected to the first node ND1. The one or more semiconductor bodies forming the first controllable semiconductor element T1 and the one or more semiconductor elements forming the first freewheeling element F1 may also be electrically coupled to the second part of the first metallization layer 111 of the first substrate 101 by means of one or more conductive connecting elements (e.g., bonding wires).

[0047] One or more semiconductor bodies 20 forming the second controllable semiconductor element T2 and one or more semiconductor elements forming the second freewheeling element F2 are arranged on the second portion and electrically coupled to the second portion. The second portion may form a first common node P or may be connected to the first common node P. One or more semiconductor bodies 20 forming the second controllable semiconductor element T2 and one or more semiconductor elements forming the second freewheeling element F2 may also be electrically coupled to a third portion of the first metallization layer 111 of the first substrate 101 by means of one or more conductive connection elements (e.g., bonding wires).

[0048] One or more semiconductor bodies 20 forming the third controllable semiconductor element T3 and one or more semiconductor elements forming the third freewheeling element F3 are arranged on the third portion and electrically coupled to the third portion. The third portion may form a fourth node NP or may be connected to a fourth node NP. One or more semiconductor bodies 20 forming the third controllable semiconductor element T3 and one or more semiconductor elements forming the third freewheeling element F3 may also be electrically coupled to a fourth portion of the first metallization layer 111 of the first substrate 101 by means of one or more conductive connection elements (e.g., bonding wires).

[0049] One or more semiconductor bodies 20 forming the fourth controllable semiconductor element T4 and one or more semiconductor elements forming the fourth freewheeling element F4 are arranged on the fourth part and electrically coupled to the fourth part. The fourth part can form a second common node N or can be connected to the second common node N. One or more semiconductor bodies 20 forming the fourth controllable semiconductor element T4 and one or more semiconductor elements forming the fourth freewheeling element F4 can also be electrically coupled to the fifth part of the first metallization layer 111 of the first substrate 101 by means of one or more conductive connecting elements (e.g., bonding wires). The fifth part can form a second node ND2 or can be connected to the second node ND2. The first metallization layer 111 of the first substrate 101 may include additional parts, for example, for providing a control signal to the control electrode of the controllable semiconductor element. However, such additional parts are not relevant to the general concept and understanding of the basic principle, so these additional parts are omitted for the sake of improved clarity.

[0050] The second portion of the first metallization layer 111 of the first substrate 101 may be electrically coupled to the second substrate 101 by means of one or more electrical connection elements (eg, bonding wires, bonding ribbons, or connection rails). 21 , and is electrically coupled to the third substrate 10 by means of one or more electrical connection elements (eg, bonding wires, bonding ribbons, or connection rails) 22 For example, a second portion of the first metallization layer 111 of the first substrate 101 that may form the first common node P or may be connected to the first common node P may be electrically coupled to the second substrate 10 21 and the third substrate 10 22 The corresponding portion of the first metallization layer 111 (as described below with respect to Figure 7 The fourth portion of the first metallization layer 111 of the first substrate 101 may be electrically coupled to the second substrate 101 by means of one or more electrical connection elements (eg, bonding wires, bonding ribbons, or connection rails). 21 , and is electrically coupled to the third substrate 10 by means of one or more electrical connection elements (eg, bonding wires, bonding ribbons, or connection rails) 22For example, a fourth portion of the first metallization layer 111 of the first substrate 101 that may form the second common node N or may be connected to the second common node N may be electrically coupled to the second substrate 10 21 and the third substrate 10 22 The corresponding portion of the first metallization layer 111 (as described below with respect to Figure 7 will be described).

[0051] As mentioned above and as Figure 4 , Figure 5 and Figure 6 Schematically shown, the first node ND1 may be a first supply node DC+, the second node ND2 may be a second supply node DC-, and the third node ND3 may be an output node OUT. However, this is only an example. In general, the ANPC topology as described above is only an example. The general principle is similarly applicable to different (three-level converter) topologies, such as a neutral point clamped NPC (e.g., NPC1 or NPC2) topology. Figure 2 and Figure 3 The depicted first node ND1 , second node ND2 , and third node ND3 may be any nodes of a topology implemented according to the principles described herein.

[0052] Now refer to Figure 7 , schematically showing a second substrate 10 of a semiconductor module device 100 according to an embodiment of the present disclosure. 21 .like Figure 7 The second substrate 10 shown 21 Usually corresponds to Figure 4 The second substrate 10 shown 21 (and the third substrate 10 22 ), but in Figure 7 In this example, the second substrate 10 21 The present invention comprises a dielectric insulating layer 11 and a first metallization layer 111 arranged on the surface of the dielectric insulating layer 11. The first metallization layer 111 comprises a first portion 1111, a second portion 1112, a third portion 111 31 and Part IV 111 32 , wherein the second portion 1112 horizontally surrounds the third portion 111 31 and Part IV 111 32 Each of the second substrate 10 21The present invention also includes a first semiconductor body 201, a second semiconductor body 202, a third semiconductor body 203 and a fourth semiconductor body 204 arranged on the first metallization layer 111, wherein each of the first semiconductor body 201, the second semiconductor body 202, the third semiconductor body 203 and the fourth semiconductor body 204 has a first contact pad, a second contact pad and a third contact pad. The third contact pad may form a control electrode (e.g., a gate electrode) of the corresponding semiconductor body 201, 202, 203, 204 or may be coupled to a control electrode (e.g., a gate electrode) of the corresponding semiconductor body 201, 202, 203, 204. In particular, each of the first semiconductor body 201, the second semiconductor body 202, the third semiconductor body 203 and the fourth semiconductor body 204 may include a control electrode and a controllable load path between the first load electrode and the second load electrode. For example, the first contact pad may form a corresponding first load electrode (e.g., a drain electrode) or may be coupled to a corresponding first load electrode (e.g., a drain electrode), and the second contact pad may form a corresponding second load electrode (e.g., a source electrode) of a corresponding semiconductor body 201, 202, 203, 204 or may be coupled to a corresponding second load electrode (e.g., a source electrode) of a corresponding semiconductor body 201, 202, 203, 204.

[0053] The third contact pad of the first semiconductor body 201 is connected by means of the first electrical connection element 3 21 The third portion 111 electrically coupled to the first metallization layer 111 31 The third contact pad of the second semiconductor body 202 is connected to the second electrical connection element 3 22 The third portion 111 electrically coupled to the first metallization layer 111 31 The third contact pad of the third semiconductor body 203 is connected to the third electrical connection element 3 23 The fourth portion 111 electrically coupled to the first metallization layer 111 32 , and the third contact pad of the fourth semiconductor body 204 is connected by means of the fourth electrical connection element 3 24 The fourth portion 111 electrically coupled to the first metallization layer 111 32 . First electrical connection element 3 21 , second electrical connection element 3 22 , the third electrical connection element 3 23 and the fourth electrical connection element 3 24 Each of the includes one or more joining wires, one or more joining strips or connecting rails.

[0054] According to one example, the first semiconductor body 201, the second semiconductor body 202, the third semiconductor body 203, and the fourth semiconductor body 204 are identical to each other. That is, for example, the semiconductor bodies may all be implemented as GaN (gallium nitride) semiconductor devices, or may all be implemented as Si (silicon) semiconductor devices, wherein each semiconductor body may be easily replaced by any other semiconductor body without affecting the electrical characteristics and functions of the semiconductor module device. Alternatively, any other kind of semiconductor device may be used. According to another example, the first semiconductor body 201 and the second semiconductor body 202 are identical to each other, the third semiconductor body 203 and the fourth semiconductor body 204 are identical to each other, and the first semiconductor body 201 and the second semiconductor body 202 are different from the third semiconductor body 203 and the fourth semiconductor body 204. For example, the first semiconductor body 201 and the second semiconductor body 202 may be implemented as a first semiconductor device (e.g., a GaN semiconductor device), while the third semiconductor body 203 and the fourth semiconductor body 204 are implemented as a second semiconductor device (e.g., a Si semiconductor device) different from the first semiconductor device, and vice versa. In the latter case, the first semiconductor body 201 can be easily replaced by the second semiconductor body 202, and vice versa, without affecting the electrical characteristics and functions of the semiconductor module arrangement. Similarly, the third semiconductor body 203 can be easily replaced by the fourth semiconductor body 204, and vice versa, without affecting the electrical characteristics and functions of the semiconductor module arrangement.

[0055] Still refer to Figure 7 , the second substrate 10 21 Also includes a third portion 111 disposed 31 At least one third terminal element 40 on 31 and arranged in the fourth section 111 32 At least one fourth terminal element 40 on 32 The third contact pad of the first semiconductor body 201 and the at least one third terminal element 40 31 A fifth current path is provided between the third contact pad of the second semiconductor body 202 and the at least one third terminal element 40 31 The sixth current path between the third semiconductor body 203 and the at least one fourth terminal element 40 has the same voltage and current transfer characteristics, and the third contact pad of the third semiconductor body 203 is connected to the at least one fourth terminal element 40 32 A seventh current path is provided between the third contact pad of the fourth semiconductor body 204 and the at least one fourth terminal element 40 32 The eighth current path has equivalent voltage and current transfer characteristics between them.

[0056] Second substrate 10 21 The fifth portion 111 of the first metallization layer 11 may also include33 , wherein the second portion 1112 horizontally surrounds the fifth portion 111 33 . Part 5 111 33 can be electrically coupled to the third part 111 by means of the electrical connection element 3 31 and can be electrically coupled to the fourth portion 111 by means of the electrical connection element 3 32 Usually, the fifth part 111 can also be omitted 33 According to other embodiments, the components respectively arranged in the third part 111 may be omitted. 31 and Part IV 111 32 At least one third terminal element 40 on 31 and at least one fourth terminal element 40 32 In the latter case, at least one fifth terminal element may be arranged in the fifth portion 111 33 That is, the fifth part 111 can be arranged 33 One or more terminal elements on the fifth portion 111 electrically coupled 33 and Part III 111 31 Electrical connection element 3, third part 111 31 and a first electrical connection element 3 21 The control signal is supplied to the first semiconductor body 201 . This applies analogously to the second semiconductor body 202 , the third semiconductor body 203 and the fourth semiconductor body 204 .

[0057] If the second substrate 10 21 The fifth portion 111 is arranged on the first metallization layer 111 33 If there is at least one fifth terminal element on the semiconductor body 201, the current path between the at least one fifth terminal element and the third contact plate of the first semiconductor body 201 can provide voltage and current transfer characteristics equivalent to each of the current path between the at least one fifth terminal element and the third contact plate of the second semiconductor body 202, the current path between the at least one fifth terminal element and the third contact plate of the third semiconductor body 203, and the current path between the at least one fifth terminal element and the third contact plate of the fourth semiconductor body 204.

[0058] The first contact pads of the first semiconductor body 201, the second semiconductor body 202, the third semiconductor body 203 and the fourth semiconductor body 204 may be electrically coupled to the first portion 1111 of the first metallization layer 111, and the second contact pads of the first semiconductor body 201, the second semiconductor body 202, the third semiconductor body 203 and the fourth semiconductor body 204 may be electrically coupled to the second portion 1112 of the first metallization layer 111. According to an example, the second contact pads of the semiconductor bodies 201, 202, 203, 204 may be source pads, and the first contact pads of the semiconductor bodies 201, 202, 203, 204 may be drain pads. Each of the first contact pads of the first semiconductor body 201, the second semiconductor body 202, the third semiconductor body 203 and the fourth semiconductor body 204 may be electrically coupled to the first portion 1111 of the first metallization layer 111 by means of an electrical connection element 3, and each of the second contact pads of the first semiconductor body 201, the second semiconductor body 202, the third semiconductor body 203 and the fourth semiconductor body 204 may be electrically coupled to the second portion 1112 of the first metallization layer 111 by means of an electrical connection element 3. For example, each of the electrical connection elements 3 may include one or more bonding wires, one or more bonding ribbons, connecting rails or a portion of an additional metallization layer of the substrate 10 contacted by corresponding through-holes. The first semiconductor body 201, the second semiconductor body 202, the third semiconductor body 203 and the fourth semiconductor body 204 may be arranged on the second portion 1112 of the first metallization layer 111. That is, the semiconductor bodies 201 , 202 , 203 , 204 may be arranged on a portion of the first metallization layer to which their respective second contact pads are electrically coupled (eg a semiconductor body arranged at source potential).

[0059] Figure 7 An exemplary second substrate 10 is schematically shown. 21 As mentioned above, this may also apply to an equivalent third substrate 10 22 Arranged on the second substrate 10 21 The first semiconductor body 201, the second semiconductor body 202, the third semiconductor body 203 and the fourth semiconductor body 204 on the first metallization layer 111 may form a fifth controllable semiconductor element T51 and be arranged on the third substrate 10. 22 The first semiconductor body 201 , the second semiconductor body 202 , the third semiconductor body 203 and the fourth semiconductor body 204 on the first metallization layer 111 may form a seventh controllable semiconductor element T52 .

[0060] Still refer to Figure 7 , the second substrate 10 21 And similarly the third substrate 10 22The first metallization layer 111 may further include a sixth portion 1114 and a seventh portion 111 34 and Part VIII 111 35 , wherein the first portion 1111 horizontally surrounds the seventh portion 111 34 and Part VIII 111 35 Each of the second substrate 10 21 The present invention may further include a fifth semiconductor body 205, a sixth semiconductor body 206, a seventh semiconductor body 207 and an eighth semiconductor body 208 arranged on the first metallization layer 111, wherein each of the fifth semiconductor body 205, the sixth semiconductor body 206, the seventh semiconductor body 207 and the eighth semiconductor body 208 has a first contact pad, a second contact pad and a third contact pad. The third contact pad of the fifth semiconductor body 205 may be connected to the fifth electrical connection element 33 by means of the fifth electrical connection element 33. 25 The seventh portion 111 electrically coupled to the first metallization layer 111 34 The third contact pad of the sixth semiconductor body 206 can be connected to the sixth electrical connection element 3 26 The seventh portion 111 electrically coupled to the first metallization layer 111 34 The third contact pad of the seventh semiconductor body 207 can be connected to the seventh electrical connection element 3 27 The eighth portion 111 electrically coupled to the first metallization layer 111 35 , and the third contact pad of the eighth semiconductor body 208 can be connected to the eighth electrical connection element 3 28 The eighth portion 111 electrically coupled to the first metallization layer 111 35 For example, the fifth electrical connection element 3 25 , sixth electrical connection element 3 26 , seventh electrical connection element 3 27 and the eighth electrical connection element 3 28 Each of these may include a

[0061] According to one example, the fifth semiconductor body 205, the sixth semiconductor body 206, the seventh semiconductor body 207 and the eighth semiconductor body 208 are identical to each other, similar to what is described above with respect to the first semiconductor body 201, the second semiconductor body 202, the third semiconductor body 203 and the fourth semiconductor body 204. According to another example, the fifth semiconductor body 205 and the sixth semiconductor body 206 are identical to each other, the seventh semiconductor body 207 and the eighth semiconductor body 208 are identical to each other, and the fifth semiconductor body 205 and the sixth semiconductor body 206 are different from the seventh semiconductor body 207 and the eighth semiconductor body 208.

[0062] Second substrate 10 21 It may also include a seventh portion 11134 At least one sixth terminal element 40 on 34 and arranged in Section 8 111 35 At least one seventh terminal element 40 on 35 The third contact pad of the fifth semiconductor body 205 and the at least one sixth terminal element 40 34 A ninth current path may be provided between the third contact pad of the sixth semiconductor body 206 and the at least one sixth terminal element 40 34 Similarly, the third contact pad of the seventh semiconductor body 207 is connected to the at least one seventh terminal element 40. 35 The eleventh current path may provide a connection between the third contact pad of the eighth semiconductor body 208 and the at least one seventh terminal element 40. 35 The twelfth current path has equivalent voltage and current transfer characteristics.

[0063] The first contact pads of the fifth semiconductor body 205, the sixth semiconductor body 206, the seventh semiconductor body 207 and the eighth semiconductor body 208 may be electrically coupled to the sixth portion 1114 of the first metallization layer 111, and the second contact pads of the fifth semiconductor body 205, the sixth semiconductor body 206, the seventh semiconductor body 207 and the eighth semiconductor body 208 may be electrically coupled to the first portion 1111 of the first metallization layer 111. According to an example, the second contact pads of the semiconductor bodies 205, 206, 207, 208 may be source pads, and the first contact pads of the semiconductor bodies 205, 206, 207, 208 may be drain pads. Each of the first contact pads of the fifth semiconductor body 205, the sixth semiconductor body 206, the seventh semiconductor body 207 and the eighth semiconductor body 208 may be electrically coupled to the sixth portion 1114 of the first metallization layer 111 by means of the electrical connection element 3, and each of the second contact pads of the fifth semiconductor body 205, the sixth semiconductor body 206, the seventh semiconductor body 207 and the eighth semiconductor body 208 may be electrically coupled to the first portion 1111 of the first metallization layer 111 by means of the electrical connection element 3. For example, each of the electrical connection elements 3 may include one or more bonding wires, one or more bonding ribbons, connecting rails or a portion of an additional metallization layer of the substrate 10 contacted by corresponding through-holes. The fifth semiconductor body 205, the sixth semiconductor body 206, the seventh semiconductor body 207 and the eighth semiconductor body 208 may be arranged on the first portion 1111 of the first metallization layer 111. That is, the semiconductor bodies 205 , 206 , 207 , 208 may be arranged on the portion of the first metallization layer 111 to which their respective second contact pads are electrically coupled (eg semiconductor bodies arranged at source potential).

[0064] The first portion 1111 of the first metallization layer 111 may form a third node ND3 or may be connected to the third node ND3, the second portion 1112 of the first metallization layer 111 may form a first common node P or may be connected to the first common node P, and the sixth portion 1114 of the first metallization layer 111 may form a second common node N or may be connected to the second common node N. That is, the second substrate 10 21 and the third substrate 10 22 The second portion 1112 of the first metallization layer 111 may be electrically coupled to the second portion of the first metallization layer 111 of the first substrate 101. 21 and the third substrate 10 22 The sixth portion 1114 of the first metallization layer 111 may be electrically coupled to the fourth portion of the first metallization layer 111 of the first substrate 101 .

[0065] In the embodiments exemplarily shown in the drawings, the semiconductor bodies 201, 202, ... 208 are shown as lateral semiconductor devices, such as, for example, GaN HEMTs, which have all contact pads (e.g., gate contact pads, source contact pads, and drain contact pads) arranged on their top sides, and no contact pads on their bottom sides. However, this is only an example. Alternatively, the semiconductor bodies 201, 202, ... 208 can also be implemented as vertical semiconductor devices. In addition, in the above examples, Figure 5 The controllable semiconductor devices T1, T2, T3, T4, T51, T61, T52, T62 of the device are each realized by means of two semiconductor bodies electrically coupled in parallel. It is also generally possible that the controllable semiconductor devices T1, T2, T3, T4, T51, T61, T52, T62 are realized by only one or even more than two semiconductor bodies. Furthermore, the ANPC topology described above is only an example. The general principle applies similarly to different (three-level converter) topologies, such as neutral point clamped NPC (e.g., NPC1 or NPC2) topologies.

[0066] By equally realizing the second substrate 10 21 and the third substrate 10 22 (Second substrate 10 21 The layout is equal to the third substrate 10 22 The second substrate 10 can be operated in parallel (parallel operation) and independently of each other (interleaved operation). 21 and the third substrate 10 22The switching performance and power dissipation of the semiconductor modules are equivalent. Therefore, for parallel operation, it is not necessary to consider the derating caused by the asymmetrically distributed parasitic effects. For example, by using different materials for different substrates, the cooling efficiency of the semiconductor module device can be improved. For example, the first substrate 101 (for example, the dielectric insulation layer 11 of the first substrate 101) can be made of the same material as the second substrate 101. 21 and the third substrate 10 22 (For example, the second substrate 10 21 and the third substrate 10 22 The dielectric insulating layer 11) is composed of different (ceramic) materials. For example, the second substrate 10 21 and the third substrate 10 22 The second substrate 101 may each include a dielectric insulating layer 11 having better thermal properties (eg, higher thermal conductivity) than the dielectric insulating layer 11 of the first substrate 101. 21 and the third substrate 10 22 The cooling efficiency can be maximized while using a cheaper first substrate 101 which does not necessarily require a very high cooling efficiency. 21 and the third substrate 10 22 The cooling efficiency can be the same so as to achieve a higher symmetry of the arrangement.

[0067] Now refer to Figure 6 , two (or more) semiconductor module devices 100 as described above can also be operated in parallel. That is, a semiconductor module device according to a further embodiment of the present disclosure may include a first semiconductor module device (for example, as described above with respect to Figure 2 , Figure 3 and Figure 4 ) and an equivalent second semiconductor module arrangement (e.g., as described above with respect to Figure 2 , Figure 3 and Figure 4 The first semiconductor module arrangement and the second semiconductor module arrangement can be arranged adjacent to each other in a plane and symmetrically about the fourth symmetry axis S4. In this way, the electrical contacts of the first semiconductor module arrangement connected to a certain potential face the electrical contacts of the second semiconductor module arrangement connected to the same potential. In this way, a maximum power density and a high symmetry can be achieved, in particular when the semiconductor module arrangements are electrically coupled to each other in parallel. For example, bus bars or connecting rails ( Figure 6 A bus bar or connecting rail (not specifically shown in the figure) can be arranged between the first semiconductor module arrangement and the second semiconductor module arrangement, the bus bar or connecting rail making equal electrical contact to both semiconductor module arrangements.

[0068] Now, refer to Figure 8, schematically shows a heat sink 12 on which a plurality of semiconductor module devices 100 are arranged. For example, each of the plurality of semiconductor module devices 100 can act as an independent output stage or branch of an inverter topology. Similar to what is described above, the plurality of semiconductor module devices 100 can be operated in parallel. In this case, the contacts of different semiconductor module devices in the plurality of semiconductor module devices can be substantially equal / identical (e.g., equivalent stray inductance).

[0069] When a plurality of semiconductor module devices are arranged on the same heat sink, the semiconductor module devices are usually arranged in a single row on the heat sink to reduce the overall size of the heat sink (minimum heat sink area). However, in such a device, the substrate having the largest dissipated power (e.g., the second substrate 10 as described above) is preferably arranged in a single row. 21 and the third substrate 10 22 ) are all located in a row and therefore in the same airflow path. That is, the airflow reaching the first semiconductor module arrangement will be heated, and the heated airflow will then reach the second semiconductor module arrangement, be heated even further, and so on. This can be done with the aid of Figure 8 This is avoided by the device shown. In this example, the semiconductor module devices 100 are all arranged offset relative to each other. In this example, two directly consecutive semiconductor module devices overlap by two-thirds of their respective sizes. The first substrate, the second substrate and the third substrate of the semiconductor module device 100 are only schematically indicated by means of dotted lines. It can be seen that in this example, the airflow first reaches the second substrate (left substrate) of the first one of the semiconductor module devices, and will then pass through the first substrate (middle substrate) of the subsequent semiconductor module device, which is generally not as hot as the second substrate (the main heat will be generated on the second substrate and the third substrate). The airflow then passes only through the third substrate (right substrate) of another semiconductor module device. This applies similarly to each of the semiconductor module devices 100. That is, the airflow will never pass through more than two second substrates / third substrates and will not be heated as in conventional devices. However, compared to conventional devices, Figure 8 The offset arrangement requires that the size of the heat sink 12 be at least doubled.

[0070] like Fig. 9 The device shown is Figure 8A compromise between the device and the conventional device as described above. In this example, different semiconductor module devices are arranged in an alternating shifted manner. That is, one semiconductor module device 100 and each directly preceding or consecutive semiconductor module device 100 are shifted relative to each other (for example, two-thirds overlap). However, each semiconductor module device 100 completely overlaps with every second preceding or consecutive semiconductor module device 100. That is, two (if four semiconductor module devices 100 are arranged on the same heat sink 12) or more (if more than two semiconductor module devices are arranged on the same heat sink 12) semiconductor module devices are arranged in the same row.

[0071] Fig. 9 The airflow in the example shown reaches, for example, the second substrate (left substrate) of the first semiconductor module device 100, the first substrate (middle substrate) of the second semiconductor module device, the second substrate (left substrate) of the third semiconductor module device, and the first substrate (middle substrate) of the fourth semiconductor module device. That is, the airflow reaches the hot part of the semiconductor module device 100 and the cooler part of the semiconductor module device in sequence. In this way, Figure 8 Compared with the device of FIG. 1 , the size of the heat sink 12 can be reduced. Fig. 9 The thicker arrows in the figure schematically show Figure 8 The required airflow is increased compared to the device with the invention, but the required airflow is still reduced compared to the conventional device.

Claims

1. A semiconductor module device (100), comprising: A first substrate (101) on which a first plurality of semiconductor bodies (20) are arranged; The second substrate (10 21 ), on which a second plurality of semiconductor bodies (20) are arranged; as well as The third substrate (10 22 ), on which a third plurality of semiconductor bodies (20) are arranged, wherein: The first plurality of semiconductor bodies (20), the second plurality of semiconductor bodies (20) and the third plurality of semiconductor bodies (20) together form a semiconductor device, the semiconductor device comprising a first node (ND1) configured to be operatively coupled to a first potential and a second node (ND2) configured to be operatively coupled to a second potential different from the first potential, The third substrate (10) on which the third plurality of semiconductor bodies (20) are arranged 22 ) is equal to the second substrate (10) on which the second plurality of semiconductor bodies (20) are arranged 21 ) layout, The first substrate (101) is configured to be connected to the first node (ND1) and the second node (ND2), The second substrate (10 21 ) and the third substrate (10 22 ) are each configured to be connected to a third node (ND3), Through the first substrate (101) and the second substrate (10 21 ) a first current path (80) extending between the first node (ND1) and the third node (ND3) 11 ) is provided via the first substrate (101) and the third substrate (10 22 ) a second current path (80) extending between the first node (ND1) and the third node (ND3) 12 ) have equivalent voltage transfer characteristics and current transfer characteristics, and Through the first substrate (101) and the second substrate (10 21 ) a third current path (80) extending between the second node (ND2) and the third node (ND3) 13 ) is provided via the first substrate (101) and the third substrate (10 22 ) a fourth current path (80) extending between the second node (ND2) and the third node (ND3) 14 ) equivalent voltage transfer characteristics and current transfer characteristics.

2. The semiconductor module arrangement (100) according to claim 1, wherein: The semiconductor bodies (20) of the first plurality of semiconductor bodies (20) are slow switching semiconductor bodies; and The semiconductor bodies (20) of the second plurality of semiconductor bodies (20) and the semiconductor bodies (20) of the third plurality of semiconductor bodies (20) are fast switching semiconductor bodies, The fast switching semiconductor body is a semiconductor body that switches between different switching states at a speed faster than a defined threshold speed, and the slow switching semiconductor body is a semiconductor body that switches between different switching states at a speed slower than the defined threshold speed.

3. The semiconductor module arrangement (100) according to claim 1 or 2, wherein: The semiconductor device formed by the first plurality of semiconductor bodies (20), the second plurality of semiconductor bodies (20) and the third plurality of semiconductor bodies (20) comprises an input stage (IPS) and an output stage (OPS), The input stage (IPS) is formed by the first plurality of semiconductor bodies (20), The output stage (OPS) comprises a first output substage (OPS1) and a second output substage (OPS2), the second plurality of semiconductor bodies (20) forming the first output substage (OPS1) and the third plurality of semiconductor bodies (20) forming an identical second output substage (OPS2), and The first output sub-stage (OPS1) and the second output sub-stage (OPS2) may operate in parallel or individually.

4. The semiconductor module arrangement (100) according to any one of claims 1 to 3, wherein: The second plurality of semiconductor bodies (20) and the third plurality of semiconductor bodies (20) each form a half-bridge arrangement.

5. The semiconductor module arrangement (100) according to any one of claims 1 to 4, wherein: The semiconductor device formed by the first plurality of semiconductor bodies (20), the second plurality of semiconductor bodies (20) and the third plurality of semiconductor bodies (20) further comprises: a fourth node (NP) configured to be operably connected to a third potential different from the first potential and the second potential, a first controllable semiconductor element (T1) and a second controllable semiconductor element (T2), each of the first controllable semiconductor element (T1) and the second controllable semiconductor element (T2) having a controllable load path between a control electrode (G1, G2) and two load electrodes, the first controllable semiconductor element (T1) and the second controllable semiconductor element (T2) being connected to each other so that their respective load paths form a series connection between the first node (ND1) and the fourth node (NP), the first controllable semiconductor element (T1) and the second controllable semiconductor element (T2) being connected to each other via a first common node (P), a third controllable semiconductor element (T3) and a fourth controllable semiconductor element (T4), each of the third controllable semiconductor element (T3) and the fourth controllable semiconductor element (T4) having a controllable load path between a control electrode (G3, G4) and two load electrodes, the third controllable semiconductor element (T3) and the fourth controllable semiconductor element (T4) being connected to each other so that their respective load paths form a series connection between the fourth node (NP) and the second node (ND2), the third controllable semiconductor element (T3) and the fourth controllable semiconductor element (T4) being connected to each other via a second common node (N), a fifth controllable semiconductor element (T51) and a sixth controllable semiconductor element (T61), each of the fifth controllable semiconductor element (T51) and the sixth controllable semiconductor element (T61) having a controllable load path between a control electrode (G51, G61) and two load electrodes, the fifth controllable semiconductor element (T51) and the sixth controllable semiconductor element (T61) being connected to each other so that their respective load paths form a series connection between the first common node (P) and the second common node (N), the fifth controllable semiconductor element (T51) and the sixth controllable semiconductor element (T61) being connected to each other via the third node (ND3), A seventh controllable semiconductor element (T52) and an eighth controllable semiconductor element (T62), each of the seventh controllable semiconductor element (T52) and the eighth controllable semiconductor element (T62) having a controllable load path between a control electrode (G52, G62) and two load electrodes, the seventh controllable semiconductor element (T52) and the eighth controllable semiconductor element (T62) are connected to each other so that their respective load paths form a series connection between the first common node (P) and the second common node (N), and the seventh controllable semiconductor element (T52) and the eighth controllable semiconductor element (T62) are connected to each other via the third node (ND3).

6. The semiconductor module arrangement (100) according to claim 5, wherein: The first plurality of semiconductor bodies (20) include at least one semiconductor body (20) forming the first controllable semiconductor element (T1), at least one semiconductor body (20) forming the second controllable semiconductor element (T2), at least one semiconductor body (20) forming the third controllable semiconductor element (T3), and at least one semiconductor body (20) forming the fourth controllable semiconductor element (T4), The second plurality of semiconductor bodies (20) includes at least one semiconductor body (20) forming the fifth controllable semiconductor element (T51) and at least one semiconductor body (20) forming the sixth controllable semiconductor element (T61), and The third plurality of semiconductor bodies (20) includes at least one semiconductor body (20) forming the seventh controllable semiconductor element (T52) and at least one semiconductor body (20) forming the eighth controllable semiconductor element (T62).

7. The semiconductor module arrangement (100) according to claim 1, wherein: The second substrate (10 21 ) and the third substrate (10 22 ) each of which includes: A dielectric insulating layer (11) and a first metallization layer (111) arranged on a surface of the dielectric insulating layer (11), wherein the first metallization layer (111) comprises a first portion (1111), a second portion (1112), a third portion (111 31 ) and Part IV (111 32 ), wherein the second portion (1112) horizontally surrounds the third portion (111 31 ) and the fourth part (111 32 ) in each; and A first semiconductor body (201), a second semiconductor body (202), a third semiconductor body (203) and a fourth semiconductor body (204) arranged on the first metallization layer (111), wherein each of the first semiconductor body (201), the second semiconductor body (202), the third semiconductor body (203) and the fourth semiconductor body (204) has a first contact pad, a second contact pad and a third contact pad, wherein The third contact pad of the first semiconductor body (201) is connected to the first electrical connection element (3 21 ) is electrically coupled to the third portion (111) of the first metallization layer (111) 31 ), The third contact pad of the second semiconductor body (202) is connected to the second electrical connection element (3 22 ) is electrically coupled to the third portion (111) of the first metallization layer (111) 31 ), The third contact pad of the third semiconductor body (203) is connected by means of a third electrical connection element (3 23 ) is electrically coupled to the fourth portion (111) of the first metallization layer (111) 32 ), The third contact pad of the fourth semiconductor body (204) is connected by means of a fourth electrical connection element (3 24 ) is electrically coupled to the fourth portion (111) of the first metallization layer (111) 32 ),and The first electrical connection element (3 21 )、the second electrical connection element (3 22 )、the third electrical connection element (3 23 ) and the fourth electrical connection element (3 24 ) each includes one or more joining wires, one or more joining strips or connecting rails.

8. The semiconductor module arrangement (100) according to claim 7, wherein: The first semiconductor body (201), the second semiconductor body (202), the third semiconductor body (203) and the fourth semiconductor body (204) are identical to each other; or The first semiconductor body (201) and the second semiconductor body (202) are identical to each other, the third semiconductor body (203) and the fourth semiconductor body (204) are identical to each other, and the first semiconductor body (201) and the second semiconductor body (202) are different from the third semiconductor body (203) and the fourth semiconductor body (204).

9. The semiconductor module arrangement (100) according to claim 7 or 8, wherein: The second substrate (10 21 ) and the third substrate (10 22 ) each of which also includes: Arranged in the third part (111 31 ) on at least one third terminal element (40 31 ),as well as Arranged in the fourth part (111 32 ) on at least one fourth terminal element (40 32 ),in, The third contact pad of the first semiconductor body (201) is connected to the at least one third terminal element (40 31 ) provides a fifth current path between a third contact pad of the second semiconductor body (202) and the at least one third terminal element (40 31 ) between the sixth current path having the same voltage transfer characteristics and current transfer characteristics, and The third contact pad of the third semiconductor body (203) is connected to the at least one fourth terminal element (40 32 ) provides a seventh current path between the third contact pad of the fourth semiconductor body (204) and the at least one fourth terminal element (40 32 ) between which the eighth current path has equivalent voltage transfer characteristics and current transfer characteristics.

10. The semiconductor module arrangement (100) according to claim 7, 8 or 9, wherein: The second substrate (10 21 ) and the third substrate (10 22 ) each further comprises a fifth portion (111) of the first metallization layer (111) 33 ), wherein the second portion (1112) horizontally surrounds the fifth portion (111 33 ),in, The fifth part (111 33 ) is electrically coupled to the third part (111) by means of an electrical connection element (3) 31 ), The fifth part (111 33 ) is electrically coupled to the fourth portion (111) by means of an electrical connection element (3) 32 ).

11. The semiconductor module arrangement (100) according to claim 10, wherein: The second substrate (10 21 ) and the third substrate (10 22 ) each of which also includes: The fifth portion (111) arranged on the first metallization layer (111) 33 ) on at least one fifth terminal element, wherein The current path between the at least one fifth terminal element and the third contact plate of the first semiconductor body (201) provides voltage transfer characteristics and current transfer characteristics equivalent to each of the current paths between the at least one fifth terminal element and the third contact plate of the second semiconductor body (202), the current path between the at least one fifth terminal element and the third contact plate of the third semiconductor body (203), and the current path between the at least one fifth terminal element and the third contact plate of the fourth semiconductor body (204).

12. The semiconductor module arrangement (100) according to any one of claims 7 to 11, wherein: Arranged on the second substrate (10 21 ), the first semiconductor body (201), the second semiconductor body (202), the third semiconductor body (203) and the fourth semiconductor body (204) on the first metallization layer (111) form the fifth controllable semiconductor element (T51), and Arranged on the third substrate (10 22 ) on the first metallization layer (111) of the semiconductor device, the first semiconductor body (201), the second semiconductor body (202), the third semiconductor body (203) and the fourth semiconductor body (204) form the seventh controllable semiconductor element (T52).

13. The semiconductor module arrangement (100) according to any one of claims 7 to 12, wherein: The second substrate (10 21 ) and the third substrate (10 22 ) each of which also includes: The sixth portion (1114) and the seventh portion (1114) of the first metallization layer (111) 34 ) and Part 8 (111 35 ), wherein the first portion (1111) horizontally surrounds the seventh portion (111 34 ) and said eighth section (111 35 ) in each; and A fifth semiconductor body (205), a sixth semiconductor body (206), a seventh semiconductor body (207) and an eighth semiconductor body (208) arranged on the first metallization layer (111), wherein each of the fifth semiconductor body (205), the sixth semiconductor body (206), the seventh semiconductor body (207) and the eighth semiconductor body (208) has a first contact pad, a second contact pad and a third contact pad, wherein The third contact pad of the fifth semiconductor body (205) is connected by means of a fifth electrical connection element (3 25 ) is electrically coupled to the seventh portion (111) of the first metallization layer (111) 34 ), The third contact pad of the sixth semiconductor body (206) is connected by means of a sixth electrical connection element (3 26 ) is electrically coupled to the seventh portion (111) of the first metallization layer (111) 34 ), The third contact pad of the seventh semiconductor body (207) is connected by means of a seventh electrical connection element (3 27 ) is electrically coupled to the eighth portion (111) of the first metallization layer (111) 35 ), The third contact pad of the eighth semiconductor body (208) is connected by means of an eighth electrical connection element (3 28 ) is electrically coupled to the eighth portion (111) of the first metallization layer (111) 35 ), The fifth electrical connection element (3 25 )、the sixth electrical connection element (3 26 )、the seventh electrical connection element (3 27 ) and the eighth electrical connection element (3 28 ) each includes one or more joining wires, one or more joining strips or connecting rails.

14. The semiconductor module arrangement (100) according to claim 13, wherein: The second substrate (10 21 ) and the third substrate (10 22 ) each of which also includes: Arranged in the seventh part (111 34 ) on at least one sixth terminal element (40 34 ),as well as Arranged in the eighth part (111 35 ) on at least one seventh terminal element (40 35 ),in, The third contact pad of the fifth semiconductor body (205) is connected to the at least one sixth terminal element (40 34 ) provides a ninth current path between the third contact pad of the sixth semiconductor body (206) and the at least one sixth terminal element (40 34 ) between the tenth current path having the same voltage transfer characteristics and current transfer characteristics, and The third contact pad of the seventh semiconductor body (207) is connected to the at least one seventh terminal element (40 35 ) provides an eleventh current path between the third contact pad of the eighth semiconductor body (208) and the at least one seventh terminal element (40 35 ) between the twelfth current path having equivalent voltage transfer characteristics and current transfer characteristics.

15. The semiconductor module arrangement (100) according to claim 1, wherein: Satisfy at least one of the following: The first plurality of semiconductor bodies (20) are arranged symmetrically on the first substrate (101) about a first symmetry axis (S1); and The second plurality of semiconductor bodies (20) are symmetrically arranged on the second substrate (10) about a second symmetry axis (S2). 21 ), and the third plurality of semiconductor bodies (20) are symmetrically arranged on the third substrate (10) about a third symmetry axis (S3). 22 )superior.

16. The semiconductor module arrangement (100) according to claim 15, wherein: The first symmetry axis (S1), the second symmetry axis (S2) and the third symmetry axis (S3) are parallel to each other.

17. The semiconductor module arrangement (100) according to claim 1, wherein: The first substrate, the second substrate, and the third substrate are arranged adjacent to each other, wherein the first substrate is arranged between the second substrate and the third substrate.

18. A semiconductor module device, comprising: A first semiconductor module arrangement (100) according to any one of claims 1 to 17; as well as An equivalent second semiconductor module arrangement (100) according to any one of claims 1 to 17, wherein The first semiconductor module arrangement (100) and the second semiconductor module arrangement (100) are arranged adjacent to each other in a plane and are symmetrical about a fourth symmetry axis (S4).

19. The semiconductor module arrangement according to claim 18, wherein: The first semiconductor module arrangement (100) and the second semiconductor module arrangement (100) are electrically coupled to each other in parallel.

Images