Semiconductor devices including diffusion interruption structures and methods of forming semiconductor devices

Abstract

The invention relates to a semiconductor device including a diffusion interruption structure and a method of forming the semiconductor device. A semiconductor device includes an insulating layer, a first semiconductor layer over the insulating layer, a diffusion interruption structure between a first active region and a second active region and including a first insulating pattern over the insulating layer and an opening over the first insulating pattern, and a conductive gate material over the opening.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor devices including diffusion break structures and methods of forming the semiconductor devices. In particular, embodiments of the present disclosure relate to semiconductor devices including single diffusion break structures (SDB) or double diffusion break structures (DDB) or both. Background Art

[0002] A semiconductor device may include various transistor devices. Some of these transistor devices may be electrically isolated from each other to function properly in a circuit region of the semiconductor device. The isolated region of the transistor device may be referred to as a "diffusion interrupt."

[0003] When a diffusion interruption structure is formed in a semiconductor device, the stress distribution in the active region of a transistor device in the semiconductor device may be undesirably changed, thereby degrading the performance of the transistor device. In addition, when a diffusion interruption structure is implemented to provide electrical isolation (which requires wiring to the diffusion interruption structure), the manufacturing process of the semiconductor device may be more complicated. Summary of the invention

[0004] Embodiments of the present disclosure relate to semiconductor devices including diffusion break structures and methods of forming the semiconductor devices. In particular, embodiments of the present disclosure relate to semiconductor devices including single diffusion break structures (SDB) or double diffusion break structures (DDB) or both.

[0005] In one embodiment, a semiconductor device includes an insulating layer, a first semiconductor layer located above the insulating layer, a diffusion interruption structure located between a first active region and a second active region and including a first insulating pattern located above the insulating layer and an opening located above the first insulating pattern, and a conductive gate material located above the opening.

[0006] In one embodiment, a semiconductor device includes an insulating layer, a first gate structure in a first active region, the first active region including a first semiconductor layer above the insulating layer, a second gate structure in a second active region, the second active region including a second semiconductor layer above the insulating layer, and a third gate structure between the first and second gate structures and including a diffusion interruption structure and a conductive gate material above the diffusion interruption structure. The diffusion interruption structure includes a first insulating pattern above the insulating layer and an opening above the first insulating pattern.

[0007] In one embodiment, a method for forming a semiconductor device includes forming an insulating layer, forming a first semiconductor layer above the insulating layer, forming a diffusion interrupt structure between a first active region and a second active region of the semiconductor device, and forming a conductive gate material. Forming the diffusion interrupt structure includes forming an opening and a first insulating pattern below the conductive gate material. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A , 1B , 1C and 1D show various schematic views of a semiconductor device including a single diffusion break (SDB) structure according to an embodiment.

[0009] Figure 2A , 2B , 3A, 3B, 4A and 4B show a method for manufacturing the semiconductor device in FIG. 1 according to one embodiment.

[0010] Figure 5A , 5B 5C show various schematic views of a semiconductor device including an SDB according to one embodiment.

[0011] Fig. 6A , 6B 7A and 7B show a method for manufacturing the semiconductor device in FIG. 5 according to one embodiment.

[0012] Fig. 8A and 8B A schematic diagram of a semiconductor device including a double diffusion break (DDB) structure according to one embodiment is shown.

[0013] Fig.9A and 9B A schematic diagram showing a semiconductor device including a DDB structure according to an embodiment. DETAILED DESCRIPTION

[0014] Embodiments of the present disclosure relate to semiconductor devices including diffusion break structures and methods of forming the semiconductor devices. In particular, embodiments of the present disclosure relate to semiconductor devices including single diffusion break structures (SDBs) or double diffusion break structures (DDBs) or both.

[0015] A detailed description of the embodiments is provided below together with the accompanying drawings. The scope of the present disclosure is limited by the claims and includes various alternatives, modifications and equivalents. Although the steps of various processes are presented in a given order, the embodiments are not necessarily limited to being performed in the listed order. In some embodiments, specific operations may be performed simultaneously, in an order different from the described order, or not performed at all.

[0016] Various specific details are set forth in the following description. These details are provided to facilitate a comprehensive understanding of the scope of the present disclosure through specific examples, and embodiments may be practiced according to the claims without these specific details. Therefore, the specific embodiments of the present disclosure are exemplary and are not intended to be exclusive or limiting. For the sake of clarity, technical materials known in the technical field related to the present disclosure are not described in detail to avoid unnecessarily obscuring the present disclosure.

[0017] Figure 1A , 1B 1C show various schematic views of a semiconductor device 110 including a single diffusion break (SDB) structure 150 according to one embodiment. For example, Figure 1A is a schematic top view of the semiconductor device 110, Figure 1B is along Figure 1A A cross-sectional view of the semiconductor device 110 taken along line AA′ in FIG. Figure 1C is along Figure 1A 1 is a cross-sectional view of the semiconductor device 110 taken along line BB′ in FIG. Figure 1D According to another embodiment, Figure 1A 1 is a cross-sectional view of the semiconductor device 110 taken along line AA′ in FIG.

[0018] In one embodiment, semiconductor device 110 may be an integrated circuit (IC) product (eg, a logic device, a storage device, etc.) and include planar transistors. For example, semiconductor device 110 may include NMOS transistors (NFETs), or PMOS transistors (PFETs), or both.

[0019] Please refer to Figure 1A, the semiconductor device 110 includes a first active region 112A, a second active region 112B, and first, second and third gate structures 120A, 120B and 120C. In one embodiment, the first and third gate structures 120A and 120C act as active gates, respectively, and the second gate structure 120B acts as a non-functional gate. The first active region 112A, the second gate structure 120B, and the second active region 112B may be arranged along a first direction (e.g., relative to Figure 1A The second gate structure 120B may be arranged in a second direction (eg, relative to the first direction) intersecting the first direction. Figure 1A The vertical direction of the orientation of the active region 112A) extends beyond the first and second active regions 112A and 112B. Figure 1A The embodiment shown in includes three gate structures 120A, 120B and 120C, but the embodiments of the present disclosure are not limited thereto. In other embodiments, one or both of the first and second active regions 112A and 112B are further extended along the first direction, and one or more additional gate structures may be disposed above one or both of the extended active regions 112A and 112B. For example, the active region (e.g., the first or second active region 112A or 112B) in the present disclosure may include a semiconductor layer (e.g., the first or second semiconductor layer 118A or 118B), and when one or more active gates (e.g., the first and second gate structures 120A and 120C) disposed above the semiconductor layer operate, one or more channels are formed in the semiconductor layer.

[0020] Please refer to Figure 1B The semiconductor device 110 further includes a semiconductor substrate 114, an insulating layer 116 disposed above the substrate 114, and first and second semiconductor layers (eg, silicon layer, silicon germanium layer) 118A and 118B disposed above the insulating layer 116. Figure 1B The second gate structure 120B in the embodiment includes a gate electrode material (e.g., polysilicon) 132, a conductive gate material (e.g., silicide) 134, and a spacer 124 including first and second portions 124A and 124B. In one embodiment, the gate electrode material 132 and the conductive gate material 134 may be disposed between the first and second portions 124A and 124B of the spacer 124. Figure 1B The semiconductor device 110 in the embodiment includes a single integrated spacer 124 (including the first and second portions 124A and 124B), but the embodiments of the present disclosure are not limited thereto. For example, in other embodiments, the semiconductor device 110 may include two independent spacers 124A and 124B.

[0021] exist Figure 1BThe second gate structure 120B in the embodiment further includes a single diffusion break (SDB) structure 150, which is disposed between the first and second active regions 112A and 112B to provide a desired isolation function. For example, the SDB structure 150 includes a first insulating pattern (e.g., a lower insulating pattern) 126, a second insulating pattern (e.g., an upper insulating pattern) 128, and an opening 130, thereby providing physical isolation between the first active region 112A and the second active region 112B. In one embodiment, the SDB structure 150 is disposed above the insulating layer 116 and between the first and second semiconductor layers 118A and 118B, thereby electrically isolating the first and second semiconductor layers 118A and 118B from each other together with the insulating layer 116.

[0022] To obtain Figure 1B The lower insulating pattern 126 of the SDB structure 150 may be formed by forming an initial semiconductor layer (eg, Figure 2A and 3A The initial semiconductor layer 118' in the first active region 112A and the second active region 112B is partially converted (e.g., oxidized) into an insulating material (e.g., silicon oxide) (which expands during the conversion process), thereby forming a lower insulating pattern 126 adjacent to the first and second semiconductor layers 118A and 118B. Therefore, the first and second active regions 112A and 112B along the first direction (e.g., in Figure 1A and 1B The stress applied by the semiconductor device 110 (in the AA' line direction) is used to keep the lattice spacing in the first and second active regions 112A and 112B narrow along the first direction, thereby improving the PFET mobility compared to conventional semiconductor devices.

[0023] Please refer to Figure 1C , an upper portion (e.g., a top surface) of the insulating layer 116 is exposed through the hole H1 and the opening 130. The hole H1 may be coupled to the opening 130 and disposed above the conductive gate material 134. In the embodiment shown in FIGS. 1 to 1C , the hole H1 is formed in a region where the second gate structure 120B extends beyond the first and second active regions 112A and 112B along the second direction. Figure 1C The gate electrode material 132 is disposed above the second insulating pattern 128 .

[0024] exist Figure 1B and 1CIn the embodiment shown in , the second gate structure 120B includes a gate electrode material 132 disposed above the upper insulating pattern 128. However, the embodiments of the present disclosure are not limited thereto. For example, in some embodiments, the second gate structure 120B may include a substantially fully silicided conductive material 134, and the gate electrode material 132 is omitted. In other embodiments, the gate electrode material 132 and the conductive gate material 134 may be substantially completely removed, thereby retaining the spacer 124 and the single SDB structure 150 including the lower insulating pattern 125, the opening 130, and the upper insulating pattern 128.

[0025] Please refer to Figure 1D The second gate structure 120B' includes an SDB structure 150, which includes an opening 130' and an insulating pattern 128' disposed above the opening 130'. The opening 130' and the insulating pattern 128' are disposed between the first and second portions 124A and 124B of the spacer 124 and are located above the insulating layer 116, thereby electrically isolating the first and second semiconductor layers 118A' and 118B' from each other together with the insulating layer 116.

[0026] Figure 2A , 2B , 3A, 3B, 4A and 4B show a method for manufacturing the semiconductor device 110 in FIG. 1 according to one embodiment. Specifically, Figure 2A , 3A 4A is a simplified cross-sectional view along the line AA' shown in FIG. 1, and Figure 2B , 3B 4B is a simplified cross-sectional view taken along line BB' shown in FIG. 1 .

[0027] Please refer to Figure 2A and 2B The method includes forming an intermediate semiconductor structure. Such an intermediate semiconductor structure includes a semiconductor substrate 114, an insulating layer 116, an initial semiconductor layer 118', and a spacer 124 including first and second portions 124A and 124B. The intermediate structure also includes a gate dielectric material (e.g., a gate oxide material) 140 and an initial gate electrode material 132' disposed between the first and second portions 124A and 124B of the spacer 124.

[0028] In one embodiment, Figure 2A and 2B The gate dielectric material 140 in the embodiment includes a high-k insulating material. For example, the gate dielectric material 140 may be hafnium oxide, and may optionally include one or more of zirconium (Zr), aluminum (Al), and lanthanum (La). In some embodiments, a gate work function material (e.g., titanium nitride) is disposed above the gate dielectric material 140.

[0029] Please refer to Figure 3A and 3B The method includes forming a hole H1 in a specific area of ​​the initial gate electrode material 132' (e.g., Figure 1A and 1C The hole H1 in the gate structure is a gate structure (for example, Figure 1A The second gate structure 120B in the longitudinal direction (eg, Figure 1A The hole H1 is formed outside the first and second active regions 112A and 112B, thereby ensuring a process margin to substantially avoid damaging the active regions 112A and 112B when forming the hole H1.

[0030] In one embodiment, a mask pattern (not shown) is formed to expose the specific region of the initial gate electrode material 132', and an etching process (e.g., a dry etching process) is performed on the initial gate electrode material 132' to form the hole H1 until the gate dielectric material 140 is exposed, thereby forming the intermediate gate electrode material 132". For example, the hole H1 may be formed using reactive ion etching.

[0031] Please refer to Figure 4A and 4B , the method also includes forming a conductive gate material 134 and a gate electrode material 132. In one embodiment, at least a portion of the intermediate gate electrode material 132" may be converted into a conductive gate material (e.g., silicide) 134 and the remainder of the intermediate gate electrode material 132" may become the gate electrode material 132. For example, a metal (e.g., nickel) may be deposited over the intermediate gate electrode material 132", and an annealing process may be performed to react the metal with a portion of the intermediate gate electrode material 132" (e.g., polysilicon) to form a conductive gate material (e.g., nickel silicide) 134.

[0032] The method also includes selectively removing the gate dielectric material 140 using the hole H1 to form the opening 130. In one embodiment, an etching process is performed by applying an etchant through the hole H1 to selectively remove the gate dielectric material 140. For example, such an etchant can have a high selectivity (e.g., equal to or greater than 50) to the gate dielectric material 140 relative to the conductive gate material 134, the gate electrode material 132, the spacer 124, and the initial semiconductor layer 118'. For example, the etchant includes a sulfuric acid and hydrogen peroxide mixture (SPM), which is also used to remove the remaining metal after the formation of the silicide 134 has been completed. In some embodiments, the etching process is performed to selectively remove the gate dielectric material 140 and the gate work function material disposed above the gate dielectric material 140.

[0033] The method further includes converting a portion of the initial semiconductor layer 118' into the first insulating pattern 126, or converting a portion of the gate electrode material 132 into the second insulating pattern 128, or both. In one embodiment, the etchant acts as an oxygen source to oxidize the portion of the initial semiconductor layer 118' and the portion of the gate electrode material 132. For example, the SPM may be used in the etching process performed at a higher temperature (e.g., 50-70° C.) during a given sufficiently long time interval (e.g., 30-300 seconds) to ensure that the SDB structure 150 including the first and second insulating patterns 126 and 128 and the opening 130 is properly formed.

[0034] In a conventional semiconductor device including a PFET, a non-functional gate structure may be coupled to a line to electrically isolate an adjacent active region while avoiding stress release in the active region. In contrast, a semiconductor device including a PFET according to an embodiment of the present disclosure (e.g., Figure 1B The semiconductor device shown in the figure provides an SDB structure, which includes an opening and one or more insulating patterns to physically separate adjacent active regions, thereby eliminating the need for wiring for electrical isolation. In addition, the insulating pattern in the semiconductor device according to an embodiment of the present disclosure can increase the stress applied to the adjacent active region, thereby improving the PFET mobility compared to the conventional semiconductor device.

[0035] In conventional semiconductor devices including NFETs, proper alignment when forming non-functional gate structures to physically separate adjacent active regions can be challenging. In contrast, a semiconductor device including NFETs according to an embodiment of the present disclosure (e.g., Figure 1D The semiconductor device shown in FIG. 1 provides an SDB structure including an opening formed by etching a gate dielectric material (e.g., a high-k insulating material) disposed between spacers, thereby facilitating self-alignment of the SDB structure with the spacers. For example, such a gate dielectric material may be formed directly on an insulating layer (e.g., in FIG. 1 ). Figure 2A Insulating layer 116 in the middle) and on two portions of the spacer (e.g., Figure 1D When the gate dielectric material is etched to form an opening (e.g., between the first and second portions 124A and 124B of the spacer 124). Figure 1D When the opening 130' in the spacer is formed, the opening can be self-aligned with the portions of the spacer to form a gap between adjacent active regions (e.g., Figure 1D Provide physical isolation between the first and second active regions 112A' and 112B').

[0036] Figure 5A , 5B5C show various schematic views of a semiconductor device 510 including a single diffusion break (SDB) 550 according to one embodiment. For example, Figure 5A is a schematic top view of a semiconductor device 510, Figure 5B is along Figure 5A A cross-sectional view of the semiconductor device 510 taken along line CC' in FIG. Figure 5C is along Figure 5A 5 is a cross-sectional view of the semiconductor device 510 taken along line DD′ in FIG.

[0037] exist Figures 5A to 5C The semiconductor device 510 includes Figures 1A to 1C Therefore, for simplicity, detailed descriptions of these similar elements may be omitted in the following disclosure.

[0038] exist Figures 5A to 5C The semiconductor device 510 in Figures 1A to 1C The difference between the semiconductor device 110 in FIG. 1 is that the hole H2 is formed in the region of the second gate structure 520B between the first and second active regions 512A and 512B along the second direction, rather than outside the first and second active regions 512A and 512B along the second direction. Figure 5B As shown in FIG. 1 , the portion of the semiconductor device 510 where the hole H2 is formed includes a first semiconductor layer 518A located in the first active region 512A, a second semiconductor layer 518B located in the second active region 512B, and a first insulating pattern 526 disposed between the first and second semiconductor layers 518A and 518B.

[0039] exist Figure 5B and 5C The SDB structure 550 of the semiconductor device 510 in the embodiment further includes a second insulating pattern (e.g., an upper insulating pattern) 528 and an opening 530, thereby providing physical isolation between the first active region 512A and the second active region 512B. In one embodiment, the SDB structure 550 is disposed above the insulating layer 516 and between the first and second semiconductor layers 518A and 518B, thereby electrically isolating the first and second semiconductor layers 518A and 518B from each other together with the insulating layer 516.

[0040] Fig. 6A , 6B 7A and 7B show a method for manufacturing the semiconductor device 510 in FIG. 5 according to one embodiment. Specifically, Fig. 6A and 7A is along Figure 5A A simplified cross-sectional view of the line CC' shown in FIG. Figure 6B and 7B is along Figure 5ASimplified cross-sectional view of line D-D' shown in FIG. Figures 5A to 5C The method of manufacturing a semiconductor device 510 includes Figures 1A to 1C The method for manufacturing the semiconductor device 110 in the embodiment of the present invention is similar to the processes described above, and therefore, for simplicity, a detailed description of these processes may be omitted in the following disclosure.

[0041] Please refer to Fig. 6A and 6B The method includes forming a hole H2 in a specific area of ​​the initial gate electrode material (not shown) to form an intermediate gate electrode material 532", wherein the specific area is a gate structure (e.g., in Figure 5A The gate structure 520B in the longitudinal direction (eg, Figure 5A The first and second active regions 512A and 512B are extended in a region located inside the initial semiconductor layer 518' in a second direction. In one embodiment, a mask pattern (not shown) is formed to expose the specific region of the initial gate electrode, and an etching process is performed on the initial gate electrode material to form a hole H2 until the gate dielectric material (e.g., gate oxide material) 540 is exposed, thereby forming an intermediate gate electrode material 532".

[0042] Please refer to Fig. 7A and 7B The method further includes forming a conductive gate material (e.g., silicide) 534 and a gate electrode material (e.g., polysilicon) 532, and selectively removing the gate dielectric material 540 to form an opening 530. The method further includes converting a portion of the initial semiconductor layer 518' into a first insulating pattern 526, or converting a portion of the gate electrode material 532 into a second insulating pattern 528, or both.

[0043] Fig. 8A and 8B A schematic diagram of a semiconductor device 810 including a double diffusion break structure (DDB) 860 is shown according to one embodiment. For example, Fig. 8A is a schematic top view of a semiconductor device 810, and Figure 8B is along Fig. 8A 8 is a cross-sectional view of a semiconductor device 810 taken along line EE′ in FIG. The semiconductor device 810 may be an integrated circuit (IC) product (eg, a logic device, a storage device, etc.) and may include an NMOS transistor (NFET).

[0044] Please refer to Fig. 8A, the semiconductor device 810 includes a first active region 812A, a second active region 812B, and first, second, third and fourth gate structures 820A, 820B, 820C and 820D. In one embodiment, the first and fourth gate structures 820A and 820D act as active gates, respectively, while the second and third gate structures 820B and 820C act as non-functional gates, respectively. Although in Fig. 8A The embodiment shown in FIG. 1 includes four gate structures 820A, 820B, 820C, and 820C, but the embodiments of the present disclosure are not limited thereto. In other embodiments, one or both of the first and second active regions 812A and 812B are further extended along the first direction (e.g., relative to Fig. 8A The active regions 812A and 812B may extend in a horizontal direction (in a horizontal direction of the orientation), and one or more additional gate structures may be disposed over one or both of the extended active regions 812A and 812B.

[0045] exist Fig. 8A The DDB structure 850 is disposed between the first and second active regions 812A and 812B to provide the required isolation function. Figure 8B The DDB structure 850 in FIG. 8 includes first and second lower insulating patterns 826A and 826B, first and second upper insulating patterns 828A and 828B, and first and second openings 830A and 830B, thereby providing physical isolation between the first active region 812A and the second active region 812B. For example, the first semiconductor layer 818A is adjacent to the lower insulating pattern 826A, and the second semiconductor layer 818B is adjacent to the second lower insulating pattern 826B, so that the first semiconductor layer 818A is separated from the second semiconductor layer 818B by the first lower insulating pattern 826A, the first opening 830A, the second opening 830B, and the second lower insulating pattern 826B.

[0046] Fig.9A and 9B A schematic diagram of a semiconductor device 910 including a double diffusion break (DDB) structure 960 is shown according to one embodiment. For example, Fig.9A is a schematic top view of a semiconductor device 910, and Fig. 9B is along Fig.9A 1 is a cross-sectional view of a semiconductor device 910 taken along line FF' in FIG. The semiconductor device 910 may be an integrated circuit (IC) product (eg, a logic device, a storage device, etc.), and may include an NMOS transistor (NFET), a PMOS transistor (PFET), or both.

[0047] Please refer to Fig.9A, the semiconductor device 910 includes a first active region 912A, a second active region 912B, and first, second, third and fourth gate structures 920A, 920B, 920C and 920D. In one embodiment, the first and fourth gate structures 920A and 920D act as active gates, respectively, while the second and third gate structures 920B and 920C act as non-functional gates, respectively.

[0048] exist Fig.9A The DDB structure 950 is disposed between the first and second active regions 912A and 912B to provide the required isolation function. Fig. 9B The DDB structure 950 in the embodiment includes first and second lower insulating patterns 926A and 926B, first and second upper insulating patterns 928A and 928B, and openings 930A and 930B, thereby providing physical isolation between the first active region 912A and the second active region 912B. The first lower insulating pattern 926A is disposed between the first semiconductor layer 918A and the second semiconductor layer 918B, and the second lower insulating pattern 926B is disposed between the second semiconductor layer 918B and the third semiconductor layer 918C. Since the first lower insulating pattern 926A is adjacent to the first semiconductor layer 918A and the second semiconductor layer 918B, and the second lower insulating pattern 926B is adjacent to the second semiconductor layer 918B and the third semiconductor layer 918C, the stress applied in the lateral direction (e.g., the first direction) in each of the first and second active regions 912A and 912B can be kept sufficiently high, thereby improving the performance of the transistor (e.g., PFET) compared to conventional semiconductor devices.

[0049] The aspects of the present disclosure have been described in conjunction with the specific embodiments of the present disclosure presented as examples. Various substitutions, modifications, and variations may be made to the embodiments described herein without departing from the scope of the claims set forth below. Therefore, the embodiments described herein are intended to be illustrative rather than limiting.

Claims

1. A semiconductor device, characterized in that: include: Insulation layer; A first semiconductor layer, located above the insulating layer; A diffusion interruption structure, located between the first active region and the second active region, the diffusion interruption structure comprising a first insulating pattern located above the insulating layer and an opening located above the first insulating pattern; as well as A conductive gate material is located above the opening.

2. The semiconductor device according to claim 1, wherein Also includes a second semiconductor layer located above the insulating layer, The first insulating pattern is adjacent to the first semiconductor layer and the second semiconductor layer.

3. The semiconductor device according to claim 2, wherein: The diffusion interruption structure further includes a second insulating pattern between the opening and the conductive gate material.

4. The semiconductor device according to claim 3, wherein: The diffusion interruption structure further includes a gate electrode material located between the second insulating pattern and the conductive gate material, and The conductive gate material includes silicide, and each of the first insulating pattern and the second insulating pattern includes silicon oxide.

5. The semiconductor device according to claim 2, wherein: Also included is a spacer, the spacer including a first portion located above the first semiconductor layer and a second portion located above the second semiconductor layer, The opening and the conductive gate material are located between the first portion and the second portion of the spacer.

6. The semiconductor device according to claim 2, wherein: The first active region, the diffusion interruption structure, and the second active region are arranged along a first direction, and The gate structure includes the diffusion interruption structure, the conductive gate material, and a hole coupled to the opening, and the gate structure extends along a second direction intersecting the first direction.

7. The semiconductor device according to claim 6, wherein: The hole is located in a region of the gate structure where the gate structure extends beyond the first active region and the second active region.

8. The semiconductor device according to claim 6, wherein: The hole is located in a region of the gate structure between the first active region and the second active region.

9. The semiconductor device according to claim 2, wherein: Also includes a third semiconductor layer located above the insulating layer, Wherein, the diffusion interruption structure further includes: A second insulating pattern located above the insulating layer and adjacent to the second semiconductor layer and the third semiconductor layer; and The second opening is located above the second insulating pattern.

10. The semiconductor device according to claim 1, wherein The opening is a first opening, and the first insulating pattern is adjacent to the first semiconductor layer. The semiconductor device further includes a second semiconductor layer located above the insulating layer. Wherein, the diffusion interruption structure further includes: A second insulating pattern located above the insulating layer and adjacent to the second semiconductor layer; and a second opening located above the second insulating pattern, and The first semiconductor layer is separated from the second semiconductor layer by the first insulating pattern, the first opening, the second insulating pattern, and the second opening.

11. A semiconductor device, characterized in that: include: Insulation layer; A first gate structure is located in a first active region, wherein the first active region includes a first semiconductor layer located above the insulating layer; A second gate structure is located in a second active region, wherein the second active region includes a second semiconductor layer located above the insulating layer; as well as The third gate structure is located between the first gate structure and the second gate structure. The third gate structure includes a diffusion interruption structure and a conductive gate material located above the diffusion interruption structure. The diffusion interruption structure includes a first insulating pattern located above the insulating layer and an opening located above the first insulating pattern.

12. The semiconductor device according to claim 11, wherein The first insulating pattern is adjacent to the first semiconductor layer and the second semiconductor layer.

13. The semiconductor device according to claim 12, wherein: The diffusion interruption structure further includes a second insulation pattern disposed between the opening and the conductive gate material.

14. The semiconductor device according to claim 12, wherein: The first active region, the diffusion interruption structure, and the second active region are arranged along a first direction, The third gate structure further includes a hole coupled to the opening, and the third gate structure extends along a second direction intersecting with the first direction.

15. The semiconductor device according to claim 14, wherein: The hole is located in a region of the third gate structure where the third gate structure extends beyond the first active region and the second active region.

16. A method for forming a semiconductor device, characterized in that: The method includes: forming an insulating layer; forming a first semiconductor layer over the insulating layer; forming a diffusion interrupt structure between the first active region and the second active region of the semiconductor device; and forming a conductive gate material, The forming of the diffusion interruption structure includes forming an opening and a first insulating pattern below the conductive gate material.

17. The method according to claim 16, characterized in that Forming the diffusion interrupt further includes forming a second semiconductor layer over the insulating layer, The first insulating pattern is adjacent to the first semiconductor layer and the second semiconductor layer.

18. The method according to claim 17, characterized in that Forming the diffusion interruption also includes forming a second insulating pattern between the opening and the conductive gate material.

19. The method according to claim 16, characterized in that The gate structure includes the diffusion interrupt structure and the conductive gate material, the method further comprising forming a hole in a region of the gate structure where the gate structure extends beyond the first active region and the second active region.

20. The method of claim 19, wherein: An etchant is applied through the hole to selectively remove the gate dielectric material in the gate structure to form the opening.

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