Integrated circuit structure with backside plug last method

Abstract

Integrated circuit structures with backside plug last methods are described. In an example, an integrated circuit structure includes a plurality of horizontally stacked nanowires or fins. A gate stack is over the plurality of horizontally stacked nanowires or fins. A conductive trench contact structure is located at a horizontal plane below the plurality of horizontally stacked nanowires or fins, the conductive trench contact structure having outwardly tapered sidewalls from a top of the conductive trench contact structure to a bottom of the conductive trench contact structure.

Description

Technical Field

[0001] Embodiments of the present disclosure pertain to the field of advanced integrated circuit structure fabrication, and more particularly to integrated circuit structures having a backside plug last approach. Background Art

[0002] Over the past several decades, the scaling of features in integrated circuits has been the driving force behind the continued growth of the semiconductor industry. Scaling to smaller and smaller features enables the density of functional units to be increased within the limited footprint of a semiconductor chip. For example, shrinking transistor size allows a greater number of memory or logic devices to be incorporated on a chip, thereby manufacturing products with increased capacity. However, the quest for greater and greater capacity is not without its problems. The necessity to optimize the performance of each device becomes increasingly important.

[0003] Variability in conventional and currently known manufacturing processes may limit the possibility of further extending them to the range of 10 nm nodes or sub-10 nm nodes. Therefore, manufacturing functional components required for future technology nodes may require the introduction of new methods in current manufacturing processes or the integration of new technologies or replacement of current manufacturing processes.

[0004] In the manufacture of integrated circuit devices, as device dimensions continue to shrink, multi-gate transistors (e.g., tri-gate transistors) have become more popular. Tri-gate transistors are typically fabricated on bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and compatibility with existing high-yield bulk silicon substrate infrastructure.

[0005] However, scaling multi-gate transistors is not without consequences. As the size of these basic building blocks of microelectronic circuits decreases, and as the absolute number of basic building blocks fabricated in a given area increases, the constraints on the semiconductor processes used to fabricate these building blocks have become unbearable. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 Cross-sectional views of an interconnect stack with front-side power delivery and an interconnect stack with back-side power delivery are shown according to embodiments of the present disclosure.

[0007] Figure 2A-2C Cross-sectional views representing various operations in a method of fabricating an integrated circuit structure using a plug-first approach are illustrated.

[0008] Figure 2D-2H Cross-sectional views representing various operations in a method of fabricating an integrated circuit structure using a plug-last approach in accordance with an embodiment of the present disclosure are illustrated.

[0009] Figure 3A cross-sectional view of a non-planar integrated circuit structure taken along a gate line according to an embodiment of the present disclosure is shown.

[0010] Figure 4A-4H A plan view of a substrate processed using a double-sided device processing method is shown in accordance with some embodiments.

[0011] Figure 5A-5H A cross-sectional view of a substrate processed using a double-sided device processing method according to some embodiments is shown.

[0012] Figure 6 A cross-sectional view taken through a nanowire and fin for a non-endcap architecture is shown in accordance with an embodiment of the present disclosure.

[0013] Figure 7 A cross-sectional view taken through a nanowire and a fin for a self-aligned gate end cap (SAGE) architecture is shown in accordance with an embodiment of the present disclosure.

[0014] Fig. 8A A three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure is shown.

[0015] Figure 8B The diagram according to an embodiment of the present disclosure is taken along the a-a' axis. Fig. 8A A cross-sectional source or drain view of a nanowire-based integrated circuit structure.

[0016] Figure 8C FIG. 2 shows a cross-sectional view taken along the bb' axis according to an embodiment of the present disclosure. Fig. 8A Cross-sectional channel view of a nanowire-based integrated circuit structure.

[0017] Fig. 9 A computing device according to one implementation of an embodiment of the present disclosure is shown.

[0018] Fig.10 An interposer including one or more embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0019] An integrated circuit structure with a backside plug last approach is described. In the following description, many specific details are set forth, such as specific integration and material systems, in order to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that the embodiments of the present disclosure can be implemented without these specific details. In other cases, well-known features (e.g., integrated circuit design layouts) are not described in detail to avoid unnecessarily obscuring the embodiments of the present disclosure. In addition, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0020] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and use of such embodiments. As used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any embodiment described herein as exemplary is not necessarily to be construed as being preferred or advantageous over other embodiments. Furthermore, there is no intention to be bound by any express or implied theory presented in the foregoing technical field, background technology, summary of the invention, or the following detailed description.

[0021] This specification includes references to "one embodiment" or "an embodiment." The appearances of the phrases "in one embodiment" or "in an embodiment" are not necessarily referring to the same embodiment. The particular features, structures, or characteristics may be combined in any suitable manner consistent with the present disclosure.

[0022] Terminology. The following paragraphs provide definitions or context for terms found in this disclosure, including the appended claims:

[0023] "Comprising". This term is open ended. As used in the appended claims, this term does not exclude additional structures or operations.

[0024] "Configured to". Various units or components may be described or claimed as being "configured to" perform one or more tasks. In such contexts, "configured to" is used to mean structure by indicating that the unit or component includes structure for performing the one or more tasks during operation. Thus, even when the specified unit or component is not currently operating (e.g., not turned on or activated), the unit or component can be said to be configured to perform a task. Reciting a unit or circuit or component as "configured to" perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112, sixth paragraph, with respect to that unit or component.

[0025] "First," "second," etc. As used herein, these terms serve as labels for the nouns that follow them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.).

[0026] "Coupled"—The following description refers to elements or nodes or features that are "coupled" together. As used herein, unless expressly stated otherwise, "coupled" means that one element or node or feature is directly or indirectly joined to (or directly or indirectly communicates with) another element or node or feature, and not necessarily mechanically.

[0027] In addition, certain terms may also be used in the following description for reference purposes only, and therefore are not intended to be limiting. For example, terms such as "upper," "lower," "above," and "below" refer to directions referenced in the accompanying drawings. Terms such as "front," "back," "rear," "side," "outer," and "inner" describe the orientation or position, or both, of portions of a component within a consistent but arbitrary reference system, which may be made clear by reference to the text and associated drawings describing the component in question. Such terms may include the words specifically mentioned above, their derivatives, and words of similar meaning.

[0028] "Inhibit" - As used herein, "inhibit" is used to describe reducing or minimizing an effect. When a component or feature is described as inhibiting an action, movement, or condition, it may completely prevent a result, consequence, or future state. Additionally, "inhibit" may also refer to reducing or mitigating a result, property, or effect that might otherwise occur. Thus, when a component, element, or feature is said to inhibit a result or state, it need not completely prevent or eliminate that result or state.

[0029] Embodiments described herein may be directed to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) manufacturing, where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL typically encompasses all processes up to (but not including) the deposition of metal interconnect layers. After the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0030] The embodiments described herein may be directed to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC manufacturing where the individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected using wiring (e.g., one or more metallization layers) on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL portion of the manufacturing stage, contacts (pads), interconnect wires, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in the BEOL.

[0031] The embodiments described below may be applied to FEOL processes and structures, BEOL processes and structures, or both FEOL and BEOL processes and structures. In particular, although FEOL process scenarios may be used to illustrate exemplary process schemes, such methods may also be applied to BEOL processes. Likewise, although BEOL process scenarios may be used to illustrate exemplary process schemes, such methods may also be applied to FEOL processes.

[0032] One or more embodiments are directed to a plug-last method for backside trench contact (TCN) etching. One or more embodiments described herein are directed to a gate-all-around integrated circuit structure fabricated using a plug-last method. It should be understood that references to nanowires herein may indicate nanowires or nanoribbons or nanosheets or forksheets, unless otherwise indicated. One or more embodiments described herein are directed to a fin-based integrated circuit structure fabricated using a plug-last method.

[0033] To provide background, backside trench contact processes are needed for size scaling and performance improvements. Existing processes involve transferring the backside trench contact pattern into the substrate while maintaining the minimum ETE feature size. However, at the small dimensions required for backside trench contact formation, the etch loading effect can be severe, resulting in the depth of the backside trench contact etch being difficult to control.

[0034] According to one or more embodiments of the present disclosure, a backside trench contact grid is etched into a substrate using a plug last method. Subsequently, the plug is patterned into a hard mask layer and then filled and recessed to its final height. Finally, a backside trench contact placeholder material is deposited in the trench. Alternatively, the backside trench contact placeholder material can be deposited before the plug is patterned. The plug patterning process can be used to "cut" the backside trench contact. Advantages for implementing the embodiments described herein can include eliminating the etch loading effect of substrate etching by replacing substrate etching with unpatterned etching. The method can also ensure consistency of the polysilicon profile / spacer between the backside trench contact lines and the frontside trench contact lines because all lines are exposed to the same substrate etching.

[0035] Detectability of implementations of the embodiments described herein may include observation of a tapered plug visible in a TEM. The plug may or may not have a liner. The combination of a tapered profile and a liner will indicate that the plug is etched into the trench, rather than the trench being etched around the plug.

[0036] To provide further context, low resistance power delivery solutions are needed as semiconductor scaling continues to squeeze interconnects into smaller and smaller spaces. Backside power delivery (i.e., a scheme where the power delivery interconnect network connects directly to the transistors from the backside of the wafer rather than sharing space with frontside wiring) is a possible solution for future semiconductor technology upgrades.

[0037] Traditionally, power is delivered from the front side interconnect. At the standard cell level, power can be delivered at the top of the transistor or from the top and bottom cell boundaries. The power delivered from the top and bottom cell boundaries can achieve a relatively short standard cell height with a slightly higher power network resistance. However, the front side power network shares the interconnect stack with the signal wiring and reduces the signal wiring trace. In addition, for high-performance designs, the top and bottom cell boundary power metal lines must be wide enough to reduce the power network resistance and improve performance. This usually causes the cell height to increase. According to one or more embodiments of the present disclosure, power can be delivered from the back side of the wafer or substrate to solve area and performance problems. At the cell level, a wider metal 0 power may no longer be needed at the top and bottom cell boundaries, and the cell height can therefore be reduced. In addition, the power network resistance can be significantly reduced, resulting in improved performance. At the block and chip level, the front side signal wiring trace is increased due to the removal of power wiring, and the power network resistance is significantly reduced due to very wide wires, large vias, and reduced interconnect layers.

[0038] In earlier technologies, the power delivery network from bumps to transistors required a large amount of block resources. Such resource usage on the metal stack manifests itself in some process nodes as a standard cell architecture with layout version control or cell placement restrictions in the block level. In an embodiment, eliminating the power delivery network from the front-side metal stack allows free sliding cell placement in the block without power delivery complexity and delay timing variations associated with placement.

[0039] As an illustrative comparison, Figure 1 Cross-sectional views of an interconnect stack with front-side power delivery and an interconnect stack with back-side power delivery are shown according to embodiments of the present disclosure.

[0040] refer to Figure 1 , an interconnect stack 100 with front-side power delivery includes a transistor 102 and a signal and power delivery metallization 104. The transistor 102 includes a bulk substrate 106, a semiconductor fin 108, a terminal 110, and a device contact 112. The signal and power delivery metallization 104 includes a conductive via 114, a conductive line 116, and a metal bump 118.

[0041] Reference again Figure 1, an interconnect stack 150 with backside power delivery includes a transistor 152, a frontside signal metallization 154A, and a power delivery metallization 154B. The transistor 152 includes a semiconductor nanowire or nanoribbon 158, a terminal 160, and a device contact 162, and a boundary deep via 163. The frontside signal metallization 154A includes a conductive via 164A, a conductive line 166A, and a metal bump 168A. The power delivery metallization 154B includes a conductive via 164B, a conductive line 166B, and a metal bump 168B. It should be understood that the backside power approach can also be implemented for structures including semiconductor fins.

[0042] To provide further background, an essential component of a backside power delivery network is an electrically functional feature that interfaces the source or drain contact of a transistor with the backside interconnect network. Therefore, a design and method for fabricating interface features that is compatible with existing library cell design practices and transistor contact process flows is needed.

[0043] There are currently no solutions that have been adopted in high volume manufacturing because backside power delivery has not been introduced in high volume manufacturing. Approaches may eventually include deep trench contacts (TCN), direct source-drain contacts from the backside, or replacing the gate contact rail with backside power contacts. Depending on the proposed scheme, the solution may suffer from high resistance contacts, thus negating the inherent value of backside power delivery co-optimized with front-end transistor processing, resulting in defects and performance risks and compromises.

[0044] According to an embodiment of the present disclosure, a plug last method for backside trench contact (TCN) etching is described.

[0045] As a comparative example, Figure 2A-2C Cross-sectional views representing various operations in a method of fabricating an integrated circuit structure using a plug-first approach are illustrated.

[0046] refer to Figure 2A , a starting structure 200 includes a stack of nanowires 204 above a dielectric layer 202, such as a stack of silicon nanowires above a silicon dioxide or silicon oxide layer. A gate stack including an intermediate portion 206 and an overlying portion 208 is associated with each of the stacks of nanowires 204. The gate stacks 206 / 208 may include a high-k gate dielectric and a metal gate electrode. A hard mask 210 (e.g., a carbon hard mask) is formed over and between selected ones of the stacks of nanowires 204.

[0047] refer to Figure 2B , from an out-of-page perspective relative to the stack of nanowires 204 , backside trench contact locations 212 are etched into dielectric layer 202 .

[0048] refer to Figure 2C , a conductive structure 214 is formed by filling the backside trench contact location 212 with a conductive material. The remaining dielectric layer 202 acts as a dielectric or isolation plug between adjacent conductive structures 214, and this process is referred to as a plug-first process. It should be understood that the backside exposure and contact formation can be used to ultimately contact the conductive structure 214 from the back side of the structure.

[0049] refer to Figure 2A-2C In the plug-first approach, the backside trench is etched only when needed to contact the etch, resulting in a tapered trench profile. In contrast, in the plug-last approach, the trench is generally formed, and then the plug is formed last.

[0050] As an exemplary process flow, Figure 2D-2H A cross-sectional view representing various operations in a method of manufacturing an integrated circuit structure using a plug-last method in accordance with an embodiment of the present disclosure is shown. It should be understood that the described and illustrated embodiments may also be applicable to fin structures that replace stacks of nanowires or nanoribbons or nanosheets or forks.

[0051] refer to Figure 2D , a starting structure 250 includes a stack of nanowires 254 above a dielectric layer 252, such as a stack of silicon nanowires above a silicon dioxide or silicon oxide layer. A gate stack including an intermediate portion 256 and an overlying portion 258 is associated with each of the stacks of nanowires 254. The gate stack 206 / 208 may include a high-k gate dielectric and a metal gate electrode. From an out-of-page perspective relative to the stack of nanowires 254, a single or global backside trench contact location 260 is etched into the dielectric layer 252.

[0052] refer to Figure 2E A hard mask 262 (eg, a carbon hard mask) is formed over selected ones of the stacks of nanowires 254 , with portions extending into the backside trench contact locations 260 .

[0053] refer to Figure 2F ,exist Figure 2E A plug liner 264, such as a silicon nitride liner, is formed on the structure. A plug filler 266, such as a silicon dioxide or silicon oxide filler, is formed on the plug liner 264.

[0054] refer to Figure 2G , plug liner 264 and plug fill 266 are recessed to about the height of backside trench contact location 260 to form plug liner 264A and plug fill 266A, respectively, and hard mask 262 is removed to leave trench 267 in backside trench contact location 260. Plug 268 and plug 270 are representative of the resulting plug structures.

[0055] refer to Figure 2H , a conductive structure 272 is formed by filling trench 267 with a conductive material. Plugs 268 and plugs 270 act as dielectrics or isolation plugs between conductive structures 272, and this process is referred to as a plug last process. It should be understood that backside exposure and contact formation can be used to finally contact conductive structure 272 from the back side of the structure.

[0056] Reference again Figure 2D-2H According to an embodiment of the present disclosure, the integrated circuit structure includes a plurality of horizontally stacked nanowires 254. The gate stack 256 / 258 is located above the plurality of horizontally stacked nanowires 254. The conductive trench contact structure 272 is located at a horizontal plane below the plurality of horizontally stacked nanowires 254. The conductive trench contact structure 272 has a sidewall that tapers outward from the top of the conductive trench contact structure 272 to the bottom of the conductive trench contact structure 272.

[0057] In an embodiment, the integrated circuit structure further includes a dielectric plug 268 or 270, which is laterally adjacent to and in contact with one of the outwardly tapered sidewalls of the conductive trench contact structure 272, as shown. In an embodiment, the dielectric plug 268 or 270 includes a plug liner 264A and a plug filler 266A, as shown.

[0058] In one embodiment, the plug liner 264A is along the bottom surface of the plug filler 266A, as shown. In one embodiment, the uppermost surface of the plug liner 264A is at the same level as the uppermost surface of the plug filler 266A, as shown.

[0059] On the other hand, it should be understood that the backside connection can be implemented using the frontside architecture. In one example, the backside connection can be implemented using an active gate contact (COAG) structure and process. One or more embodiments of the present disclosure are directed to a semiconductor structure or device having one or more gate contact structures (e.g., as gate contact vias) disposed above an active portion of a gate electrode of the semiconductor structure or device. One or more embodiments of the present disclosure are directed to a method for manufacturing a semiconductor structure or device having one or more gate contact structures formed above an active portion of a gate electrode of the semiconductor structure or device. The methods described herein can be used to reduce the standard cell area by forming a gate contact portion above an active gate region. According to one or more embodiments, a tapered gate and a trench contact portion are implemented to achieve COAG manufacturing. Embodiments can be implemented to achieve patterning with tight spacing.

[0060] It should be understood that, as used throughout this disclosure, the sub-fins, nanowires, nanoribbons, or fins described herein may be silicon sub-fins, silicon nanowires, silicon nanoribbons, or silicon fins. As used throughout the text, a silicon layer or structure may be used to describe a silicon material composed of a very large amount (if not all) of silicon. However, it should be understood that, in practice, 100% pure Si may be difficult to form, and may therefore include a small percentage of carbon, germanium, or tin. Such impurities may be included as unavoidable impurities or components during the deposition of Si, or may "contaminate" Si when diffused during post-deposition processing. Therefore, the embodiments described herein for silicon layers or structures may include silicon layers or structures containing relatively small amounts (e.g., "impurity" levels) of non-Si atoms or substances (e.g., Ge, C, or Sn). It should be understood that the silicon layer or structure as described herein may be undoped or may be doped with dopant atoms such as boron, phosphorus, or arsenic.

[0061] It should be understood that as used throughout this disclosure, the sub-fins, nanowires, nanoribbons, or fins described herein may be silicon germanium sub-fins, silicon germanium nanowires, silicon germanium nanoribbons, or silicon germanium fins. As used throughout, a silicon germanium layer or structure may be used to describe a silicon germanium material that is composed of a majority of both silicon and germanium (e.g., at least 5% of both). In some embodiments, the amount of germanium is greater than the amount of silicon. In a specific embodiment, the silicon germanium layer or structure includes approximately 60% germanium and approximately 40% silicon (Si 40 Ge 60 In other embodiments, the amount of silicon is greater than the amount of germanium. In a particular embodiment, the silicon germanium layer or structure includes about 30% germanium and about 70% silicon (Si 70 Ge 30 ). It should be understood that, in practice, 100% pure silicon germanium (commonly referred to as SiGe) may be difficult to form, and therefore may include a minute percentage of carbon or tin. Such impurities may be included as unavoidable impurities or components during deposition of SiGe, or may "contaminate" SiGe when diffused during post-deposition processing. Therefore, the embodiments described herein for silicon germanium layers or structures may include silicon germanium layers or structures that include relatively small amounts (e.g., "impurity" levels) of non-Ge and non-Si atoms or substances (e.g., carbon or tin). It should be understood that silicon germanium layers or structures as described herein may be undoped or may be doped with dopant atoms such as boron, phosphorus, or arsenic.

[0062] It should be understood that the above Figure 2D-2H The described integrated circuit structures may be integrated with other backside exposed integrated circuit structures. Additionally or alternatively, a combination of Figure 2D-2H The process described can be used to manufacture other integrated circuit structures. As an example of a device with a backside exposed, Figure 3 A cross-sectional view of a non-planar integrated circuit structure taken along a gate line according to an embodiment of the present disclosure is shown.

[0063] refer to Figure 3 , the semiconductor structure or device 300 includes a non-planar active region (e.g., a solid fin structure including a protruding fin portion 304 and a sub-fin region 305) located within a trench isolation region 306. In another embodiment, instead of a solid fin, the non-planar active region is separated into nanowires (e.g., nanowires 304A and 304B) above the sub-fin region 305, as shown by the dotted lines. In either case, for ease of describing the non-planar integrated circuit structure 300, the non-planar active region 304 is referred to below as a protruding fin portion. It should be understood that in one embodiment, there is no bulk substrate coupled to the sub-fin region 305.

[0064] The gate line 308 is disposed over the protruding portion 304 of the non-planar active area (including the surrounding nanowires 304A and 304B, if applicable) and over a portion of the trench isolation region 306. As shown, the gate line 308 includes a gate electrode 350 and a gate dielectric layer 352. In one embodiment, the gate line 308 may also include a dielectric cap layer 354. Also visible from this view is the gate contact 314 and the overlying gate contact via 316, along with the overlying metal interconnect 360, all of which are disposed in an interlayer dielectric stack or layer 370. From Figure 3 It can also be seen from the perspective of FIG. 3 that, in one embodiment, the gate contact 314 is disposed above the trench isolation region 306 but not above the non-planar active region.

[0065] In an embodiment, the semiconductor structure or device 300 is a non-planar device, such as, but not limited to, a fin-FET device, a tri-gate device, a nanoribbon device, or a nanowire device. In such an embodiment, the corresponding semiconductor channel region is formed by or in a three-dimensional body. In one such embodiment, the gate electrode stack of the gate line 308 surrounds at least a top surface and a pair of sidewalls of the three-dimensional body.

[0066] Also like Figure 3As shown, in an embodiment, an interface 380 exists between the protruding fin portion 304 and the sub-fin region 305. The interface 380 can be a transition region between the doped sub-fin region 305 and the lightly doped or undoped upper fin portion 304. In one such embodiment, each fin is approximately 10 nanometers wide or less, and the sub-fin dopant is supplied from an adjacent solid-state doping layer at the sub-fin location. In a particular such embodiment, each fin is less than 10 nanometers wide. In another embodiment, the sub-fin region is a dielectric material formed by recessing the fin by wet or dry etching and filling the recessed cavity with a conformal or flowable dielectric.

[0067] although Figure 3 304, i.e., into and out of the page. In one embodiment, the source or drain region is a doped portion of the original material of the protruding fin portion 304. In another embodiment, the material of the protruding fin portion 304 is removed and replaced with another semiconductor material, for example by epitaxial deposition, to form a discrete epitaxial block or a non-discrete epitaxial structure. In either embodiment, the source or drain region may extend below the height of the dielectric layer of the trench isolation region 306, i.e., into the sub-fin region 305. According to an embodiment of the present disclosure, the more heavily doped sub-fin region (i.e., the doped portion of the fin located below the interface 380) suppresses source-to-drain leakage through this portion of the bulk semiconductor fin.

[0068] Reference again Figure 3 In an embodiment, the fins 304 / 305 (and possibly the nanowires 304A and 304B) are composed of crystalline silicon, silicon / germanium, or germanium layers doped with charge carriers such as, but not limited to, phosphorus, arsenic, boron, or a combination thereof. In one embodiment, the concentration of silicon atoms is greater than 93%. In another embodiment, the fins 304 / 305 are composed of III-V materials such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. The trench isolation region 306 may be composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0069] The gate line 308 may be composed of a gate electrode stack including a gate dielectric layer 352 and a gate electrode layer 350. In an embodiment, the gate electrode of the gate electrode stack is composed of a metal gate, and the gate dielectric layer is composed of a high-k material. For example, in one embodiment, the gate dielectric layer is composed of materials such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. In addition, a portion of the gate dielectric layer may include a native oxide layer formed by the top layers of the substrate fin 304. In an embodiment, the gate dielectric layer is composed of a high-k portion at the top and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride. In some embodiments, a portion of the gate dielectric is a “U” shaped structure including a bottom portion substantially parallel to a surface of the substrate and two sidewall portions substantially perpendicular to a top surface of the substrate.

[0070] In one embodiment, the gate electrode is composed of a metal layer, such as but not limited to metal nitride, metal carbide, metal silicide, metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or conductive metal oxide. In a specific embodiment, the gate electrode is composed of a non-work function setting filling material formed above the metal work function setting layer. Depending on whether the transistor is a PMOS transistor or an NMOS transistor, the gate electrode layer can be composed of a P-type work function metal or an N-type work function metal. In some embodiments, the gate electrode layer can be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers, and at least one metal layer is a conductive filling layer. For PMOS transistors, metals that can be used for the gate electrode include but are not limited to ruthenium, palladium, platinum, cobalt, nickel and conductive metal oxides (e.g., ruthenium oxide). The P-type metal layer will enable the formation of a PMOS gate electrode with a work function between about 4.9eV and about 5.2eV. For NMOS transistors, metals that can be used for gate electrodes include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). The N-type metal layer will enable the formation of an NMOS gate electrode having a work function between about 3.9 eV and about 4.2 eV. In some embodiments, the gate electrode may be composed of a "U"-shaped structure, the U-shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In another embodiment, at least one of the metal layers forming the gate electrode may be only a planar layer substantially parallel to the top surface of the substrate and not including a sidewall portion substantially perpendicular to the top surface of the substrate. In other embodiments of the present disclosure, the gate electrode may be composed of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be composed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0071] The spacer associated with the gate electrode stack can be composed of a material suitable for ultimately electrically isolating or contributing to the isolation of the permanent gate structure from an adjacent conductive contact (e.g., a self-aligned contact). For example, in one embodiment, the spacer is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0072] The gate contact 314 and the overlying gate contact via 316 may be made of a conductive material. In an embodiment, one or more of the contacts or vias are made of a metallic substance. The metallic substance may be a pure metal (e.g., tungsten, nickel, or cobalt), or may be an alloy (e.g., a metal-metal alloy or a metal-semiconductor alloy (e.g., a silicide material)).

[0073] In an embodiment (although not shown), a contact pattern is formed that is substantially perfectly aligned with the existing gate pattern 308, while eliminating the use of a lithography step with a very tight registration budget. In one such embodiment, the self-alignment method enables the use of an inherently highly selective wet etch (e.g., compared to conventionally implemented dry or plasma etching) to generate contact openings. In an embodiment, the contact pattern is formed by utilizing the existing gate pattern in conjunction with a contact plug lithography operation. In one such embodiment, the method enables the elimination of the need for critical lithography operations for other methods of generating contact patterns as used in conventional methods. In an embodiment, the trench contact grid is not patterned separately, but is formed between the polysilicon (gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grid is patterned but before the gate grid is cut.

[0074] In an embodiment, providing structure 300 involves manufacturing gate stack structure 308 by a replacement gate process. In such a scheme, dummy gate material (e.g., polysilicon or silicon nitride pillar material) can be removed and replaced with permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in the process, as opposed to being processed from an earlier time. In an embodiment, the dummy gate is removed by a dry etch or wet etch process. In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed by a dry etch process including the use of SF6. In another embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed by a wet etch process including the use of aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is composed of silicon nitride and is removed by a wet etch including aqueous phosphoric acid.

[0075] Reference again Figure 3 , the arrangement of the semiconductor structure or device 300 places the gate contact above the isolation region. Such an arrangement may be viewed as an inefficient use of layout space. However, in another embodiment, the semiconductor device has a contact structure that contacts a portion of the gate electrode formed above the active region (e.g., above the sub-fin 305) and located in the same layer as the trench contact via.

[0076] It should be understood that not all aspects of the above-described processes need to be implemented to fall within the spirit and scope of the embodiments of the present disclosure. For example, in one embodiment, it is not even necessary to form a dummy gate before manufacturing a gate contact on the active portion of the gate stack. The above-described gate stack may actually be a permanent gate stack as initially formed. In addition, the processes described herein may be used to manufacture one or more semiconductor devices. The semiconductor device may be a transistor or similar device. For example, in an embodiment, the semiconductor device is a metal oxide semiconductor (MOS) transistor for logic or memory, or a bipolar transistor. In addition, in an embodiment, the semiconductor device has a three-dimensional architecture, such as a tri-gate device, an independently accessed dual-gate device, a full-ring gate (GAA) device, a nanowire device, a nanobelt device, or a FIN-FET. One or more embodiments may be particularly useful for manufacturing semiconductor devices at sub-10 nanometer (10nm) technology nodes.

[0077] In an embodiment, as used throughout this specification, an interlayer dielectric (ILD) material is composed of a dielectric layer or an insulating material layer, or includes a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), doped oxides of silicon, fluorinated oxides of silicon, carbon-doped oxides of silicon, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material can be formed by conventional techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

[0078] In an embodiment, as also used throughout this specification, metal lines or interconnect materials (and via materials) are composed of one or more metals or other conductive structures. Common examples are lines and structures using copper, which may or may not include a barrier layer between copper and the surrounding ILD material. As used herein, the term "metal" includes alloys, stacks, and other combinations of multiple metals. For example, a metal interconnect may include a barrier layer (e.g., a layer including one or more of Ta, TaN, Ti, or TiN), a stack of different metals or alloys, etc. Therefore, the interconnect may be a single material layer or may be formed by several layers (including a conductive liner and a filling layer). Any appropriate deposition process (e.g., electroplating, chemical vapor deposition, or physical vapor deposition) may be used to form the interconnect. In an embodiment, the interconnect is composed of a conductive material, such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or their alloys. Interconnects are sometimes also referred to as traces, wires, lines, metals, or simply interconnects in the art.

[0079] In an embodiment, as also used throughout this specification, a hard mask material, a capping layer or a plug is composed of a dielectric material with an interlayer dielectric material. In one embodiment, different hard mask, capping or plug materials can be used in different regions to provide different growth or etching selectivities relative to each other and relative to the underlying dielectric and metal layers. In some embodiments, the hard mask layer, capping or plug layer includes a layer of silicon nitride (e.g., silicon nitride), or a layer of silicon oxide, or both, or a combination thereof. Other suitable materials may include carbon-based materials. Depending on the specific embodiment, other hard mask, capping or plug layers known in the art may be used. The hard mask, capping or plug layer may be formed by CVD, PVD or other deposition methods.

[0080] In an embodiment, as also used throughout this specification, lithography operations are performed using 193nm immersion lithography (i193), EUV and / or EBDW lithography, etc. Positive or negative resists may be used. In one embodiment, the lithography mask is a three-layer mask consisting of a topography mask portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a specific such embodiment, the topography mask portion is a carbon hard mask (CHM) layer, and the anti-reflective coating layer is a silicon ARC layer.

[0081] On the other hand, the integrated circuit structures described herein can be manufactured using a backside exposure manufacturing method for a frontside structure. In some exemplary embodiments, the exposure of the backside of a transistor or other device structure requires wafer-level backside processing. Compared to conventional TSV-type technology, the exposure of the backside of a transistor as described herein can be performed at the density of a device unit and even within a sub-region of a device. In addition, such exposure of the backside of a transistor can be performed to substantially remove all donor substrates on which the device layer is disposed during frontside device processing. Therefore, in the case where the thickness of the semiconductor in the device unit is potentially only tens or hundreds of nanometers after the backside of the transistor is exposed, micron-deep TSVs become unnecessary.

[0082] The exposure techniques described herein can enable a paradigm shift from "bottom-to-top" device fabrication to "center-to-outside" fabrication, where the "center" is any layer employed in front-side fabrication, exposed from the backside, and employed again in back-side fabrication. Processing both the front side and the exposed back side of a device structure can address many of the challenges associated with fabricating 3D ICs when relying primarily on front-side processing.

[0083] A backside exposure method of the transistor may be employed, for example, to remove at least a portion of the carrier layer and the intermediate layer of the donor-host substrate assembly, e.g. Figure 4A-4H and Figure 5A-5HAs shown, as described below. The process flow begins with the input of a donor-host substrate assembly. The thickness of the carrier layer in the donor-host substrate is polished (e.g., CMP) and / or etched using a wet or dry (e.g., plasma) etching process. Any grinding, polishing and / or wet / dry etching process known to be suitable for the composition of the carrier layer can be used. For example, in the case where the carrier layer is a Group IV semiconductor (e.g., silicon), a CMP slurry known to be suitable for thinning semiconductors can be used. Similarly, any wet etchant or plasma etching process known to be suitable for thinning Group IV semiconductors can also be used.

[0084] In some embodiments, prior to the above, the carrier layer is split along a fracture plane substantially parallel to the intermediate layer. A splitting or fracture process can be used to remove a large portion of the carrier layer as a bulk, thereby reducing the polishing or etching time required to remove the carrier layer. For example, in the case where the carrier layer thickness is 400-900 μm, 100-700 μm can be split off by implementing any blanket implant known to promote wafer-level fracture. In some exemplary embodiments, light elements (e.g., H, He, or Li) are implanted to a uniform target depth of the desired fracture plane within the carrier layer. After such a splitting process, the thickness of the carrier layer remaining in the donor-host substrate assembly can then be polished or etched to complete the removal. Alternatively, in the case where the carrier layer is not fractured, grinding, polishing, and / or etching operations can be used to remove a greater thickness of the carrier layer.

[0085] Next, the exposure of the intermediate layer is detected. The detection is used to identify the point when the backside surface of the donor substrate has advanced to the point close to the device layer. Any endpoint detection technology known to be suitable for detecting the transition between the materials used for the carrier layer and the intermediate layer can be implemented. In some embodiments, one or more endpoint criteria are based on detecting the change in light absorption or emission of the backside surface of the donor substrate during the polishing and / or etching. In some other embodiments, the endpoint criteria are associated with the change in light absorption or emission of the byproducts during the polishing or etching of the backside surface of the donor substrate. For example, the absorption or emission wavelength associated with the carrier layer etching byproduct can be changed according to the different composition of the carrier layer and the intermediate layer. In other embodiments, the endpoint criteria are associated with the change in the mass of the substance in the byproduct of polishing or etching the backside surface of the donor substrate. For example, the byproducts of the process can be sampled by a quadrupole mass analyzer, and the change in the mass of the substance can be related to the different composition of the carrier layer and the intermediate layer. In another exemplary embodiment, the endpoint criteria are associated with the change in friction between the backside surface of the donor substrate and the polishing surface in contact with the backside surface of the donor substrate.

[0086] In cases where the removal process is selective for the carrier layer relative to the intermediate layer, detection of the intermediate layer can be enhanced because non-uniformities in the carrier removal process can be mitigated by the difference in etch rates between the carrier layer and the intermediate layer. If the grinding, polishing and / or etching operation removes the intermediate layer at a rate sufficiently lower than the rate at which the carrier layer is removed, detection can even be skipped. If no endpoint criteria are used, a predetermined fixed duration of grinding, polishing and / or etching operation can be stopped on the intermediate layer material if the thickness of the intermediate layer is sufficient for the selectivity of the etching. In some examples, the carrier etch rate:intermediate layer etch rate is 3:1-10:1 or greater.

[0087] Once the intermediate layer is exposed, at least a portion of the intermediate layer can be removed. For example, one or more component layers of the intermediate layer can be removed. For example, the thickness of the intermediate layer can be uniformly removed by polishing. Alternatively, the thickness of the intermediate layer can be removed by a mask or blanket etching process. The process can use the same polishing or etching process used to thin the carrier, or it can be a different process with different process parameters. For example, in the case where the intermediate layer provides an etch stop for the carrier removal process, the latter operation can use a different polishing or etching process that is more conducive to the removal of the intermediate layer than the removal of the device layer. In the case of removing the thickness of the intermediate layer less than a few hundred nanometers, the removal process can be relatively slow, can be optimized for uniformity across the wafer, and can be more accurately controlled than the removal process used to remove the carrier layer. The CMP process used can, for example, use a slurry that provides very high selectivity (e.g., 100:1-300:1 or greater) between a semiconductor (e.g., silicon) and a dielectric material (e.g., SiO) surrounding the device layer and embedded in the intermediate layer (e.g., as electrical isolation between adjacent device regions).

[0088] For embodiments in which the device layer is exposed by completely removing the intermediate layer, backside processing can be initiated on the exposed backside of the device layer or a specific device region therein. In some embodiments, the backside device layer processing includes further polishing or wet / dry etching through the thickness of the device layer disposed between the intermediate layer and a device region previously fabricated in the device layer (e.g., a source or drain region).

[0089] In some embodiments where wet and / or plasma etching is used to recess the back side of the carrier layer, the intermediate layer, or the device layer, such etching can be a patterned etch or a material selective etch that imparts significant non-planarity or topography to the back side surface of the device layer. As further described below, the patterning can be within the device unit (i.e., "intra-unit" patterning) or can span the device unit (i.e., "inter-unit" patterning). In some patterned etching embodiments, at least a portion of the thickness of the intermediate layer is used as a hard mask for patterning the back side device layer. Therefore, the mask etching process can begin with etching the device layer corresponding to the mask.

[0090] The processing scheme described above can produce a donor-host substrate assembly that includes an IC device having a backside of an intermediate layer, a backside of a device layer, and / or a backside of one or more semiconductor regions within a device layer, and / or exposed front-side metallization. Additional backside processing can then be performed on any of these exposed regions during downstream processing.

[0091] According to one or more embodiments of the present disclosure, in order to achieve back-side access to partitioned source or drain contact structures, a double-sided device processing scheme can be implemented at the wafer level. In some exemplary embodiments, large formal substrate (e.g., 300 or 450 mm diameter) wafers can be processed. In an exemplary processing scheme, a donor substrate including a device layer is provided. In some embodiments, the device layer is a semiconductor material used by an IC device. As an example, in a transistor device such as a field effect transistor (FET), the channel semiconductor is formed by a semiconductor device layer. As another example, for an optical device such as a photodiode, a drift and / or gain semiconductor is formed by a device layer. The device layer can also be used in a passive structure with an IC device. For example, an optical waveguide can use a semiconductor patterned from a device layer.

[0092] In some embodiments, the donor substrate includes a stack of material layers. Such a material stack can facilitate the subsequent formation of an IC device layer, which includes the device layer but lacks other layers of the donor substrate. In an exemplary embodiment, the donor substrate includes a carrier layer separated from the device layer by one or more intermediate material layers. The carrier layer is used to provide mechanical support during the front side processing of the device layer. The carrier can also provide a basis for crystallinity in the semiconductor device layer. (One or more) intermediate layers can facilitate the removal of the carrier layer and / or expose the back side of the device layer.

[0093] The front side manufacturing operation is then performed to form a device structure including one or more regions in the device layer. Any known front side processing technology can be used to form any known IC device, and exemplary embodiments are further described elsewhere in this article. The front side of the donor substrate is then bonded to the host substrate to form a device host assembly. The host substrate will provide front side mechanical support during the back side processing of the device layer. The host substrate may also require an integrated circuit, and the IC device manufactured on the donor substrate is interconnected with the integrated circuit. For such an embodiment, the bonding of the host and donor substrates may further require the formation of a 3D interconnect structure by hybrid (dielectric / metal) bonding. Any known host substrate and wafer level bonding technology can be used.

[0094] The process flow continues, wherein the back side of the device layer is exposed by removing at least a portion of the carrier layer. In some other embodiments, any intermediate layer and / or portion of the front side material deposited on the device layer may also be removed during the revealing operation. As described elsewhere herein in the context of some exemplary embodiments, the intermediate layer may facilitate highly uniform exposure of the back side of the device layer, such as being used as one or more of the etching marks or etching stops employed in the wafer-level backside revealing process. The device layer surface exposed from the back side is processed to form a double-sided device layer. The native material that interfaces with the device region may then be replaced with one or more non-native materials, such as any of the native materials of the donor substrate. For example, a portion of the semiconductor device layer or intermediate layer may be replaced with one or more other semiconductor, metal, or dielectric materials. In some other embodiments, a portion of the front side material removed during the revealing operation may also be replaced. For example, during the backside de-processing / re-processing of the front side device, a portion of the dielectric spacer, gate stack, or contact metallization formed during the front side device manufacturing may be replaced with one or more other semiconductor, metal, or dielectric materials. In yet other embodiments, a second device layer or a metal interposer is bonded to the exposed backside.

[0095] The above process flow provides a device layer-host substrate assembly. The device layer-host assembly can then be further processed. For example, any known technology can be used to singulate and package the device layer-host substrate assembly. In the case where the host substrate is completely sacrificial, the packaging of the device layer-host substrate may require the separation of the host substrate from the device layer. In the case where the host substrate is not completely sacrificial (for example, in the case where the host substrate also includes a device layer), the device layer-host assembly output can be fed back as a host substrate input during subsequent iterations of the above process flow. For example, iterations of the above method can therefore form wafer-level assemblies of any number of double-sided device layers, each layer having a thickness of only tens or hundreds of nanometers. In some embodiments, and as further described elsewhere herein, one or more device units within the device layer are electrically tested, for example as a yield control point in the manufacture of wafer-level assemblies of double-sided device layers. In some embodiments, electrical testing requires back-side device detection.

[0096] Figure 4A-4H A plan view of a substrate processed using a double-sided device processing method is shown in accordance with some embodiments. Figure 5A-5H A cross-sectional view of a substrate processed using a double-sided device processing method according to some embodiments is shown.

[0097] like Figure 4A and Figure 5A As shown, the donor substrate 401 includes a plurality of IC dies 411 in an arbitrary spatial arrangement above the front side wafer surface. The front side processing of the IC dies 411 may have been performed according to any technology to form any device structure. In an exemplary embodiment, the die 411 includes one or more semiconductor regions within the device layer 415. The intermediate layer 410 separates the device layer 415 from the carrier layer 405. In an exemplary embodiment, the intermediate layer 410 is in direct contact with both the carrier layer 405 and the device layer 415. Alternatively, one or more spacer layers may be disposed between the intermediate layer 410 and the device layer 415 and / or the carrier layer 405. The donor substrate 401 may also include other layers, for example, disposed above the device layer 415 and / or below the carrier layer 405.

[0098] Device layer 415 may include one or more layers of any device material composition known to be suitable for a particular IC device (e.g., but not limited to, transistors, diodes, and resistors). In some exemplary embodiments, device layer 415 includes one or more Group IV (i.e., IUPAC Group 14) semiconductor material layers (e.g., Si, Ge, SiGe), Group III-V semiconductor material layers (e.g., GaAs, InGaAs, InAs, InP), or Group III-N semiconductor material layers (e.g., GaN, AlGaN, InGaN). Device layer 415 may also include one or more semiconductor transition metal chalcogenide (TMD or TMDC) layers. In other embodiments, device layer 415 includes one or more graphene layers or graphene material layers having semiconductor properties. In yet other embodiments, device layer 415 includes one or more oxide semiconductor layers. Exemplary oxide semiconductors include oxides of transition metals (e.g., IUPAC Groups 4-10) or post-transition metals (e.g., IUPAC Groups 11-14). In a preferred embodiment, the oxide semiconductor includes at least one of Cu, Zn, Sn, Ti, Ni, Ga, In, Sr, Cr, Co, V, or Mo. The metal oxide may be a secondary oxide (A2O), a monoxide (AO), a binary oxide (AO2), a ternary oxide (ABO3), and mixtures thereof. In other embodiments, the device layer 415 includes one or more layers of magnetic, ferromagnetic, or ferroelectric materials. For example, the device layer 415 may include one or more layers of any material known to be suitable for a tunneling junction device, such as, but not limited to, a magnetic tunneling junction (MTJ) device.

[0099] In some embodiments, device layer 415 is substantially single crystalline. Although single crystalline, a large number of crystal defects may still be present. In other embodiments, device layer 415 is amorphous or nanocrystalline. Device layer 415 may be of any thickness (e.g., Figure 5A In some exemplary embodiments, the thickness of device layer 415 is greater than the z-thickness of at least some of the semiconductor regions employed by die 411 because the functional semiconductor regions of die 411 built on and / or embedded in device layer 415 do not necessarily extend through the entire thickness of device layer 415. In some embodiments, the semiconductor regions of die 411 are only disposed at Figure 5A 410. The top side thickness of the device layer 415 is defined by the dashed line 412. For example, the semiconductor region of the die 411 may have a z-thickness of 200-300 nm or less, while the device layer may have a z-thickness of 700-1000 nm or more. Thus, a device layer thickness of about 600 nm may separate the semiconductor region of the die 411 from the intermediate layer 410.

[0100] The carrier layer 405 may have the same material composition as the device layer 415, or may have a different material composition than the device layer 415. For embodiments where the carrier layer 405 and the device layer 415 have the same composition, the two layers may be identified by their position relative to the intermediate layer 410. In some embodiments where the device layer 415 is a crystalline Group IV, Group III-V, or Group III-N semiconductor, the carrier layer 405 is the same crystalline Group IV, Group III-V, or Group III-N semiconductor as the device layer 415. In alternative embodiments where the device layer 415 is a crystalline Group IV, Group III-V, or Group III-N semiconductor, the carrier layer 405 is a different crystalline Group IV, Group III-V, or Group III-N semiconductor than the device layer 415. In still other embodiments, the carrier layer 405 may include or may be a material onto which the device layer 415 is transferred or grown. For example, the carrier layer may include one or more amorphous oxide layers (e.g., glass) or crystalline oxide layers (e.g., sapphire), a polymer sheet, or any material(s) built into or laminated into a structural support known to be suitable as a carrier during IC device processing. The carrier layer 405 may be of any thickness (e.g., Figure 5A For example, in case the carrier layer 405 is a large format (eg, 300-450 mm) semiconductor substrate, the carrier layer thickness may be 700-1000 μm or more.

[0101] In some embodiments, one or more intermediate layers 410 are disposed between the carrier layer 405 and the device layer 415. In some exemplary embodiments, the intermediate layer 410 is compositionally different from the carrier layer 405 so that it can be used as a detectable mark during subsequent removal of the carrier layer 405. In some such embodiments, the intermediate layer 410 has a composition that will be etched at a significantly slower rate than the carrier layer 405 when exposed to an etchant for the carrier layer 405 (i.e., the intermediate layer 410 serves as an etch stop for the carrier layer etching process). In still other embodiments, the intermediate layer 410 has a composition that is different from that of the device layer 415. For example, the intermediate layer 410 can be a metal, a semiconductor, or a dielectric material.

[0102] In some exemplary embodiments where at least one of the carrier layer 405 and the device layer 415 is a crystalline semiconductor, the intermediate layer 410 is also a crystalline semiconductor layer. The intermediate layer 410 may also have the same crystallinity and crystal orientation as the carrier layer 405 and / or the device layer 415. Such embodiments may have the advantage of reducing the cost of the donor substrate relative to alternative embodiments where the intermediate layer 410 is a material that requires bonding (e.g., thermocompression bonding) the intermediate layer 410 to the intermediate layer 410 and / or the carrier layer 405.

[0103] For embodiments where the intermediate layer 410 is a semiconductor, one or more of the main semiconductor lattice element, alloy composition, or impurity concentration may vary between at least the carrier layer 405 and the intermediate layer 410. In some embodiments where at least the carrier layer 405 is a Group IV semiconductor, the intermediate layer 410 may also be a Group IV semiconductor, but with a different Group IV element or alloy and / or doped with an impurity species to an impurity level different from that of the carrier layer 405. For example, the intermediate layer 410 may be a silicon-germanium alloy epitaxially grown on a silicon carrier. For such embodiments, the pseudomorphic intermediate layer may be heteroepitaxially grown to any thickness below the critical thickness. Alternatively, the intermediate layer 410 may be a relaxed buffer layer having a thickness greater than the critical thickness.

[0104] In other embodiments where at least the carrier layer 405 is a III-V semiconductor, the intermediate layer 410 may also be a III-V semiconductor, but having a different III-V alloy and / or being doped with impurity species to different impurity levels than the carrier layer 405. For example, the intermediate layer 410 may be an AlGaAs alloy epitaxially grown on a GaAs carrier. In some other embodiments where both the carrier layer 405 and the device layer 415 are crystalline semiconductors, the intermediate layer 410 is also a crystalline semiconductor layer, which may also have the same crystallinity and crystal orientation as the carrier layer 405 and / or the device layer 415.

[0105] In embodiments where both the carrier layer 405 and the intermediate layer 410 have the same or different host semiconductor lattice elements, the impurity dopant may differentiate between the carrier and the intermediate layer. For example, the intermediate layer 410 and the carrier layer 405 may both be silicon crystals, wherein the intermediate layer 410 lacks an impurity present in the carrier layer 405, or is doped with an impurity not present in the carrier layer 405, or is doped to a different level of an impurity present in the carrier layer 405. The impurity differentiation may impart etch selectivity between the carrier and the intermediate layer, or simply introduce a detectable species.

[0106] Intermediate layer 410 may be doped with electrically active impurities (i.e., to make it an n-type or p-type semiconductor), or undoped, as the impurities may provide any basis for detecting intermediate layer 410 during subsequent carrier removal. Exemplary electrically active impurities of some semiconductor materials include Group III elements (e.g., B), Group IV elements (e.g., P). Any other element may be used as a non-electroactive substance. The impurity dopant concentration within intermediate layer 410 need only differ from the impurity dopant concentration of carrier layer 405 by an amount sufficient for detection, which may be predetermined based on the detection technique and detector sensitivity.

[0107] As further described elsewhere herein, the intermediate layer 410 can have a different composition than the device layer 415. In some such embodiments, the intermediate layer 410 can have a bandgap that is different than the bandgap of the device layer 415. For example, the intermediate layer 410 can have a wider bandgap than the device layer 415.

[0108] In embodiments where the intermediate layer 410 comprises a dielectric material, the dielectric material may be an inorganic material (e.g., SiO, SiN, SiON, SiOC, hydrogen silsesquioxane, methyl silsesquioxane) or an organic material (polyimide, polynorbornene, benzocyclobutene). For some dielectric embodiments, the intermediate layer 410 may be formed as an embedded layer (e.g., by implanting oxygen into SiOx in a silicon device and / or carrier layer). Other embodiments of the dielectric intermediate layer may require bonding (e.g., thermocompression bonding) the carrier layer 405 to the device layer 415. For example, where the donor substrate 401 is a semiconductor on oxide (SOI) substrate, either or both of the carrier layer 405 and the device layer 415 may be oxidized and bonded together to form the SiO intermediate layer 410. Similar bonding techniques may be used for other inorganic or organic dielectric materials.

[0109] In some other embodiments, the intermediate layer 410 includes two or more materials spaced laterally apart within the layer. The two or more materials may include a dielectric and a semiconductor, a dielectric and a metal, a semiconductor and a metal, a dielectric and an alloy, two different dielectrics, two different semiconductors, or two different metals. Within such an intermediate layer, a first material may surround an island of a second material extending through the thickness of the intermediate layer. For example, the intermediate layer may include a field isolation dielectric that surrounds a semiconductor island extending through the thickness of the intermediate layer. The semiconductor may be epitaxially grown within the opening of the patterned dielectric, or a dielectric material may be deposited within the opening of the patterned semiconductor.

[0110] In some exemplary embodiments, semiconductor features such as fins or terraces are etched into the front side surface of the semiconductor device layer. For example, after any known shallow trench isolation (STI) process, the trenches surrounding these features can be subsequently backfilled with an isolation dielectric. One or more of the semiconductor features or the isolation dielectric can be used to terminate the backside carrier removal process, for example as a backside exposure etch stop. In some embodiments, the exposure of the trench isolation dielectric can stop, significantly delay, or induce a detectable signal for terminating the backside carrier polishing. For example, when the (bottom) surface of the trench isolation dielectric surrounding the semiconductor features including the device layer is exposed, the CMP polishing of the carrier semiconductor using a slurry with a high selectivity that is more conducive to removing the carrier semiconductor (e.g., Si) than removing the isolation dielectric (e.g., SiO) can be significantly slowed down. Since the device layer is disposed on the front side of the intermediate layer, the device layer does not need to be directly exposed to the backside exposure process.

[0111] It is noteworthy that for embodiments where the intermediate layer includes both semiconductor and dielectric, the intermediate layer thickness can be significantly greater than a critical thickness associated with the lattice mismatch of the intermediate layer and the carrier. Although the thickness of the intermediate layer below the critical thickness may not be sufficient to accommodate the non-uniformity of the wafer-level backside exposure process, embodiments with a greater thickness can advantageously increase the backside exposure process window. Embodiments with pinhole dielectrics can otherwise facilitate subsequent separation of the carrier layer and the device layer as well as improve crystal quality within the device layer.

[0112] Semiconductor material within the intermediate layer including both semiconductor and dielectric may also be homoepitaxial.In some exemplary embodiments, silicon epitaxial device layers are grown through a pinhole dielectric disposed over a silicon carrier layer.

[0113] continue Figure 4A and Figure 5A 4. In the description of the embodiment of the present invention, the intermediate layer 410 can also be a metal. For such an embodiment, the metal can have any composition known to be suitable for bonding to the carrier layer 405 or the device layer 415. For example, either or both of the carrier layer 405 and the device layer 415 can be finished with a metal (such as but not limited to Au or Pt) and then bonded together, for example, to form an Au or Pt intermediate layer 410. Such a metal can also be part of an intermediate layer that also includes a patterned dielectric surrounding the metal features.

[0114] The intermediate layer 410 may have any thickness (eg, Figure 5A410). The intermediate layer should be thick enough to ensure that the carrier removal operation can be reliably terminated before exposing the device region and / or device layer 415. For example, an exemplary thickness of the intermediate layer 410 ranges from a few hundred nanometers to a few microns and can vary depending on the amount of carrier material to be removed, the uniformity of the carrier removal process, and the selectivity of the carrier removal process. For embodiments in which the intermediate layer has the same crystallinity and crystallographic orientation as the carrier layer 405, the carrier layer thickness can be reduced by the thickness of the intermediate layer 410. In other words, the intermediate layer 410 can be the top portion of a 700-1000 μm thick Group IV crystalline semiconductor substrate, which also serves as a carrier layer. In pseudomorphic heteroepitaxial embodiments, the intermediate layer thickness can be limited to a critical thickness. For heteroepitaxial intermediate layer embodiments employing aspect ratio trapping (ART) or another fully relaxed buffer architecture, the intermediate layer can have any thickness.

[0115] like Figure 4B and Figure 5B As further shown in the figure, the donor substrate 401 can be bonded to the host substrate 402 to form a donor-host substrate assembly 403. In some exemplary embodiments, the front side surface of the donor substrate 401 is bonded to the surface of the host substrate 402, so that the device layer 415 is close to the host substrate 402, and the carrier layer 405 is away from the host substrate 402. The host substrate 402 can be any substrate known to be suitable for bonding to the device layer 415 and / or a front side stack fabricated on the device layer 415. In some embodiments, the host substrate 402 includes one or more additional device layers. For example, the host substrate 402 may also include one or more device layers (not shown). The host substrate 402 may include an integrated circuit, and the IC devices fabricated in the device layer of the host substrate 402 are interconnected with the integrated circuit. In this case, bonding the device layer 415 to the host substrate 402 may also require forming a 3D interconnect structure by wafer-level bonding.

[0116] although Figure 5B 4. Although not shown in detail, there may be any number of front-side layers, such as interconnect metallization layers and interlayer dielectric (ILD) layers, between the device layer 415 and the host substrate 402. Any technique may be employed to bond the host substrate 402 and the donor substrate 401. In some exemplary embodiments further described elsewhere herein, the bonding of the donor substrate 401 to the host substrate 402 is by metal-metal, oxide-oxide, or hybrid (metal / oxide-metal / oxide) thermocompression bonding.

[0117] In the case where the host substrate 402 faces the device layer 415 on the side opposite to the carrier layer 405, at least a portion of the carrier layer 405 may be removed, such as Figure 4C and Figure 5CAs shown. With the entire carrier layer 405 removed, the donor-host substrate assembly 403 maintains a highly uniform thickness with flat backside and frontside surfaces. Alternatively, the carrier layer 405 can be masked and the intermediate layer 410 exposed only in unmasked sub-regions to form a non-planar backside surface. Figure 4C and Figure 5C In the exemplary embodiment shown, the carrier layer 405 is removed from the entire backside surface of the donor-host substrate assembly 403. The carrier layer 405 can be removed, for example, by cutting, grinding and / or polishing (e.g., chemical mechanical polishing), and / or wet chemical etching and / or plasma etching through the thickness of the carrier layer to expose the intermediate layer 410. One or more operations can be used to remove the carrier layer 405. Advantageously, the removal operation(s) can be terminated based on a duration or endpoint signal sensitive to the exposure of the intermediate layer 410.

[0118] In a further embodiment, for example, Figure 4D and Figure 5D As shown, the intermediate layer 410 is also at least partially etched to expose the back side of the device layer 415. At least a portion of the intermediate layer 410 can be removed after it serves as a carrier layer etch stop and / or a carrier layer etch endpoint trigger. With the entire intermediate layer 410 removed, the donor-host substrate assembly 403 maintains a highly uniform device layer thickness, wherein the flat backside and frontside surfaces provided by the intermediate layer are much thinner than the carrier layer. Alternatively, the intermediate layer 410 can be masked and the device layer 415 exposed only in unmasked sub-regions, thereby forming a non-planar backside surface. Figure 4D and Figure 5D In the exemplary embodiment shown, the intermediate layer 410 is removed from the entire backside surface of the donor-host substrate assembly 403. The intermediate layer 410 can be so removed, for example, by polishing (e.g., chemical mechanical polishing), and / or blanket wet chemical etching and / or blanket plasma etching through the thickness of the intermediate layer to expose the device layer 415. One or more operations can be employed to remove the intermediate layer 410. Advantageously, the removal operation(s) can be terminated based on a duration or endpoint signal that is sensitive to the exposure of the device layer 415.

[0119] In some further embodiments, for example, Figure 4E and Figure 5EAs shown, the device layer 415 is partially etched to expose the back side of the device structures previously formed during the front side processing. At least a portion of the device layer 415 can be removed after it is used to fabricate one or more device semiconductor regions and / or it is used as an intermediate layer etch stop or endpoint trigger. Where the device layer 415 is thinned over the entire substrate area, the donor-host substrate assembly 403 maintains a highly uniform reduced thickness with flat rear and front surfaces. Alternatively, the device layer 415 can be masked and the device structures (e.g., device semiconductor regions) selectively revealed only in unmasked sub-regions, thereby forming a non-planar back side surface. Figure 4E and Figure 5E In the exemplary embodiment shown, the device layer 415 is thinned over the entire backside surface of the donor-host substrate assembly 403. The device layer 415 can be thinned, for example, by polishing (e.g., chemical mechanical polishing), and / or wet chemical etching and / or plasma etching through the thickness of the device layer to expose one or more device semiconductor regions, and / or one or more other device structures previously formed during front-side processing (e.g., front-side device terminal contact metallization, spacer dielectric, etc.). One or more operations can be used to thin the device layer 415. Advantageously, the device layer thinning can be terminated based on a duration or endpoint signal that is sensitive to the exposure of patterned features within the device layer 415. For example, in the case of front-side processing to form device isolation features (e.g., shallow trench isolation), the backside thinning of the device layer 415 can be terminated when the isolation dielectric material is exposed.

[0120] The non-native material layer may be deposited on the backside surface of the intermediate layer, the device layer and / or specific device regions within the device layer 415, and / or deposited on one or more other device structures (e.g., front-side device terminal contact metallization, spacer dielectric, etc.). One or more materials exposed (revealed) from the backside may be covered with a non-native material layer or replaced with such a material. In some embodiments, as Figure 4F and Fig. 5FAs shown, a non-native material layer 420 is deposited on the device layer 415. The non-native material layer 420 can be any material having a composition and / or microstructure different from the composition and / or microstructure of the material removed to reveal the back side of the device layer. For example, in the case where the intermediate layer 410 is removed to expose the device layer 415, the non-native material layer 420 can be another semiconductor having a composition or microstructure different from the composition or microstructure of the intermediate layer 410. In some such embodiments where the device layer 415 is a III-N semiconductor, the non-native material layer 420 can also be a III-N semiconductor of the same or different composition that is regrown on the exposed backside surface of the III-N device region. The material can be epitaxially regrown from the exposed III-N device region, for example, to have better crystal quality than the removed material, and / or induce strain within the device layer and / or within the device region within the device layer, and / or form a vertical (e.g., z-dimension) stack of device semiconductor regions suitable for stacking devices.

[0121] In some other embodiments where the device layer 415 is a III-V semiconductor, the non-native material layer 420 may also be a III-V semiconductor of the same or different composition regrown on the exposed backside surface of the III-V device region. The material may be epitaxially regrown from the exposed III-V device region, for example, to have relatively better crystal quality than the removed material, and / or to induce strain within the device layer or within a specific device region within the device layer, and / or to form a vertical stack of device semiconductor regions suitable for stacking devices.

[0122] In some other embodiments where the device layer 415 is a Group IV semiconductor, the non-native material layer 420 may also be a Group IV semiconductor of the same or different composition that is regrown on the exposed backside surface of the Group IV device region. The material may be epitaxially regrown from the exposed Group IV device region, for example, to have relatively better crystal quality than the removed material, and / or to induce strain in the device region, and / or to form a stack of device semiconductor regions suitable for stacking devices.

[0123] In some other embodiments, the non-native material layer 420 is a dielectric material, such as but not limited to SiO, SiON, SiOC, hydrogen silsesquioxane, methyl silsesquioxane, polyimide, polynorbornene, benzocyclobutene, etc. The deposition of such a dielectric can be used to electrically isolate various device structures (e.g., semiconductor device regions) that may have been previously formed during the front-side processing of the donor substrate 401.

[0124] In some other embodiments, the non-native material layer 420 is a conductive material, such as any elemental metal or metal alloy known to be suitable for contacting one or more surfaces of the device region exposed from the back side. In some embodiments, the non-native material layer 420 is a metallization suitable for contacting the device region (e.g., transistor source or drain region) exposed from the back side. In embodiments, metal-to-metal contacts such as NixSiy, TixSiy, Ni:Si:Pt, TiSi, CoSi, etc. can be formed. In addition, implants can be used to achieve robust contacts (e.g., P, Ge, B, etc.).

[0125] In some embodiments, the non-native material layer 420 is a stack of materials, such as a FET gate stack including both a gate dielectric layer and a gate electrode layer. As an example, the non-native material layer 420 can be a gate dielectric stack suitable for contacting a semiconductor device region (e.g., a transistor channel region) exposed from the back side. Any other material described as an option for the device layer 415 can also be deposited on the back side of the device layer 415 and / or formed on the device region within the device layer 415. For example, the non-native material layer 420 can be any of the above-mentioned oxide semiconductors, TMDCs, or tunneling materials, which can be deposited on the back side, for example, to incrementally manufacture vertically stacked device layers.

[0126] Backside wafer-level processing can continue in any manner known to be suitable for front-side processing. For example, the non-native material layer 420 can be patterned into active device areas, device isolation areas, device contact metallizations, or device interconnects using any known photolithography and etching techniques. Backside wafer-level processing can also fabricate one or more interconnect metallization layers that couple the terminals of different devices to the IC. In some embodiments further described elsewhere herein, backside processing can be employed to interconnect power buses to various device terminals within the IC.

[0127] In some embodiments, the backside processing includes bonding to a secondary host substrate. Such bonding can employ any layer transfer process to bond a backside (e.g., non-native) material layer to another substrate. After such bonding, the previous host substrate can be removed as a sacrificial donor to re-expose the front side stack and / or the front side of the device layer. Such embodiments can enable repeated side-to-side lamination of device layers with the first device layer as the core of the assembly. Figure 4G and Figure 5G In some of the embodiments shown, a secondary host substrate 440 bonded to the non-native material layer 420 provides at least mechanical support when the host substrate 402 is removed.

[0128] Any bonding (e.g., but not limited to, thermocompression bonding) may be employed to bond the secondary host substrate 440 to the non-native material layer 420. In some embodiments, both the surface layer of the secondary host substrate 440 and the non-native material layer 420 are continuous dielectric layers (e.g., SiO) that are thermocompression bonded. In some other embodiments, both the surface layer of the secondary host substrate 440 and the non-native material layer 420 include metal layers (e.g., Au, Pt, etc.) that are thermocompression bonded. In other embodiments, at least one of the surface layer of the secondary host substrate 440 and the non-native material layer 420 is patterned, including both a patterned metal surface (i.e., traces) and a surrounding dielectric (e.g., isolation) that are thermocompression bonded to form a hybrid (e.g., metal / oxide) joint. For such embodiments, structural features in the secondary host substrate 440 and the patterned non-native material layer 420 are aligned (e.g., optically) during the bonding process. In some embodiments, non-native material layer 420 includes one or more conductive backside traces coupled to terminals of transistors fabricated in device layer 415. The conductive backside traces may be bonded to metallization on secondary host substrate 440, for example.

[0129] Bonding of the device layer may be performed from the front side and / or back side of the device layer before or after the front side processing of the device layer has been completed. The back side bonding process may be performed after the front side fabrication of the device (e.g., transistor) is substantially complete. Alternatively, the back side bonding process may be performed before the front side fabrication of the device (e.g., transistor) is completed, in which case the front side of the device layer may receive additional processing after the back side bonding process. Figure 4H and Figure 5H As further shown, for example, front-side processing includes removing host substrate 402 (as a second donor substrate) to re-expose the front side of device layer 415. At this point, donor-host substrate assembly 403 includes secondary host 440 bonded to device layer 415 via non-native material layer 420.

[0130] On the other hand, the above combined Figure 2D-2H The described integrated circuit structure can be integrated with other back-exposed integrated circuit structures (e.g., adjacent semiconductor structures or devices separated by self-aligned gate end caps (SAGE) structures). Specific embodiments can be directed to the integration of multi-width (multi-Wsi) nanowires and nanoribbons in a SAGE architecture and separated by SAGE walls. In an embodiment, nanowires / nanoribbons are integrated with multi-Wsi in the SAGE architecture portion of the front-end process flow. Such a process flow can involve the integration of nanowires and nanoribbons of different Wsi to provide robust functionality of next-generation transistors with low power and high performance. The associated epitaxial source or drain region can be embedded (e.g., removing a portion of the nanowire and then performing source or drain (S / D) growth).

[0131] To provide further context, the advantages of a self-aligned gate end cap (SAGE) architecture can include enabling higher layout density, especially diffusion-to-diffusion spacing scaling. To provide an illustrative comparison, Figure 6 A cross-sectional view taken through a nanowire and fin for a non-endcap architecture is shown in accordance with an embodiment of the present disclosure. Figure 7 A cross-sectional view taken through a nanowire and a fin for a self-aligned gate end cap (SAGE) architecture is shown in accordance with an embodiment of the present disclosure.

[0132] refer to Figure 6 , the integrated circuit structure 600 includes a substrate 602 having a fin 604, the fin 604 protruding an amount 606 above an isolation structure 608 that laterally surrounds a lower portion of the fin 604. As shown, the upper portion of the fin may include a local isolation structure 622 and a growth enhancement layer 620. A corresponding nanowire 605 is located above the fin 604. A gate structure may be formed on the integrated circuit structure 600 to fabricate a device. However, such a discontinuity in the gate structure may be accommodated by increasing the spacing between the fin 604 / nanowire 605 pairs.

[0133] refer to Figure 6 In an embodiment, after the gate is formed, the lower portion of structure 600 may be planarized and / or etched to level 634 to leave a backside surface including the gate structure and the exposed bottom surface of the epitaxial source or drain structure. It should be understood that a backside (bottom) contact may be formed on the exposed bottom surface of the epitaxial source or drain structure. It should also be understood that planarization and / or etching may be performed to other levels such as 630 or 632.

[0134] In contrast, reference Figure 7, the integrated circuit structure 750 includes a substrate 752 having a fin 754, the fin 754 protruding an amount 756 above an isolation structure 758 that laterally surrounds the lower portion of the fin 754. As shown, the upper portion of the fin may include a local isolation structure 772 and a growth enhancement layer 770. The corresponding nanowire 755 is located above the fin 754. An isolation SAGE wall 760 (which may include a hard mask, as shown) is included within the isolation structure 758 and between adjacent fins 754 / nanowires 755 pairs. The distance between the isolation SAGE wall 760 and the nearest fin 754 / nanowire 755 pair defines a gate end cap spacing 762. A gate structure can be formed above the integrated circuit structure 750 and between the isolation SAGE walls to manufacture a device. The interruption in such a gate structure is enforced by the isolation SAGE wall. Since the isolation SAGE wall 760 is self-aligned, the limitations from conventional methods can be minimized to achieve a more aggressive diffusion to diffusion spacing. Furthermore, since the gate structure includes interruptions at all locations, the various gate structure portions can be layered together by local interconnects formed over the isolated SAGE walls 760. In an embodiment, as shown, the SAGE walls 760 each include a lower dielectric portion and a dielectric cap over the lower dielectric portion.

[0135] refer to Figure 7 In an embodiment, after the gate is formed, the lower portion of structure 700 may be planarized and / or etched to level 784 to leave a backside surface including the gate structure and the exposed bottom surface of the epitaxial source or drain structure. It should be understood that a backside (bottom) contact may be formed on the exposed bottom surface of the epitaxial source or drain structure. It should also be understood that planarization and / or etching may be performed to other levels such as 780 or 782.

[0136] A self-aligned gate end cap (SAGE) processing scheme involves forming a gate / trench contact end cap that is self-aligned with the fin without requiring additional length to account for mask misalignment. Thus, embodiments may be implemented to achieve a reduction in transistor layout area. Embodiments described herein may involve the manufacture of a gate end cap isolation structure, which may also be referred to as a gate wall, an isolation gate wall, or a self-aligned gate end cap (SAGE) wall.

[0137] In an embodiment, as described throughout, a self-aligned gate end cap (SAGE) isolation structure may be composed of one or more materials suitable for ultimately electrically isolating or contributing to isolating portions of a permanent gate structure from one another. Exemplary materials or material combinations include single material structures such as silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride. Other exemplary materials or material combinations include a multilayer stack having a lower portion of silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride and an upper portion of a higher dielectric constant material (e.g., hafnium oxide).

[0138] It should be understood that the above Figure 2D-2H The described integrated circuit structures can be integrated with other backside exposed integrated circuit structures (e.g., nanowire or nanoribbon based devices). Additionally or alternatively, a combination of Figure 2D-2H To highlight an exemplary integrated circuit structure having three vertically arranged nanowires, Fig. 8A A three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure is shown. Figure 8B The image taken along the a-a' axis is shown. Fig. 8A A cross-sectional source or drain view of a nanowire-based integrated circuit structure. Figure 8C The image taken along the b-b' axis is shown. Fig. 8A Cross-sectional channel view of a nanowire-based integrated circuit structure.

[0139] refer to Fig. 8A , the integrated circuit structure 800 includes one or more vertically stacked nanowires (804 groups) located above a substrate 802. In an embodiment, as shown, a local isolation structure 802C, a growth enhancement layer 802B, and a lower substrate portion 802A are included in the substrate 802, as shown. For illustrative purposes, in order to emphasize the nanowire portion, the optional fins below the bottommost nanowire and formed by the substrate 802 are not shown. The embodiments herein are directed to both single-wire devices and multi-wire devices. As an example, for illustrative purposes, three nanowire-based devices with nanowires 804A, 804B, and 804C are shown. For ease of description, nanowire 804A is used as an example, wherein the description focuses on one nanowire in the nanowire. It should be understood that in the case of describing the properties of a nanowire, embodiments based on multiple nanowires may have the same or substantially the same properties for each nanowire in the nanowire.

[0140] Each of the nanowires 804 includes a channel region 806 in the nanowire. The channel region 806 has a length (L). Figure 8C , the channel region also has a perimeter (Pc) orthogonal to the length (L). Fig. 8A and Figure 8C In both cases, the gate electrode stack 808 surrounds the entire perimeter (Pc) of each of the channel regions 806. The gate electrode stack 808 includes a gate electrode and a gate dielectric layer located between the channel region 806 and the gate electrode (not shown). In an embodiment, the channel region is discrete because the channel region is completely surrounded by the gate electrode stack 808 without any intermediate material (e.g., underlying substrate material or overlying channel fabrication material). Therefore, in an embodiment with multiple nanowires 804, the channel regions 806 of the nanowires are also discrete relative to each other.

[0141] refer to Fig. 8A and Figure 8B In both, the integrated circuit structure 800 includes a pair of non-discrete source or drain regions 810 / 812. The pair of non-discrete source or drain regions 810 / 812 are on either side of a channel region 806 of a plurality of vertically stacked nanowires 804. In addition, the pair of non-discrete source or drain regions 810 / 812 abut the channel region 806 of the plurality of vertically stacked nanowires 804. In one such embodiment not shown, the pair of non-discrete source or drain regions 810 / 812 directly vertically abut the channel region 806 because epitaxial growth is on and between the nanowire portions extending beyond the channel region 806, where the nanowire ends are shown as being within the source or drain structure. In another embodiment, as shown Fig. 8A As shown, the pair of non-discrete source or drain regions 810 / 812 do not directly vertically adjoin the channel region 806 because they are formed at the ends of the nanowires rather than between the nanowires.

[0142] In an embodiment, as shown, the source or drain regions 810 / 812 are non-discrete in that there is no separate and discrete source or drain region for each channel region 806 of the nanowire 804. Thus, in an embodiment having multiple nanowires 804, the source or drain regions 810 / 812 of the nanowires are global or unified source or drain regions as opposed to being discrete for each nanowire. That is, the non-discrete source or drain regions 810 / 812 are global in the sense that a single unified feature serves as a source or drain region for multiple (in this case, 3) nanowires 804, and more specifically, for more than one discrete channel region 806. In one embodiment, each of the pair of non-discrete source or drain regions 810 / 812 is substantially rectangular in shape, having a bottom tapered portion and a top apex portion, as viewed from a cross-sectional perspective orthogonal to the length of the discrete channel region 806. Figure 8BHowever, in other embodiments, the source or drain regions 810 / 812 of the nanowires are relatively large but discrete non-vertically merged epitaxial structures, such as tiles.

[0143] According to the embodiments of the present disclosure, and as Fig. 8A and Figure 8B As shown, the integrated circuit structure 1100 also includes a pair of contacts 814, each contact 814 being located on one of the pair of non-discrete source or drain regions 810 / 812. In one such embodiment, each contact 814 completely surrounds the corresponding non-discrete source or drain region 810 / 812 in a vertical sense. On the other hand, the entire perimeter of the non-discrete source or drain region 810 / 812 may not be accessible for contact with the contact 814, and the contact 814 therefore only partially surrounds the non-discrete source or drain region 810 / 812, as shown in FIG. Figure 8B In a comparative embodiment not shown, the entire perimeter of the non-discrete source or drain region 810 / 812 is surrounded by the contact 814 as taken along the aa′ axis.

[0144] Reference again Fig. 8A In an embodiment, the integrated circuit structure 800 further includes a pair of spacers 816. As shown, outer portions of the pair of spacers 816 may overlap portions of the non-discrete source or drain regions 810 / 812, thereby providing an "embedded" portion of the non-discrete source or drain regions 810 / 812 under the pair of spacers 816. As also shown, the embedded portion of the non-discrete source or drain regions 810 / 812 may not extend under the entirety of the pair of spacers 816.

[0145] Substrate 802 may be made of a material suitable for integrated circuit structure fabrication. In one embodiment, substrate 802 includes a lower bulk substrate made of a single crystal material, which may include, but is not limited to, silicon, germanium, silicon-germanium, germanium-tin, silicon-germanium-tin, or a III-V compound semiconductor material. An upper insulator layer is located on the lower bulk substrate, and the upper insulator layer is made of a material that may include, but is not limited to, silicon dioxide, silicon nitride, or silicon oxynitride. Thus, structure 800 may be manufactured from a starting insulator-on-semiconductor substrate. Alternatively, structure 800 is formed directly from a bulk substrate, and local oxidation is used to form an electrically insulating portion to replace the upper insulator layer described above. In another alternative embodiment, structure 800 is formed directly from a bulk substrate, and electrically isolated active regions (e.g., nanowires) are formed thereon using doping. In one such embodiment, the first nanowire (i.e., close to the substrate) is in the form of an omega-FET type structure.

[0146] In an embodiment, nanowires 804 may be dimensioned as wires or ribbons (as described below), and may have square or rounded corners. In an embodiment, nanowires 804 are composed of materials such as, but not limited to, silicon, germanium, or a combination thereof. In one such embodiment, the nanowires are single crystalline. For example, for silicon nanowires 804, single crystalline nanowires may be based on a (100) global orientation, for example, having a square in the z direction. <100> Plane. Other orientations are also contemplated as described below. In an embodiment, the dimensions of nanowire 804 are nanometer-scale from a cross-sectional perspective. For example, in a specific embodiment, the smallest dimension of nanowire 804 is less than about 20 nanometers. In an embodiment, nanowire 804 is composed of strained material, particularly in channel region 806.

[0147] refer to Figure 8C , in an embodiment, each of the channel regions 806 has a width (Wc) and a height (Hc), the width (Wc) being approximately the same as the height (Hc). That is, in both cases, the cross-sectional profile of the channel regions 806 is square, or if rounded, the cross-sectional profile of the channel regions 806 is circular. On the other hand, the width and height of the channel regions need not be the same, for example, as is the case with nanoribbons as described throughout.

[0148] Reference again Fig. 8A , Figure 8B and Figure 8C In an embodiment, the lower portion of structure 800 may be planarized and / or etched to a horizontal plane 899 to leave a backside surface including an exposed bottom surface of the gate structure and the epitaxial source or drain structure. It should be understood that a backside (bottom) contact may be formed on the exposed bottom surface of the epitaxial source or drain structure.

[0149] In an embodiment, as described throughout, an integrated circuit structure includes a non-planar device, such as, but not limited to, a finFET or tri-gate structure having corresponding one or more overlying nanowire structures, and an isolation structure between the finFET or tri-gate structure and the corresponding one or more overlying nanowire structures. In some embodiments, the finFET or tri-gate structure is retained. In other embodiments, the finFET or tri-gate structure may be ultimately removed in a substrate removal process.

[0150] The embodiments disclosed herein can be used to manufacture various types of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, etc. In other embodiments, semiconductor memories can be manufactured. In addition, integrated circuits or other microelectronic devices can be used in various electronic devices known in the art. For example, in computer systems (e.g., desktop computers, laptops, servers), cellular phones, personal electronic devices, etc. The integrated circuit can be coupled to buses and other components in the system. For example, a processor can be coupled to a memory, a chipset, etc. via one or more buses. Each of the processor, memory, and chipset can potentially be manufactured using the methods disclosed herein.

[0151] Fig. 9 A computing device 900 is shown in accordance with one implementation of an embodiment of the present disclosure. The computing device 900 houses a board 902. The board 902 may include a plurality of components, including, but not limited to, a processor 904 and at least one communication chip 906. The processor 904 is physically and electrically coupled to the board 902. In some implementations, the at least one communication chip 906 is also physically and electrically coupled to the board 902. In further implementations, the communication chip 906 is part of the processor 904.

[0152] Depending on its application, the computing device 900 may include other components that may or may not be physically and electrically coupled to the board 902. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touch screen displays, touch screen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (e.g., hard drives, compact discs (CDs), digital versatile discs (DVDs), etc.).

[0153] The communication chip 906 is capable of wireless communication for data transmission to and from the computing device 900. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data via a non-solid medium using modulated electromagnetic radiation. The term does not imply that the associated device does not contain any wires, although in some embodiments, they may not contain wires. The communication chip 906 may implement any of a plurality of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher. The computing device 900 may include multiple communication chips 906. For example, the first communication chip 906 may be dedicated to short-range wireless communications, such as Wi-Fi and Bluetooth, while the second communication chip 906 may be dedicated to long-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO and others.

[0154] The processor 904 of the computing device 900 includes an integrated circuit die packaged within the processor 904. The integrated circuit die of the processor 904 may include one or more structures, such as integrated circuit structures constructed according to implementations of embodiments of the present disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be stored in registers and / or memory.

[0155] The communication chip 906 also includes an integrated circuit die packaged within the communication chip 906. The integrated circuit die of the communication chip 906 may include one or more structures, such as integrated circuit structures constructed according to implementations of embodiments of the present disclosure.

[0156] In further implementations, another component housed within computing device 900 may contain an integrated circuit die that includes one or more structures, such as integrated circuit structures constructed in accordance with implementations of embodiments of the present disclosure.

[0157] In various embodiments, computing device 900 may be a laptop, netbook, notebook, ultrabook, smartphone, tablet, personal digital assistant (PDA), ultra mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In further embodiments, computing device 900 may be any other electronic device that processes data.

[0158] Fig.10 An interposer 1000 including one or more embodiments of the present disclosure is shown. Interposer 1000 is an intermediate substrate for bridging a first substrate 1002 to a second substrate 1004. First substrate 1002 may be, for example, an integrated circuit die. Second substrate 1004 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Typically, the purpose of interposer 1000 is to extend connections to a wider pitch or to rewire connections to different connections. For example, interposer 1000 may couple an integrated circuit die to a ball grid array (BGA) 1006, which may then be coupled to a second substrate 1004. In some embodiments, first substrate 1002 and second substrate 1004 are attached to opposite sides of interposer 1000. In other embodiments, first substrate 1002 and second substrate 1004 are attached to the same side of interposer 1000. And in further embodiments, three or more substrates are interconnected through interposer 1000.

[0159] Interposer 1000 may be formed of epoxy, glass fiber reinforced epoxy, ceramic material, or polymer material such as polyimide. In further embodiments, interposer 1000 may be formed of alternative rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other III-V and IV materials.

[0160] The interposer 1000 may include metal interconnects 1008 and vias 1010, including but not limited to through silicon vias (TSVs) 1012. The interposer 1000 may also include embedded devices 1014, including both passive devices and active devices. Such devices include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1000. According to an embodiment of the present disclosure, the apparatus or process disclosed herein may be used in the manufacture of the interposer 1000 or in the manufacture of components included in the interposer 1000.

[0161] Thus, embodiments of the present disclosure include integrated circuit structures having a backside plug last approach.

[0162] The above description of the illustrated implementations of the embodiments of the present disclosure (including what is described in the Abstract) is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Although specific implementations and examples of the present disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure as will be appreciated by those skilled in the relevant art.

[0163] Based on the above detailed description, these modifications may be made to the present disclosure. The terms used in the appended claims should not be interpreted as limiting the present disclosure to the specific embodiments disclosed in the specification and claims. On the contrary, the scope of the present disclosure is determined entirely by the appended claims, which will be interpreted according to the established principles of claim interpretation.

[0164] The scope of the present disclosure includes any feature or combination of features disclosed herein (explicitly or implicitly), or any generalization thereof, whether or not it mitigates any or all of the problems addressed herein. Accordingly, new claims may be made during the examination of the present application (or an application claiming priority thereto) for any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with features of the independent claims, and features from corresponding independent claims may be combined in any appropriate manner, and not merely in the specific combinations listed in the appended claims.

[0165] The following examples relate to further embodiments. The various features of the different embodiments can be combined in different ways with some features included and other features not included to suit a variety of different applications.

[0166] Example embodiment 1: An integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate stack is located above the plurality of horizontally stacked nanowires. A conductive trench contact structure is located at a level below the plurality of horizontally stacked nanowires, the conductive trench contact structure having a sidewall tapered outward from a top of the conductive trench contact structure to a bottom of the conductive trench contact structure.

[0167] Example Embodiment 2: The integrated circuit structure according to Example Embodiment 1, further comprising a dielectric plug laterally adjacent to and in contact with one of the outwardly tapered sidewalls of the conductive trench contact structure.

[0168] Example Embodiment 3: The integrated circuit structure according to Example Embodiment 2, wherein the dielectric plug includes a plug liner and a plug filler.

[0169] Example Embodiment 4: The integrated circuit structure of Example Embodiment 3, wherein the plug liner is along a bottom surface of the plug filling.

[0170] Example embodiment 5: The integrated circuit structure according to example embodiment 3 or 4, wherein an uppermost surface of the plug liner and an uppermost surface of the plug filling are located at the same level.

[0171] Example embodiment 6: An integrated circuit structure includes a fin. A gate stack is located above the fin. A conductive trench contact structure is located at a level below the fin, the conductive trench contact structure having a sidewall tapered outward from a top of the conductive trench contact structure to a bottom of the conductive trench contact structure.

[0172] Example Embodiment 7: The integrated circuit structure of Example Embodiment 6, further comprising a dielectric plug laterally adjacent to and in contact with one of the outwardly tapered sidewalls of the conductive trench contact structure.

[0173] Example Embodiment 8: The integrated circuit structure according to Example Embodiment 7, wherein the dielectric plug includes a plug liner and a plug filler.

[0174] Example Embodiment 9: The integrated circuit structure of Example Embodiment 8, wherein the plug liner is along a bottom surface of the plug filling.

[0175] Example Embodiment 10: The integrated circuit structure according to Example Embodiment 8 or 9, wherein an uppermost surface of the plug liner and an uppermost surface of the plug filling are located at the same level.

[0176] Example embodiment 11: A computing device includes a board and a component coupled to the board. The component includes an integrated circuit structure, the integrated circuit structure including a plurality of horizontally stacked nanowires or fins. A gate stack is located above the plurality of horizontally stacked nanowires or fins. A conductive trench contact structure is located at a level below the plurality of horizontally stacked nanowires or fins, the conductive trench contact structure having a sidewall tapered outwardly from a top of the conductive trench contact structure to a bottom of the conductive trench contact structure.

[0177] Example Embodiment 12: The computing device according to Example Embodiment 11, comprising a plurality of laterally stacked nanowires.

[0178] Example Embodiment 13: The computing device according to Example Embodiment 11, comprising a fin.

[0179] Example Embodiment 14: The computing device of Example Embodiment 11, 12 or 13, further comprising a memory coupled to the board.

[0180] Example Embodiment 15: The computing device of Example Embodiment 11, 12, 13 or 14, further comprising a communication chip coupled to the board.

[0181] Example Embodiment 16: The computing device of Example Embodiment 11, 12, 13, 14 or 15, further comprising a battery coupled to the board.

[0182] Example Embodiment 17: The computing device of Example Embodiment 11, 12, 13, 14, 15 or 16, further comprising a camera coupled to the board.

[0183] Example Embodiment 18: The computing device of Example Embodiment 11, 12, 13, 14, 15, 16 or 17, further comprising a display coupled to the board.

[0184] Example Embodiment 19: The computing device of Example Embodiment 11, 12, 13, 14, 15, 16, 17 or 18, wherein the component is a packaged integrated circuit die.

[0185] Example Embodiment 20: The computing device of Example Embodiment 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the component is selected from the group consisting of a processor, a communication chip, and a digital signal processor.

Claims

1. An integrated circuit structure, comprising: multiple horizontally stacked nanowires; a gate stack disposed above the plurality of horizontally stacked nanowires; as well as A conductive trench contact structure is located at a horizontal plane below the plurality of horizontally stacked nanowires, the conductive trench contact structure having a sidewall tapered outward from a top of the conductive trench contact structure to a bottom of the conductive trench contact structure.

2. The integrated circuit structure of claim 1, further comprising a dielectric plug laterally adjacent to and in contact with one of the outwardly tapered sidewalls of the conductive trench structure.

3. The integrated circuit structure according to claim 2, wherein: The dielectric plug includes a plug liner and a plug filler.

4. The integrated circuit structure according to claim 3, wherein: The plug liner is along a bottom surface of the plug filler.

5. The integrated circuit structure according to claim 3 or 4, wherein: The uppermost surface of the plug liner is at the same level as the uppermost surface of the plug filler.

6. An integrated circuit structure comprising: fins; a gate stack, the gate stack being located on the fin; as well as A conductive trench contact structure is located at a level below the fin, the conductive trench contact structure having a sidewall tapered outward from a top of the conductive trench contact structure to a bottom of the conductive trench contact structure.

7. The integrated circuit structure of claim 6, further comprising a dielectric plug laterally adjacent to and in contact with one of the outwardly tapered sidewalls of the conductive trench structure.

8. The integrated circuit structure according to claim 7, wherein: The dielectric plug includes a plug liner and a plug filler.

9. The integrated circuit structure according to claim 8, wherein: The plug liner is along a bottom surface of the plug filler.

10. The integrated circuit structure according to claim 8 or 9, wherein: The uppermost surface of the plug liner is at the same level as the uppermost surface of the plug filler.

11. A computing device comprising: plate; as well as a component coupled to the board, the component comprising an integrated circuit structure, the integrated circuit structure comprising: multiple horizontally stacked nanowires or fins; a gate stack disposed on the plurality of horizontally stacked nanowires or the fins; and A conductive trench contact structure is located at a horizontal plane below the multiple horizontally stacked nanowires or the fins, and the conductive trench contact structure has a sidewall that tapers outward from the top of the conductive trench contact structure to the bottom of the conductive trench contact structure.

12. The computing device of claim 11, comprising the plurality of laterally stacked nanowires.

13. The computing device of claim 11, comprising the fin.

14. The computing device of claim 11, 12 or 13, further comprising: A memory is coupled to the board.

15. The computing device of claim 11, 12 or 13, further comprising: A communication chip is coupled to the board.

16. The computing device of claim 11, 12 or 13, further comprising: A battery coupled to the board.

17. The computing device of claim 11, 12 or 13, further comprising: A camera is coupled to the board.

18. The computing device of claim 11, 12 or 13, further comprising: A display is coupled to the panel.

19. The computing device of claim 11, 12 or 13, wherein: The component is a packaged integrated circuit die.

20. The computing device of claim 11, 12 or 13, wherein: The component is selected from the group consisting of a processor, a communication chip and a digital signal processor.

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