Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes: a first source / drain region; a second source / drain region; a channel structure connecting the first source / drain region to the second source / drain region; a gate structure surrounding the channel structure; a back contact structure under the first source / drain region, connected to the first source / drain region; and a first backside spacer at a lateral side of the backside contact structure.

Description

Technical Field

[0001] Apparatus and methods related to the present disclosure relate to a semiconductor device in which a backside contact structure is formed in a self-aligned manner. Background Art

[0002] Backside power distribution network (BSPDN) for semiconductor devices has been introduced to address the heavy traffic of signal lines at the front side of semiconductor devices. BSPDN includes connection structures formed at the back side of semiconductor devices. Here, the front side refers to the side where the transistor is formed relative to the top surface of the substrate, and the back side refers to the side opposite to the front side.

[0003] The BSPDN formed on the back side of the 3D stacked semiconductor device may include a back side metal line (such as a buried power rail) and a back side contact structure. The back side contact structure may be formed on the bottom surface of the lower source / drain region (epitaxial structure) of a field effect transistor (such as a nanosheet transistor or a fin field effect transistor (FinFET)), and the back side metal line may connect the back side contact structure to a voltage source or another circuit element for signal routing.

[0004] FinFET has one or more fin structures as the channel structure of the transistor. The fin structure protrudes vertically from the substrate and extends horizontally, and at least three of its surfaces are surrounded by a gate structure. The nanosheet transistor is characterized by one or more nanosheet channel layers as the channel structure of the transistor. The nanosheet channel layers are stacked vertically and extend horizontally based on the substrate, and all four surfaces of each nanosheet channel layer are surrounded by a gate structure. Nanosheet transistors are called gate all around (GAA) transistors or multi-bridge channel field effect transistors (MBCFETs).

[0005] As the contact polysilicon pitch (CPP) of semiconductor devices including multiple field effect transistors decreases to increase device density, it becomes more difficult and complicated to form a back contact structure in the back side of the semiconductor device. For example, due to at least substrate warping, etching variations, etc. that occur during thermal processing of the device, the back contact structure may not be accurately aligned and connected with the bottom surface of the source / drain region of the semiconductor device at a nanometer scale. In addition, when etching the substrate of the semiconductor device to form a hole or a recess in which the back contact structure is to be formed, the hole or the recess may have a tapered shape or a conical shape, which may cause the metal deposited from the back side of the semiconductor device during the back side process to be destroyed.

[0006] The information disclosed in this background technology section is known to the inventor or derived by the inventor before or during the process of implementing the embodiments of the present application, or is technical information acquired in the process of implementing the embodiments. Therefore, it may contain information that does not constitute prior art known to the public. Summary of the invention

[0007] The present disclosure provides a semiconductor device, wherein a lower source / drain region for a lower transistor under an upper transistor is formed in a backside process of forming a backside contact structure. The present disclosure also provides a method for manufacturing the semiconductor device.

[0008] According to an embodiment, a semiconductor device is provided, which may include: a first source / drain region; a second source / drain region; a channel structure connecting the first source / drain region to the second source / drain region; a gate structure surrounding the channel structure; a back contact structure, below the first source / drain region, connected to the first source / drain region; and a first back spacer at a lateral side of the back contact structure.

[0009] According to an embodiment, the semiconductor device may further include: an isolation stack below the gate structure, including at least one isolation layer and a substrate layer vertically stacked; and a backside isolation structure below the isolation stack.

[0010] According to an embodiment, the at least one isolation layer may include a plurality of vertically stacked isolation layers, and the substrate layer may be disposed between two adjacent isolation layers among the isolation layers.

[0011] According to an embodiment, the semiconductor device may also include: a first source / drain region; a second source / drain region; a channel structure connecting the first source / drain region to the second source / drain region; a gate structure surrounding the channel structure; a back contact structure, below the first source / drain region, connected to the first source / drain region; and an isolation stack, which is below the gate structure and includes multiple isolation layers and a substrate layer arranged between two adjacent isolation layers among the isolation layers.

[0012] According to an embodiment, the semiconductor device may further include: a first back spacer at a lateral side of the back contact structure; a placeholder structure, under the second source / drain region, connected to the second source / drain region; and a second back spacer at a lateral side of the placeholder structure.

[0013] According to an embodiment, a method for manufacturing a semiconductor device is provided. The method may include: forming an isolation stack including a plurality of isolation layers and a substrate layer between a substrate and a channel stack; etching the isolation stack to form a recess; forming a back spacer at a side surface of the recess; forming a placeholder structure in the recess based on the back spacer; forming a source / drain region on the placeholder structure based on the channel stack; and replacing the placeholder structure with a back contact structure based on the back spacer. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Example embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0015] Figure 1A shows a top view of a semiconductor device including a self-aligned backside contact structure according to an embodiment;

[0016] Figure 1B According to the embodiment Figure 1A A cross-sectional view of the semiconductor device along the line II' shown therein in the direction D1;

[0017] Figures 2A to 2P shows an intermediate semiconductor device obtained after respective steps of manufacturing a semiconductor device including a self-aligned contact structure according to an embodiment;

[0018] Figure 3 The description of the embodiment shows that the manufacturing method includes reference Figures 2A to 2P A flowchart of a method for providing a semiconductor device with a self-aligned contact structure; and

[0019] Figure 4 1 is a schematic block diagram showing an electronic device including one or more semiconductor devices according to an embodiment, wherein the one or more semiconductor devices include Figure 1A and Figure 1B The self-aligned back contact structure shown in . DETAILED DESCRIPTION

[0020] The embodiments of the present disclosure described herein are example embodiments, and therefore, the present disclosure is not limited thereto and may be implemented in various other forms. Each embodiment provided in the following description does not exclude association with one or more features of another example or another embodiment that is also provided herein or is not provided herein but is consistent with the present disclosure. For example, even if the content described in a specific example or embodiment is not described in different examples or embodiments, these contents may also be understood to be related to or combined with different examples or embodiments, unless otherwise mentioned in its description. In addition, it should be understood that all descriptions of the principles, aspects, examples and embodiments of the present disclosure are intended to cover their structural and functional equivalents. In addition, these equivalents should be understood to include not only currently known equivalents, but also equivalents to be developed in the future, that is, all devices invented to perform the same function, regardless of their structure. For example, the channel layer, sacrificial layer and isolation layer described herein may take different types or forms, as long as the present invention is applicable thereto.

[0021] It will be understood that when an element, component, layer, pattern, structure, region, etc. (hereinafter collectively referred to as an "element") of a semiconductor device is referred to as being "above" another element of the semiconductor device, "above" another element of the semiconductor device, "on" another element of the semiconductor device, "below" another element of the semiconductor device, "below" another element of the semiconductor device, "below" another element of the semiconductor device, "connected to" or "coupled to" another element of the semiconductor device, it may be directly above, over, on, below, below, below, connected to or coupled to the other element, or there may be intervening elements. Conversely, when an element of a semiconductor device is referred to as being "directly above" another element of the semiconductor device, "directly above" another element of the semiconductor device, "directly on" another element of the semiconductor device, "directly below" another element of the semiconductor device, "directly below" another element of the semiconductor device, "directly below" another element of the semiconductor device, "directly below" another element of the semiconductor device, "directly connected to" or "directly coupled to" another element of the semiconductor device, there are no intervening elements. Throughout this disclosure, the same reference numerals refer to the same elements.

[0022] For ease of description, spatially relative terms such as "above", "above", "on", "below", "below", "below", "below", "below", "below", "left", "right", "lower left", "lower right", "upper left", "upper right", "center", "middle", etc. may be used herein to describe the relationship of one element to another element as shown in the figure. It will be understood that in addition to the orientation depicted in the figure, the spatially relative terms are intended to cover different orientations of the semiconductor device in use or operation. For example, if the semiconductor device in the figure is flipped, the element described as "below" or "below" another element will be oriented to be "above" another element. Therefore, the term "below" can cover both the above and below orientations. The semiconductor device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein are interpreted accordingly. As another example, when the device or structure including the "left" element and the "right" element is oriented differently, the elements referred to as the "left" element and the "right" element can be the "right" element and the "left" element. Therefore, in the following description, the "left" element and the "right" element may also be referred to as the "first" element or the "second" element, respectively, as long as their structural relationship is clearly understood in the context of the description. Similarly, the terms "lower" element and "upper" element may be referred to as the "first" element and the "second" element, respectively, with the necessary description to distinguish the two elements.

[0023] It will be understood that although the terms "first," "second," "third," "fourth," "fifth," "sixth," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure.

[0024] As used herein, expressions such as "at least one of..." when following a list of elements modify the entire list of elements, rather than the individual elements in the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. In this document, when the term "same" or "equal" is used to compare the size of two or more elements, the term can cover "substantially the same" or "substantially equal" sizes. In addition, when the term "coplanar" or "aligned" is used to compare the positional relationship between two or more elements, the term can also cover the positional relationship of "substantially coplanar" or "substantially aligned."

[0025] It will also be understood that even if a step or operation of manufacturing a device or structure is described later than another step or operation, the step or operation may be performed earlier than the other step or operation unless the other step or operation is described as being performed before the step or operation.

[0026] Many embodiments are described herein with reference to cross-sectional views as schematic illustrations of embodiments (and intermediate structures). Therefore, changes in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are anticipated. Therefore, the embodiments should not be interpreted as being limited to the specific shapes of the regions shown herein, but rather include deviations in shape, for example, caused by manufacturing. The various regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the present disclosure. In addition, in the drawings, the sizes and relative sizes of the layers and regions may be exaggerated for clarity. Therefore, it should be understood that such schematic illustrations may not reflect actual images when any structure described herein is examined by a scanning electron microscope (SEM), a transmission electron microscope (TEM), a focused ion beam (FIB) microscope, or the like.

[0027] For the sake of brevity, conventional elements, structures or layers of semiconductor devices including nanosheet transistors and fin field effect transistors and the materials forming them may or may not be described in detail herein. For example, when a certain isolation layer or structure of a semiconductor device is irrelevant to the novel features of an embodiment, the layer or structure and the materials forming it may be omitted herein. In addition, when the materials forming the known structural elements of the semiconductor device are irrelevant to the novel features of an embodiment, the description of these materials may be omitted herein.

[0028] Figure 1A A top view of a semiconductor device including a self-aligned backside contact structure according to an embodiment is shown. Figure 1B According to the embodiment Figure 1A A cross-sectional view of the semiconductor device along the line II' shown therein in the direction D1.

[0029] It is to be understood here that the D1 direction is a channel length direction intersecting the D2 direction which is a channel width direction and the D3 direction which is a perpendicular direction.

[0030] Reference Figure 1A and Figure 1B , the semiconductor device 10 may include first to third semiconductor stacks 10A, 10B and 10C, each of which may include a plurality of channel layers 112 vertically stacked on the front surface of the semiconductor device 10 and surrounded by a gate structure 115. Each of the channel layers 112 may be referred to as a nanosheet or a nanobelt. Each of the semiconductor stacks 10A-10C may also include an isolation stack 100, which includes a pair of isolation layers 103 and a substrate layer 105 therebetween. A backside isolation structure 161 may be formed below the semiconductor stacks 10A-10C.

[0031] The channel layer 112 of each of the semiconductor stacks 10A-10C surrounded by the gate structure 115 can form a channel structure that connects the source / drain regions formed at both sides of the channel structure to each other to form a nanosheet field effect transistor. For example, a nanosheet field effect transistor can be formed by a channel structure including the channel layer 112, a gate structure 115 surrounding the channel structure, and a first source / drain region 130L and a second source / drain region 130R connected to each other through the channel structure.

[0032] The one or more materials forming the channel layer 112 may include, for example, silicon (Si), silicon germanium (SiGe). The gate structure 115 may be formed of one or more materials, including, for example, copper (Cu), aluminum (Al), cobalt (Co), tungsten (W), titanium (Ti), tantalum (Ta), or a combination thereof. Each of the source / drain regions 130L and 130R may include one or more materials, such as silicon (Si), silicon germanium (SiGe) doped with impurities. The source / drain regions 130L and 130R may be p-type or n-type.

[0033] Each of the semiconductor stacks 10A-10C may further include an inner spacer 131 formed at a side surface of a lower portion of the gate structure 115 and a gate spacer 116 formed at a side surface of an upper portion of the gate structure 115. The inner spacer 131 may isolate the gate structure 115 from the source / drain regions 130L and 130R, and the gate spacer 116 may isolate the gate structure 115 from the source / drain regions 130L and 130R and another front isolation structure 162. The one or more materials forming the inner spacer 131 and the gate spacer 116 may include, for example, silicon oxide (e.g., SiO 2 ) or silicon nitride (Si 3 N 4 The front isolation structure 162 may be made of, for example, silicon oxide (eg, SiO or SiO 2 )form.

[0034] The semiconductor device 10 may further include a plurality of contact structures, including a front contact structure 170, a gate contact structure 180, and a back contact structure 150. The front contact structure 170 may be formed on the top surface of the first source / drain region 130L to connect the source / drain region to a voltage source or another semiconductor device. The gate contact structure 180 may be formed on the top surface of the gate structure 115 to receive a gate input signal for the gate structure 115. The front contact structure 170 and the gate contact structure 180 may be isolated from each other by the front isolation structure 162. The back contact structure 150 may be formed on the bottom surface of the second source / drain region 130R to connect the source / drain region to a voltage source or another semiconductor device. These contact structures 170, 180, and 150 may each be formed of one or more materials such as copper (Cu), aluminum (Al), tungsten (W), ruthenium (Ru), molybdenum (Mo), etc.

[0035] The semiconductor device 10 may be characterized by an isolation stack 100 formed at a lower portion of each of the semiconductor stacks 10A-10C. The isolation stack 100 may include two isolation layers 103 and a substrate layer 105 disposed therebetween.

[0036] The uppermost isolation layer among the isolation layers 103 may be formed under the lowermost portion of the gate structure 115 and the lowermost inner spacer among the inner spacers 131. The uppermost isolation layer 103 may suppress current leakage from the gate structure 115 above it. The isolation layer 103 with the substrate layer 105 therebetween may also structurally support each of the semiconductor stacks 10A to 10C. The substrate layer 105 may be formed of silicon (Si), but is not limited thereto. The isolation layer 103 may be made of a material such as silicon oxide (e.g., SiO 2 ) materials, but not limited thereto.

[0037] Figure 1B The isolation stack 100 is shown to include two vertically stacked isolation layers 103 and a substrate layer 105 disposed therebetween. When the substrate layer 105 is disposed between the two isolation layers 103, the isolation stack 100 can be structurally strengthened to more stably support each of the semiconductor stacks 10A to 10C. In addition, the number of isolation layers 103 and substrate layers 105 can be controlled so that the entire thickness of the isolation stack 100 corresponds to or is equal to the thickness of the back contact structure 150 in the D3 direction. For example, the isolation stack 100 may include more than two isolation layers and more than one substrate layer disposed between each two vertically adjacent isolation layers. As another example, the isolation stack 100 may include only one isolation layer and only one substrate layer having a thickness corresponding to the thickness of the two isolation layers 103 and the substrate layer 105 therebetween. However, the isolation layer 103 can still be formed as the top layer of the isolation stack 100 to prevent current leakage from the gate structure 115 above it.

[0038] The semiconductor device 10 may also be characterized by a back spacer 151 formed at a lateral side of the isolation stack 100. Since the isolation stack 100 includes two isolation layers 103 and a substrate layer 105 vertically stacked on a back isolation structure 161, the back spacer 151 may contact side surfaces of the isolation layers 103 and the substrate layer 105. In addition, the back spacer 151 may be formed such that its top surface is horizontally aligned or coplanar with the top surface of the back contact structure 150, the top surface of the uppermost isolation layer 103, and the bottom surface of the lowermost inner spacer 131 and the gate structure 115.

[0039] When manufacturing the semiconductor device 10, the back side spacer 151 can be used to form a back side contact structure 150 in a self-aligned manner, which will be further described later. The back side contact structure 150 can be formed between the back side spacers 151 formed at the side surfaces of two adjacent isolation stacks 100, and connected to the back side metal line 155 formed thereunder in the back side isolation structure 161. Because the back side contact structure 150 is accurately self-aligned under each of the source / drain regions 130L and 130R due to the back side spacer 151, the semiconductor device 10 can have improved back side contact performance.

[0040] The back spacer 151 may be formed of one or more materials including silicon nitride (e.g., SiN, SiBCN, SiOCN, SiOC, etc.). The back spacer 151, the inner spacer 131, and the gate spacer 116 may be the same or different material compositions from each other. The back metal line 155 may be formed of one or more materials such as copper (Cu), aluminum (Al), tungsten (W), ruthenium (Ru), molybdenum (Mo), etc., which may be the same or different from the materials forming the contact structures 150, 170, and 180. The back isolation structure 161 may be formed of the same material as the front isolation structure 162.

[0041] Meanwhile, the semiconductor device 10 may include a placeholder structure 140 formed below the first source / drain region 130L. Similar to the back contact structure 150, the placeholder structure 140 may be formed laterally between the back spacers 151. The placeholder structure 140 may have been formed to provide a space for forming another back contact structure during the manufacturing process of the semiconductor device 10. Therefore, the back contact structure 150 formed below the second source / drain region 130R may be formed by replacing the placeholder structure formed below the second source / drain region. However, since the front contact structure 170 is formed on the first source / drain region 130L to connect the first source / drain region 130L to a voltage source or another circuit element, the placeholder structure 140 below the first source / drain region 130L may remain there without being replaced by another back contact structure. The placeholder structure 140 may be made of a material including silicon germanium (SiGe) or silicon oxide (e.g., SiO, SiO 2 etc.), but is not limited thereto.

[0042] When the placeholder structure 140 is replaced by the back contact structure 150, the two structures may have the same structural shape. Therefore, the top surface of the placeholder structure 140 may be horizontally aligned or coplanar with the top surface of the back spacer 151 formed at the side of the placeholder structure 140, the top surface of the uppermost isolation layer 103, and the bottom surfaces of the lowermost inner spacer 131 and the gate structure 115.

[0043] In the present embodiment, the isolation stack 100 including the isolation layer 103 and the substrate layer 105 may have the same thickness as the placeholder structure 140 and the back contact structure 150 and the back spacer 151 in the D3 direction.

[0044] In the above embodiment, Figure 1A and Figure 1B The semiconductor device 10 is shown to include only three semiconductor stacks 10A-10C, one back contact structure 150 having back spacers 151 at two opposite side surfaces thereof, and one placeholder structure having back spacers 151 at two opposite side surfaces thereof. However, the present disclosure is not limited thereto. According to an embodiment, the semiconductor device 10 may include more than three semiconductor stacks to form more nanosheet field effect transistors, and more than one back contact structure and one placeholder structure may be formed to connect to the bottom surface of the corresponding source / drain region of the nanosheet field effect transistor. In addition, according to an embodiment, at least one of the nanosheet field effect transistors may include only one of the back contact structure 150 and the placeholder structure 140, which is formed on the bottom surface of the source / drain region and has a back spacer 151 on its side surface.

[0045] Hereinafter, a method of manufacturing the semiconductor device 10 including the self-aligned back side contact structure 150 will be described.

[0046] Figures 2A to 2P FIG. 1 shows an intermediate semiconductor device obtained after the respective steps of manufacturing a semiconductor device including a self-aligned contact structure according to an embodiment. Figure 1A and Figure 1B The semiconductor device 10 shown in FIG. 1 is the same as or corresponds to the semiconductor device 10 shown in FIG. 1 , and thus a repeated description thereof may be omitted, and the same reference numerals may be used in the following description.

[0047] Reference Figure 2A , the intermediate semiconductor device 10 ′ may include a substrate 101 , on which a preliminary isolation stack 100 ′, a preliminary channel stack 110 ′, a dummy gate structure 115 ′, and three hard mask patterns 160 are formed in this order.

[0048] The preliminary isolation stack 100' and the preliminary channel stack 110' may include a plurality of nanosheet layers epitaxially grown and stacked on the substrate 101 in the following order: a first sacrificial layer 102, a substrate layer 105, a first sacrificial layer 102, a second sacrificial layer 111, a channel layer 112, a second sacrificial layer 111, a channel layer 112, a second sacrificial layer 111, and a channel layer 112. However, unlike Figure 2ADifferently, according to an embodiment, the preliminary isolation stack 100' may include more than two first sacrificial layers 102, and the substrate layer 105 may be disposed between every two vertically adjacent first sacrificial layers 102. Figure 2A Differently, the preliminary channel stack 110 ′ may include more or less than three second sacrificial layers 111 and three channel layers 112 alternately stacked on the uppermost first sacrificial layer 102 .

[0049] The first sacrificial layer 102 and the second sacrificial layer 111 may each be formed of silicon germanium (SiGe). However, the first sacrificial layer 102 may have a higher germanium concentration (e.g., 55%) than in the second sacrificial layer 111, so that the first sacrificial layer 102 may be selectively etched relative to the second sacrificial layer 111 in the next step. The channel layer 112 may include silicon (Si) or SiGe having a lower germanium concentration than in the second sacrificial layer 111, so that when the second sacrificial layer 111 and the dummy gate structure 115' are replaced by the gate structure to form a channel layer 112, the channel layer 112 may be selectively etched relative to the second sacrificial layer 111. Figure 1A and Figure 1B When the semiconductor device of the present invention is an intermediate semiconductor device of the semiconductor device, the channel layer 112 can withstand the selective etching of the second sacrificial layer 111 in a later step.

[0050] The dummy gate structure 115' may be formed on the uppermost channel layer 112 and planarized by, for example, chemical mechanical polishing (CMP), but is not limited thereto. The hard mask pattern 160 may be formed in a later step. Figure 1A and Figure 1B The gate structure of each of the first to third semiconductor stacks 10A-10C shown in FIG. 1 is formed on a dummy gate structure 115' at a location to be formed. The dummy gate structure may be formed of a material such as polysilicon or amorphous silicon, and the hard mask pattern 160 may be formed of a material such as silicon nitride (e.g., SiN, Si 3 N 4 , SiBCN, SiNC, SiNOC, etc.) materials.

[0051] Reference Figure 2B , the dummy gate structure 115 ′ may be patterned based on the hard mask pattern 160 to form three dummy gate structures 115 ′, and the first sacrificial layer 102 may be removed from the preliminary isolation stack 100 ′.

[0052] The formation of the three dummy gate structures 115′ may be performed, for example, by dry etching (such as reactive ion etching (RIE)) based on the hard mask pattern 160. The first sacrificial layer 102 may be formed by dry etching (such as reactive ion etching (RIE)) or using hydrofluoric acid (HF) and / or nitric acid (HNO 3) is removed by wet etching (which can selectively etch the first sacrificial layer 102 having a high germanium concentration relative to the channel layer 112 and the second sacrificial layer 111 having a low germanium concentration).

[0053] When the dummy gate structure 115' is formed based on the hard mask pattern 160, the top surface of the preliminary channel stack 110' (e.g., the top surface of the uppermost channel layer 112) may be exposed through the first recess R1 and the second recess R2. In addition, a gap or space may be formed by removing the first sacrificial layer 102 between the substrate 101 and the substrate layer 105 and between the substrate layer 105 and the lowermost second sacrificial layer 111.

[0054] Reference Figure 2C , a gate spacer 116 may be formed on a side surface of each dummy gate structure 115' having the hard mask pattern 160 thereon, and an isolation layer 103 may be formed in a gap or space formed by removing the first sacrificial layer 102. The substrate 101 and the substrate layer 105 may have the same material composition.

[0055] When the isolation layer 103 fills in the voids of the space where the first sacrificial layer 102 was formed, the isolation layer 103 together with the substrate layer 105 now forms a preliminary isolation stack 100 ′.

[0056] The formation of the gate spacer 116 and the isolation layer 103 may be performed by, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), physical vapor deposition (PVD), or a combination thereof, but is not limited thereto.

[0057] Although not shown in the figures, a material such as silicon nitride forming the gate spacer 116 may be deposited on the entire intermediate semiconductor device 10' obtained in the previous step and etched back to leave the gate spacer material only on the side surface of each dummy gate structure 115' having the hard mask pattern 160 thereon.

[0058] The isolation layer 103 may be made of silicon oxide (eg, SiO 2 ) or silicon nitride (e.g., Si 3 N 4 ) to prevent or inhibit current leakage from at least a gate structure to be formed thereover in a later step.

[0059] Reference Figure 2D The preliminary channel stack 110 ′ may be etched downward through the recesses R1 and R2 based on the hard mask pattern 160 and the gate spacer 116 (see Figure 2A ) to form three trench stacks 110 exposing the top surface of the preliminary isolation stack 100' therebetween.

[0060] By etching back the preliminary channel stack 110', the recesses R1 and R2 may extend downward to expose the top surface of the uppermost isolation layer 103. The etching back operation may be performed by, for example, dry etching, but is not limited thereto.

[0061] Reference Figure 2E The preliminary isolation stack 100 ′ may be etched downward through the recesses R1 and R2 based on the hard mask pattern 160 and the gate spacers 116 to form three isolation stacks 100 on the substrate 101 .

[0062] The preliminary isolation stack 100' can be etched to form three isolation stacks 100 and further extend the recesses R1 and R2 downward to provide space for forming a back contact structure in a later step. In addition, the three isolation stacks 100 patterned from the preliminary isolation stack 100' together with the three channel stacks 110 now form the first to third intermediate semiconductor stacks 10A'-10C'.

[0063] As previously described in the background technology section, a semiconductor device of the related art may provide a back side contact structure that is filled in a hole or a recess obtained by etching a substrate formed of silicon, and thus, the hole or the recess may have a conical shape or a conical shape, which may disrupt the formation (deposition) of metal therein.

[0064] However, as previously referenced Figure 1A and Figure 1B As described above, the isolation layer 103 of the isolation stack 100 may be made of silicon oxide (eg, SiO 2 ), which silicon oxide has a higher etching rate than silicon. Therefore, when etching the preliminary isolation stack 100' including the isolation layer 103 to form a hole or a recess in which a back contact structure is to be formed, the hole or the recess may have, for example, a substantially cylindrical shape to better facilitate the deposition of metal therein to form a back contact structure. Therefore, the lower portions of the extended recesses R1 and R2 formed by etching the preliminary isolation stack 100' may provide a constant width in the vertical direction. For example, the top width W1 of the lower portion of the recess R1 measured between the uppermost isolation layers 103 and the bottom width W2 of the lower portion of the recess R1 measured between the lowermost isolation layers 103 may be equal to each other.

[0065] Reference Figure 2F , a side portion of each of the second sacrificial layers 111 in each of the intermediate semiconductor stacks 10A′- 10C′ may be recessed or etched to provide a space for forming an inner spacer 131 therein in the next step.

[0066] The etching operation in this step may be performed by, for example, selective wet etching or dry etching, but is not limited thereto, to remove only silicon germanium included in the second sacrificial layer 111 relative to silicon included in the channel layer 112, the substrate layer 105, and silicon oxide included in the isolation layer 103. For example, hydrofluoric acid (HF) and nitric acid (HNO 3 ) can be used for selective etching.

[0067] Reference Figure 2G , an inner spacer 131 may be formed at a side surface of the recessed second sacrificial layer 111 , and a back side spacer 151 may be formed on the intermediate semiconductor device 10 ′ obtained in the previous step to surround each of the intermediate semiconductor stacks 10A′- 10C′ on the substrate 101 .

[0068] Each inner spacer 131 may be formed such that an outer side surface opposite to the inner side surface of the second sacrificial layer 111 contacting the recess is vertically aligned or coplanar with the side surfaces of the channel layer 112 and the isolation stack 100. The back spacer 151 may be conformally formed on the outer surface of each of the intermediate semiconductor stacks 10A'-10C' including the side surface of each of the isolation stacks 100. The formation of the inner spacer 131 and the back spacer 151 may be performed by, for example, atomic layer deposition (ALD) or any other suitable deposition process or electroplating.

[0069] Although not shown in the figures, the material forming the back spacer 151 (e.g., silicon nitride (e.g., SiN, SiBCN, SiOCN, SiOC, etc.)) can be deposited on the entire intermediate semiconductor device 10' obtained in the previous step and etched back to divide the back spacer 151 into three back spacers that respectively surround the intermediate semiconductor stack 10A'-10C'.

[0070] Forming the back spacer 151 in this manner can expose the top surface of the substrate 101 through the recesses R1 and R2. In addition, the back spacer 151 formed on the right side surface of the first intermediate semiconductor stack 10A' can face the back spacer 151 formed on the left side surface of the second intermediate semiconductor stack 10B' with the recess R1 therebetween, and the back spacer 151 formed on the right side surface of the second intermediate semiconductor stack 10B' can face the back spacer 151 formed on the left side surface of the third intermediate semiconductor stack 10C' with the recess R2 therebetween.

[0071] Reference Figure 2H , a placeholder structure 140 may be formed in a lower portion of each of the recesses R1 and R2 between back-side spacers 151 formed at side surfaces of the isolation stack 100 .

[0072] The placeholder structure 140 may be formed to have the same thickness as the isolation stack 100 in the D3 direction. The placeholder structure 140 may include a material such as silicon germanium (SiGe) or silicon oxide (eg, SiO, SiO 2 The formation of the placeholder structure 140 in the lower portion of each of the recesses R1 and R2 may be performed by, for example, CVD, PVD, PECVD, ALD, or a combination thereof, but is not limited thereto.

[0073] Although not shown in the drawings, a material such as silicon germanium or silicon oxide forming the placeholder structure 140 may be deposited on the entire intermediate semiconductor device 10′ obtained in the previous step to fill the recesses R1 and R2, and etched back so that the top surface of the placeholder structure 140 may be horizontally aligned or coplanar with the bottom surface of the lowermost second sacrificial layer 111 and the top surface of the uppermost isolation layer 103.

[0074] Reference Fig.2I , the back spacer 151 may be etched back, and a source / drain region including a first source / drain region 130L and a second source / drain region 130R may be formed based on the channel layer 112 .

[0075] The back side spacers 151 may be etched back so that the thickness of each back side spacer 151 may be the same as the thickness of the placeholder structure 140 and the isolation stack 100 .

[0076] The etch-back of the back spacer 151 may be performed by, for example, dry etching, but is not limited thereto, such that the top surface thereof is horizontally aligned or coplanar with the top surface of the placeholder structure 140 .

[0077] Source / drain regions including the first source / drain region 130L and the second source / drain region 130R may be epitaxially grown from the channel layer 112 on or over the top surfaces of the placeholder structure 140 and the back spacer 151 .

[0078] Reference Figure 2J The hard mask pattern 160 may be removed from each of the intermediate semiconductor stacks 10A′- 10C′, and a front isolation structure 162 may be formed at the front of the intermediate semiconductor device 10 ′ to surround the intermediate semiconductor stacks 10A′- 10C′.

[0079] Removal of the hard mask pattern 160 may be performed by, for example, plasma ashing, stripping, etc. Furthermore, the gate spacers 116 may be etched back so that top surfaces thereof may be horizontally aligned or coplanar with top surfaces of the dummy gate structures 115 ′ in each of the intermediate semiconductor stacks 10A′- 10C′.

[0080] The front isolation structure 162 may be formed by, for example, CVD, PVD, PECVD, ALD, or a combination thereof, but is not limited thereto, and planarized by, for example, a CMP operation.

[0081] Reference Figure 2K The dummy gate structure 115 ′ and the second sacrificial layer 111 may be replaced by the gate structure 115 , and a front contact structure 170 and a gate contact structure 180 may be formed to contact the first source / drain region 130L and the gate structure 115 , respectively.

[0082] The dummy gate structure 115' and the second sacrificial layer 111 can be removed by, for example, wet etching and / or dry etching to leave gaps or spaces in each of the intermediate semiconductor stacks 10A'-10C', and the gate structure 115 can be formed in these gaps or spaces by, for example, CVD, PVD, PECVD, ALD or a combination thereof (but not limited to these).

[0083] The formation of the front contact structure 170 and the gate contact structure 180 may be performed by similar deposition processes after the photolithography / masking / etching operations on the front isolation structure 162 .

[0084] Reference Figure 2L , the intermediate semiconductor device 10 ′ obtained in the previous step may be turned upside down, and the substrate 101 may be removed and replaced by a back side isolation structure 161 , which is patterned to expose the placeholder structure 140 and the back side spacer 151 formed under the second source / drain region 130R.

[0085] Although not shown in the drawings, a carrier substrate may be formed on the top surface of the intermediate semiconductor device 10 ′ obtained in the previous step before the intermediate semiconductor device 10 ′ is turned upside down for a backside process.

[0086] The substrate 101 may be removed by, for example, dry etching, wet etching, ashing, and / or stripping, and the back side isolation structure 161 may be formed by, for example, PVD, CVD, PECVD, etc. (but not limited thereto), and then planarized.

[0087] In addition, the back isolation structure 161 may be patterned by, for example, photolithography / masking / etching to expose the bottom surfaces of the placeholder structure 140 and the back spacer 151 on which subsequent back processes will be performed in the next step. Figure 2J The bottom surfaces of the middle placeholder structure 140 and the back side spacers 151 are shown as their top surfaces because the intermediate semiconductor device 10 ′ has been inverted for back side processing.

[0088] Reference Figure 2M, the placeholder structure 140 formed on the bottom surface of the second source / drain region 130R between the back spacers 151 may be removed by selective etching with respect to the back spacers 151 .

[0089] The selective etching of the placeholder structure 140 including, for example, silicon germanium or silicon oxide relative to the back side spacer 151 including, for example, silicon nitride may be performed using, for example, hot phosphoric acid (H 3 PO 4 ) or potassium hydroxide (KOH) etchant wet etching and / or dry etching, but not limited thereto.

[0090] Reference Figure 2N , a back contact structure 150 may be formed in a self-aligned manner in a void or space from which the placeholder structure 140 has been removed in a previous step based on the back spacers 151 .

[0091] As previously discussed, metals such as copper (Cu), aluminum (Al), tungsten (W), ruthenium (Ru), molybdenum (Mo), etc. may be deposited in the void or space by, for example, CVD, PVD, PECVD, or a combination thereof, but are not limited thereto. Due to the backside spacers 151 formed on both sides of the void or space left by removing the placeholder structure 140, the metal deposited in the void or space may contact the bottom surface ( Figure 2M The top surface in the self-alignment.

[0092] Since the back contact structure 150 is formed by filling the void or space left by removing the placeholder structure 140, the back contact structure 150 may have the same shape as the placeholder structure 140. For example, the thickness of the back contact structure 150 may be the same as the thickness of the placeholder structure 140 in the D3 direction.

[0093] Reference Fig.2O , a back side metal line 155 may be formed to connect to the back side contact structure 150 to complete the BSPDN of the intermediate semiconductor device 10 ′.

[0094] A metal similar to that forming the back contact structure 150 may be deposited by, for example, CVD, PVD, PECVD, or a combination thereof to form a back metal line 155 that connects the second source / drain region 130R to a voltage source or another circuit element for internal routing purposes.

[0095] Reference Figure 2P , the intermediate semiconductor device 10 ′ obtained in the previous step may be turned upside down again to at least partially complete the manufacturing operation of the semiconductor device 10 .

[0096] The above embodiments for manufacturing a semiconductor device including a plurality of nanosheet field effect transistors have been described. However, the present disclosure may not be limited thereto but may also be applied to semiconductor devices including different types of field effect transistors such as FinFETs.

[0097] Figure 3 The description according to the embodiment is shown with reference to Figures 2A to 2P A flow chart of a method of manufacturing a semiconductor device including a self-aligned contact structure.

[0098] In step S10, a preliminary isolation stack including two or more vertically stacked isolation layers and a substrate layer therebetween may be formed between the substrate thereunder and the plurality of channel stacks thereover to form an intermediate semiconductor device. FIG. 2A to FIG. 2C .

[0099] The isolation layer may be formed of a material including silicon oxide, which may be easier to etch than silicon. The number of isolation layers and the vertical thickness of the isolation stack may be controlled to correspond to or be the same as the vertical thickness of a back contact structure to be formed in a later step.

[0100] In step S20, the preliminary isolation stack may be etched downward between the channel stacks to form a plurality of isolation stacks respectively below the channel stacks and recesses in which corresponding placeholder structures for backside contact structures are to be formed. Figures 2D to 2F .

[0101] Since the preliminary isolation stack includes an isolation layer formed of easily etched silicon oxide, holes or recesses having a profile that is easily deposited for the metal for the back contact structure can be etched.

[0102] In step S30, back side spacers may be formed on the side surfaces of the recess for the placeholder structure, which will facilitate the self-aligned formation of the back side contact structure in a later step. Figure 2G .

[0103] The back side spacer may be formed to contact the side surface of each of the isolation stacks. The back side spacer may be formed of a material such as silicon nitride.

[0104] In step S40, a placeholder structure may be formed in the recess between the backside spacers. Figure 2H .

[0105] The placeholder structure may be formed of a material such as silicon germanium or silicon oxide.

[0106] In step S50, source / drain regions may be formed from the channel stack at the sides of the channel stack on or over the placeholder structure and the back spacer, and a gate structure may be formed to surround the channel stack. Figures 2I to 2K .

[0107] The source / drain regions may be formed such that the placeholder structures contact bottom surfaces of the source / drain regions, respectively, and a gate structure may be formed by replacing the dummy gate structure and the second sacrificial layer included in each channel stack.

[0108] In step S60, the substrate may be removed and replaced by a backside isolation structure, and the backside isolation structure may be patterned to expose at least one of a placeholder structure and a backside spacer thereon. Figure 2L .

[0109] The removal of the substrate and the formation of the back side isolation structure may be performed after inverting the intermediate semiconductor device obtained in the previous step so that the bottom surface of the substrate points upward in the D3 direction.

[0110] The placeholder structure including silicon germanium or silicon oxide may be selectively etched relative to the backside spacer including silicon nitride.

[0111] In step S70, the placeholder structure may be removed and replaced by a back contact structure in a self-aligned manner based on the back spacers. Figure 2M to Figure 2N .

[0112] Due to the back side spacers, the back side contact structure can be precisely aligned with the bottom surface of the source / drain regions.

[0113] In step S80, a back side metal line may be formed in the back side isolation structure to contact the back side contact structure to at least partially complete the BSPDN of the semiconductor device. Figure 2O to Figure 2P .

[0114] Figure 4 It is shown that according to the embodiment, Figure 1A and Figure 1B Schematic block diagram of an electronic device including one or more semiconductor devices shown in , the one or more semiconductor devices including a self-aligned back side contact structure.

[0115] Reference Figure 4 , the electronic device 4000 may include at least one application processor 4100, a communication module 4200, a display / touch module 4300, a storage device 4400, and a buffer RAM 4500. According to an embodiment, the electronic device 4000 may be a mobile device such as a smart phone or a tablet computer, but is not limited thereto.

[0116] The application processor 4100 may control the operation of the electronic device 4000. The communication module 4200 is implemented to perform wireless or wired communication with an external device. The display / touch module 4300 is implemented to display data processed by the application processor 4100 and / or receive data through a touch panel. The storage device 4400 is implemented to store user data. The storage device 4400 may be an embedded multimedia card (eMMC), a solid state drive (SSD), a universal flash storage (UFS) device, etc. The storage device 4400 may perform a cache of user data and mapping data as described above.

[0117] The buffer RAM 4500 may temporarily store data used for processing operations of the electronic device 4000. For example, the buffer RAM 4500 may be a volatile memory such as a double data rate (DDR) synchronous dynamic random access memory (SDRAM), a low power double data rate (LPDDR) SDRAM, a graphics double data rate (GDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), etc.

[0118] At least one component in the electronic device 4000 may include: Figure 1A and Figure 1B One or more semiconductor devices including a self-aligned back side contact structure are shown in FIG.

[0119] The foregoing is a description of exemplary embodiments and should not be construed as limiting the present disclosure. Although several exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the above-described embodiments without materially departing from the present disclosure.

Claims

1. A semiconductor device, comprising: a first source / drain region; a second source / drain region; a channel structure connecting the first source / drain region to the second source / drain region; a gate structure surrounding the channel structure; a back contact structure, below the first source / drain region and connected to the first source / drain region; as well as First back side spacers at lateral sides of the back side contact structure.

2. The semiconductor device according to claim 1, further comprising: an isolation stack, below the gate structure, comprising at least one isolation layer and a substrate layer stacked vertically; as well as A backside isolation structure underlying the isolation stack. 3 . The semiconductor device according to claim 2 , wherein the at least one isolation layer comprises a plurality of vertically stacked isolation layers, and the substrate layer is disposed between two adjacent isolation layers among the isolation layers.

4. The semiconductor device according to claim 3, further comprising: A placeholder structure is below the second source / drain region and connected to the second source / drain region.

5. The semiconductor device according to claim 4, further comprising: A second back spacer at a lateral side of the placeholder structure. 6 . The semiconductor device according to claim 5 , further comprising a front contact structure on the second source / drain region.

7. The semiconductor device according to claim 1, further comprising: a placeholder structure, below the second source / drain region and connected to the second source / drain region; as well as A second back spacer at a lateral side of the placeholder structure.

8. The semiconductor device according to claim 1, further comprising: A back side metal line, beneath the back side contact structure, is connected to the back side contact structure. 9 . The semiconductor device of claim 1 , wherein the back side contact structure and the first back side spacer have the same vertical thickness.

10. The semiconductor device according to claim 1, further comprising: an isolation stack, below the gate structure, comprising at least one isolation layer, Wherein the isolation stack and the back contact structure have the same vertical thickness. The semiconductor device according to claim 10 , wherein the isolation stack comprises two or more isolation layers and a substrate layer.

12. A semiconductor device comprising: a first source / drain region; a second source / drain region; a channel structure connecting the first source / drain region to the second source / drain region; a gate structure surrounding the channel structure; a back contact structure, below the first source / drain region and connected to the first source / drain region; as well as The isolation stack, below the gate structure, includes a plurality of isolation layers and a substrate layer disposed between two adjacent isolation layers among the isolation layers.

13. The semiconductor device according to claim 12, further comprising: First back side spacers at lateral sides of the back side contact structure.

14. The semiconductor device according to claim 13, further comprising: a placeholder structure, below the second source / drain region and connected to the second source / drain region; as well as A second back spacer at a lateral side of the placeholder structure. 15 . The semiconductor device of claim 12 , wherein the isolation stack and the backside contact structure have the same vertical thickness.

16. The semiconductor device according to claim 12, further comprising: a substrate beneath the isolation stack, wherein one of the isolation layers of the isolation stack is disposed between the substrate and the substrate layer, and The substrate and the substrate layer have the same material composition.

17. A method for manufacturing a semiconductor device, the method comprising the following operations: forming an isolation stack between the substrate and the channel stack, the isolation stack comprising a plurality of isolation layers and a substrate layer; etching the isolation stack to form a recess; forming a back spacer at a side surface of the recess; forming a placeholder structure in the recess based on the back spacer; forming a source / drain region on the placeholder structure based on the channel stack; as well as The placeholder structure is replaced by a back side contact structure based on the back side spacer.

18. The method of claim 17, wherein the back side spacer and the isolation stack have the same vertical thickness. 19 . The method according to claim 18 , wherein an isolation layer among the isolation layers is disposed between the substrate and the substrate layer.

20. The method of claim 19, wherein the placeholder structure, the back contact structure, and the isolation stack have the same vertical thickness.

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