Epitaxial structure in image sensor

Abstract

The invention relates to an epitaxial structure in an image sensor. The invention discloses a semiconductor device having an image sensor and a method of manufacturing the same. The semiconductor device includes a substrate, a pixel region having a pixel structure, an isolation region having an isolation structure adjacent to the pixel region, and a contact pad region having a pad structure adjacent to the isolation region. The pixel structure includes an epitaxial structure including an embedded portion having a stepped structure disposed in the substrate and a protruding portion extending above a top surface of the substrate. The pixel structure further includes a capping layer disposed on the protruding portion.

Description

Technical Field

[0001] The present disclosure relates to epitaxial structures in image sensors. Background Art

[0002] Image sensors are used to sense incoming visible or invisible light radiation, such as visible light and infrared light. Complementary metal oxide semiconductor (CMOS) image sensors (CIS) and charge coupled device (CCD) sensors are used in a variety of applications (e.g., cameras, cell phones, tablets, and goggles). These image sensors utilize an array of pixel structures that absorb (e.g., sense) incoming radiation and convert it into an electrical signal. An example of an image sensor is a back-side illuminated (BSI) image sensor, which detects radiation from the "back" of the substrate of the BSI image sensor. Summary of the invention

[0003] According to one embodiment of the present disclosure, a semiconductor device is provided, comprising: a substrate; a pixel region having a pixel structure, wherein the pixel structure comprises: an epitaxial structure comprising: an embedded portion having a step structure, the embedded portion being arranged in the substrate, and a protruding portion extending above the top surface of the substrate; and a capping layer being arranged on the protruding portion; an isolation region having an isolation structure, the isolation region being adjacent to the pixel region; and a contact pad region having a pad structure, the contact pad region being adjacent to the isolation region.

[0004] According to one embodiment of the present disclosure, a semiconductor device is provided, comprising: a substrate; a pixel structure, comprising: an epitaxial structure, arranged in the substrate, wherein the epitaxial structure comprises a bottom surface having a first width and a top surface having a second width greater than the first width; and a capping layer, arranged on the epitaxial structure, comprising a band gap, the band gap being different from the band gap of a material of the epitaxial structure; and an isolation structure, comprising a doped region adjacent to the pixel structure.

[0005] According to one embodiment of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming a trench having a stepped cross-sectional profile in a substrate; forming an epitaxial structure in the trench; forming a capping layer on the epitaxial structure; forming a doped region in the epitaxial structure and the capping layer; forming a silicide layer on the doped region; forming an etch stop layer on the silicide layer; and forming a conductive plug on the silicide layer through the etch stop layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures.

[0007] Figure 1A A cross-sectional view of a semiconductor device having a BSI image sensor is shown in accordance with some embodiments.

[0008] Figure 1B and Figure 1C Different cross-sectional views of a pixel structure of a BSI image sensor according to some embodiments are shown.

[0009] Figure 1D A cross-sectional view of another semiconductor device having a BSI image sensor in accordance with some embodiments is shown.

[0010] Figure 1E is a cross-sectional view of another pixel structure of a BSI image sensor according to some embodiments.

[0011] Figure 2 is a flow chart of a method for manufacturing a semiconductor device having a BSI image sensor according to some embodiments.

[0012] Figure 3-Figure 20 Cross-sectional views of a semiconductor device having a BSI image sensor at different stages of its fabrication process are shown in accordance with some embodiments.

[0013] Illustrative embodiments will now be described with reference to the drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various embodiments. This repetition is for simplicity and clarity and does not itself determine the relationship between the various embodiments and / or configurations discussed.

[0015] Spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0016] Please note that references to "one embodiment", "an embodiment", "example embodiment", "exemplary", etc. in this specification indicate that the described embodiment may include a particular feature, structure, or characteristic, but not necessarily every embodiment includes the particular feature, structure, or characteristic. In addition, these phrases do not necessarily refer to the same embodiment. In addition, those skilled in the art should understand that when a particular feature, structure, or characteristic is described in relation to one embodiment, these features, structures, or characteristics can be implemented in relation to other embodiments whether or not explicitly described.

[0017] It should be understood that the phraseology or terminology herein is intended to be descriptive rather than limiting, and thus the phraseology or terminology in this specification is to be interpreted by one or more persons skilled in the relevant technical field in view of the teachings herein.

[0018] In some embodiments, the terms "about" and "substantially" may indicate a given value that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are merely examples and are not intended to be limiting. The terms "about" and "substantially" may refer to percentages of values ​​interpreted by a person skilled in the relevant art based on the teachings herein.

[0019] A BSI image sensor (e.g., a time-of-flight sensor) includes a pixel region (also referred to as a "radiation sensing region") having an array of pixel structures formed on a substrate (e.g., a semiconductor substrate). The pixel structure is configured to receive reflected radiation (e.g., infrared radiation) from an object and convert photons from the received radiation into electrical signals. The electrical signals are then distributed to processing components that are attached to the BSI image sensor. Therefore, the pixel structure is covered on a multi-level metallization layer that is configured to distribute the electrical signals generated in the pixel structure to appropriate processing elements.

[0020] The multi-level metallization layer is coupled to a first surface (also referred to as a "front side surface") of the substrate. A pixel structure is formed on the front side surface of the substrate, and radiation is received by the pixel structure through a second surface (also referred to as a "back side surface") of the substrate opposite to the front side surface of the substrate. Each pixel structure may include an epitaxial structure disposed in the substrate, a silicon-based capping layer disposed on the epitaxial structure, and a doped region disposed in the epitaxial structure and the silicon-based capping layer. The silicon-based capping layer may passivate the epitaxial structure and provide silicon atoms for forming a silicide structure on the doped region.

[0021] One of the challenges in forming a BSI image sensor is to control the top surface profile of the epitaxial structure during the following periods: during the formation of the epitaxial structure, and / or during the formation of a silicon-based capping layer and / or other capping layers. Non-uniformity in the top surface profile of the epitaxial structure may be introduced during a high temperature reflow process performed on the epitaxial structure and / or during high temperature (e.g., temperature above 500°C) processing of an overlying layer (e.g., a silicon-based capping layer). High temperatures may cause the material of the epitaxial structure to become ductile and to flow laterally on the edges of the trenches in which the epitaxial structure is formed and on the dielectric layer (the dielectric layer surrounds the epitaxial structure) and / or the silicon-based capping layer. Such non-uniformity in the top surface of the epitaxial structure may result in the formation of air gaps between the epitaxial structure and the silicon-based capping layer, and / or between the epitaxial structure and the sidewalls of the trench. These air gaps may introduce chemicals (e.g., etching solutions or cleaning solutions) being processed into the epitaxial structure during the processing of the overlying layer, thereby damaging the epitaxial structure.

[0022] To overcome the above challenges, the present disclosure provides example structures and methods for improving the surface uniformity of epitaxial structures in BSI image sensors, and thereby improving the interface between the epitaxial structure and the silicon-based capping layer and / or between the epitaxial structure and the trench sidewalls. In some embodiments, the epitaxial structure can be formed in a trench having a sidewall with a stepped profile or a curved profile. Such a structure of the trench can prevent or minimize the lateral expansion of the material of the epitaxial structure on the trench edge and the dielectric layer during a high temperature process.

[0023] Figure 1A A cross-sectional view of a semiconductor device 100 is shown in accordance with some embodiments. Figure 1B and Figure 1C It shows various embodiments Figure 1A 101 in FIG. 102 is a schematic diagram of a cross-sectional view of an area 101 in FIG. 103. Unless otherwise indicated, the Figure 1A , Figure 1B and Figure 1C Discussions of elements with the same annotation apply to each other.

[0024] In some embodiments, semiconductor device 100 may include: (i) a BSI image sensor 102 ; (ii) a first multi-level metallization layer 104 ; (iii) a second multi-level metallization layer 105 ; and (iv) an application specific integrated circuit (ASIC) 106 .

[0025] refer to Figure 1A , the BSI image sensor 102 may be disposed on and electrically connected to the first multi-level metallization layer 104. The first multi-level metallization layer 104 may be disposed on a second multi-level metallization layer 105, and the second multi-level metallization layer 105 may be disposed on and electrically connected to the ASIC 106. The first multi-level metallization layer 104 may include a multi-level interconnect structure 104A embedded in an inter-metal dielectric (IMD) layer 104B, and the multi-level interconnect structure 104A is disposed on a bonding layer 104C with a metal line 104D. Similarly, the second multi-level metallization layer 105 may include a multi-level interconnect structure 105A embedded in an IMD layer 105B and a bonding layer 105C with a metal line 105D disposed on the IMD layer 105B. The bonding layers 104C and 105C may be bonded to each other by an appropriate bonding method, such as direct bonding, eutectic bonding, hybrid bonding, and optical fusion bonding, and may be electrically connected to each other by metal lines 104D and 105D. Thus, the BSI image sensor 102 may be electrically connected to the ASIC 106 through the first and second multi-level metallization layers 104 and 105. The ASIC 106 may include active devices 106A (e.g., transistor structures) to form logic and memory circuits. In some embodiments, the active devices 106A may be configured to process electrical signals received from the BSI image sensor 102.

[0026] In some embodiments, the BSI image sensor 102 may include: (i) a substrate 108 having a front side surface 108a and a back side surface 108b; (ii) a stack of layers 110 disposed on the front side surface 108a; and (iii) a micro lens 125 disposed on the back side surface 108b. In some embodiments, the substrate 108 may include a single crystal silicon substrate. In some embodiments, the substrate 108 may include a semiconductor material such as Si, Ge, SiGe, silicon carbide (SiC), indium phosphide (InP), gallium arsenide (GaAs), silicon arsenide (SiAs), gallium phosphide (GaP), indium phosphide (InP), silicon germanium carbide (SiGeC), germanium tin (GeSn), silicon germanium tin (SiGeSn), gallium arsenide phosphide (GaAsP), gallium indium phosphide (GaInP), gallium indium arsenide (GaInAs), gallium indium arsenide phosphide (GaInAsP), and any other suitable semiconductor material. In some embodiments, the substrate 108 may include a silicon-on-insulator (SOI) structure or a germanium-on-insulator (GOI) structure.

[0027] refer to Figure 1A and Figure 1B In some embodiments, the stack 110 may include: (i) a passivation layer 112 disposed on the first multi-level metallization layer 104, (ii) an interlayer dielectric (ILD) layer 114 disposed on the passivation layer 112, (iii) an etch stop layer (ESL) 116 disposed on the ILD layer 114, and (iv) a dielectric layer 118 disposed on the ESL 116. In some embodiments, the dielectric layer 118 may include a nitride layer, an oxide layer, an oxynitride layer, or a suitable dielectric material. In some embodiments, the dielectric layer 118 may include an oxide of the material of the substrate 108, such as silicon oxide (SiO x In some embodiments, ESL 116 may include a nitride layer, an oxide layer, an oxynitride layer, a carbide layer, or a suitable dielectric material. In some embodiments, ESL 116 may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbon nitride (SiCN), boron nitride (BN), silicon boron nitride (SiBN), silicon carbon boron nitride (SiCBN), or a combination thereof. In some embodiments, the ILD layer 114 may include a low-k dielectric layer (e.g., a dielectric layer having a dielectric constant less than about 3.9), an ultra-low-k dielectric layer (e.g., a dielectric layer having a dielectric constant less than about 2.5), or an oxide layer (e.g., silicon oxide (SiO x)). In some embodiments, the passivation layer 112 may include a nitride layer, an oxide layer, an oxynitride layer, a polymer layer (eg, polyimide or polybenzoxazole), or a combination thereof.

[0028] refer to Figure 1A In some embodiments, according to some embodiments, the BSI image sensor 102 may further include: (i) a pixel region 102A; (ii) an isolation region 102B; and (iii) a contact pad region 102C. In some embodiments, the pixel region 102A may include an array of pixel structures 122A and 122B. Although an array of two pixel structures 122A and 122B is shown, the BSI image sensor 102 may arrange any number of pixel structures in a one-dimensional array or a two-dimensional array. The pixel structures 122A and 122B are configured to receive an incident radiation beam 123 through a microlens 125 on the back surface 108b and convert the radiation beam 123 into an electrical signal. The electrical signal is distributed to the ASIC 106 and / or other external circuits through the pad structure 120 and the first and second multi-level metallization layers 104 and 105. Pixel structures 122A and 122B can be electrically isolated from each other by dielectric layer 118 and protected by passivation layer 112, ILD layer 114, and ESL 116 during the manufacturing process of BSI image sensor 102. In some embodiments, pixel structures 122A and 122B can be similar to each other in structure and composition. The discussion of pixel structure 122A applies to pixel structure 122B unless otherwise mentioned.

[0029] refer to Figure 1A and Figure 1B In some embodiments, the pixel structure 122A may include: (i) an epitaxial structure 124A disposed in the substrate 108; (ii) a capping layer 126 disposed on the epitaxial structure 124A; (iii) a p-type doped region 130 disposed in the epitaxial structure 124A and the capping layer 126; (iv) an n-type doped region 132 disposed in the epitaxial structure 124A and the capping layer 126; (v) a contact structure 134 disposed on the p-type and n-type doped regions 130 and 132; and (vi) a through-hole structure 136 disposed on the contact structure 134.

[0030] Epitaxial structure 124A may be formed on front side surface 108a and may include quantum effect materials such as silicon, silicon germanium (SiGe), and III-V group elements in the periodic table. In some embodiments, epitaxial structure 124A may include a group IV element different from the group IV element of substrate 108. In some embodiments, epitaxial structure 124A may include undoped Ge or SiGe.

[0031] In some embodiments, the epitaxial structure 124A may include an embedded portion 124e and a protruding portion 124p. The embedded portion 124e may be disposed in the substrate 108, and the protruding portion 124p may extend above the front side surface 108f of the substrate 108. In some embodiments, the protruding portion 124p may have a substantially planar top surface 124pt and an inclined sidewall 124ps. The inclined sidewall 124ps may be separated from the dielectric layer 118 by a portion of the capping layer 126, and may form an angle A of about 5 degrees or less with the vertical sidewall 126s of the capping layer 126. If the angle A is greater than about 5 degrees, the chemicals (e.g., cleaning solution) used during the processing of the epitaxial structure 124A and / or the capping layer 126 penetrate into the interface between the embedded portion 124e and the substrate 108, thereby damaging the epitaxial structure 124A. In some embodiments, the sidewall 124ps of the protruding portion 124p may be substantially vertical (not shown) and may contact the dielectric layer 118.

[0032] In some embodiments, the embedded portion 124e of the epitaxial structure 124A may have a stepped structure with a sidewall having a stepped profile. The stepped structure of the embedded portion 124e may have a bottom portion 124e1 and a top portion 124e2, the top portion 124e2 being wider than the bottom portion 124e1. In some embodiments, the bottom portion 124e1 may have a width W1 equal to or greater than about 0.5 μm, and the top portion 124e2 may have a width W2 equal to or greater than about 1.2 times the width W1. In some embodiments, the bottom portion 124e1 may have a height H1 of about 175 nm to about 200 nm, and the top portion 124e2 may have a height H2 of about 50 nm to about 100 nm. In some embodiments, the height H2 may be equal to or greater than the total height H1 of the embedded portion 124e. T In some embodiments, the embedded portion 124e may extend below the front side surface 108f of the substrate 108 to a height H1 of about 100 nm to about 200 nm. T , and the backside surface 124eb of the embedded portion 124e can be higher than the backside surface 108b of the substrate 108 by a distance D1 of about 75nm to about 125nm. As described in detail below, within these ranges of widths W1 and W2, heights H1 and H2, and distance D1, the stepped structure of the embedded portion 124e can prevent or minimize the material of the epitaxial structure 124A from being deposited in the trench 524 (such as during high temperature processes). Figure 5 lateral extension of the edge.

[0033] Although the step structure of the embedded portion 124e is Figure 1BAlthough shown as having a single step level, the embedded portion 124e may have any number of steps. For example, in some embodiments, the epitaxial structure 124A may have a Figure 1C The embedded portion 124e* shown has multiple steps, rather than Figure 1B In some embodiments, the stepped structure of the embedded portion 124e* may have a bottommost portion 124e3, a middle portion 124e4, and a topmost portion 124e5. The topmost portion 124e5 may be wider than the middle portion 124e4, and the middle portion 124e4 may be wider than the bottommost portion 124e3. In some embodiments, the bottommost portion 124e3 may have a width W1 equal to or greater than about 0.5 μm, and the topmost portion 124e5 may have a width W2 equal to or greater than about 1.2 times the width W1. In some embodiments, a height H3 of the bottommost portion 124e3 may be greater than a height H4 of the middle portion 124e4 and a height H5 of the topmost portion 124e5. In some embodiments, the height H5 may be equal to or greater than a total height H of the embedded portion 124e*. T About 25% of

[0034] refer to Figure 1A-Figure 1C In some embodiments, the capping layer 126 may include a silicon layer or a silicon-based layer (e.g., silicon nitride (SiN)). In some embodiments, the capping layer 126 may include an element having a band gap different from the band gap of the element included in the epitaxial structure 124A, which results in a band discontinuity between the epitaxial structure 124A and the capping layer 126 (e.g., a difference between the minimum conduction band energy and / or the maximum valence band energy of the epitaxial structure 124 and the capping layer 126). In some embodiments, the capping layer 126 may have a thickness T1 of about 10 nm to about 15 nm. In some embodiments, the doped regions 130 and 132 may be present in the epitaxial structure 124A and the capping layer 126. In some embodiments, the doped regions 130 and 132 may not be present in the epitaxial structure 124A and the capping layer 126.

[0035] In some embodiments, the contact structure 134 may be configured to electrically connect the epitaxial structure 124A to the first multi-level metallization layer 104 through the via structure 136. Each contact structure 134 may include a silicide layer 134A and a contact plug 134B. The silicide layer 134A is disposed on the p-type and n-type doped regions 130 and 132 and in the capping layer 126. In some embodiments, the silicide layer 134A may include nickel silicide (NiSi), tungsten silicide (WSi2), titanium silicide (TiSi2), cobalt silicide (CoSi2) or a suitable metal silicide. The contact plug 134B is located in the silicide layer 134A and the ILD layer 114. In some embodiments, the contact plug 134B may include a conductive material, such as ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), tungsten (W), cobalt (Co), copper (Cu) and any suitable metal material. The via structure 136 is disposed in the contact plug 134B and the passivation layer 112. In some embodiments, the via structure 136 may include a conductive material such as Ru, Co, Ni, Al, Mo, W, Ir, Os, Cu, Pt, and any other suitable metal material.

[0036] refer to Figure 1A , the isolation region 102B may include an isolation structure 140, the isolation structure 140 having an n-type doped region 140A and a p-type doped region 140B, the n-type doped region 140A and the p-type doped region 140B being configured to form an isolation structure based on a PN junction. The isolation structure may be electrically connected to the first multi-level metallization layer 104 and / or other circuits through the contact structure 134 and the through-hole structure 136. The contact pad region 102C may include a pad structure 120 and one or more conductive bonding pads or solder bumps (not shown) on the pad structure 120, through which an electrical connection between the BSI image sensor 102 and an external circuit may be established. The pad structure 120 is an input / output (I / O) port of the BSI image sensor 102, and includes a conductive layer electrically coupled to the multi-layer interconnect structure 104A.

[0037] Figure 1D Another cross-sectional view of a semiconductor device 100 is shown in accordance with some embodiments. Figure 1E According to some embodiments Figure 1D Unless otherwise stated, Figure 1A-1E The discussion of elements with the same annotations in FIG. 1 and FIG. 2 applies to each other. In some embodiments, the pixel structure 122A may have Figure 1D and Figure 1E The epitaxial structure 124B shown, instead of Figure 1A and Figure 1B The epitaxial structure 124e or Figure 1C In some embodiments, epitaxial structure 124B may have a tapered structure with sidewalls having a curved profile. The tapered structure of epitaxial structure 124B may have a bottom surface 124Bb having a width W1 and a top surface 124Bt having a width W2 greater than width W1. In some embodiments, width W1 may be equal to or greater than about 0.5 μm, and width W2 may be equal to or greater than about 1.2 times width W1. In some embodiments, epitaxial structure 124B may extend to a height H of about 100 nm to about 200 nm below front side surface 108 f of substrate 108. T , and the back side surface 124Bb of the epitaxial structure 124B may be higher than the back side surface 108b of the substrate 108 by a distance D1 of about 75 nm to about 125 nm. T Within these ranges of distance D1, the tapered structure of epitaxial structure 124B can prevent or minimize the material of epitaxial structure 124B from being deposited in trench 1724 (eg, Fig.17 lateral expansion on the edge of the PCB (as shown), as described below.

[0038] In some embodiments, the top surface 124Bt of the epitaxial structure 124B may have a surface portion 124Bt1 having a substantially planar profile and a surface portion 124Bt2 surrounding the surface portion 124Bt1 and having a curved profile. In some embodiments, the surface portion 124Bt1 may be substantially coplanar with the front side surface 108f of the substrate 108, while the surface portion 124Bt2 may extend above the front side surface 108f of the substrate 108.

[0039] Figure 2 According to some embodiments, a method for manufacturing a Figure 1A 1. For illustration purposes, reference will be made to FIG. 1. Figure 3-Figure 15 The example manufacturing process of the semiconductor device 100 is described as follows. Figure 2 The operations shown in . Figure 3-Figure 15 2 is a cross-sectional view of a semiconductor device 100 at different manufacturing stages according to some embodiments. The operations may be performed in different orders or not performed according to the specific application. It should be noted that the method 200 may not be able to manufacture a complete semiconductor device 100. Therefore, it is understood that other processes may be provided before, during, and after the method 200, and some other processes may only be briefly described herein. Figure 3-Figure 15 Zhongyu Figure 1A and Figure 1B Elements with the same annotations as those described above.

[0040] In operation 205, an isolation structure is formed on the front side surface of the substrate. Figure 3 As shown, the n-type doped region 140A and the p-type doped region 140B of the isolation structure 140 are formed on the front side surface 108a of the substrate 108. The n-type doped region 140A and the p-type doped region 140B can be formed by implanting dopants into the substrate 108 through the front side surface 108a. After forming the doped regions 140A and 140B, a dielectric layer 318 can be deposited on the front side surface 108a, as shown in FIG. Figure 3 As shown. Dielectric layer 318 may include the material of dielectric layer 118. The formation of dielectric layer 318 may include using a CVD process, an ALD process, a thermal oxidation process, or a deposition process suitable for the dielectric material.

[0041] refer to Figure 2 In operation 210, an epitaxial structure is formed on the front side surface of the substrate. Figure 4-Figure 6 As described above, the epitaxial structure 124A may be formed simultaneously on the front side surface 108a of the substrate 108. The formation of the epitaxial structure 124A may include the following sequential operations: (i) Figure 4 As shown, a trench 424 having a vertical sidewall profile is formed in the substrate 108 through the dielectric layer 318; (ii) as shown in Figure 5 As shown, the trench 424 is modified to form a trench 524 having a stepped sidewall profile; (iii) as shown Figure 6 As shown, epitaxial structure 124A is formed in trench 524 at the same time.

[0042] In some embodiments, the formation of the trench 424 may include a dry etching process using an etchant (eg, chlorine-based gas, helium, fluorine-based gas, argon, and combinations thereof). In some embodiments, each trench 424 may be formed with a width W1 and a height H2. T , trench 424 extends into substrate 108. In some embodiments, modifying trench 424 to form trench 524 may include etching exposed areas of substrate 108 and dielectric layer 318 in trench 424 to increase width W1 at the top of trench 424 to width W2. Thus, trench 524 may form a bottom trench portion 524A having width W1 and a top trench portion 524 having width W2, where width W2 is greater than width W1. In some embodiments, width W1 may be equal to or greater than approximately 0.5 μm, and width W2 may be equal to or greater than approximately 1.2 times width W1. In some embodiments, bottom trench portion 524A may have a height H1 of approximately 175 nm to approximately 200 nm, and top trench portion 524B may have a height H2 of approximately 50 nm to approximately 100 nm. In some embodiments, height H2 may be equal to or greater than a total height H1 of trench 524 in substrate 108.T The stepped structure of the trench 524 having the above-mentioned range of widths W1 and W2 and heights H1 and H2 can prevent or minimize the lateral expansion of the material of the subsequently formed epitaxial structure 124A on the edge of the trench 524 and the dielectric layer 318 during the subsequent high temperature process.

[0043] In some embodiments, trench 524 may be formed by forming top trench portion 524B before forming bottom trench portion 524A, rather than by forming and modifying trench 424. In this case, formation of epitaxial structure 124A may include the following sequential operations: (i) Figure 3 In the structure of FIG. 1 , the substrate 108 is etched through the dielectric layer 318 to form a top channel portion 524B having a width of W2 and a height of H2; (ii) the substrate 108 is etched through the channel 524B to form a bottom channel portion 524A having a width of W1 and a height of H1; (iii) Figure 6 As shown, epitaxial structure 124A is formed in trench 524 at the same time.

[0044] In some embodiments, forming the epitaxial structure 124A may include: (i) epitaxially growing a layer of Si, SiGe, or a III-V element in the periodic table (not shown) in the trench 524; (ii) performing a chemical mechanical polishing (CMP) process (also referred to as a “surface treatment process”) on the layer of Si, SiGe, or a III-V element in the periodic table (not shown); (iii) performing a surface treatment process such as Figure 6 As shown, the polished Si, SiGe or III-V element layer is etched to form epitaxial structures 124A having top surfaces 124pt lower than top surface 318t of dielectric layer 318; and (v) Figure 6 In some embodiments, between operations (i) and (ii) of forming the epitaxial structure 124A, a photolithography process may be performed to form a mask layer on the dielectric layer 318. After the photolithography process, an etching process may be performed on the Si, SiGe, or III-V group element layer in the trench 524, and then the CMP process of operation (ii) may be performed.

[0045] The epitaxial growth of Si, SiGe or III-V group element layer may include epitaxially growing a single crystal or polycrystalline structure of Si, SiGe or III-V group elements in the periodic table. In some embodiments, due to the presence of the dielectric layer 318, which may have an amorphous structure, the Si, SiGe or III-V group element layer may be selectively grown in the groove 524. The amorphous dielectric layer 318 may prevent the silicon, germanium or III-V group element layer from epitaxially growing on the area covered by the dielectric layer 318. In some embodiments, the selective growth of silicon, germanium or III-V group element layer may result in a single crystal structure of silicon, germanium or III-V group elements in the periodic table. In some embodiments, the selective epitaxial growth of Ge in the groove 524 may be performed using a germanium (GeH4) precursor gas with a flow rate of about 100 sccm to about 5000 sccm, a hydrogen carrier gas with a flow rate of about 1000 sccm to about 20000 sccm, and a hydrochloric acid etching gas with a flow rate of about 50 sccm to about 1000 sccm. In some embodiments, the selective epitaxial growth of Ge in the trench 524 may be performed at a temperature of about 300° C. to about 1000° C. and a pressure of about 5 Torr to about 50 Torr.

[0046] The CMP process may include using a CMP slurry that has a higher removal selectivity for epitaxial structure 124A material than for dielectric layer 318 material. The term "removal selectivity" refers to the ratio of removal rates of two different materials under the same removal conditions. In some embodiments, the CMP slurry has a removal selectivity for epitaxial structure 124A material that is about 20 times to about 200 times higher than the removal selectivity for dielectric layer 318 material. The CMP slurry may include hydrogen peroxide, potassium persulfate, oxynitride-based compounds, polyethylene glycol, abrasive particles (e.g., colloidal silicon dioxide, fumed silicon dioxide, aluminum oxide), and combinations thereof. In some embodiments, during etching of the polishing layer of silicon, silicon germanium, or III-V elements, dielectric layer 318 may be protected by a mask layer (e.g., a photoresist layer), which may be formed in a photolithography process.

[0047] The etching of the Si, SiGe or III-V polishing layer may include a wet etching process, a dry etching process or a vapor phase etching process using a halogen-based etchant. The etchant has a higher etch selectivity (e.g., about 20 to about 50 times higher) for the epitaxial structure 124A material than for the dielectric layer 318 and the substrate 108 material. The cleaning process may include cleaning with an acid-based cleaning solution (e.g., dilute hydrofluoric acid (DHF) and / or hydrogen peroxide (H2O2)). Figure 6 structure to remove contaminants and / or residues from a CMP process and / or an etching process.

[0048] refer to Figure 2In operation 215, a capping layer is formed on the epitaxial structure. Figure 7 As shown, a capping layer 126 may be formed on the epitaxial structure 124A. In some embodiments, the formation of the capping layer 126 may include epitaxially growing a Si, Ge, or SiGe layer on the epitaxial structure 124A. In some embodiments, as opposed to epitaxially growing the capping layer 126, the formation of the capping layer 126 may include the following sequence of operations: (i) Figure 6 (ii) forming a patterned masking layer (not shown) on the Si, Ge, SiGe or SiN layer to protect the Si, Ge, SiGe or SiN layer portion on the epitaxial structure 124A; and (iii) selectively etching the Si, Ge, SiGe or SiN layer portion not protected by the patterned masking layer to form Figure 7 The deposition of the Si, Ge or SiGe layer may include using a silicon precursor (e.g., silane (SiH4) or dichlorosilane (DCS)) and / or a germanium precursor (e.g., germanium (GeH4)) in a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. In some embodiments, a capping layer 126 may be formed, and a top surface 126t of the capping layer 126 is substantially coplanar with a top surface 318t of the dielectric layer 318, such as Figure 7 shown.

[0049] In some embodiments, after forming the capping layer 126, Figure 7 A dielectric layer 818 similar to the material of the dielectric layer 318 is deposited on the structure to form Figure 8 The formation of the dielectric layer 818 may include using a CVD process, an ALD process, or a thermal oxidation process.

[0050] refer to Figure 2 In operation 220, doped regions are formed in the epitaxial structure and the capping layer. Fig. 9 and Fig.10 As described above, a p-type doping region 130 and an n-type doping region 132 may be formed in the capping layer 126 and the epitaxial structure 124A. The formation of the p-type doping region 130 and the n-type doping region 132 may include the following sequential operations: (i) Fig. 9 As shown, a patterned mask layer 942 with an opening 944 is formed; (ii) as shown Fig. 9 As shown, n-type dopant 946 is ion-implanted into capping layer 126 and epitaxial structure 124A through opening 944 to form doped region 132; (iii) patterned layer 942 is removed (not shown); (iv) Fig.10 As shown, a patterned masking layer 1048 having an opening 1050 is formed; (v) as shown Fig.10 As shown, a p-type dopant 1052 is ion-implanted into the capping layer 126 and the epitaxial structure 124A through the opening 1050 to form a p-type doped region 130; and (vii) after removing the patterned layer 1048, Fig.10 An annealing process is performed on the structure to activate the dopants in the doped regions 130 and 132.

[0051] refer to Figure 2 In operation 225, a contact structure and a via structure are formed on the doped region and the isolation structure. Figure 11-13 As described above, a contact structure 134 having a silicide layer 134A and a contact plug 134B is formed on the doped regions 130 and 132 and 140A and 140B, and a through hole structure 136 is formed on the contact structure 134. The formation of the contact structure 134 may include the following sequential operations: (i) Fig.11 As shown, a silicide opening 1154 is formed on the doped regions 130 and 132 and 140A and 140B; (ii) as shown Fig.12 As shown, a silicide layer 134A is formed on the doped regions 130 and 132 and 140A and 140B; (iii) as shown Fig.13 As shown, ESL 116 is deposited on silicide layer 134A and dielectric layer 118; (iv) as shown Fig.13 As shown, an ILD layer 114 is deposited on the ESL 116; (v) as shown Fig.13 As shown, contact openings (not shown) are formed in the ILD layer 114 and the ESL 116 to expose a portion of the silicide layer 134A; and (vi), as shown Fig.13 As shown, a contact plug 134B is formed in the contact opening.

[0052] The formation of the silicide layer 134A may include the following sequential operations: (i) Fig.11 (ii) performing an annealing process on the structure with the metal layer; and (iii) removing an unreacted portion of the metal layer on the dielectric layer 118 to form Fig.12 The formation of the through hole structure 136 may include: depositing a metal layer (not shown) on the structure after forming the contact plug 134B, and patterning the deposited metal layer to form Fig.13 After forming the through hole structure 136, a passivation layer 112 may be deposited on the ILD layer 114 and the through hole structure 136. Fig.14 shown.

[0053] refer to Figure 2 In operation 230, a multi-level metallization layer is formed on the via structure and bonded to the integrated circuit. Fig.14As shown, a first multi-level metallization layer 104 having a multi-level interconnect structure 104A with an embedded IMD layer 104B is formed on the via structure 136 and the passivation layer 112. After the multi-level metallization layer 104 is formed, a second multi-level metallization layer 105 and an ASIC 106 may be bonded to the multi-level metallization layer 104, as shown in FIG. Fig.14 shown.

[0054] refer to Figure 2 In operation 235, a pad structure is formed on the multi-level metallization layer through the back side surface of the substrate. Fig.15 As shown, a pad structure 120 is formed on the multi-level interconnect structure 104A through the backside surface 108b. The formation of the pad structure 120 may include the following sequential operations: (i) forming a pad opening (not shown) in the substrate 108, the dielectric layer 118, the ESL 116, the ILD layer 114, the passivation layer 112, and a portion of the IMD layer 104B; (ii) depositing a conductive layer (not shown) in the pad opening; and (iii) Fig.15 As shown, the conductive layer is patterned and etched to form a pad structure 120 in the pad opening. After forming the pad structure 120, an array of microlenses 125 may be formed on the back side surface 108b, as shown in FIG. Fig.15 shown.

[0055] In some embodiments, the Figure 2 Operations 205-235 of method 200 are similar to operations to form a Figure 1D The cross-sectional view of the semiconductor device 100 is shown in FIG. 1 , except that the semiconductor device 100 is formed in operation 210 of the method 200 Figure 1D The epitaxial structure 124B of the semiconductor device 100 (as shown in reference Figure 16-Figure 18 described), rather than referring to Figure 4-Figure 6 The formation described Figure 1A Operation of the epitaxial structure 124A of the semiconductor device 100.

[0056] In some embodiments, the formation of epitaxial structure 124B may include the following sequential operations: (i) forming a patterned masking layer 1654 on dielectric layer 318, such as Fig.16 (ii) forming a groove 1724 having a tapered structure and a curved sidewall profile in the substrate 108 through the opening 1656, as shown Fig.17 (iii) removing the patterned masking layer 1654, as shown; Fig.17 as shown; and (iv) as Fig.18As shown, an epitaxial structure 124B is formed in the trench 1724. In some embodiments, the sidewall 1654t of the patterned mask layer 1654 facing the opening 1656 may form an inclined profile. The inclined profile of the sidewall 1654t may control the etching profile of the trench 1724. In some embodiments, each sidewall 1654t may form an angle B of about 135 degrees to about 140 degrees relative to the top surface of the dielectric layer 318. Within this range of angle B, the inclined profile of the sidewall 1654t may control the etching profile of the trench 1724 to form a trench 1724 having a tapered cross-sectional profile and a curved sidewall profile, as shown in FIG. Fig.17 In some embodiments, the process of forming the epitaxial structure 124B in the trench 1724 can be similar to that described in reference to Figure 6 A process for forming epitaxial structure 124A in trench 524 is described.

[0057] As reference Figure 7 As described, after the operation of forming the epitaxial structure 124B in the trench 1724, operation 215 of the method 200 may be performed to form a capping layer 126 on the epitaxial structure 124B, such as Fig.19 As shown in reference Figure 8-Figure 15 As described above, after forming the capping layer 126, operations similar to operations 220-235 of method 200 may be performed to form Fig. 20 structure.

[0058] The present disclosure provides example structures and methods for improving the surface uniformity of epitaxial structures (e.g., epitaxial structures 124A and 124B) in a BSI image sensor (e.g., BSI image sensor 102), and thereby improving the interface between the epitaxial structure and a silicon-based capping layer (e.g., silicon-based capping layer 126) and / or between the epitaxial structure and the sidewalls of a trench (e.g., trenches 524 and 1724). In some embodiments, the epitaxial structure can be formed in a trench having stepped sidewalls or having curved sidewalls. Such a structure of the trench can prevent or minimize lateral expansion of the material of the epitaxial structure at the edge of the trench during a high temperature process.

[0059] In some embodiments, a semiconductor device includes a substrate, a pixel region having a pixel structure, an isolation region having an isolation structure disposed adjacent to the pixel region, and a contact pad region having a pad structure disposed adjacent to the isolation region. The pixel structure includes an epitaxial structure, the epitaxial structure including an embedded portion having a step structure disposed in the substrate and a protruding portion extending above a top surface of the substrate. The pixel structure also includes a capping layer disposed on the protruding portion.

[0060] In some embodiments, a semiconductor device includes a substrate, a pixel structure, and an isolation structure. The pixel structure includes an epitaxial structure disposed in the substrate and a silicon-based capping layer disposed on the epitaxial structure. The epitaxial structure includes a bottom surface having a first width and a top surface having a second width greater than the first width. The isolation structure includes a doped region adjacent to the pixel structure.

[0061] In some embodiments, a method includes: forming a trench having a step cross-sectional profile in a substrate, forming an epitaxial structure in the trench, forming a silicon-based capping layer on the epitaxial structure, forming a doped region in the epitaxial structure and the capping layer, forming a silicide layer in the doped region, forming an etch stop layer on the silicide layer, and forming a conductive plug on the silicide layer through the etch stop layer.

[0062] The features of several embodiments are summarized above so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0063] Example 1 is a semiconductor device, comprising: a substrate; a pixel region having a pixel structure, wherein the pixel structure comprises: an epitaxial structure comprising: an embedded portion having a step structure, the embedded portion being disposed in the substrate, and a protruding portion extending above a top surface of the substrate; and a capping layer being disposed on the protruding portion; an isolation region having an isolation structure, the isolation region being adjacent to the pixel region; and a contact pad region having a pad structure, the contact pad region being adjacent to the isolation region.

[0064] Example 2 is the semiconductor device of Example 1, wherein the embedded portion includes a sidewall having a stepped profile.

[0065] Example 3 is the semiconductor device of Example 1, wherein the embedded portion includes: a bottom portion having a first width; and a top portion having a second width greater than the first width.

[0066] Example 4 is the semiconductor device of Example 1, wherein the embedded portion includes: a bottom portion having a first width; and a top portion having a second width that is approximately 1.2 times the first width.

[0067] Example 5 is the semiconductor device of Example 1, wherein the embedded portion includes: a bottom portion having a first width equal to or greater than approximately 0.5 μm; and a top portion having a second width approximately 1.2 times the first width.

[0068] Example 6 is the semiconductor device of Example 1, wherein the embedded portion includes: a bottom portion having a first height; and a top portion having a second height less than the first height.

[0069] Example 7 is the semiconductor device of Example 1, wherein the embedded portion includes: a bottom portion having a first height; and a top portion having a second height, the second height being approximately 25% of the sum of the first height and the second height.

[0070] Example 8 is the semiconductor device of Example 1, wherein the protruding portion includes: a top surface, the top surface is substantially flat; and a sidewall, the sidewall having an inclined profile.

[0071] Example 9 is the semiconductor device of Example 1, wherein the protruding portion includes an inclined sidewall that forms an angle of about 5 degrees or less with a sidewall of the capping layer.

[0072] Example 10 is the semiconductor device described in Example 1, wherein the pixel structure further includes a doped region disposed in the epitaxial structure and the capping layer.

[0073] Example 11 is a semiconductor device, comprising: a substrate; a pixel structure, comprising: an epitaxial structure, disposed in the substrate, wherein the epitaxial structure comprises a bottom surface having a first width and a top surface having a second width greater than the first width; and a capping layer, disposed on the epitaxial structure, comprising a band gap, the band gap being different from a band gap of a material of the epitaxial structure; and an isolation structure, comprising a doped region adjacent to the pixel structure.

[0074] Example 12 is the semiconductor device described in Example 11, wherein the epitaxial structure includes a stepped structure.

[0075] Example 13 is the semiconductor device of Example 11, wherein the epitaxial structure includes a tapered structure.

[0076] Example 14 is the semiconductor device of Example 11, wherein the epitaxial structure includes a layer of silicon, silicon germanium, or a Group III-V element in the periodic table.

[0077] Example 15 is the semiconductor device of Example 11, wherein the capping layer comprises a silicon-based material.

[0078] Example 16 is the semiconductor device of Example 11, wherein the top surface of the epitaxial structure includes a first surface portion having a linear profile and a second surface portion having a curved profile.

[0079] Example 17 is a method for forming a semiconductor device, comprising: forming a trench having a stepped cross-sectional profile in a substrate; forming an epitaxial structure in the trench; forming a capping layer on the epitaxial structure; forming a doped region in the epitaxial structure and the capping layer; forming a silicide layer on the doped region; forming an etch stop layer on the silicide layer; and forming a conductive plug on the silicide layer through the etch stop layer.

[0080] Example 18 is the method described in Example 17, wherein forming the groove includes: forming a first groove having a first width in the substrate; and modifying a top portion of the first groove to form a second groove having a second width greater than the first width.

[0081] Example 19 is the method described in Example 17, wherein forming the epitaxial structure includes: selectively growing a quantum effect material having a single crystal structure.

[0082] Example 20 is the method of Example 17, wherein forming the epitaxial structure includes: forming an embedded portion in the substrate; and forming a protruding portion extending above a top surface of the substrate.

Claims

1. A semiconductor device, comprising: substrate; The pixel region has a pixel structure, wherein the pixel structure includes: Epitaxial structure, including: an embedded portion having a stepped structure, the embedded portion being disposed in the substrate, and a protruding portion extending above the top surface of the substrate; and A capping layer, disposed on the protruding portion; an isolation region having an isolation structure, wherein the isolation region is adjacent to the pixel region; and The contact pad region has a pad structure, and the contact pad region is adjacent to the isolation region.

2. The semiconductor device according to claim 1, wherein The embedded portion includes a side wall having a stepped profile.

3. The semiconductor device according to claim 1, wherein The embedded part includes: a bottom portion having a first width; and The top portion has a second width greater than the first width.

4. The semiconductor device according to claim 1, wherein: The embedded part includes: a bottom portion having a first width; and The top portion has a second width that is 1.2 times the first width.

5. The semiconductor device according to claim 1, wherein The embedded part includes: a bottom portion having a first width equal to or greater than 0.5 μm; and The top portion has a second width that is 1.2 times the first width.

6. The semiconductor device according to claim 1, wherein The embedded part includes: a bottom portion having a first height; and The top portion has a second height that is less than the first height.

7. The semiconductor device according to claim 1, wherein The embedded part includes: a bottom portion having a first height; and The top portion has a second height, wherein the second height is 25% of the sum of the first height and the second height.

8. The semiconductor device according to claim 1, wherein The protruding parts include: a top surface, the top surface being generally planar; and A side wall has an inclined profile.

9. A semiconductor device comprising: substrate; Pixel structure, including: an epitaxial structure disposed in the substrate, wherein the epitaxial structure includes a bottom surface having a first width and a top surface having a second width greater than the first width; and a capping layer disposed on the epitaxial structure, comprising a bandgap that is different from a bandgap of a material of the epitaxial structure; and The isolation structure includes a doped region adjacent to the pixel structure.

10. A method of forming a semiconductor device, comprising: forming a trench having a stepped cross-sectional profile in a substrate; forming an epitaxial structure in the trench; forming a capping layer on the epitaxial structure; forming doped regions in the epitaxial structure and the capping layer; forming a silicide layer on the doped region; forming an etch stop layer on the silicide layer; as well as A conductive plug is formed on the silicide layer through the etch stop layer.

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