Semiconductor device

Abstract

The present disclosure provides a semiconductor device capable of suppressing a sudden increase in current when the semiconductor device is turned on without significantly damaging an effective area of the semiconductor device. The planar layout on the semiconductor substrate (SB) has a distribution of threshold voltages for the switches. When a histogram is defined by a plurality of bins having a bin width of 100 mV for the threshold voltage, and a plurality of frequencies corresponding to an area of the planar layout belonging to each of the plurality of bins, the planar layout has a plurality of regions (RG1-RGn) belonging to different bins among the plurality of bins. The plurality of regions (RG1-RGn) include first to third regions (RG1-RG3). The histogram has a distribution (PFL) in which a hem is continuously drawn out from a normal distribution (PNM) to a low-voltage side on the basis of the normal distribution (PNM).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and more particularly to an insulated gate bipolar transistor or a reverse conducting insulated gate bipolar transistor. Background Art

[0002] According to International Publication No. 2012 / 141121 (Patent Document 1), in a semiconductor device having a power system active element having an insulated gate such as a power MOSFET, a sub-active cell region having a lower threshold voltage than other regions and occupying a relatively narrow area is provided in an active cell region. Therefore, according to the above document, it is claimed that since the sub-active cell region is turned on first when turning on, the generation of overshoot voltage can be reduced.

[0003] According to Japanese Patent Publication No. 2016-154218 (Patent Document 2), a semiconductor device includes a transistor unit and an enhancement unit. Each transistor unit includes a drift structure and a main body region forming a first pn junction. The transistor unit forms an inversion channel in the main body region when a first control signal exceeds a first threshold. The delay unit generates a second control signal whose trailing edge is delayed relative to the trailing edge of the first control signal. The enhancement unit forms an inversion layer in the drift structure when the second control signal is lower than a second threshold lower than the first threshold.

[0004] Patent Document 1: International Publication No. 2012 / 141121

[0005] Patent Document 2: Japanese Patent Application Publication No. 2016-154218

[0006] In the technology of International Publication No. 2012 / 141121, simply providing the sub-active cell region tends to increase the variation in switching characteristics originally required by users of the semiconductor device.

[0007] The technology disclosed in the above-mentioned Japanese Patent Publication No. 2016-154218 forms different types of gate electrodes in different types of units and sends delayed signals corresponding to the units. As a result, some units are turned off first to promote carrier discharge. This can reduce the turn-off loss. In this way, the structure of providing a separate control signal to each unit is not limited to reducing the turn-off loss, and it is also conceivable to be a structure that can obtain various effects. For example, it is conceivable that by suppressing the sharp rise in current when turned on, the radiation noise from the semiconductor device can also be suppressed. However, in order to receive multiple types of control signals, the semiconductor device needs to have multiple types of control pads (gate pads). As a result, the effective area for the semiconductor device is greatly damaged. Summary of the invention

[0008] The present disclosure has been made to solve the above-mentioned problems, and one object of the present disclosure is to provide a semiconductor device capable of suppressing a sharp increase in current when the semiconductor device is turned on without significantly reducing the effective area of ​​the semiconductor device.

[0009] A semiconductor device in one form involved in the present disclosure is an insulated gate bipolar transistor or a reverse conducting insulated gate bipolar transistor, and the semiconductor device comprises: a semiconductor substrate including a drift layer having a first conductivity type; and a gate structure having a gate electrode and a gate insulating film for a switch of the semiconductor device. The plane layout on the semiconductor substrate has a distribution of threshold voltages for the switches. In the case where a histogram is defined by a plurality of boxes having a box width of 100 mV for the threshold voltage and a plurality of frequencies corresponding to the area of ​​each of the plurality of boxes in the plane layout, the plane layout has a plurality of regions belonging to different boxes in the plurality of boxes, the plurality of regions include the first to third regions, and the histogram has a distribution that continuously swings downward from the normal distribution to the low voltage side based on the normal distribution.

[0010] According to one aspect of the present disclosure, the histogram has a continuous distribution that is lower than the normal distribution toward the low voltage side. By utilizing this distribution, a sharp increase in current when the semiconductor device is turned on can be suppressed without significantly reducing the effective area of ​​the semiconductor device.

[0011] The objects, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a plan view for explaining the definition of a plurality of regions in a planar layout on a semiconductor substrate of a semiconductor device.

[0013] Figure 2 This is a graph showing a histogram of the distribution of the threshold voltage in the planar layout of the semiconductor device according to the first comparative example.

[0014] Figure 3 It is a plan view showing a structure of a planar layout on a semiconductor substrate of a semiconductor device according to a first comparative example.

[0015] Figure 4 This is a graph showing a histogram of the distribution of the threshold voltage in the planar layout of the semiconductor device according to the second comparative example.

[0016] Figure 5 This is a graph showing a histogram of the distribution of threshold voltages in the planar layout of the semiconductor device according to the first embodiment.

[0017] Figure 6 It is a plan view showing the structure of a planar layout on a semiconductor substrate of the semiconductor device involved in Embodiment 1 or 2.

[0018] Figure 7 Yes means Figure 6 A top view of a modified example of .

[0019] Figure 8 This is a graph showing an example of the transfer characteristic of the semiconductor device according to the first embodiment.

[0020] Fig. 9 This is a graph showing a histogram of the distribution of threshold voltages in the planar layout of the semiconductor device according to the second embodiment.

[0021] Fig.10 This is a graph showing an example of the transfer characteristics of the semiconductor device according to the second embodiment.

[0022] Fig.11 FIG. 1 is a cross-sectional view conceptually showing the structure of a typical insulated gate bipolar transistor.

[0023] Fig.12 This is a cross-sectional view showing the structure of an insulated gate bipolar transistor which is a semiconductor device according to the first or second embodiment.

[0024] Fig.13 Yes means Fig.12 A cross-sectional view of a modified example of .

[0025] Fig.14 Yes means Figure 6 A top view of a modified example of .

[0026] Fig.15 Yes means Figure 6 A top view of a modified example of .

[0027] Fig.16 Yes means Figure 6 A top view of a modified example of .

[0028] Fig.17 Yes means Figure 6 A top view of a modified example of .

[0029] Fig.18 It means along Fig.17 Line XVIII-XVIII is a graph of a conceivable example of the distribution of threshold voltages.

[0030] Description of Reference Numerals

[0031] 10...active IGBT cell region; 41...gate pad region; 42...gate wiring; 50...emitter electrode; 51...gate structure; 51a...gate electrode; 51b...gate insulating film; 52...n － Drift layer; 53, 53a, 53b...n + type source layer; 54, 54a~54d...p-type base layer; 56, 56a...charge storage layer; 59...lifetime control layer; 101, 101M, 102, 111~114...semiconductor device; RG1~RGn...first to nth regions; SB...semiconductor substrate. DETAILED DESCRIPTION

[0032] Hereinafter, the embodiment will be described based on the drawings. In the following drawings, the same reference numerals are given to the same or corresponding parts, and the description thereof will not be repeated.

[0033] In addition, although the following mainly describes the case where the first conductivity type is n-type and the second conductivity type is p-type, the first conductivity type may be p-type and the second conductivity type may be n-type. － " indicates a lower concentration than "n", "n + ” indicates that the impurity concentration is higher than “n”. Similarly, “p － " indicates that the impurity concentration is lower than "p", "p + ” indicates that the impurity concentration is higher than “p”.

[0034] In addition, although only the concentration of impurities that determine the conductivity type is mentioned in the following description, carbon, which is an element of the same group as silicon, which is the main component of the semiconductor, may also be contained. In addition, when the MCZ (Magnetic Field Applied Czochralski) method is applied, oxygen, boron or nitrogen introduced along with it may also be contained.

[0035] In addition, the following describes a case where the active cell region has regions RG1 to RGn (first to nth regions) corresponding to the distribution of the threshold voltage of the switch of the semiconductor device. The region that occupies the largest area ratio of the active cell region is called region RG1, and the other regions are called region RG2, region RG3, ... region RGn in order of the area ratio from large to small. In addition, regarding regions RG1 to RGn, the histogram is defined in detail as described later. Before describing the implementation method, first, the definitions of these regions in this specification are described. In addition, the threshold voltage can be specifically defined as the gate voltage required for a current of one ten-thousandth of the rated current density to pass when the rated voltage is applied between the collector and the emitter. In this case, for example, if the rated current density of the semiconductor device is 15A / cm 2 , the current density becomes 1.5 mA / cm 2 The gate voltage is the threshold voltage.

[0036] First, refer to Figure 1 The matters common to the present embodiment and comparative examples described below will be described. Figure 1 This is a top view for explaining the definition of a plurality of regions RG1 to RGn in the planar layout on the semiconductor substrate SB of the semiconductor device 100. The semiconductor device 100 is an insulated gate bipolar transistor (IGBT) or a reverse conducting insulated gate bipolar transistor (RC-IGBT). The planar layout of the semiconductor device 100 includes an active IGBT cell region 10, a terminal region 30, and a gate pad region 41. The semiconductor device 100 may have a diode region (not shown) in a region different from the active IGBT cell region 10.

[0037] The planar layout has a distribution of threshold voltages for switches of the semiconductor device 100. A plurality of bins are defined with a bin width of 100 mV (in other words, a representative value of ±50 mV) for the threshold voltage. The planar layout has a plurality of regions RG1 to RGn belonging to different bins of the plurality of bins. In other words, different regions belong to different bins, and one region belongs to one bin. A histogram (e.g., referring to Figure 2 ) is defined by these boxes and multiple frequencies corresponding to the area belonging to each of these multiple boxes in the plan layout.

[0038] In addition, when the box width is too small, the number of boxes required to express the distribution of the threshold voltage increases infinitely, and therefore, the number of regions also increases infinitely. On the contrary, when the box width is too large, the number of regions will be reduced to one in extreme cases regardless of the distribution of the threshold voltage. In the histogram under these inappropriate box widths, the distribution characteristics of the threshold voltage in the present embodiment described later cannot be properly evaluated. In order to clearly distinguish and evaluate this characteristic from the manufacturing deviation that was taken for granted in the past, it is necessary to appropriately select the box width. According to the research of the inventors, 100mV is one of the best values. Since the distribution range of the threshold voltage in the same substrate (in other words, the same chip) of a general IGBT that does not intend to have multiple threshold voltages is less than 100mV, by setting the box width to 100mV, it can be expected that the histogram of the general IGBT converges to less than two boxes (in other words, the voltage range ±100mV), and even if it is overestimated, it can be expected to converge to five boxes corresponding to the five regions RG1 to RG5.

[0039] Figure 2 : is a graph showing a histogram of the distribution of the threshold voltage Vth in the planar layout of the semiconductor device 100P according to the first comparative example. Figure 3 1 is a top view showing the structure of the planar layout on the semiconductor substrate SB of the semiconductor device 100P involved in the first comparative example. The semiconductor device 100P has a distribution of threshold voltages represented by five boxes corresponding to the five regions RG1 to RG5 as described above. In addition, the distribution of the histogram of the semiconductor device 100P is substantially a normal distribution PNM as a whole. Figure 2 The frequency of each box in the histogram of is equivalent to Figure 3 For example, in Figure 3 In the figure, region RG2 has 10 scattered small parts, the total area of ​​which is equivalent to Figure 2 The frequency of the box "5.85-5.94" [V]. Figure 3 As shown, the distribution of threshold voltages containing unintentional manufacturing deviations includes, for example, randomly dispersed areas with tiny portions. It is appropriate to evaluate the characteristic distribution of semiconductor devices in a planar layout in terms of unit cells of the semiconductor device. Therefore, if the area of ​​a unit cell is defined as a unit area, then when the above-mentioned tiny portion is composed of one unit cell, the area of ​​the tiny portion corresponds to the unit area. In addition, in the case where an island-shaped portion spanning multiple unit cells is formed by a collection of tiny portions, the area of ​​the tiny portion is a value obtained by multiplying the unit area by the number of multiple unit cells.

[0040] Figure 4It is a graph showing a histogram of the distribution of threshold voltages in the planar layout of the semiconductor device 100Q involved in the second comparative example. This can be considered to be equivalent to an example of simply applying the technology of the above-mentioned International Publication No. 2012 / 141121. Therefore, the semiconductor device 100Q is an example of a semiconductor device in which a plurality of regions with different threshold voltages are intentionally formed. Specifically, as shown in the figure, a large area A and a large area B are provided corresponding to each intended threshold voltage. In each large area A and large area B, due to manufacturing deviations, etc., there is actually a normal distribution. On the other hand, the distribution of large area A and the distribution of large area B are discontinuous. In other words, the distribution of large area A and the distribution of large area B do not overlap. Here, the so-called discontinuity (or, non-overlapping) means that a box with a frequency of zero is sandwiched between large area A and large area B.

[0041] Furthermore, as described above, when a histogram with an excessively wide bin width is used for evaluation, the distribution of the large area A and the distribution of the large area B can be continuous. Figure 4 The degree of separation of large area A and large area B by boxes with a frequency of zero as shown in the histogram is more of a designer's intention than a manufacturing deviation in the technical field of the present invention. In order to be able to properly evaluate such a feature, the evaluation was performed in this specification using a box width of 100 mV.

[0042] Figure 5 This is a graph showing a histogram of the distribution of threshold voltages in the planar layout of the semiconductor device 101 according to the first embodiment. Figure 6 1 is a plan view showing the structure of a planar layout on a semiconductor substrate SB of the semiconductor device 101 .

[0043] Histogram of the semiconductor device 101 ( Figure 5 ) includes a histogram ( Figure 2 ) The same essential normal distribution PNM (in Figure 5 Specifically, the histogram of the semiconductor device 101 has a distribution that is further deviated toward the low voltage side than the normal distribution PNM in addition to the normal distribution PNM, namely, a distribution that is further deviated toward the low voltage side, that is, a deviated distribution PFL (in Figure 5 In other words, the histogram has a swing-out distribution PFL that continuously swings out from the normal distribution PNM toward the low voltage side based on the normal distribution PNM. The semiconductor device 101 ( Figure 5 ) and the histogram of the semiconductor device 100Q ( Figure 4 ) is different from the histogram in that there are no bins with zero frequency between bins with non-zero frequency. Figure 5In the above example, the histogram distribution is formed by overlapping the low voltage side of the downswing drag distribution PFL with the normal distribution PNM. Therefore, the histogram is continuous.

[0044] Floor plan ( Figure 6 ) has the Figure 5 The eight regions RG1 to RG8 of different boxes among the multiple boxes shown. In addition, although the regions RG1 to RGn included in the planar layout are not limited to the eight regions RG1 to RG8, it is sufficient to include at least the regions RG1 to RG3, and preferably include the regions RG1 to RG6. This also applies to the second embodiment described later.

[0045] Figure 5 (as well as Fig. 9 The frequency of each box in the histogram (Implementation 2 described later) is equivalent to Figure 6 The areas of regions RG1 to RG8. Figure 6 In the semiconductor device 101 of the first embodiment shown in the figure, for example, the region RG2 has 16 dispersed micro-parts, and the total area of ​​these micro-parts is equivalent to Figure 5 The frequency of the box "5.85-5.94" [V]. In addition, Figure 7 As in the semiconductor device 101M of the illustrated modification, an island-shaped portion spanning a plurality of unit cells may be formed by a collection of minute portions.

[0046] exist Figure 5 In the example shown, the region RG8, which is the lowest voltage portion of the hem drag-out distribution PFL, does not overlap with the normal distribution PNM. Therefore, the lowest voltage portion of the distribution of the histogram is composed only of the hem drag-out distribution PFL. On the other hand, the region RG4, which is the lowest voltage portion of the normal distribution PNM, overlaps with the hem drag-out distribution PFL.

[0047] Reference Figure 8 , the solid line in the graph represents the semiconductor device 101 ( Figure 5 ) is an example of the transfer characteristics of the semiconductor device 100P ( Figure 2 ) is an example of a transfer characteristic. Semiconductor device 101 ( Figure 5 ) has a downward swing distribution PFL on the low voltage side, and the cells in the corresponding area become conductive first in the conduction operation. Therefore, compared with the semiconductor device 100P of the comparative example, the current starts to flow from a lower voltage. As the gate voltage increases, the reference Figure 5The current gradually increases by turning on regions RG8, RG6, RG5, RG4, and RG2 in this order, then increases sharply by turning on the largest region RG1, and then increases slightly by turning on regions RG3 and RG7 in this order, and reaches a saturation state. Figure 8 is an example. According to the design, the threshold voltage of the lower swing distribution PFL can also differ from the threshold voltage of the region RG1 by only 100mV. In this case, although it is difficult to observe Figure 8 Such a clear inflection point can achieve the effect of PFL dragging out the distribution of the hem.

[0048] According to the first embodiment, the histogram ( Figure 5 ) has a continuous distribution that is lower than the normal distribution toward the low voltage side. As a result, the sharp rise of the current when the semiconductor device 101 is turned on is suppressed. In other words, di / dt (time differential of current) can be reduced. Therefore, the radiation noise from the semiconductor device 101 can be suppressed. On the other hand, by making the active IGBT cell area 10 ( Figure 1 ) has a large enough proportion of the region RG1 with the largest area, which can avoid a significant increase in conduction loss caused by the lower swing dragging distribution PFL. Figure 5 The ratio of the total occupied area of ​​the other regions except the region RG1 to the occupied area of ​​the region RG1 may be, for example, 1:10 to 1:10. 7 Even if the ratio of the total occupied area of ​​the regions other than the region RG1 is suppressed to 1 / 10 7 Even such a small value can be obtained by applying the downswing draw distribution PFL. In a general IGBT with a saturation current of about several A, the downswing draw distribution PFL can flow 10 －7 The current is of the order of A (100 nA), so the presence of the pull-out distribution PFL can be easily determined from the waveform of the transfer characteristic.

[0049] Fig. 9 : is a graph showing a histogram of the distribution of threshold voltages in the planar layout of the semiconductor device 102 according to the second embodiment. Histogram of the semiconductor device 102 ( Fig. 9 ) includes a histogram ( Figure 2 ) The same substantial normal distribution PNM (in Fig. 9 Specifically, the histogram of the semiconductor device 102 has a distribution that is continuously shifted toward the high voltage side compared to the normal distribution PNM in addition to the normal distribution PNM, that is, the swing-out distribution PFH (in Fig. 9In other words, the histogram has a swing-out distribution PFH that continuously swings out from the normal distribution PNM toward the high voltage side based on the normal distribution PNM. The semiconductor device 102 ( Fig. 9 ) and the histogram of the semiconductor device 100Q ( Figure 4 ) is different from the histogram in that there are no bins with zero frequency between bins with non-zero frequency. Fig. 9 In the example, the histogram is formed by overlapping the high voltage side of the normal distribution PNM with the PFH distribution. Therefore, the histogram is continuous.

[0050] exist Fig. 9 In the example shown, the region RG8, which is the highest voltage portion of the hem drag-out distribution PFH, does not overlap with the normal distribution PNM. Therefore, the highest voltage portion of the distribution of the histogram is composed only of the hem drag-out distribution PFH. On the other hand, the region RG4, which is the highest voltage portion of the normal distribution PNM, overlaps with the hem drag-out distribution PFH.

[0051] Reference Fig.10 , the solid line in the graph represents the semiconductor device 102 ( Fig. 9 ) is an example of the transfer characteristics of the semiconductor device 100P ( Figure 2 ) is an example of a transfer characteristic. Semiconductor device 102 ( Fig. 9 ) has a downward swing distribution PFH on the high voltage side, and as a result, a waveform different from the dotted line (the semiconductor device 100P of the comparative example) appears near the saturation current. The cells in the corresponding area are turned off first in the shutdown operation. As a result, the sweeping out of carriers is promoted compared with the semiconductor device 100P of the comparative example.

[0052] According to the second embodiment, the histogram ( Fig. 9 ) has a continuous distribution that is lower than the normal distribution toward the high voltage side. This promotes the discharge of minority carriers when the semiconductor device 102 is turned off. Therefore, the turn-off loss of the semiconductor device 102 can be reduced. In addition, since the histogram of the threshold voltage is as follows Fig. 9 In the case of continuous changes as shown, it is difficult for the entire chip (in other words, one semiconductor substrate) constituting the semiconductor device 102 to be suddenly turned off, so that the effect of suppressing voltage surge can be obtained.

[0053] also, Fig. 9 The ratio of the total occupied area of ​​the hem drag-out distribution PFH to the total occupied area of ​​the normal distribution PNM can be, for example, 1:10 to 1:10. 7 When the hem is pulled out of the distribution, the ratio of the total occupied area of ​​PFH is suppressed to 1 / 10 7When the value is so small, it is sometimes difficult to determine whether the PFH is present or not by the transfer characteristic (see Fig.10 ) to judge. Even in this case, the presence or absence of the PFH can be judged by thermal analysis. Specifically, when the gate voltage is gradually increased by, for example, a few mV, if there is a region with a high threshold voltage inside the chip, only the amount of conduction in this part becomes low, thereby suppressing heat generation. That is, in the result of thermal analysis, a distribution is generated inside the chip. In general, thermal analysis is a technology that can analyze defective parts at the unit cell level, so even if there is only 1 / 10 7 Such a small area with a ratio can also distinguish areas with different threshold voltages. Therefore, heat analysis is a useful means to see whether the structure of embodiment 2 can be applied. Similarly, luminescence analysis is also a useful means. In addition, the same method can also be used to determine whether the structure of embodiment 1 can be applied.

[0054] Fig.11 The active IGBT cell region 10 of a semiconductor device corresponding to a typical trench gate IGBT is shown in FIG. Figure 1 ) is a cross-sectional view of a specific structure. This semiconductor device is different from the first or second embodiment in that each unit CM has substantially the same structure in design. If manufacturing variations are taken into account, the histogram of this semiconductor device is similar to that of the semiconductor device 100P ( Figure 2 ) similarly has a normal distribution PNM.

[0055] In semiconductor devices ( Fig.11 ) of the active IGBT cell region 10 (refer to Figure 1 ), the semiconductor substrate SB has an upper surface (first main surface) and a lower surface (second main surface). + Type source layer 53 and p + The contact layer 57 constitutes a portion of the upper surface of the semiconductor substrate SB. In addition, the p-type collector layer 55 constitutes at least a portion of the lower surface of the semiconductor substrate SB. － Drift layer 52. In n － There is an n-type electrode between the drift layer 52 and the p-type collector layer 55. + Buffer layer 58. In n － Between the drift layer 52 and the upper surface, n － The drift layer 52 includes a charge storage layer (CS layer) 56. The CS layer 56 has a higher impurity concentration than the drift layer 52. A p-type base layer 54 is included between the CS layer 56 and the upper surface. Each n + Type source layer 53 and p + Contact layer 57.

[0056] In addition, a gate structure 51 for switching the semiconductor device is provided on the semiconductor substrate SB so as to penetrate the p-type base layer 54 and the CS layer 56 from the upper surface. The gate structure 51 includes a gate electrode 51a and a gate insulating film 51b that are in contact with each other. The gate insulating film 51b is connected to the n-type base layer 54 in the groove in which the gate structure 51 is buried. － Drift layer 52, n + The gate insulating film 51b is, for example, an oxide film. In addition, an interlayer insulating film 60 is provided on the upper surface of the semiconductor substrate SB so that the gate electrode 51a is in contact with the emitter electrode (on the upper surface of the semiconductor substrate SB). Fig.11 A collector electrode (not shown) is provided on the lower surface of the semiconductor substrate SB.

[0057] By appropriately replacing a portion of the plurality of cells CM included in the semiconductor device described above with at least one cell having a different threshold voltage, the semiconductor device 101 or the semiconductor device 102 described above can be obtained. Fig.12 or Fig.13 The structure of this unit will be described.

[0058] Reference Fig.12 , and unit CM( Fig.11 ), the cells CL1-CL3 have lower threshold voltages, and the cells CH1-CH3 have higher threshold voltages.

[0059] The p-type base layer 54a of the cell CL1 has a larger Fig.11 ) has a lower impurity concentration in the p-type base layer 54. In contrast, the p-type base layer 54c of the cell CH1 has a lower impurity concentration than that of the cell CM ( Fig.11 ) has a high impurity concentration in the p-type base layer 54. By applying at least one of the cell CL1 and the cell CH1, the distribution of the threshold voltage of the semiconductor device can be controlled. In other words, the p-type base layer can have an impurity concentration distribution in the planar layout corresponding to the distribution of the threshold voltage required by the semiconductor device.

[0060] The p-type base layer 54b of the cell CL2 and the cell CM ( Fig.11 ) has a smaller depth from the upper surface of the semiconductor substrate SB than the p-type base layer 54 of the cell CH2. Fig.11 ) has a greater depth from the upper surface of the semiconductor substrate SB than the p-type base layer 54 of the semiconductor substrate SB. By applying at least one of the unit CL2 and the unit CH2, the distribution of the threshold voltage of the semiconductor device can be controlled. In other words, the p-type base layer can have a depth distribution in the planar layout corresponding to the distribution of the threshold voltage required by the semiconductor device.

[0061] Unit CL3 n + Type source layer 53a and unit CM ( Fig.11 ) + The depth from the upper surface of the semiconductor substrate SB is greater than that of the n-type source layer 53. + Type source layer 53b and unit CM ( Fig.11 ) + The depth from the upper surface of the semiconductor substrate SB is smaller than that of the type source layer 53. By applying at least one of the unit CL3 and the unit CH3, the distribution of the threshold voltage of the semiconductor device can be controlled. In other words, n + The type source layer can have a depth distribution in a planar layout according to the distribution of threshold voltages required for the semiconductor device.

[0062] In addition, the threshold voltage of the cell can be reduced by reducing the thickness of the gate insulating film 51b, and can be increased by increasing the thickness of the gate insulating film 51b. By applying such a cell, the distribution of the threshold voltage of the semiconductor device can be controlled. In other words, the gate insulating film 51b can have a thickness distribution in the planar layout corresponding to the distribution of the threshold voltage.

[0063] In addition, the threshold voltage of the cell can also be controlled by the surface orientation of the channel of the gate structure 51. This is described below. The p-type base layer 54 of the semiconductor substrate SB has a portion facing the gate structure 51 on the inner wall of the trench as a channel region. The threshold voltage has a dependency on the surface orientation of this portion (when the semiconductor substrate SB is a Si substrate, it is the crystallographic surface orientation of Si). Therefore, by applying the surface orientation of this portion and the cell CM ( Fig.11 ) different units, the distribution of the threshold voltage of the semiconductor device can be controlled. In other words, the portion of the p-type base layer 54 facing the gate structure 51 can have a surface orientation distribution in the planar layout corresponding to the distribution of the threshold voltage.

[0064] In addition, the threshold voltage of the cell can also be controlled by the internal stress of the semiconductor substrate SB. In other words, the semiconductor substrate SB can have an internal stress distribution in the plane layout corresponding to the distribution of the threshold voltage. In general, it is known that the internal stress inherent in the channel region of a semiconductor is related to the interatomic distance. When the interatomic distance changes, the band gap changes, and thus the threshold voltage is easily changed. As a method for controlling internal stress, heat treatment for alleviating ion implantation damage, formation conditions of the gate oxide film, film type or formation conditions of the interlayer insulating film, formation conditions of the emitter electrode, formation conditions of the glass coating film, or formation conditions of the polyimide coating film can be listed. Here, the formation conditions of each element are, for example, the temperature during formation, the formation speed, the film thickness, or the conditions of the heat treatment after formation.

[0065] Fig.13 Yes means Fig.12 sectional views of the cells CL11 to CL13 and the cells CH11 to CH13 which are respective modified examples of the cells CL1 to CL3 and the cells CH1 to CH3.

[0066] exist Fig.13 In the example shown, the drift layer 52 of the semiconductor substrate SB includes the lifetime control layer 52L in the cells CH11 to CH13. Therefore, in the semiconductor device to which the cells CH11 to CH13 are applied, the plurality of regions RG1 to RGn may include regions where the lifetime control layer 52L is disposed and regions where the lifetime control layer 52L is not disposed. By appropriately providing the lifetime control layer 52L, the discharge of minority carriers becomes smoother and the turn-off loss is further reduced.

[0067] In addition, Fig.13 In the example shown, the charge storage layer 56 ( Fig.12 Specifically, the charge storage layer 56a of the cells CL11 to CL13 has the same structure as the cell CM ( Fig.11 ) has different impurity concentrations in the charge storage layer 56. Therefore, in the semiconductor device using the units CL11 to CL13, the plurality of regions RG1 to RGn may have differences in the impurity concentrations in the charge storage layer. Thus, by adjusting the impurity concentration distribution of the charge storage layer, the discharge of minority carriers becomes smoother and the turn-off loss is reduced.

[0068] Furthermore, as described above, by applying the unit CM ( Fig.11 ) At least one of the above-mentioned various units having different threshold voltages can obtain the above-mentioned semiconductor device 101 or semiconductor device 102. In addition, a unit having the characteristics of two or more units among these various units can also be applied.

[0069] Fig.14Yes means Figure 6 A top view of the structure of the planar layout on the semiconductor substrate SB of the semiconductor device 111 according to the modified example. In the semiconductor device 111, the largest region RG1 among the multiple regions RG1 to RGn (regions RG1 and RG2 in the example shown in the figure) of the planar layout includes the center of the semiconductor substrate SB. The region RG2 roughly surrounds the region RG1. In the example shown in the figure, the region RG2 and the gate pad region 41 surround the region RG1.

[0070] The advantages of the semiconductor device 111 will be described below by dividing into cases where the threshold voltage of the region RG1 is higher and lower than that of the region RG2 .

[0071] First, when the threshold voltage in the region RG1 is relatively high, the turn-off loss in the center of the semiconductor substrate SB can be reduced. The IGBT in stable operation generally accumulates the most heat in the center of the chip, so by reducing the turn-off loss in the center, the heat distribution in the semiconductor device 111 can be made uniform. The effect of this uniformization is particularly significant during high-speed switching. By making the heat distribution uniform, the wear life of the semiconductor device 111 is improved.

[0072] Second, when the threshold voltage in the region RG1 is relatively low, the distance from the gate wiring 42 (see Fig.15 ) is easily far away. Generally speaking, the gate signal of the IGBT tends to be delayed in reaching the center of the semiconductor substrate SB. Therefore, the delay can be offset by designing the threshold voltage of the region RG1 located in the center of the semiconductor substrate SB to be low. Therefore, uniform switching can be performed on the entire chip. As a result, an increase in short-circuit tolerance can be expected.

[0073] Therefore, according to the semiconductor device 111 , in either case where the threshold voltage of the region RG1 is higher or lower than the threshold voltage of the region RG2 , one of the above-mentioned two effects can be obtained.

[0074] Fig.15 Yes means Figure 6 FIG. 1 is a top view of a structure of a planar layout on a semiconductor substrate SB of a semiconductor device 112 according to a modified example of FIG. The semiconductor device 112 has a gate wiring 42 provided on the semiconductor substrate SB. The gate wiring 42 is used to apply a potential applied to the gate pad region 41 for switching to the gate electrode 51a (see FIG. 1 ). Fig.11 ). The gate wiring 42 includes a Fig.15The boundary between mutually adjacent regions in the plurality of regions RG1 to RG3 in the planar layout, in other words, the boundary between region RG1 and region RG2 and the boundary between region RG2 and region RG3, includes the boundary along the above-mentioned one direction ( Fig.15 The longitudinally extending portion of the

[0075] According to this variation, when the boundary between mutually adjacent regions in the plurality of regions RG1 to RG3 in the planar layout includes a portion extending in one direction, the configuration of the plurality of regions RG1 to RG3 becomes a configuration corresponding to the distance from the portion extending in one direction of the gate wiring. In this case, if the threshold voltage distribution is higher the farther from the portion of the gate wiring, the switching of the region far from the portion of the gate wiring is further delayed, thereby further reducing the turn-off loss. If the threshold voltage distribution is lower the farther from the portion of the gate wiring, the timing of the switching in the chip can be made more uniform.

[0076] Specifically, the semiconductor substrate SB has a substantially rectangular shape, and at least a portion of the above-mentioned boundary is along its long side or short side (in Fig.15 The gate wiring 42 is generally arranged in parallel with the long side or the short side of the chip. The gate signal sent from the gate wiring 42 generally has the characteristic of arriving early near the gate wiring 42 and arriving late far from the gate wiring 42. This characteristic is related to the effect of suppressing turn-off loss. Therefore, if the distribution of the threshold voltage is set so that the threshold voltage is higher as the distance from the gate wiring 42 increases, the above effect can be further improved. On the contrary, if the distribution of the threshold voltage is set so that the threshold voltage is lower as the distance from the gate wiring 42 increases, uniform switching can be performed within the chip by offsetting the delay in signal transmission that depends on the distance from the gate wiring 42.

[0077] The semiconductor device 112 is designed to be connected to the main portion of the gate wiring 42 (in Fig.15 The above effect is obtained by adjusting the distribution of threshold voltages corresponding to the distance of the portion extending in the longitudinal direction. The above boundary is substantially along the above long side or short side (more generally, the above one direction) to a sufficient extent to obtain the above effect. The above one direction is not necessarily limited to the direction along the long side or short side of the semiconductor substrate SB. For example, the above one direction may be the extension direction of the terminal electrode pattern on the semiconductor substrate SB.

[0078] Fig.16 Yes means Figure 6A top view of the structure of the planar layout on the semiconductor substrate SB of the semiconductor device 113 involved in the modification example. Among them, for the emitter electrode 50 arranged on the semiconductor substrate SB, only its edge is represented by a double-dashed line. The multiple regions RG1~RGn possessed by the planar layout include the largest region RG1 and the region RG2 (more generally, at least one region) having a higher threshold voltage than the region RG1. In the planar layout, at least a portion of the edge of the emitter electrode 50 is configured in the region RG2. As shown in the figure, substantially all of the edge of the emitter electrode 50 can be configured in the region RG2. In addition, the region RG2 (more generally, at least one region other than the region RG1) can extend in a manner along the edge of the emitter electrode 50.

[0079] According to this modification, short circuit tolerance can be increased. Generally, short circuit failure tends to occur at the edge of the emitter electrode 50 where current concentrates. Therefore, by forming the region RG2 having a high threshold voltage along the edge of the emitter electrode 50, current concentration during short circuit can be suppressed.

[0080] Fig.17 Yes means Figure 6 A top view of a planar layout structure on a semiconductor substrate SB of a semiconductor device 114 according to a modified example of FIG. In the planar layout, the semiconductor substrate SB is in a rectangular shape having long sides and short sides. In the planar layout, the boundary between mutually adjacent regions in the plurality of regions RG1 to RGn extends along at least a portion of an ellipse. The major axis of the ellipse extends along the short side ( Fig.17 Therefore, the ellipse has a pair of foci (not shown) facing each other in the direction along the short side.

[0081] In addition, the boundary between mutually adjacent regions in the plurality of regions RG1 to RGn may substantially extend along at least a portion of an ellipse, and need not be completely along a geometrically accurate ellipse. The ellipse is a closed curve shape that is line-symmetric about the X direction and the Y direction in the XY coordinate system in the plane layout. Therefore, the boundary is also substantially line-symmetric about the X direction and the Y direction. The axis of line symmetry passes through the approximate center of the semiconductor substrate SB.

[0082] Fig.17 Such regions RG1 to RGn can be obtained by warping of the substrate. Fig.18 It means along Fig.17A graph of a conceivable example of the distribution of the threshold voltage Vth along the line XVIII-XVIII. The solid line of the graph is a line that assumes the measurement result of the warpage of the semiconductor substrate SB and converts it into Vth. The range NA is different from the area outside the active unit in the semiconductor substrate SB. In addition, a conceivable measurement deviation DM is also shown. The dotted line of the graph is an approximate line excluding the influence of the range NA and the measurement deviation DM. According to the approximate line, the distribution of the threshold voltage along the long side direction of the chip has a symmetry axis approximately in the center of the semiconductor substrate SB. In addition, although the illustration is omitted, the distribution of the threshold voltage along the short side direction of the chip also has a symmetry axis approximately in the center of the semiconductor substrate SB.

[0083] Furthermore, the various embodiments may be freely combined, or may be appropriately modified or omitted.

[0084] <Note>

[0085] Hereinafter, various aspects of the present disclosure are collectively described as supplementary notes.

[0086] (Supplementary Note 1) A semiconductor device, the semiconductor device being an insulated gate bipolar transistor or a reverse conducting insulated gate bipolar transistor, wherein:

[0087] The semiconductor device comprises:

[0088] a semiconductor substrate including a drift layer having a first conductivity type; and

[0089] A gate structure comprising a gate electrode for switching the semiconductor device and a gate insulating film,

[0090] The planar layout on the semiconductor substrate has a distribution of threshold voltages for the switches.

[0091] In a case where a histogram is defined by a plurality of boxes having a box width of 100 mV for the threshold voltage and a plurality of frequencies corresponding to an area of ​​each of the plurality of boxes in the planar layout, the planar layout has a plurality of regions belonging to different boxes among the plurality of boxes, the plurality of regions include a first region to a third region, and the histogram has a distribution that continuously swings downward from the normal distribution toward a low voltage side based on a normal distribution.

[0092] (Supplementary Note 2) A semiconductor device, the semiconductor device being an insulated gate bipolar transistor or a reverse conducting insulated gate bipolar transistor, wherein:

[0093] The semiconductor device comprises:

[0094] a semiconductor substrate including a drift layer having a first conductivity type; and

[0095] A gate structure comprising a gate electrode for switching the semiconductor device and a gate insulating film,

[0096] The planar layout on the semiconductor substrate has a distribution of threshold voltages for the switches.

[0097] In a case where a histogram is defined by a plurality of boxes having a box width of 100 mV for the threshold voltage and a plurality of frequencies corresponding to an area of ​​each of the plurality of boxes in the planar layout, the planar layout has a plurality of regions belonging to different boxes among the plurality of boxes, the plurality of regions include a first region to a third region, and the histogram has a distribution that continuously swings downward from the normal distribution toward a high voltage side based on a normal distribution.

[0098] (Supplementary Note 3) The semiconductor device according to Supplementary Note 1 or 2, wherein:

[0099] The semiconductor substrate further includes a base layer having a second conductivity type different from the first conductivity type.

[0100] The base layer has an impurity concentration distribution in the planar layout corresponding to the distribution of the threshold voltage.

[0101] (Supplement 4) The semiconductor device according to Supplement 1 or 2, wherein:

[0102] The semiconductor substrate further includes a base layer having a second conductivity type different from the first conductivity type.

[0103] The base layer has a depth distribution in the planar layout corresponding to the distribution of the threshold voltage.

[0104] (Supplementary Note 5) The semiconductor device according to Supplementary Note 1 or 2, wherein:

[0105] The semiconductor substrate further includes a source layer having the first conductivity type.

[0106] The source layer has a depth distribution in the planar layout corresponding to the distribution of the threshold voltage.

[0107] (Supplementary Note 6) The semiconductor device according to Supplementary Note 1 or 2, wherein:

[0108] The gate insulating film has a thickness distribution in the planar layout corresponding to the distribution of the threshold voltage.

[0109] (Supplementary Note 7) The semiconductor device according to Supplementary Note 1 or 2, wherein:

[0110] The semiconductor substrate is provided with a trench in which the gate structure is buried.

[0111] The semiconductor substrate further includes a base layer having a second conductivity type different from the first conductivity type and having a portion facing the gate structure, wherein the portion facing the gate structure has a surface orientation distribution in the planar layout corresponding to the distribution of the threshold voltage.

[0112] (Supplementary Note 8) The semiconductor device according to any one of Supplementary Notes 1 to 7, wherein:

[0113] The largest region among the plurality of regions in the planar layout includes a center of the semiconductor substrate.

[0114] (Supplementary Note 9) The semiconductor device according to any one of Supplementary Notes 1 to 7, wherein:

[0115] A gate wiring is provided on the semiconductor substrate, includes a portion extending in one direction, and is used to apply the switching potential to the gate electrode.

[0116] The boundary between mutually adjacent regions among the plurality of regions in the planar layout includes a portion extending along the one direction.

[0117] (Supplementary Note 10) The semiconductor device according to any one of Supplementary Notes 1 to 7, wherein:

[0118] An emitter electrode having an edge is further provided on the semiconductor substrate.

[0119] The plurality of regions include a first region which is the largest among the plurality of regions, and at least one region having a threshold voltage higher than that of the first region.

[0120] In the planar layout, at least a portion of the edge of the emitter electrode is arranged in the at least one region.

[0121] (Supplement 11) The semiconductor device according to any one of Supplements 1 to 7, wherein

[0122] In the above-mentioned planar layout, the above-mentioned semiconductor substrate has a rectangular shape having long sides and short sides.

[0123] In the planar layout, a boundary between mutually adjacent regions among the plurality of regions extends along at least a portion of an ellipse having a major axis along the short side of the rectangular shape.

[0124] (Supplementary Note 12) A semiconductor device, the semiconductor device being an insulated gate bipolar transistor or a reverse conducting insulated gate bipolar transistor, wherein:

[0125] The semiconductor device comprises:

[0126] a semiconductor substrate including a drift layer having a first conductivity type; and

[0127] A gate structure comprising a gate electrode for switching the semiconductor device and a gate insulating film,

[0128] The planar layout on the semiconductor substrate has a distribution of threshold voltages for the switches.

[0129] In the case where a plurality of bins having a bin width of 100 mV for the threshold voltage are defined, the planar layout has a plurality of regions belonging to different bins among the plurality of bins,

[0130] The largest region among the plurality of regions in the planar layout includes a center of the semiconductor substrate.

[0131] (Supplementary Note 13) A semiconductor device, the semiconductor device being an insulated gate bipolar transistor or a reverse conducting insulated gate bipolar transistor, wherein:

[0132] The semiconductor device comprises:

[0133] a semiconductor substrate including a drift layer having a first conductivity type; and

[0134] A gate structure having a gate electrode and a gate insulating film for switching the semiconductor device; and

[0135] a gate wiring, which is provided on the semiconductor substrate, includes a portion extending in one direction and is used to apply the potential for the switch to the gate electrode,

[0136] The planar layout on the semiconductor substrate has a distribution of threshold voltages for the switches.

[0137] In the case where a plurality of bins having a bin width of 100 mV for the threshold voltage are defined, the planar layout has a plurality of regions belonging to different bins among the plurality of bins,

[0138] The boundary between mutually adjacent regions among the plurality of regions in the planar layout includes a portion extending along the one direction.

[0139] (Supplementary Note 14) A semiconductor device, the semiconductor device being an insulated gate bipolar transistor or a reverse conducting insulated gate bipolar transistor, wherein:

[0140] The semiconductor device comprises:

[0141] a semiconductor substrate including a drift layer having a first conductivity type; and

[0142] A gate structure comprising a gate electrode for switching the semiconductor device and a gate insulating film,

[0143] An emitter electrode having an edge is further provided on the semiconductor substrate.

[0144] The planar layout on the semiconductor substrate has a distribution of threshold voltages for the switches.

[0145] In the case where a plurality of bins having a bin width of 100 mV for the threshold voltage are defined, the planar layout has a plurality of regions belonging to different bins among the plurality of bins,

[0146] The plurality of regions include a first region which is the largest among the plurality of regions, and at least one region having a threshold voltage higher than that of the first region.

[0147] In the planar layout, at least a portion of the edge of the emitter electrode is arranged in the at least one region.

[0148] (Supplementary Note 15) A semiconductor device, the semiconductor device being an insulated gate bipolar transistor or a reverse conducting insulated gate bipolar transistor, wherein:

[0149] The semiconductor device comprises:

[0150] a semiconductor substrate including a drift layer having a first conductivity type; and

[0151] A gate structure comprising a gate electrode for switching the semiconductor device and a gate insulating film,

[0152] The planar layout on the semiconductor substrate has a distribution of threshold voltages for the switches.

[0153] In the case where a plurality of bins having a bin width of 100 mV for the threshold voltage are defined, the planar layout has a plurality of regions belonging to different bins among the plurality of bins,

[0154] An emitter electrode having an edge is further provided on the semiconductor substrate.

[0155] The plurality of regions include the largest region and at least one region among the plurality of regions,

[0156] In the above-mentioned planar layout, the above-mentioned semiconductor substrate has a rectangular shape having long sides and short sides.

[0157] In the planar layout, a boundary between mutually adjacent regions among the plurality of regions extends along at least a portion of an ellipse having a major axis along the short side of the rectangular shape.

[0158] (Supplement 16) The semiconductor device according to any one of Supplements 1, 2, and 12 to 15, wherein:

[0159] The semiconductor substrate has an internal stress distribution in the planar layout corresponding to the distribution of the threshold voltage.

[0160] (Supplementary Note 17) The semiconductor device according to any one of Supplementary Notes 1 to 16, wherein

[0161] The semiconductor substrate further includes a charge storage layer on the drift layer, the charge storage layer having the first conductivity type and having a higher impurity concentration than the drift layer.

[0162] The plurality of regions include a plurality of regions having different impurity concentrations in the charge storage layer.

[0163] (Supplementary Note 18) The semiconductor device according to any one of Supplementary Notes 1 to 16, wherein

[0164] The drift layer of the semiconductor substrate includes a lifetime control layer.

[0165] The plurality of regions include a region where the lifetime control layer is arranged and a region where the lifetime control layer is not arranged.

Claims

1. A semiconductor device, the semiconductor device being an insulated gate bipolar transistor or a reverse conducting insulated gate bipolar transistor, wherein: The semiconductor device comprises: A semiconductor substrate including a drift layer having a first conductivity type; and A gate structure comprising a gate electrode and a gate insulating film for switching the semiconductor device. The planar layout on the semiconductor substrate has a distribution of threshold voltages for the switches, In a case where a histogram is defined by a plurality of boxes having a box width of 100 mV for the threshold voltage and a plurality of frequencies corresponding to an area of ​​the planar layout belonging to each of the plurality of boxes, the planar layout has a plurality of regions belonging to different boxes of the plurality of boxes, the plurality of regions including a first region to a third region, and the histogram has a distribution that continuously swings downward from the normal distribution to a low voltage side or a high voltage side based on a normal distribution.

2. The semiconductor device according to claim 1, wherein The semiconductor substrate further includes a base layer having a second conductivity type different from the first conductivity type, The base layer has an impurity concentration distribution in the planar layout corresponding to the distribution of the threshold voltage.

3. The semiconductor device according to claim 1, wherein The semiconductor substrate further includes a base layer having a second conductivity type different from the first conductivity type, The base layer has a depth distribution in the planar layout corresponding to the distribution of the threshold voltage.

4. The semiconductor device according to claim 1, wherein The semiconductor substrate further includes a source layer having the first conductivity type, The source layer has a depth distribution in the planar layout corresponding to the distribution of the threshold voltage.

5. The semiconductor device according to claim 1, wherein The gate insulating film has a thickness distribution in the planar layout corresponding to the distribution of the threshold voltage.

6. The semiconductor device according to claim 1, wherein The semiconductor substrate is provided with a trench in which the gate structure is buried. The semiconductor substrate further includes a base layer having a second conductivity type different from the first conductivity type and having a portion facing the gate structure, the portion facing the gate structure having a surface orientation distribution in the planar layout corresponding to the distribution of the threshold voltage.

7. The semiconductor device according to claim 1, wherein The largest region among the plurality of regions of the planar layout includes the center of the semiconductor substrate.

8. The semiconductor device according to any one of claims 1 to 6, wherein A gate wiring is provided on the semiconductor substrate, includes a portion extending in one direction, and is used to apply a potential for the switch to the gate electrode. A boundary between mutually adjacent regions among the plurality of regions of the planar layout includes a portion extending along the one direction.

9. The semiconductor device according to any one of claims 1 to 6, wherein: An emitter electrode having an edge is also provided on the semiconductor substrate. The plurality of regions include a first region that is the largest among the plurality of regions, and at least one region having the threshold voltage higher than that of the first region, In the planar layout, at least a portion of the edge of the emitter electrode is arranged in the at least one region.

10. The semiconductor device according to any one of claims 1 to 6, wherein In the planar layout, the semiconductor substrate has a rectangular shape having long sides and short sides, In the planar layout, a boundary between mutually adjacent regions among the plurality of regions extends along at least a portion of an ellipse having a major axis along the short side of the rectangular shape.

11. A semiconductor device, the semiconductor device being an insulated gate bipolar transistor or a reverse conducting insulated gate bipolar transistor, wherein: The semiconductor device comprises: A semiconductor substrate including a drift layer having a first conductivity type; and A gate structure comprising a gate electrode and a gate insulating film for switching the semiconductor device. The planar layout on the semiconductor substrate has a distribution of threshold voltages for the switches, In a case where a plurality of bins having a bin width of 100 mV for the threshold voltage is defined, the planar layout has a plurality of regions belonging to different bins of the plurality of bins, The largest region among the plurality of regions of the planar layout includes the center of the semiconductor substrate.

12. A semiconductor device, the semiconductor device being an insulated gate bipolar transistor or a reverse conducting insulated gate bipolar transistor, wherein: The semiconductor device comprises: A semiconductor substrate including a drift layer having a first conductivity type; and A gate structure having a gate electrode and a gate insulating film for switching the semiconductor device; as well as a gate wiring, which is provided on the semiconductor substrate, includes a portion extending in one direction and is used to apply a potential for the switch to the gate electrode, The planar layout on the semiconductor substrate has a distribution of threshold voltages for the switches, In a case where a plurality of bins having a bin width of 100 mV for the threshold voltage is defined, the planar layout has a plurality of regions belonging to different bins of the plurality of bins, A boundary between mutually adjacent regions among the plurality of regions of the planar layout includes a portion extending along the one direction.

13. A semiconductor device, the semiconductor device being an insulated gate bipolar transistor or a reverse conducting insulated gate bipolar transistor, wherein: The semiconductor device comprises: A semiconductor substrate including a drift layer having a first conductivity type; and A gate structure comprising a gate electrode and a gate insulating film for switching the semiconductor device. An emitter electrode having an edge is also provided on the semiconductor substrate. The planar layout on the semiconductor substrate has a distribution of threshold voltages for the switches, In a case where a plurality of bins having a bin width of 100 mV for the threshold voltage is defined, the planar layout has a plurality of regions belonging to different bins of the plurality of bins, The plurality of regions include a first region that is the largest among the plurality of regions, and at least one region having the threshold voltage higher than that of the first region, In the planar layout, at least a portion of the edge of the emitter electrode is arranged in the at least one region.

14. A semiconductor device, the semiconductor device being an insulated gate bipolar transistor or a reverse conducting insulated gate bipolar transistor, wherein: The semiconductor device comprises: A semiconductor substrate including a drift layer having a first conductivity type; and A gate structure comprising a gate electrode and a gate insulating film for switching the semiconductor device. The planar layout on the semiconductor substrate has a distribution of threshold voltages for the switches, In a case where a plurality of bins having a bin width of 100 mV for the threshold voltage is defined, the planar layout has a plurality of regions belonging to different bins of the plurality of bins, An emitter electrode having an edge is also provided on the semiconductor substrate. The plurality of regions include a largest region and at least one region among the plurality of regions, In the planar layout, the semiconductor substrate has a rectangular shape having long sides and short sides, In the planar layout, a boundary between mutually adjacent regions among the plurality of regions extends along at least a portion of an ellipse having a major axis along the short side of the rectangular shape.

15. The semiconductor device according to any one of claims 1 and 11 to 14, wherein: The semiconductor substrate has an internal stress distribution in the planar layout corresponding to the distribution of the threshold voltage.

16. The semiconductor device according to any one of claims 1 to 15, wherein The semiconductor substrate further includes a charge storage layer on the drift layer, the charge storage layer having the first conductivity type and having a higher impurity concentration than the drift layer, The plurality of regions include a plurality of regions having differences in impurity concentration of the charge storage layer.

17. The semiconductor device according to any one of claims 1 to 15, wherein: The drift layer of the semiconductor substrate includes a lifetime control layer, The plurality of regions include a region where the lifetime control layer is arranged and a region where the lifetime control layer is not arranged.

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