Display chip and manufacturing method thereof

Abstract

The present invention discloses a display chip and a manufacturing method thereof. The display chip comprises at least two stacked light-emitting units, wherein the light-emitting units comprise stacked N-type conductive contact layers, light-emitting functional layers and P-type conductive contact layers; in the light-emitting units, at least one P-type conductive contact layer is provided with a tunnel junction on a side away from the light-emitting functional layer; the tunnel junction comprises stacked p-type doping layers, multiple aluminum gallium nitride insertion layers and n-type doping layers; the N-type conductive contact layer of one light-emitting unit is arranged adjacent to the n-type doping layer, and the P-type conductive contact layer of another light-emitting unit is arranged adjacent to the p-type doping layer; along the direction from the n-type doping layer to the p-type doping layer, the aluminum doping concentration of at least part of the aluminum gallium nitride insertion layer gradually increases. The light-emitting efficiency of the display chip is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of display technology, and in particular to a display chip and a manufacturing method thereof. Background Art

[0002] Light Emitting Diode (LED) has the advantages of high brightness, low voltage, low power consumption, long life, impact resistance and stable performance, making it more and more widely used in the display field. Micro-LED, or micro light-emitting diode, is a traditional LED with its size further reduced to the micron level. Micro-LED display technology refers to a display technology that uses self-luminous micron-level LEDs as light-emitting pixel units, assembles them on a display substrate, and arranges red, blue and green micro light-emitting diodes that can emit light independently in an array to form a high-density LED array. Due to the small size, high integration and self-luminescence of micro light-emitting diode chips, micro light-emitting diodes have greater advantages in brightness, resolution, contrast, energy consumption, service life, response speed and thermal stability compared with liquid crystal displays (LCD) and organic light-emitting diodes (OLED).

[0003] In the prior art, the luminous efficiency of vertically stacked Micro-LED chips is low and the turn-on voltage is relatively high, which reduces the performance of the Micro-LED chips. Summary of the invention

[0004] The present invention provides a display chip and a manufacturing method thereof, so as to improve the luminous efficiency of the display chip, reduce the start-up voltage of the display chip, and improve the performance of the display chip.

[0005] In a first aspect, an embodiment of the present invention provides a display chip, comprising at least two stacked light-emitting units, the light-emitting units comprising a stacked N-type conductive contact layer, a light-emitting functional layer and a P-type conductive contact layer; in the light-emitting units, at least one of the P-type conductive contact layers is provided with a tunnel junction on a side away from the light-emitting functional layer; the tunnel junction comprises a stacked p-type doped layer, a plurality of aluminum gallium nitride insertion layers and an n-type doped layer; the N-type conductive contact layer of one light-emitting unit is adjacent to the n-type doped layer, and the P-type conductive contact layer of another light-emitting unit is adjacent to the p-type doped layer; along the direction from the n-type doped layer to the p-type doped layer, the aluminum doping concentration of at least part of the aluminum gallium nitride insertion layer gradually increases.

[0006] Optionally, the multiple layers of aluminum gallium nitride insertion layers include a first group of aluminum gallium nitride insertion layers and a second group of aluminum gallium nitride insertion layers, and the first group of aluminum gallium nitride insertion layers are arranged on a side of the second group of aluminum gallium nitride insertion layers close to the n-type doped layer; along the direction from the n-type doped layer to the p-type doped layer, the aluminum doping concentration of the first group of aluminum gallium nitride insertion layers gradually increases, and the aluminum doping concentration of the second group of aluminum gallium nitride insertion layers gradually decreases.

[0007] Optionally, the thickness of the first group of aluminum gallium nitride insertion layers is greater than the thickness of the second group of aluminum gallium nitride insertion layers.

[0008] Optionally, the first group of aluminum gallium nitride insertion layers includes a first Al2O3 layer stacked in sequence along a direction from the n-type doped layer to the p-type doped layer. x1 Ga y1 N insertion layer, second Al x2 Ga y2 N insertion layer and the third Al x3 Ga y3 N insertion layer, the second group of aluminum gallium nitride insertion layers includes a fourth Al x4 Ga y4 N insertion layers, where x1<x2, x2<x3, x4<x3, x1+y1=1, x2+y2=1, x3+y3=1, x4+y4=1.

[0009] Optionally, x1=0.2, x2=0.4, x3=0.6, x4=0.3.

[0010] Optionally, the overall thickness of the multiple layers of the aluminum gallium nitride insertion layer is less than or equal to 7.5 nm.

[0011] Optionally, the thickness of each aluminum gallium nitride insertion layer is in the range of 0.4-2 nm.

[0012] Optionally, the material of the p-type doping layer includes p-type gallium nitride, and the material of the n-type doping layer includes n-type gallium nitride.

[0013] Optionally, the light emitting colors of different light emitting units are the same or different.

[0014] In a second aspect, an embodiment of the present invention further provides a method for manufacturing a display chip, comprising:

[0015] Growing a p-type doped layer on a p-type conductive contact layer of a light-emitting unit; the light-emitting unit comprises an n-type conductive contact layer, a light-emitting functional layer and a p-type conductive contact layer which are stacked;

[0016] Growing multiple aluminum gallium nitride insertion layers on the p-type doped layer; along the direction from the n-type doped layer to the p-type doped layer, the aluminum doping concentration of at least part of the aluminum gallium nitride insertion layer gradually increases;

[0017] Growing the n-type doped layer on the multi-layer aluminum gallium nitride insertion layer;

[0018] Another light emitting unit is grown on the n-type doped layer.

[0019] The technical solution of the embodiment of the present invention can reduce the light absorption rate of the tunnel junction and improve the luminous efficiency of the display chip by arranging an aluminum gallium nitride insertion layer between the p-type doping layer and the n-type doping layer. At the same time, the current diffusion and hole injection efficiency of the tunnel junction can be improved, which is conducive to improving the tunneling probability of the tunnel junction. The contact interface between the aluminum gallium nitride insertion layer and the p-type doping layer, and the contact interface between the aluminum gallium nitride insertion layer and the n-type doping layer can form a high concentration of two-dimensional electron gas and two-dimensional hole gas, which can improve the contact performance of the aluminum gallium nitride insertion layer with the p-type doping layer and the n-type doping layer, respectively, and can improve the performance of the display chip. Moreover, along the direction from the n-type doping layer to the p-type doping layer, the aluminum doping concentration of at least part of the aluminum gallium nitride insertion layer gradually increases, so that the stress of the multi-layer aluminum gallium nitride insertion layer is compressive stress, so that the internal polarization electric field direction of the multi-layer aluminum gallium nitride insertion layer can be the same as the built-in electric field direction. This is conducive to improving the quantum tunneling probability of the tunnel junction, thereby improving the carrier transport efficiency of the p-type doping layer and improving the luminous efficiency of the display chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of the structure of a display chip provided by an embodiment of the present invention;

[0021] Figure 2 A schematic diagram of the structure of a tunnel junction provided by an embodiment of the present invention;

[0022] Figure 3 A schematic diagram of the structure of another display chip provided by an embodiment of the present invention;

[0023] Figure 4 A schematic diagram of the luminescence spectrum of a different luminescence unit provided in a trial embodiment of the present invention;

[0024] Figure 5 A schematic flow chart of a method for manufacturing a display chip provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0026] Figure 1A schematic diagram of the structure of a display chip provided by an embodiment of the present invention, Figure 2 A schematic diagram of the structure of a tunnel junction provided by an embodiment of the present invention. Figure 1 and Figure 2 As shown, the display chip includes at least two stacked light-emitting units 10, and the light-emitting unit 10 includes a stacked N-type conductive contact layer 110, a light-emitting functional layer 120 and a P-type conductive contact layer 130; in the light-emitting unit 10, at least one P-type conductive contact layer 130 is provided with a tunnel junction 20 on a side away from the light-emitting functional layer 120; the tunnel junction 20 includes a stacked p-type doped layer 210, a plurality of aluminum gallium nitride insertion layers 220 and an n-type doped layer 230; the N-type conductive contact layer 110 of one light-emitting unit 10 is adjacent to the n-type doped layer 230, and the P-type conductive contact layer 130 of another light-emitting unit 10 is adjacent to the p-type doped layer 210; along the direction X from the n-type doped layer 230 to the p-type doped layer 210, the aluminum doping concentration of at least part of the aluminum gallium nitride insertion layer 220 gradually increases.

[0027] Specifically, Figure 1 exemplarily shows that the display chip includes two stacked light-emitting units 10. The display chip may also include a substrate 30 and a buffer layer 40, wherein the buffer layer 40 is disposed on the substrate 30, and the light-emitting unit 10 is disposed on the buffer layer 40. By arranging the buffer layer 40 between the light-emitting unit 10 and the substrate 30, the lattice mismatch between the substrate 30 and the light-emitting unit 10 can be reduced, which is conducive to growing the light-emitting unit 10 on the substrate 30 to form an epitaxial structure. The material of the N-type conductive contact layer 110 may be n-type gallium nitride, the material of the P-type conductive contact layer 130 may be p-type gallium nitride, and the light-emitting functional layer 120 may include a quantum well layer, which may be a single quantum well layer or a multiple quantum well layer. An electron blocking layer 121 may be further disposed on the quantum well layer, and the quantum well layer is disposed on the side of the electron blocking layer 121 close to the N-type conductive contact layer 110. Figure 1 exemplarily shows that the display chip includes two light-emitting units 10. The N-type conductive contact layer 110 of the first light-emitting unit 10 is arranged on the buffer layer 40, a tunnel junction 20 is arranged between the first light-emitting unit 10 and the second light-emitting unit 10, the P-type conductive contact layer 130 of the first light-emitting unit 10 is arranged adjacent to the p-type doped layer 210, and the N-type conductive contact layer 110 of the second light-emitting unit 10 is arranged adjacent to the n-type doped layer 230. At this time, the two light-emitting units 10 are connected in series through the tunnel junction 20. The tunnel junction 20 can improve the high resistance characteristics, poor conductivity and high light absorption rate of the P-type conductive contact layer 130, thereby improving the luminous efficiency of the display chip.

[0028] The tunnel junction 20 includes a p-type doped layer 210 and an n-type doped layer 230 stacked. In some embodiments, the p-type doped layer 210 and the n-type doped layer 230 may be highly doped gallium nitride layers. During the operation of the display chip, the tunnel junction 20 is reverse biased, and electrons tunnel from the valence band of the p-type doped layer 210 to the conduction band of the n-type doped layer 230, so that holes are injected into the p-type doped layer 210, quantum tunneling is achieved, and the conductivity of the p-type doped layer 210 is improved. At the same time, the tunnel junction 20 also includes a multi-layer aluminum gallium nitride insertion layer 220, and the material of the aluminum gallium nitride insertion layer 220 may be aluminum gallium nitride, so that the band gap of the aluminum gallium nitride insertion layer 220 is relatively large, and the aluminum gallium nitride insertion layer 220 can be prevented from absorbing ultraviolet light, thereby reducing the light absorption rate of the tunnel junction 20, improving the luminous efficiency of the display chip, and reducing the loss of the tunnel junction 20 when it is used as a laser cladding. At the same time, the dielectric constant of aluminum gallium nitride is relatively low, which can improve the current diffusion and hole injection efficiency of the junction area of ​​the tunnel junction 20, improve the current expansion, improve the external quantum efficiency, and help improve the tunneling probability of the tunnel junction 20. In addition, the contact interface between the aluminum gallium nitride insertion layer 220 and the p-type doping layer 210, and the contact interface between the aluminum gallium nitride insertion layer 220 and the n-type doping layer 230 can form high-concentration two-dimensional electron gas and two-dimensional hole gas, which can improve the contact performance between the aluminum gallium nitride insertion layer 220 and the p-type doping layer 210 and the n-type doping layer 230, respectively, forming a good ohmic contact, reducing the turn-on voltage and series resistance of the tunnel junction 20, and thus improving the performance of the display chip.

[0029] Moreover, along the direction X from the n-type doped layer 230 to the p-type doped layer 210, the aluminum doping concentration of at least part of the aluminum gallium nitride insertion layer 220 gradually increases, so that the stress of the multi-layer aluminum gallium nitride insertion layer 220 is compressive stress, that is, the strain of the multi-layer aluminum gallium nitride insertion layer 220 is compressive strain, so that the internal polarization electric field direction of the multi-layer aluminum gallium nitride insertion layer 220 can be the same as the built-in electric field direction. In the process of quantum tunneling, the influence of the internal polarization electric field direction of the aluminum gallium nitride itself being opposite to the built-in electric field direction on the tunneling efficiency can be weakened, which is beneficial to improve the quantum tunneling probability of the tunneling junction 20, thereby improving the carrier transport efficiency of the p-type doped layer 210 and improving the luminous efficiency of the display chip. Exemplary, Figure 2 The multilayer AlGaN insertion layer 220 includes four AlGaN insertion layers 220, along the direction X from the n-type doping layer 230 to the p-type doping layer 210, and the AlGaN material of the first AlGaN insertion layer 220 is Al 0.2 Ga 0.8 N, the aluminum gallium nitride material of the second aluminum gallium nitride insertion layer 220 is Al 0.4 Ga 0.6 N, the aluminum gallium nitride material of the third aluminum gallium nitride insertion layer 220 is Al 0.6 Ga 0.4N. The strain of the multilayer AlGaN insertion layer 220 is compressive strain along the direction X pointing from the n-type doping layer 230 to the p-type doping layer 210, so that the internal polarization electric field direction of the multilayer AlGaN insertion layer 220 is the same as the built-in electric field direction, thereby improving the quantum tunneling probability of the tunneling junction 20.

[0030] It should be noted that, in other embodiments, the display chip may also include a plurality of light-emitting units stacked in layers. A tunnel junction may be provided on the side of the p-type doped layer in each light-emitting unit away from the light-emitting functional layer, which is not limited here. For example, Figure 3 FIG. 1 is a schematic diagram of the structure of another display chip provided by an embodiment of the present invention. Figure 3 As shown, the display chip includes three stacked light-emitting units 10 and three tunnel junctions 20. Each tunnel junction 20 is arranged on a side of the P-type conductive contact layer 130 in each light-emitting unit 10 away from the light-emitting functional layer 120, and is used to improve the effects of the high resistance characteristics, poor conductivity and high light absorption rate of the P-type conductive contact layer 130, thereby improving the luminous efficiency of the display chip.

[0031] The technical solution of this embodiment can reduce the light absorption rate of the tunnel junction and improve the luminous efficiency of the display chip by setting an aluminum gallium nitride insertion layer between the p-type doped layer and the n-type doped layer. At the same time, the current diffusion and hole injection efficiency of the tunnel junction can be improved, which is conducive to improving the tunneling probability of the tunnel junction. The contact interface between the aluminum gallium nitride insertion layer and the p-type doped layer, and the contact interface between the aluminum gallium nitride insertion layer and the n-type doped layer can form a high concentration of two-dimensional electron gas and two-dimensional hole gas, which can improve the contact performance of the aluminum gallium nitride insertion layer with the p-type doped layer and the n-type doped layer, respectively, and can improve the performance of the display chip. Moreover, along the direction from the n-type doped layer to the p-type doped layer, the aluminum doping concentration of at least part of the aluminum gallium nitride insertion layer gradually increases, so that the stress of the multi-layer aluminum gallium nitride insertion layer is compressive stress, so that the internal polarization electric field direction of the multi-layer aluminum gallium nitride insertion layer can be the same as the built-in electric field direction. This is conducive to improving the quantum tunneling probability of the tunnel junction, thereby improving the carrier transport efficiency of the p-type doped layer and improving the luminous efficiency of the display chip.

[0032] Continue to refer Figure 1 and Figure 3 , along the direction of the substrate pointing to the light-emitting unit, an ohmic contact layer 50 can also be provided on the side of the last tunnel junction 20 away from the light-emitting unit 10. The material of the ohmic contact layer 50 can be silicon-doped n-type GaN, which is beneficial to the ohmic contact of the display chip, thereby avoiding the provision of a transparent conductive layer such as indium tin oxide.

[0033] Continue to refer Figure 2The multilayer AlGaN insertion layer 220 includes a first group of AlGaN insertion layers 221 and a second group of AlGaN insertion layers 222. The first group of AlGaN insertion layers 221 is arranged on a side of the second group of AlGaN insertion layers 222 close to the n-type doping layer 230. Along the direction X from the n-type doping layer 230 to the p-type doping layer 210, the Al doping concentration of the first group of AlGaN insertion layers 221 gradually increases, and the Al doping concentration of the second group of AlGaN insertion layers 222 gradually decreases.

[0034] Specifically, the first group of AlGaN insertion layers 221 is close to the n-type doping layer 230, and the second group of AlGaN insertion layers 222 is close to the p-type doping layer 210. On the side close to the n-type doping layer 230, along the direction X from the n-type doping layer 230 to the p-type doping layer 210, the aluminum doping concentration of the first group of AlGaN insertion layers 221 gradually increases, so that the strain of the first group of AlGaN insertion layers 221 is compressive strain, so that the direction of the internal polarization electric field of the first group of AlGaN insertion layers 221 is the same as the direction of the built-in electric field. In the process of quantum tunneling, the influence of the direction of the internal polarization electric field of AlGaN itself being opposite to the direction of the built-in electric field on the tunneling efficiency can be weakened, which is conducive to improving the quantum tunneling probability of the tunneling junction 20, thereby improving the carrier transportation efficiency between the p-type doping layers 210, and improving the luminous efficiency of the display chip. At the same time, the aluminum doping concentration of the second group of aluminum gallium nitride insertion layers 222 gradually decreases, so that the aluminum doping concentration in the second group of aluminum gallium nitride insertion layers 222 adjacent to the p-type doped layer 210 in the multi-layer aluminum gallium nitride insertion layer 220 is relatively small, thereby reducing the difficulty of growing the second group of aluminum gallium nitride insertion layers 222 on the p-type doped layer 210 and reducing the process difficulty of the display chip.

[0035] In some embodiments, continue to refer to Figure 2 , the thickness d1 of the first group of AlGaN insertion layers 221 is greater than the thickness d2 of the second group of AlGaN insertion layers 222 .

[0036] Specifically, along the direction X from the n-type doping layer 230 to the p-type doping layer 210, the aluminum doping concentration of the second group of aluminum gallium nitride insertion layers 222 gradually decreases, so that the strain of the aluminum gallium nitride insertion layer 220 close to the p-type doping layer 210 in the multi-layer aluminum gallium nitride insertion layer 220 is tensile strain. By setting the thickness d1 of the first group of aluminum gallium nitride insertion layers 221 to be greater than the thickness d2 of the second group of aluminum gallium nitride insertion layers 222, the tensile stress of the second group of aluminum gallium nitride insertion layers 222 can be made smaller than the compressive stress of the first group of aluminum gallium nitride insertion layers 221. Not only can the difficulty of growing the aluminum gallium nitride insertion layer 220 on the p-type doping layer 210 be reduced, but also the overall strain of the multi-layer aluminum gallium nitride insertion layer 220 can be ensured to be compressive strain, thereby increasing the quantum tunneling probability of the tunneling junction 20 and improving the luminous efficiency of the display chip. Figure 2FIG. 2 exemplarily shows that the first group of AlGaN insertion layers 221 includes a first AlGaN layer 222 disposed in sequence along a direction X from the n-type doping layer to the p-type doping layer. x1 Ga y1 N insertion layer, second Al x2 Ga y2 N insertion layer and the third Al x3 Ga y3 N insertion layer, wherein x1<x2, x2<x3, x1+y1=1, x2+y2=1, x3+y3=1. At this time, the thickness d1 of the first group of AlGaN insertion layers 221 is the first Al x1 Ga y1 N insertion layer, second Al x2 Ga y2 N insertion layer and the third Al x3 Ga y3 N is the sum of the thicknesses of the inserted layers. Figure 2 The second group of aluminum gallium nitride insertion layers 222 includes a fourth Al x4 Ga y4 N insertion layer, the fourth Al x4 Ga y4 The aluminum doping concentration of the N insertion layer is less than that of the third Al x3 Ga y3 The aluminum doping concentration of the N insertion layer, that is, x4<x3, makes the aluminum doping concentration of the second group of aluminum gallium nitride insertion layers 222 gradually decrease along the direction X from the n-type doping layer to the p-type doping layer. Wherein, x4+y4=1. At this time, the thickness d2 of the second group of aluminum gallium nitride insertion layers 222 is the fourth Al x4 Ga y4 The thickness of the N insertion layer can be set at this time. x4 Ga y4 The thickness of the N insertion layer is less than that of the first Al x1 Ga y1 N insertion layer, second Al x2 Ga y2 N insertion layer and the third Al x3 Ga y3 N is the sum of the thicknesses of the inserted layers.

[0037] It should be noted that Figure 2 The second group of aluminum gallium nitride insertion layers 222 only includes the fourth Al x4 Ga y4 In other embodiments, the second group of AlGaN insertion layers 222 may include at least two AlGaN insertion layers. Along the direction X from the n-type doped layer to the p-type doped layer, the Al doping concentration in the at least two AlGaN insertion layers gradually decreases.

[0038] In some embodiments, x1=0.2, x2=0.4, x3=0.6, x4=0.3.

[0039] Specifically, when x1=0.2, the first Al x1 Ga y1 The aluminum gallium nitride material of the N insertion layer is Al 0.2 Ga 0.8 N. When x2=0.4, the second Al x2 Ga y2 The aluminum gallium nitride material of the N insertion layer is Al 0.4 Ga 0.6 N. When x3=0.6, the third Al x3 Ga y3 The aluminum gallium nitride material of the N insertion layer is Al 0.6 Ga 0.4 N. When x4=0.3, the fourth Al x4 Ga y4 The aluminum gallium nitride material of the N insertion layer is Al 0.3 Ga 0.7 N. At this time, the fourth Al adjacent to the p-type doped layer 210 x4 Ga y4 The aluminum gallium nitride material of the N insertion layer is Al 0.3 Ga 0.7 N, that is, a fourth Al is grown on the p-type doped layer 210 x4 Ga y4 When the N-type insertion layer is formed, the doping concentration of aluminum changes from 0 to 0.3, which can reduce the difficulty of growing the aluminum gallium nitride insertion layer 220 on the p-type doped layer 210. At the same time, the first Al2O3 adjacent to the n-type doped layer 230 x1 Ga y1 The aluminum gallium nitride material of the N insertion layer is Al 0.2 Ga 0.8 N, that is, in the first Al x1 Ga y1 When the n-type doping layer 230 is grown on the N insertion layer, the doping concentration of aluminum changes from 0.2 to 0, which can also reduce the concentration of aluminum in the first Al x1 Ga y1 The difficulty of growing the n-type doping layer 230 on the N insertion layer. Therefore, the process difficulty of the display chip can be reduced on the basis of improving the quantum tunneling probability of the tunneling junction 20 by the multi-layer aluminum gallium nitride insertion layer 220.

[0040] It should be noted that x1=0.2, x2=0.4, x3=0.6, and x4=0.3 are only examples. In other embodiments, x3 can be set larger according to the process level and the light-emitting requirements of the display chip, for example, it can be close to 1, which is not limited here. In addition, the difference in aluminum doping concentration between adjacent aluminum gallium nitride insertion layers 220 can be set as needed, for example, it can be 0.3 to reduce the number of aluminum gallium nitride insertion layers 220, or it can be 0.1 to reduce the difficulty of growing the aluminum gallium nitride insertion layer 220.

[0041] In some embodiments, the overall thickness of the multi-layer AlGaN insertion layer is less than or equal to 7.5 nm to minimize the thickness of quantum tunneling from the p-type doped layer 210 to the n-type doped layer 230 , thereby ensuring the probability of quantum tunneling and improving the quantum tunneling probability of the tunneling junction 20 .

[0042] In some embodiments, the thickness of each AlGaN insertion layer is in the range of 0.4-2 nm.

[0043] Specifically, the thickness of each aluminum gallium nitride insertion layer is greater than or equal to 0.4nm to ensure the film integrity of each aluminum gallium nitride insertion layer. The thickness of each aluminum gallium nitride insertion layer is less than or equal to 2nm, which can make the overall thickness of the multiple aluminum gallium nitride insertion layers less than or equal to 7.5nm, thereby ensuring the probability of quantum tunneling. Exemplarily, the thickness of each aluminum gallium nitride insertion layer can be 0.5nm, 0.6nm, 0.8nm, 1nm and 1.5nm, etc.

[0044] In some embodiments, the light-emitting colors of different light-emitting units are the same or different.

[0045] Specifically, when the light-emitting unit in the display chip is a micro light-emitting device, the light-emitting efficiency of the display chip is relatively low. By setting the light-emitting colors of different light-emitting units to be the same, the light-emitting brightness of the display chip can be increased, thereby increasing the scope of use of the display chip. In some embodiments, the light-emitting colors of different light-emitting units can be different. In this case, the tunnel junction can connect the light-emitting units of different light-emitting colors in series and stack them to form a display chip. In the process of mass transfer, the transfer process can be saved, the production cost of the display chip is reduced, and the yield of the display chip can be improved. Exemplary, Figure 4 The schematic diagram of the luminous spectrum of different luminous units provided in the trial embodiment of the present invention. The horizontal axis is the wavelength (nm) and the vertical axis is the light intensity. Curve 1 is the spectral curve of the first luminous unit, and curve 2 is the spectral curve of the second luminous unit. Figure 4 As shown, when the display chip includes two light-emitting units, the light-emitting color of the first light-emitting unit may be green, and the light-emitting color of the second light-emitting unit may be blue. In this case, the display chip can display mixed light of green and blue.

[0046] An embodiment of the present invention further provides a method for manufacturing a display chip, which is used to manufacture the display chip provided by any embodiment of the present invention. Figure 5 A schematic diagram of a method for manufacturing a display chip provided by an embodiment of the present invention is shown in FIG. Figure 5 As shown, the method includes:

[0047] S110, growing a p-type doped layer on a P-type conductive contact layer of a light-emitting unit; the light-emitting unit comprises an N-type conductive contact layer, a light-emitting functional layer and a P-type conductive contact layer which are stacked;

[0048] S120, growing multiple aluminum gallium nitride insertion layers on the p-type doped layer; along the direction from the n-type doped layer to the p-type doped layer, the aluminum doping concentration of at least part of the aluminum gallium nitride insertion layer gradually increases;

[0049] S130, growing an n-type doped layer on the multi-layer aluminum gallium nitrogen insertion layer;

[0050] S140 , growing another light-emitting unit on the n-type doped layer.

[0051] The technical solution of this embodiment, by growing a tunnel junction on the P-type conductive contact layer of the light-emitting unit, the tunnel junction includes a multi-layer aluminum gallium nitride insertion layer, which can reduce the light absorption rate of the tunnel junction and improve the luminous efficiency of the display chip. At the same time, the current diffusion and hole injection efficiency of the tunnel junction can be improved, which is conducive to improving the tunneling probability of the tunnel junction. The contact interface between the aluminum gallium nitride insertion layer and the p-type doped layer, and the contact interface between the aluminum gallium nitride insertion layer and the n-type doped layer can form a high concentration of two-dimensional electron gas and two-dimensional hole gas, which can improve the contact performance of the aluminum gallium nitride insertion layer with the p-type doped layer and the n-type doped layer, respectively, and can improve the performance of the display chip. Moreover, along the direction from the n-type doped layer to the p-type doped layer, the aluminum doping concentration of at least part of the aluminum gallium nitride insertion layer gradually increases, so that the stress of the multi-layer aluminum gallium nitride insertion layer is compressive stress, so that the internal polarization electric field direction of the multi-layer aluminum gallium nitride insertion layer can be the same as the built-in electric field direction. This is conducive to improving the quantum tunneling probability of the tunnel junction, thereby improving the carrier transport efficiency of the p-type doped layer and improving the luminous efficiency of the display chip.

[0052] In some embodiments, at least one tunneling junction disposed on a side of the P-type conductive contact layer away from the light-emitting functional layer may include multiple aluminum gallium nitride insertion layers, and at least one tunneling junction disposed on a side of the P-type conductive contact layer away from the light-emitting functional layer may include an InGaN insertion layer. The following is an example of a display chip including two light-emitting units, a tunneling junction on a side of the P-type conductive contact layer of the first light-emitting unit away from the light-emitting functional layer including an InGaN insertion layer, and a tunneling junction on a side of the P-type conductive contact layer of the second light-emitting unit away from the light-emitting functional layer including multiple aluminum gallium nitride insertion layers.

[0053] Before growing the p-type doped layer, it also includes:

[0054] growing a buffer layer on the substrate;

[0055] Specifically, the substrate can be sapphire, silicon, silicon carbide or patterned sapphire, etc. Before growing the buffer layer, the substrate can be cleaned. After the substrate is cleaned, the buffer layer can be deposited using a metal-organic chemical vapor deposition process to reduce the lattice mismatch between the substrate and the gallium nitride of the light-emitting unit. The buffer layer can be composed of a multilayer or single-layer structure such as AlN, AlGaN and u-GaN. Among them, the thickness range of AlN can be 10-300nm, the thickness range of AlGaN can be 10-350nm, the thickness range of u-GaN can be 10-3000nm, and the growth temperature range of u-GaN can be 500-1150℃.

[0056] A light emitting unit is grown on the buffer layer.

[0057] Specifically, after forming the buffer layer, the first light-emitting unit can be grown on the buffer layer. For example, a silicon-doped n-type GaN layer can be first grown on the buffer layer to form an N-type conductive contact layer of the first light-emitting unit. The thickness of the n-type GaN layer can be in the range of 1-3.5 μm, the growth temperature can be in the range of 1000-1100°C, and the silicon doping concentration can be in the range of 1E18 / cm 2 -7E18 / cm 2 .

[0058] After forming the N-type conductive contact layer of the first light-emitting unit, the light-emitting functional layer of the first light-emitting unit is grown on the N-type conductive contact layer. For example, a quantum well layer can be grown on the N-type conductive contact layer. The number of multiple quantum wells (MQW) contained in the quantum well region can range from 1 to 11 pairs, the barrier thickness of the quantum well can range from 5 to 50 nm, the potential well thickness can range from 3 to 30 nm, and the growth temperature of the quantum well layer can range from 700 to 900°C. After forming the quantum well layer, an electron blocking layer can be grown on the quantum well layer. The electron blocking layer can be a Mg-doped p-type AlGaN layer, the thickness of which can range from 40 to 100 nm, and the growth temperature can range from 900 to 1000°C.

[0059] After forming the light-emitting functional layer of the first light-emitting unit, a P-type conductive contact layer of the first light-emitting unit can be grown on the light-emitting functional layer. For example, a p-type GaN layer doped with Mg can be grown on the electron blocking layer as the P-type conductive contact layer of the first light-emitting unit. The thickness of the p-type GaN layer can range from 100 to 250 nm, and the growth temperature can range from 900 to 1000° C. The doping concentration of Mg can range from 1E19 / cm 2 -5E19 / cm 2 .

[0060] After forming the P-type conductive contact layer of the first light-emitting unit, the growth temperature of the P-type conductive contact layer of the first light-emitting unit can be kept unchanged, and the doping concentration of Mg can be increased by using delta doping to grow the p-type doped layer in the tunnel junction on the side of the P-type conductive contact layer of the first light-emitting unit away from the light-emitting functional layer. The thickness of the p-type doped layer can range from 10-50nm, and the doping concentration of Mg can range from 1E20 / cm 2 -4E20 / cm 2 .

[0061] After growing the p-type doped layer of the first tunnel junction, the growth temperature can be lowered to 700-830°C, and then silicon-doped InGaN is grown as an insertion layer of the tunnel junction on one side of the P-type conductive contact layer of the first light-emitting unit, which is used to reduce the forward conduction resistance of the first light-emitting unit and improve the optoelectronic performance of the display chip. The thickness of the silicon-doped InGaN layer can range from 2-5nm.

[0062] After forming the insertion layer of the first tunnel junction, the growth temperature is raised to 1020℃-1060℃, and a delta growth mode is adopted to grow an n-type GaN layer with a high silicon doping concentration as the n-type doping layer of the first tunnel junction. The thickness of the n-type GaN layer can range from 10-50nm, and the silicon doping concentration can range from 1E20 / cm 2 -5E20 / cm 2 .

[0063] After forming the first tunnel junction, an n-type GaN layer doped with silicon is grown on the n-type GaN layer to form an N-type conductive contact layer of the second light-emitting unit. The thickness of the n-type GaN layer can range from 200 to 400 nm, and the growth temperature can range from 1000 to 1100°C. The doping concentration of silicon can range from 1E19 / cm 2 -5E19 / cm 2 .

[0064] After forming the N-type conductive contact layer of the second light-emitting unit, the light-emitting functional layer of the second light-emitting unit can be grown on the layer. For example, a quantum well layer can be grown on the N-type conductive contact layer. The number of MQW pairs contained in the quantum well region can range from 1 to 11 pairs, the barrier thickness of the quantum well can range from 5 to 50 nm, the potential well thickness can range from 3 to 30 nm, and the growth temperature of the quantum well layer can range from 700 to 900°C. After forming the quantum well layer, an electron blocking layer can be grown on the quantum well layer. The electron blocking layer can be a Mg-doped p-type AlGaN layer, the thickness of which can range from 40 to 100 nm, and the growth temperature can range from 900 to 1000°C.

[0065] After forming the light-emitting functional layer of the second light-emitting unit, a P-type conductive contact layer of the second light-emitting unit can be formed on the light-emitting functional layer. For example, a p-type GaN layer doped with Mg can be grown on the electron blocking layer as the P-type conductive contact layer of the second light-emitting unit. The thickness of the p-type GaN layer can range from 100 to 250 nm, and the growth temperature can range from 900 to 1000° C. The doping concentration of Mg can range from 1E19 / cm 2 -8E19 / cm 2 .

[0066] After forming the P-type conductive contact layer of the second light-emitting unit, the growth temperature of the P-type conductive contact layer of the second light-emitting unit can be kept unchanged, and the doping concentration of Mg can be increased by using delta doping to grow the p-type doped layer in the tunnel junction on the side of the P-type conductive contact layer of the second light-emitting unit away from the light-emitting functional layer. The thickness of the p-type doped layer can range from 10-50nm, and the doping concentration of Mg can range from 1E20 / cm 2 -4E20 / cm 2 .

[0067] After forming the p-type doped layer of the second tunnel junction, the growth temperature can be lowered to 700-830°C, and then the AlGaN composition is gradually grown as the insertion layer of the tunnel junction on the P-type conductive contact layer side of the second light-emitting unit. For example, the composition of the AlGaN insertion layer can be Al, 0.3 Ga 0.7 N / A 0.6 Ga 0.4 N / A 0.4 Ga 0.6 N / A 0.2 Ga 0.8 N, and the thickness can be 1nm / 1.5nm / 2nm / 1.5nm respectively.

[0068] After forming the insertion layer of the second tunnel junction, the growth temperature is raised to 1020℃-1060℃, and a delta growth mode is adopted to grow an n-type GaN layer with a high silicon doping concentration as the n-type doping layer of the second tunnel junction. The thickness of the n-type GaN layer can range from 10-50nm, and the silicon doping concentration can range from 1E20 / cm 2 -5E20 / cm 2 .

[0069] After forming the second tunnel junction, a silicon-doped n-type GaN layer is grown on the n-type GaN layer as an N-type conductive contact layer to improve the ohmic contact of the display chip, thereby avoiding the need to set up a transparent conductive layer such as indium tin oxide. The thickness of the n-type GaN layer can range from 200 to 400 nm, and the growth temperature can range from 1000 to 1100 ° C. The doping concentration of silicon can range from 1E19 / cm 2 -5E19 / cm 2 .

[0070] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display chip, characterized in that: The invention comprises at least two stacked light-emitting units, wherein the light-emitting units comprise a stacked N-type conductive contact layer, a light-emitting functional layer and a P-type conductive contact layer; in the light-emitting units, at least one of the P-type conductive contact layers is provided with a tunnel junction on a side away from the light-emitting functional layer; the tunnel junction comprises a stacked p-type doped layer, a plurality of aluminum gallium nitride insertion layers and an n-type doped layer; the N-type conductive contact layer of one light-emitting unit is arranged adjacent to the n-type doped layer, and the P-type conductive contact layer of another light-emitting unit is arranged adjacent to the p-type doped layer; along the direction from the n-type doped layer to the p-type doped layer, the aluminum doping concentration of at least part of the aluminum gallium nitride insertion layer gradually increases; The multiple aluminum gallium nitride insertion layers include a first group of aluminum gallium nitride insertion layers and a second group of aluminum gallium nitride insertion layers, wherein the first group of aluminum gallium nitride insertion layers is arranged on a side of the second group of aluminum gallium nitride insertion layers close to the n-type doping layer; along a direction from the n-type doping layer to the p-type doping layer, the aluminum doping concentration of the first group of aluminum gallium nitride insertion layers gradually increases, and the aluminum doping concentration of the second group of aluminum gallium nitride insertion layers gradually decreases; The thickness of the first group of aluminum gallium nitride insertion layers is greater than the thickness of the second group of aluminum gallium nitride insertion layers.

2. The display chip according to claim 1, characterized in that: The first group of AlGaN insertion layers includes a first AlGaN layer stacked in sequence along a direction from the n-type doping layer to the p-type doping layer. x1 Ga y1 N insertion layer, second Al x2 Ga y2 N insertion layer and the third Al x3 Ga y3 N insertion layer, the second group of aluminum gallium nitride insertion layers includes a fourth Al x4 Ga y4 N insertion layers, where x1<x2, x2<x3, x4<x3, x1+y1=1, x2+y2=1, x3+y3=1, x4+y4=1.

3. The display chip according to claim 2, characterized in that: x1=0.2, x2=0.4, x3=0.6, x4=0.

3.

4. The display chip according to claim 1, characterized in that: The overall thickness of the multiple aluminum gallium nitride insertion layers is less than or equal to 7.5 nm.

5. The display chip according to claim 1, characterized in that: The thickness of each aluminum gallium nitride insertion layer is in the range of 0.4-2 nm.

6. The display chip according to claim 1, characterized in that: The material of the p-type doping layer includes p-type gallium nitride, and the material of the n-type doping layer includes n-type gallium nitride.

7. The display chip according to claim 1, characterized in that: The light emitting colors of different light emitting units are the same or different.

8. A method for manufacturing a display chip, characterized in that: include: Growing a p-type doped layer on a p-type conductive contact layer of a light-emitting unit; the light-emitting unit comprises an n-type conductive contact layer, a light-emitting functional layer and a p-type conductive contact layer which are stacked; A plurality of aluminum gallium nitride insertion layers are grown on the p-type doped layer; along the direction from the n-type doped layer to the p-type doped layer, the aluminum doping concentration of at least part of the aluminum gallium nitride insertion layers gradually increases; the plurality of aluminum gallium nitride insertion layers include a first group of aluminum gallium nitride insertion layers and a second group of aluminum gallium nitride insertion layers, the first group of aluminum gallium nitride insertion layers being arranged on a side of the second group of aluminum gallium nitride insertion layers close to the n-type doped layer; along the direction from the n-type doped layer to the p-type doped layer, the aluminum doping concentration of the first group of aluminum gallium nitride insertion layers gradually increases, and the aluminum doping concentration of the second group of aluminum gallium nitride insertion layers gradually decreases; the thickness of the first group of aluminum gallium nitride insertion layers is greater than the thickness of the second group of aluminum gallium nitride insertion layers; Growing the n-type doped layer on the multi-layer aluminum gallium nitride insertion layer; Another light emitting unit is grown on the n-type doped layer.

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