Antenna device

Abstract

An antenna device comprises a transparent substrate and a plurality of antenna units arranged on the transparent substrate. Each antenna unit comprises an antenna electrode, a grounding electrode, a thin film circuit structure, a redistribution structure and a wafer. The redistribution line comprises a digital signal connecting pad, an analog signal connecting pad, a radio frequency signal connecting pad and an antenna signal connecting pad. The wafer is bonded to the digital signal pads, the analog signal pads, the radio frequency signal pads and the antenna signal pads. The digital signal connecting pad and the analog signal connecting pad are arranged in the first joint area. The radio frequency signal connecting pad and the antenna signal connecting pad are arranged in the second bonding area.

Description

Technical Field

[0001] The invention relates to an antenna device. Background Art

[0002] In modern life, wireless communication technology is everywhere. In major cities or public spaces, wireless local area networks have become a necessary facility, and many people have even set up their own wireless networks at home. With the advancement of wireless communication technology, many manufacturers are committed to developing antenna devices with better performance. At present, antenna devices have complex circuit designs inside, involving various different signals. If the distance between signal lines is too close, the signals are likely to interfere with each other, which in turn affects the performance of the antenna device. Summary of the invention

[0003] An object of the present invention is to provide an antenna device which can improve the problem of mutual interference of signals.

[0004] At least one embodiment of the present invention provides an antenna device, which includes a transparent substrate and a plurality of antenna units disposed on the transparent substrate. Each antenna unit includes an antenna electrode, a ground electrode, a thin film circuit structure, a rewiring structure, and a chip. The antenna electrode is disposed on a first surface of the transparent substrate. The ground electrode is disposed on a second surface of the transparent substrate opposite to the first surface. The thin film circuit structure is located on the ground electrode and includes a digital signal line. The rewiring structure is located on the thin film circuit structure and includes a digital signal pad electrically connected to the digital signal line, an analog signal line, an analog signal pad electrically connected to the analog signal line, a radio frequency signal line, a radio frequency signal pad electrically connected to the radio frequency signal line, and an antenna signal pad electrically connected to the antenna electrode. The chip is bonded to the digital signal pad, the analog signal pad, the radio frequency signal pad, and the antenna signal pad. The digital signal pad and the analog signal pad are disposed in a first bonding area. The radio frequency signal pad and the antenna signal pad are disposed in a second bonding area separated from the first bonding area.

[0005] At least one embodiment of the present invention provides an antenna device, which includes a transparent substrate and a plurality of antenna units disposed on the transparent substrate. Each antenna unit includes an antenna electrode, a ground electrode, a thin film circuit structure, a rewiring structure, and a chip. The antenna electrode is disposed on a first surface of the transparent substrate. The ground electrode is disposed on a second surface of the transparent substrate opposite to the first surface. The thin film circuit structure is located on the ground electrode. The rewiring structure is located on the thin film circuit structure and includes a first ground structure, a second ground structure separated from the first ground structure, a dielectric layer, a first pad, and a second pad. The first ground structure and the second ground structure overlap the ground electrode. The dielectric layer is located on the first ground structure and the second ground structure. The first pad and the second pad are located on the dielectric layer. The first pad overlaps the first opening of the first ground structure. The second pad overlaps the second opening of the second ground structure. The first ground structure and the first pad overlap the first bonding area. The second ground structure and the second pad overlap the second bonding area separated from the first bonding area. The chip overlaps the first bonding area and the second bonding area and is bonded to the first pad and the second pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a cross-sectional schematic diagram of an antenna device according to an embodiment of the present invention.

[0007] Figure 2 is a cross-sectional schematic diagram of an antenna device according to an embodiment of the present invention.

[0008] Figure 3 is a schematic top view of an antenna device according to an embodiment of the present invention.

[0009] 4A to 4F yes Figure 3 A top view of the various conductive layers in the antenna unit 10B.

[0010] Figure 5A yes Figure 3 A partial enlarged view of the antenna device.

[0011] Figure 5B yes Figure 5A Schematic cross-sectional view along line BB'.

[0012] Fig. 6A is a simulation curve of S11 parameters of some antenna devices according to an embodiment of the present invention.

[0013] Figure 6B is a simulated graph of S21 parameters of some antenna devices according to an embodiment of the present invention.

[0014] Figure 7 is a schematic top view of an antenna unit according to another embodiment of the present invention.

[0015] Figure 8 is a cross-sectional schematic diagram of an antenna device according to an embodiment of the present invention.

[0016] Fig. 9 is a schematic top view of an antenna device according to an embodiment of the present invention.

[0017] Fig.10 is a functional block diagram of an antenna device according to an embodiment of the present invention.

[0018] The reference numerals are as follows:

[0019] 1A, 1B, 1D: Antenna device

[0020] 10A, 10B, 10C, 10D: Antenna unit

[0021] 100:Transparent substrate

[0022] 110: Antenna electrode

[0023] 120:Conductive through hole in substrate

[0024] 132: Grounding electrode

[0025] 132a: block portion

[0026] 132b, 132c, 132d: wire portion

[0027] 132h, 313h, 314h: Open

[0028] 134:Joint structure

[0029] 140: Buffer layer

[0030] 200,200D: Thin film circuit structure

[0031] 210: first thin film conductive layer

[0032] 211a,211b,212,213,214,215,216,217,218,316,333,334: signal line

[0033] 219: Digital signal line

[0034] 220: first dielectric layer

[0035] 230: second thin film conductive layer

[0036] 231a, 231b, 231c, 231d, 231e: first conductive feature

[0037] 231a-1: Extension

[0038] 232a, 232b: second conductive feature

[0039] 240: Second dielectric layer

[0040] 250: gate dielectric layer

[0041] 300: Rewiring structure

[0042] 310: First redistribution layer

[0043] 311b, 311c, 311d, 311e: first transfer structure

[0044] 312b, 312c: second transfer structure

[0045] 313: Second grounding structure

[0046] 314: first grounding structure

[0047] 313a, 314a: block part

[0048] 313b, 314b: wire part

[0049] 320: Insulation layer

[0050] 330: Second redistribution layer

[0051] 331a, 331b, 331c, 331d, 331e: first pad

[0052] 332a: shielding layer

[0053] 332b, 332c, 332d, 332e: second pad

[0054] 410: Chip

[0055] 412: Conductive connection structure

[0056] 420: Bottom filling material

[0057] GL, DL: Digital signal line

[0058] G: Gate

[0059] LH1, LH2, LH3a, LH3b: Conductive vias

[0060] MC:Memory Circuit Module

[0061] P: Pad

[0062] PALNA: Power amplifier and / or low loss amplifier module

[0063] PD: Passive Components

[0064] PH1, PH2, PH2-1: Contact part

[0065] S1: Side 1

[0066] S2: Side 2

[0067] SD: Source / Drain

[0068] SM: Semiconductor layer

[0069] SCC:Signal Control Circuit Module

[0070] T: Thin Film Transistor

[0071] TR: Light Transmission Zone

[0072] VGPS: Variable Gain Amplifier and Phase Shifter Module DETAILED DESCRIPTION

[0073] Figure 1 is a cross-sectional diagram of an antenna device 1A according to an embodiment of the present invention. Figure 1 A, the antenna device 1A includes a transparent substrate 100 and a plurality of antenna units 10A disposed on the transparent substrate 100. The antenna units 10A are arranged in an array, for example, and a light transmission region TR is provided between the antenna units 10A. In some embodiments, the antenna device 1A can be applied to a window of a transportation vehicle (e.g., a sunroof of a car), a window of a building, etc.

[0074] The transparent substrate 100 has a first surface S1 and a second surface S2 opposite to the first surface S1. In some embodiments, the material of the transparent substrate 100 includes glass, quartz, organic polymer or other applicable materials. In some embodiments, the thickness of the transparent substrate 100 is 0.15 mm to 1.1 mm. For example, the thickness of the transparent substrate 100 is 0.5 mm, 0.7 mm or 1.1 mm.

[0075] Each antenna unit 10A includes an antenna electrode 110 , a ground electrode 132 , a thin film circuit structure 200 , a redistribution structure 300 , and a chip 410 .

[0076] The antenna electrode 110 is disposed on the first surface S1 of the transparent substrate 100 .

[0077] The ground electrode 132 is disposed on the second surface S2 of the transparent substrate 110. In the present embodiment, the ground electrode 132 has at least one opening 132h, and each opening 132h has a bonding structure 134. The bonding structure 134 is electrically connected to the antenna electrode 110 through the substrate conductive through hole 120. Therefore, the antenna signal of the antenna electrode 110 can be transmitted through the bonding structure 134 and the substrate conductive through hole 120. In other embodiments, the substrate conductive through hole 120 can be omitted, and the antenna signal of the antenna electrode 110 is transmitted between the antenna electrode and the driving electrode (not shown) overlapping the opening 132h by radiation.

[0078] In some embodiments, the materials of the antenna electrode 110, the ground electrode 132, the bonding structure 134, and the substrate conductive through hole 120 include copper (Cu), aluminum (Al), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), tungsten (W), conductive oxides (such as indium tin oxide, indium zinc oxide, etc.) or other suitable materials or combinations of the above materials.

[0079] In some embodiments, the method of forming the substrate conductive via 120 includes a glass modification process and a process of filling a conductive material. For example, a through hole is first formed on the transparent substrate 100 by laser, and then the through hole is enlarged by a wet etching process to form a through hole extending from the first surface S1 to the second surface S2. Finally, a conductive material is filled into the through hole to form the substrate conductive via 120. In some embodiments, the angle between the side wall of the substrate conductive via 120 and the first surface S1 or the second surface S2 (i.e., the inclination angle of the side wall of the substrate conductive via 120) is 88 degrees to 90 degrees.

[0080] In some embodiments, the method of forming the antenna electrode 110, the ground electrode 132, the bonding structure 134 and the substrate conductive through hole 120 includes first forming a seed layer on the first surface S1 and the second surface S2 of the transparent substrate 100 and in the through hole of the substrate by sputtering, chemical plating or other suitable processes. Then, a metal layer is formed on the seed layer by an electroplating process. The resulting seed layer and metal layer can be patterned by a lithography process and an etching process to obtain the antenna electrode 110, the ground electrode 132 and the bonding structure 134. In other embodiments, the seed layer can be omitted.

[0081] The buffer layer 140 is located on the transparent substrate 100, the ground electrode 132 and the bonding structure 134. In some embodiments, the buffer layer 140 includes a transparent material, such as an organic material (such as polyimide, polyethylene terephthalate, epoxy resin, etc.) or an inorganic material (such as silicon nitride, silicon oxide, etc.) or a combination of the above materials. In some embodiments, since the thickness of the antenna electrode 110, the ground electrode 132 and the bonding structure 134 is 2 microns to 10 microns. In order to achieve the effect of planarization, the thickness of the buffer layer 140 is preferably 2 microns to 15 microns, and the thickness of the buffer layer 140 is not less than the thickness of the ground electrode 132. For example, the thickness of the buffer layer 140 is 1.3 times the thickness of the ground electrode 132. In order to achieve this thickness to obtain the effect of planarization, the buffer layer 140 is preferably made of an organic material.

[0082] The thin film circuit structure 200 is located on the ground electrode 132 and the bonding structure 134. In this embodiment, the thin film circuit structure 200 is located on the buffer layer 140. In some embodiments, the entire thickness of the thin film circuit structure 200 is less than 10 micrometers.

[0083] The thin film circuit structure 200 includes a first thin film conductive layer 210, a first dielectric layer 220, a second thin film conductive layer 230, and a second dielectric layer 240 deposited in sequence. In some embodiments, at least one contact portion PH1 of the second thin film conductive layer 230 passes through the first dielectric layer 220 and is electrically connected to the first thin film conductive layer 210. In some embodiments, the thin film circuit structure 200 may further include more conductive layers and dielectric layers, and the present invention does not limit the number of conductive layers and dielectric layers in the thin film circuit structure 200.

[0084] In some embodiments, the materials of the first thin film conductive layer 210 and the second thin film conductive layer 230 include copper (Cu), aluminum (Al), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), tungsten (W), conductive oxides (such as indium tin oxide, indium zinc oxide, etc.) or other suitable materials or combinations of the above materials. The first thin film conductive layer 210 and the second thin film conductive layer 230 each have a single-layer structure or a multi-layer structure. For example, the first thin film conductive layer 210 and the second thin film conductive layer 230 each have a molybdenum / aluminum / molybdenum stacked structure, a titanium / aluminum / titanium stacked structure, or a stacked structure composed of other conductive materials.

[0085] In some embodiments, the material of the first dielectric layer 220 and the second dielectric layer 240 includes an organic polymer (such as polyimide, polyethylene terephthalate, etc.) or an inorganic material (such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide, hafnium oxide or other suitable materials or combinations of the above materials).

[0086] In some embodiments, before forming the second thin film conductive layer 230, an opening exposing the first thin film conductive layer 210 is formed in the first dielectric layer 220 by using a photolithography process and an etching process, and then the second thin film conductive layer 230 is deposited in the opening to form a contact portion PH1 of the second thin film conductive layer 230, so that the second thin film conductive layer 230 contacts the first thin film conductive layer 210. In some embodiments, the angle between the sidewall and the bottom surface of the contact portion PH1 (i.e., the inclination angle of the sidewall of the contact portion PH1) is 50 degrees to 70 degrees.

[0087] The redistribution structure 300 is located on the thin film circuit structure 200 . In this embodiment, the redistribution structure 300 is located on the second dielectric layer 240 .

[0088] The redistribution structure 300 includes a first redistribution layer 310, an insulating layer 320, and a second redistribution layer 330 that are sequentially deposited. In some embodiments, at least one contact portion PH2 of the first redistribution layer 310 passes through the second dielectric layer 240 and is electrically connected to the second thin film conductive layer 230. In some embodiments, the first redistribution layer 310 and / or the second redistribution layer 330 are electrically connected to the ground electrode 132 and the bonding structure 134 through a conductive via LH1. The conductive via LH1 passes through the thin film circuit structure 200 and the buffer layer 140, and optionally passes through the insulating layer 320. In some embodiments, the second redistribution layer 330 is electrically connected to the first redistribution layer 310 through at least one conductive via LH2 in the insulating layer 320. The redistribution structure 300 may further include more conductive layers and insulating layers, and the present invention does not limit the number of conductive layers and insulating layers in the redistribution structure 300.

[0089] In some embodiments, the materials of the first redistribution layer 310 and the second redistribution layer 330 include copper (Cu), aluminum (Al), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), tungsten (W), conductive oxides (such as indium tin oxide, indium zinc oxide, etc.) or other suitable materials or combinations of the above materials. In some embodiments, the first redistribution layer 310 and the second redistribution layer 330 each include a seed layer and a metal layer formed thereon. The seed layer is formed by, for example, sputtering, chemical plating or other suitable methods, and the metal layer is formed by electroplating. In some embodiments, the seed layer can be omitted.

[0090] In some embodiments, the material of the insulating layer 320 includes an organic material (e.g., polyimide, polyethylene terephthalate, epoxy resin, etc.) or an inorganic material (e.g., silicon nitride, silicon oxide, etc.) or a combination of the above materials. In some embodiments, the method of forming the insulating layer 320 includes attaching a dry film to the first redistribution layer 310 or coating a liquid organic material (e.g., liquid polyimide (PI) material) on the first redistribution layer 310.

[0091] In some embodiments, the insulating layer 320 has high transmittance and low dissipation factor (Df). For example, the transmittance of the insulating layer 320 for light with a wavelength of 400nm to 800nm ​​is greater than or equal to 90%. In some embodiments, the dielectric constant (Dk) of the insulating layer 320 is less than 4, and the dielectric loss is less than 0.004.

[0092] In some embodiments, the first rewiring layer 310 of the rewiring structure 300 is configured to transmit a ground signal, and the second rewiring layer 330 is configured to transmit a chip power signal and a radio frequency (RF) signal (e.g., a radio frequency input signal (RF_in)). In some embodiments, the first thin film conductive layer 210 and the second thin film conductive layer 230 of the thin film circuit structure 200 include a digital signal line and an analog signal line, and the digital signal line and the analog signal line are respectively configured to transmit a digital signal and an analog signal for controlling the chip 410 or the circuit in the circuit structure 200. Since the operating frequency of the digital signal and the analog signal transmitted in the thin film circuit structure 200 is relatively low, even if the film thickness of the first thin film conductive layer 210, the first dielectric layer 220, the second thin film conductive layer 230 and the second dielectric layer 240 in the thin film circuit structure 200 is relatively thin, the signal will not be significantly lost. In contrast, since the rewiring structure 300 is used to transmit a high frequency RF signal, the insulating layer 320 in the rewiring structure 300 needs to be thicker. Therefore, the thickness of the insulating layer 320 is greater than the thickness of each of the first dielectric layer 220 and the second dielectric layer 240. In some embodiments, the thickness of the insulating layer 320 is 10 microns to 60 microns. In some embodiments, the thickness of each of the first dielectric layer 220 and the second dielectric layer 240 is 0.03 microns to 1 micron, for example, 0.5 microns to 1 micron or 0.7 microns to 1 micron. In some embodiments, the thickness of each of the first thin film conductive layer 210 and the second thin film conductive layer 230 is less than the thickness of each of the first redistribution layer 310 and the second redistribution layer 330. In some embodiments, the thickness of each of the first thin film conductive layer 210 and the second thin film conductive layer 230 is 0.01 microns to 0.7 microns, for example, 0.01 microns to 0.3 microns or 0.01 microns to 0.05 microns. In some embodiments, the thickness of each of the first redistribution layer 310 and the second redistribution layer 330 is 2 microns to 10 microns.

[0093] In some embodiments, before forming the first redistribution layer 310, an opening exposing the second thin-film conductive layer 230 is formed in the second dielectric layer 240 by using a lithography process and an etching process, and then the first redistribution layer 310 is deposited in the opening to form a contact portion PH2 of the first redistribution layer 310, so that the first redistribution layer 310 contacts the second thin-film conductive layer 230. In some embodiments, the angle between the sidewall and the bottom surface of the contact portion PH2 (i.e., the inclination angle of the sidewall of the contact portion PH2) is 50 degrees to 70 degrees.

[0094] In some embodiments, a laser drilling process is performed before forming the first redistribution layer 310 or before forming the second redistribution layer 330. For example, a laser drilling process is performed to form a laser hole, and then the first redistribution layer 310 or the second redistribution layer 330 is filled in the laser hole to form a conductive via LH1 or a conductive via LH2. In this embodiment, the conductive via LH2 passes through the insulating layer 320, and the second redistribution layer 330 contacts the first redistribution layer 310 through the conductive via LH2. The conductive via LH1 passes through the insulating layer 320, the second dielectric layer 240, the first dielectric layer 220, and the buffer layer 140, and the second redistribution layer 330 contacts the ground electrode 132 and the bonding structure 134 through the conductive via LH1. In some embodiments, the angle between the sidewall and the bottom surface of the conductive vias LH1 and LH2 (i.e., the inclination angle of the sidewalls of the conductive vias LH1 and LH2) is 70 degrees to 75 degrees. In this embodiment, since the contact portions PH1 and PH2 are formed in different ways, the conductive through holes LH1 and LH2 are formed in different ways, and the substrate conductive through hole 120 is formed in different ways, the three have different sidewall inclination angles.

[0095] The wafer 410 is bonded to the second redistribution layer 330 . In some embodiments, the width of the antenna electrode 110 is greater than or equal to the width of the wafer 410 .

[0096] In some embodiments, the wafer 410 is bonded to the second redistribution layer 330 through a conductive connection structure 412. The conductive connection structure 412 is, for example, solder, conductive glue or other suitable structures. In some embodiments, the surface of the second redistribution layer 330 may be treated with electroless nickel immersion gold (ENIG), immersion silver plating, etc. to improve the yield of the wafer bonding process. In some embodiments, before the wafer bonding process, an organic material such as an organic solderability preservative (OSP) may be formed on the second redistribution layer 330, which can protect the metal pads from rusting (e.g., sulfide or oxidation) due to contact with air to improve the yield of the wafer bonding process. In some embodiments, the spacing between the conductive connection structures 412 is 100 microns to 1000 microns.

[0097] An underfill material 420 is formed between the chip 410 and the second redistribution layer 330. In some embodiments, the underfill material 420 is located between the chip 410 and the redistribution structure 300, and surrounds the connection point (i.e., the conductive connection structure 412) between the chip 410 and the redistribution structure 300. In some embodiments, the underfill material 420 may include a thermal interface material (TIM) to facilitate heat dissipation of the chip 410. For example, the thermal conductivity of the underfill material 420 is greater than 0.3 W / m K.

[0098] In some embodiments, the chip 410 includes a beamformer integrated circuit (BFIC) or other active / passive components. In some embodiments, the beamformer integrated circuit includes a variable gain amplifier (VGA), a phase shifter (PS), a signal control and memory circuit, a power amplifier (PA) and / or a low noise amplifier (LNA). In some embodiments, the circuit including the active components can be disposed in the thin film circuit structure 200, thereby reducing the circuits required to be disposed in the chip 410, and thus the size of the chip 410 can be reduced. For example, the signal control and memory circuits in the beamformer integrated circuit can be disposed in the thin film circuit structure 200. In some embodiments, by making the antenna units 10A each include a chip 410, the signal path between the chip 410 and the antenna electrode 110 can be shortened. If one chip 410 provides signals to multiple antenna electrodes, more signal paths will need to be disposed, thereby reducing the light penetration area of ​​the antenna device. In other words, in this embodiment, by making each antenna unit 10A include one chip 410 , the light transmission area of ​​the antenna device 1A can be increased.

[0099] In some embodiments, an up / down converter (UDC) may be used to convert a relatively low frequency signal (e.g., a signal with a frequency below 2 GHz or other intermediate frequency (IF) or low frequency signal) into a high frequency RF signal, and the high frequency RF signal is further transmitted to the chip 410.

[0100] In the present embodiment, the chip 410 is bonded to a plurality of pads in the second redistribution layer 330. These pads are configured to transmit various signals. For example, ground signals (e.g., AGND, DGND, RF_GND, etc.), power signals (e.g., AVDD, DVDD, etc.), radio frequency signals (RF signal), radio frequency enable signals (RF_en), reference voltage signals (Vref), bias adjustment signals (Rbias), circuit control signals (e.g., digital signals such as CS, CLK, SDI, SDO, PDI, etc.), antenna signals (e.g., horizontally polarized electric field antenna signals (RF_out_H), vertically polarized electric field antenna signals (RF_out_V), etc.). In some embodiments, at least a portion of the circuit control signals are provided by an external circuit board (not shown). For example, they are provided by a field programmable gate array (FPGA) and a power module on the external circuit board.

[0101] In some embodiments, the usage descriptions of various signals and the main transmission layers are shown in Table 1.

[0102] Table 1

[0103]

[0104]

[0105] In some embodiments, to reduce interference between high frequency signals and low frequency signals, chip pads corresponding to low frequency signals are grouped in a first bonding area, while chip pads corresponding to high frequency signals are grouped in a second bonding area separated from the first bonding area.

[0106] The low-frequency signal can be an analog signal or a digital signal, and includes a power supply signal (such as AVDD, DVDD, etc.), a radio frequency enable signal (RF_en), a reference voltage signal (Vref), a bias adjustment signal (Rbias), and a circuit control signal (such as CS, CLK, SDI, SDO, PDI, etc.), and the chip pads corresponding to the above-mentioned low-frequency signals (such as digital signal pads connected to digital signal lines and analog signal pads connected to analog signal lines) are gathered in the first bonding area.

[0107] The high frequency signal includes, for example, a radio frequency signal (RF signal) and an antenna signal (RF_out), and the chip pads corresponding to the high frequency signal (for example, the radio frequency signal pad connected to the radio frequency signal line and the antenna signal pad connected to the antenna signal line) are assembled in the second bonding area. In this article, the low frequency signal refers to a signal with an operating frequency lower than 500 MHz, and the high frequency signal refers to a signal with an operating frequency higher than 500 MHz (for example, 10 GHz to 300 GHz or 10 GHz to 500 GHz).

[0108] In some embodiments, the ground signal AGND and the ground signal RF_GND can be used for shielding to reduce mutual interference between signals. In some embodiments, a first ground structure for transmitting the ground signal AGND is provided in the first bonding area, and a second ground structure for transmitting the ground signal RF_GND is provided in the second bonding area. By separating the first ground structure from the second ground structure, mutual interference between high-frequency signals and low-frequency signals can be further reduced. For detailed description of the first ground structure and the second ground structure, please refer to the following embodiments.

[0109] In some embodiments, the ground signal DGND is mainly transmitted in the thin film circuit structure 200, and the thin film circuit structure 200 is mainly used to transmit low frequency signals. To avoid the influence of low frequency signals on high frequency signals, the chip pad corresponding to the ground signal DGND is preferably also disposed in the first bonding area.

[0110] Figure 2 FIG. 1 is a cross-sectional diagram of an antenna device 1B according to an embodiment of the present invention. The antenna device 1B includes an array antenna unit 10B. For the convenience of description, Figure 2 Only one of the antenna units 10B is shown. Figure 3 is a schematic top view of an antenna device 1B according to an embodiment of the present invention. 4A to 4F yes Figure 3 A top view of the various conductive layers in the antenna unit 10B. Figure 2 Corresponding Figures 3 to 4F The position of the line A-A'.

[0111] It must be pointed out here that Figures 2 to 4F The implementation examples are used Figure 1 The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0112] Please refer to Figure 2 , Figure 3 and Figure 4A, the antenna electrode 110 is disposed on the first surface S1 of the transparent substrate 100 .

[0113] Please refer to Figure 2 , Figure 3 and Figure 4B , the ground electrode 132 and the bonding structure 134 are disposed on the second surface S2 of the transparent substrate 110. In this embodiment, the ground electrode 132 has two openings 132h, and the two bonding structures 134 are respectively disposed in the two openings 132h. The two bonding structures 134 are respectively electrically connected to the antenna electrode 110 through two substrate conductive through holes 120. For example, one is used to transmit a horizontally polarized electric field signal, and the other is used to transmit a vertically polarized electric field signal.

[0114] In the present embodiment, the ground electrode 132 includes a block portion 132a and wire portions 132b, 132c, and 132d extending outward from the block portion 132a. The block portion 132a overlaps the antenna electrode 110. In some embodiments, the width of the block portion 132a is greater than or equal to the width of the antenna electrode 110. The wire portion 132b is substantially parallel to the wire portion 132c and extends from the block portion 132a to both sides. The wire portion 132d is substantially perpendicular to the wire portion 132c and extends from the block portion 132a to the other two sides. In some embodiments, the area not covered by the ground electrode 132 is defined as the light transmission area of ​​the antenna unit 10B.

[0115] Please refer to Figure 2 , Figure 3 and Figure 4C , the first thin film conductive layer 210 includes a plurality of signal lines 211a, 211b, 212, 213, 214, 215, 216, 217, and 218. In some embodiments, the signal line 211a is used to transmit a circuit control signal SDI. In some embodiments, the signal line 211b is used to transmit a circuit control signal SDO. In some embodiments, the signal line 212 is used to transmit a power signal DVDD. In some embodiments, the signal line 213 is used to transmit a ground signal DGND. In some embodiments, the signal line 214 is used to transmit a reference voltage signal Vref. In some embodiments, the signal line 215 is used to transmit a radio frequency enable signal RF_en. In some embodiments, the signal line 216 is used to transmit a circuit control signal CS. In some embodiments, the signal line 217 is used to transmit a circuit control signal CLK. In some embodiments, the signal line 218 is used to transmit a circuit control signal PDI.

[0116] In some embodiments, the arrangement order of the signal lines 211a, 211b, 212, 213, 214, 215, 216, 217, 218 can be adjusted according to actual needs. In some embodiments, the signal lines 211a, 211b, 212, 213, 214, 215, 216, 217, 218 overlap the ground electrode 132, such as the block portion 132a and the wire portion 132c of the ground electrode 132.

[0117] In some embodiments, the signal lines 211 a , 211 b , 215 , 216 , 217 , and 218 may also be referred to as digital signal lines, and the signal lines 212 , 213 , and 214 may also be referred to as analog signal lines.

[0118] Please refer to Figure 2 , Figure 3 , Figure 4C and Figure 4D , the second thin film conductive layer 230 includes a plurality of first conductive features 231a, 231b, 231c, 231d, 231e and a plurality of second conductive features 232a, 232b. In the present embodiment, the first conductive features 231c extend from above the corresponding signal lines 211a, 211b, 212, 214, 215, 216, 217, 218 to below the chip 410, wherein the first conductive features 231c are connected to the signal lines 211a, 211b, 212, 214, 215, 216, 217, 218 through the corresponding contact portions PH1. The first conductive feature 231e is connected to the signal line 213 through the corresponding contact portion PH1. The first conductive features 231a, 231b, 231d and the second conductive features 232a, 232b are disposed below the chip 410.

[0119] In some embodiments, the first conductive feature 231a and the first conductive feature 231e are configured to transmit the ground signal AGND / DGND. In some embodiments, one or more of the first conductive features 231a include an extension 231a-1, and the extension 231a-1 can extend between two adjacent first conductive features 231c. In this embodiment, the extension 231a-1 is located between the first conductive feature 231c for transmitting the reference voltage signal Vref and the first conductive feature 231c for transmitting the circuit control signal SDO.

[0120] Please refer to Figure 2 , Figure 3 , Figure 4D and Figure 4EThe first redistribution layer 310 includes a first grounding structure 314 , a second grounding structure 313 , a plurality of first transfer structures 311 b , 311 c , 311 d , and 311 e , and a plurality of second transfer structures 312 b and 312 c , which are separated from each other.

[0121] The first ground structure 314 overlaps with the first transfer structures 311b, 311c, 311d, 311e at the first bonding region BR1. The second ground structure 313 and the second transfer structures 312b, 312c overlap at the second bonding region BR2. At least part of the first transfer structures 311b, 311c, 311d, 311e are surrounded by the first ground structure 314. More specifically, each of the first transfer structures 311b, 311c, 311d, 311e is completely or partially surrounded by the first ground structure 314, thereby reducing signal interference on the first transfer structures 311b, 311c, 311d, 311e. Similarly, at least part of the second transfer structures 312b, 312c are surrounded by the second ground structure 313. More specifically, each of the second switching structures 312 b and 312 c is completely or partially surrounded by the second ground structure 313 , thereby reducing signal interference on the second switching structures 312 b and 312 c.

[0122] The first ground structure 314 includes a block portion 314a overlapping the first bonding region BR1 and a wire portion 314b extending outward from the block portion 314a. The block portion 314a of the first ground structure 314 overlaps the block portion 132a of the ground electrode 132 (see Figure 4B ), and the wire portion 314b of the first grounding structure 314 overlaps the wire portion 132c of the grounding electrode 132 (please refer to Figure 4B ). The first ground structure 314 is connected to the first conductive feature 231a through the corresponding contact portion PH2.

[0123] In some embodiments, the first ground structure 314 is optionally connected to the extension 231a-1 of one or more first conductive features 231a of the second thin film conductive layer 230 through one or more contacts PH2-1. The width of the contact PH2-1 is less than the width of the contact PH2. In some embodiments, the contact PH2-1 and the extension 231a-1 can be omitted.

[0124] The second ground structure 313 includes a block portion 313a overlapping the second bonding region BR2 and a wire portion 313b extending outward from the block portion 313a. The block portion 313a of the second ground structure 313 overlaps the block portion 132a of the ground electrode 132 (see Figure 4B ), and the wire portion 313b of the second grounding structure 313 overlaps the wire portion 132b of the grounding electrode 132 (please refer to Figure 4B ). The first ground structure 314 is connected to the second conductive feature 232a through the corresponding contact portion PH2.

[0125] In the present embodiment, the second ground structures 313 are connected to the corresponding first conductive features 232 a through a plurality of contacts PH2 .

[0126] In the present embodiment, the first transfer structure 311b overlaps the first conductive feature 231b and is connected to the first conductive feature 231b through the corresponding contact portion PH2. The plurality of first transfer structures 311c overlap the plurality of first conductive features 231c, respectively, and are connected to the corresponding first conductive features 231c through the corresponding contact portion PH2. In the present embodiment, the first transfer structure 311d overlaps the first conductive feature 231d and is connected to the corresponding first conductive feature 231d through the corresponding contact portion PH2.

[0127] In the present embodiment, the first transfer structure 311e overlaps the first conductive feature 231e, and is connected to the corresponding first conductive feature 231e through the corresponding contact portion PH2, and is further connected to the signal line 213 for transmitting the ground signal DGND through the first conductive feature 231e. In some embodiments, the first transfer structure 311e is separated from the first ground structure 314, but the present invention is not limited thereto. In other embodiments, the first transfer structure 311e is connected to the first ground structure 314 as a whole. In other words, the first ground structure 314 is electrically connected to the signal line 213, so that the ground signal AGND on the first ground structure 314 is substantially equal to the ground signal DGND on the signal line 213.

[0128] In the present embodiment, the second transfer structure 312 b overlaps the second conductive feature 232 b and is connected to the second conductive feature 232 b through the corresponding contact portion PH2 .

[0129] The second transfer structures 312c overlap the bonding structures 134, respectively, and are connected to the corresponding bonding structures 134 through the corresponding conductive vias LH3a. The conductive vias LH3a pass through the second dielectric layer 240, the first dielectric layer 220, and the buffer layer 140.

[0130] In some embodiments, the conductive via LH3a is formed by a laser drilling process, and the angle between the sidewall and the bottom surface of the conductive via LH3a (ie, the inclination angle of the sidewall of the conductive via LH3) is 70 degrees to 75 degrees.

[0131] In the present embodiment, the second ground structure 313 is connected to the ground electrode 132 through a plurality of conductive vias LH3b. The conductive vias LH3b pass through the second dielectric layer 240, the first dielectric layer 220, and the buffer layer 140. In some embodiments, the conductive vias LH3b are formed by a laser drilling process, and the angle between the sidewall and the bottom surface of the conductive vias LH3b (i.e., the inclination angle of the sidewall of the conductive vias LH3b) is 70 degrees to 75 degrees. The conductive vias LH3b are arranged around the conductive vias LH3a.

[0132] The insulating layer 320 is located on the first grounding structure 314 , the second grounding structure 313 , the plurality of first transfer structures 311 b , 311 c , 311 d , and 311 e , and the plurality of second transfer structures 312 b and 312 c .

[0133] Please refer to Figure 2 , Figure 3 , Figure 4E and Figure 4F , the second redistribution layer 330 includes a plurality of first pads 331a, 331b, 331c, 331d, 331e located in the first junction region BR1 and a plurality of shielding layers 332a and a plurality of second pads 332b, 332c, 332d located in the second junction region BR2. In the present embodiment, the second redistribution layer 330 further includes a signal line 333 extending outward from the first junction region BR1 and a signal line 334 extending outward from the second junction region BR2. The first pads 331a, 331b, 331c, 331d, the shielding layer 332a, the second pads 332b, 332c, 332d, the signal line 333 and the signal line 334 are located on the insulating layer 320. The second redistribution layer 330 is connected to the first redistribution layer 310 through a plurality of conductive vias LH2a passing through the insulating layer 320.

[0134] The first pads 331 a are connected to the first ground structure 314 through the corresponding conductive vias LH2 a.

[0135] The first pad 331b overlaps the corresponding opening 314h of the first ground structure 314, and is connected to the first transfer structure 311b in the opening 314h through the corresponding conductive via LH2a, and is electrically connected to the first conductive feature 231b through the first transfer structure 311b (see Figure 4D In some embodiments, the first transfer structure 311b and the first conductive feature 231b may be omitted. The signal line 333 is connected to the first pad 331b. In some embodiments, the signal line 333 is configured to transmit the power signal AVDD.

[0136] The first pads 331c overlap the corresponding openings 314h of the first ground structure 314, and are connected to the first transfer structures 311c in the openings 314h through the corresponding conductive vias LH2a. The first pads 331c are electrically connected to the first conductive features 231c through the first transfer structures 311c (see Figure 4D ), and then electrically connected to signal lines 211a, 211b, 212, 214, 215, 216, 217, 218 (please refer to Figure 4C In the present embodiment, the first pad 331c is configured to transmit the low-frequency signal (including the power signal (DVDD), the RF enable signal (RF_en), the reference voltage signal (Vref) and the circuit control signal (CS, CLK, SDI, SDO, PDI)) required by the control chip 410, wherein the first pad 331c for transmitting the power signal (DVDD) and the reference voltage signal (Vref) may also be referred to as an analog signal pad, and the first pad 331c for transmitting the RF enable signal (RF_en) and the circuit control signal (CS, CLK, SDI, SDO, PDI) may also be referred to as a digital signal pad.

[0137] The first pad 331d overlaps the corresponding opening 314h of the first ground structure 314, and is connected to the first transfer structure 311d in the aforementioned opening 314h through the corresponding conductive via LH2a. The first pad 331d is electrically connected to the first conductive feature 231d through the first transfer structure 311d. In some embodiments, the first pad 331d is used to transmit a bias adjustment signal (Rbias), and the first pad 331d can also be called an analog signal pad.

[0138] The digital signal pads and the analog signal pads are electrically connected to the first transfer structures 311c and 311d respectively.

[0139] The first pad 331 e is connected to the corresponding first transfer structure 311 e or the first ground structure 314 through the corresponding conductive via LH2 a and is used to transmit the ground signal AGND / DGND.

[0140] The shielding layer 332a is connected to the second grounding structure 313 through the corresponding plurality of conductive vias LH2a. In the present embodiment, each shielding layer 332a is also electrically connected to the second grounding structure 313 through a plurality of conductive vias LH2b, and further electrically connected to the grounding electrode 132 through LH3b of the second grounding structure 313 (see Figure 4B) In the present embodiment, the shielding layer 332a, the ground electrode 132 and the second ground structure 313 are all configured to transmit a ground signal (RF_GND). In other embodiments, LH3b of the second ground structure 313 may be omitted, and the conductive via LH2b of the shielding layer 332a may continuously pass through the insulating layer 320, the second dielectric layer 240, the first dielectric layer 220 and the buffer layer 310, and be connected to the ground electrode 132.

[0141] The second pad 332b overlaps the corresponding opening 313h of the second ground structure 313 and is connected to the second transfer structure 312b in the opening 313h through the corresponding conductive via LH2a. The second pad 332b is electrically connected to the second conductive feature 232b through the second transfer structure 312b (see Figure 4D ). In some embodiments, the second transfer structure 312b and the second conductive feature 232b can be omitted. The second pad 332b is connected to the signal line 334. In some embodiments, the signal line 334 is configured to transmit a radio frequency signal (RF signal) and can be referred to as an RF signal line. The second pad 332b can also be referred to as an RF signal pad. In some embodiments, the RF signal pad is disposed at a corner of the chip 410.

[0142] The second pads 332c overlap the corresponding openings 313h of the second ground structure 313, and are connected to the second transfer structures 312c in the openings 313h through the corresponding conductive vias LH2a. The second pads 332c are electrically connected to the plurality of bonding structures 134 through the second transfer structures 312c (see Figure 4B ) and the antenna electrode 110 (please refer to Figure 4A ). The second pad 332c is electrically connected to the chip 410 and the antenna electrode, and is used to transmit the antenna signal (RF_out). The second pad 332c may also be referred to as the antenna signal pad. The RF signal pad and the antenna signal pad are electrically connected to the second adapter structure 312b and the second adapter structure 312c, respectively.

[0143] In some embodiments, in orthographic projection, the distance between the center of the antenna signal pad (ie, the second pad 332c) and the center of the antenna electrode 110 is about 800 microns. In addition, the risk of short circuit between the antenna signal pad (ie, the second pad 332c) and other pads can be reduced.

[0144] In other embodiments, the second transfer structure 312c may be omitted, so that the conductive via LH2a of the second pad 332c continuously passes through the insulating layer 320, the second dielectric layer 240, the first dielectric layer 220 and the buffer layer 310, and is connected to the bonding structure 134. In this way, the impedance variation problem of signal transmission between different conductive layers can be reduced.

[0145] The shielding layer 332a at least partially surrounds the second pad 332c to reduce interference of external signals on the antenna signal (RF_out).

[0146] In some embodiments, the conductive vias LH2b of the shielding layer 332a are arranged around the conductive vias LH2a of the second pad 332c, thereby further reducing the interference of external signals on the antenna signal (RF_out).

[0147] The second pad 332d is connected to the second ground structure 313 through the corresponding conductive via LH2a. In some embodiments, the second pad 332d may be omitted, or the second pad 332d may be connected to the shielding layer 332a.

[0148] The chip 410 is bonded to the first pads 331a, 331b, 331c, 331d, the shielding layer 332a and the second pads 332b, 332c, 332d. In some embodiments, in the orthographic projection, the RF signal line (i.e., the signal line 334) is close to one side (e.g., the upper side) of the chip 410, and the signal lines 211a, 211b, 212, 213, 214, 215, 216, 217, 218 are close to the other side (e.g., the lower side) of the chip 410.

[0149] Figure 5A yes Figure 3 A partially enlarged view of the antenna device 1B. Figure 5B yes Figure 5A Schematic diagram of the cross section of line B-B'. Please refer to Figure 3 , Figure 5A and Figure 5B The signal line 334 (RF signal line) is located on the insulating layer 320 . The signal line 334 overlaps the wire portion 313 b of the second ground structure 313 , and the width SW of the wire portion 313 b of the second ground structure 313 is greater than the width IW of the signal line 334 .

[0150] In the present embodiment, the wire portion 313b is electrically connected to the second thin film conductive layer 230 through a plurality of conductive vias H1 formed by a laser process. A plurality of openings are formed in the first dielectric layer 220 and the second dielectric layer 240 by lithography and etching processes. A plurality of contact portions H2 of the second thin film conductive layer 230 are respectively filled in the plurality of openings of the second dielectric layer 240 and contact the first thin film conductive layer 210. A plurality of contact portions H3 of the first thin film conductive layer 210 are respectively filled in the plurality of openings of the first dielectric layer 220 and contact the wire portion 132b of the ground electrode 132. In the present embodiment, each conductive via H1 overlaps a corresponding contact portion H2 and a corresponding contact portion H3. In some embodiments, the conductive via H1, the contact portion H2, and the contact portion H3 have different widths. For example, the width of the contact portion H3 is greater than the width of the contact portion H2, and the width of the contact portion H2 is greater than the width of the conductive via H1.

[0151] Fig. 6A is a simulation curve of S11 parameters of some antenna devices according to an embodiment of the present invention. Figure 6B 1 is a simulation curve diagram of the S21 parameters of some antenna devices according to an embodiment of the present invention. In the antenna device used in the simulation, the RF signal line (refer to Figure 5A The signal line 334 has a width of 130 microns, a length of 1 mm and a thickness of 10 microns. A conductor portion of a second grounding structure is provided 50 microns below the RF signal line (see Figure 5A The conductor portion 313b is formed by adjusting the width of the conductor portion while fixing the width of the RF signal line to 130 μm. Assume that there is a dielectric having a thickness of 50 μm and a relative dielectric constant εr of 2.5 between the RF signal line and the second ground structure, and the vacuum dielectric constant ε0 is 1.

[0152] When the signal frequency is 30 GHz, the dB value of S11 and the dB value of S21 are shown in Table 2 respectively.

[0153] Table 2

[0154] Width of lead wire S11 dB value S21 dB value 260 microns -20.637112 -0.20318622 390 microns -24.194646 -0.17211097 520 microns -26.087466 -0.16263169 650 microns -27.396037 -0.15755175 780 microns -27.966025 -0.1557127 910 microns -28.180495 -0.15488827

[0155] It can be seen from Table 2 that when the width SW of the conductor portion 313b (see Figure 5A ) is about three times the width IW of the signal line 334, the signal loss will gradually tend to saturation. Figure 5A ) is about five times or more the width IW of the signal line 334, the insertion loss difference is only about 2% or less.

[0156] Figure 7FIG. 1 is a schematic top view of an antenna unit 10C according to another embodiment of the present invention. It must be noted that: Figure 7 The implementation examples are used Figure 2 The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0157] Please refer to Figure 7 In this embodiment, the thin film circuit structure includes one or more digital signal lines 219. The digital signal lines 219 are electrically connected to the chip 410 through one or more first pads 331c in the first bonding region BR1.

[0158] One or more signal lines 316 are used to transmit a ground signal (DGND) and / or a power signal (DVDD). In this embodiment, the signal line 316 does not extend below the chip 410, but the invention is not limited thereto.

[0159] The first ground structure 314 is used to transmit a ground signal (AGND). The signal line 333 is used to transmit a power signal (AVDD). The first ground structure 314 is electrically connected to the chip 410 through the first pad 331a in the first bonding region BR1. The signal line 333 is electrically connected to the chip 410 through the first pad 331b in the first bonding region BR1.

[0160] The second ground structure 313 is used to transmit a ground signal (RF_GND). The signal line 334 is used to transmit a radio frequency signal (RFsignal). The second ground structure 313 is electrically connected to the chip 410 through the second pad 332d in the second bonding region BR2. The signal line 334 is electrically connected to the chip 410 through the second pad 332b in the second bonding region BR2. The second pad 332c in the second bonding region BR2 is electrically connected to the chip 410 and the antenna electrode 110, and is used to transmit an antenna signal (RF_out). For example, the two second pads 332c are respectively used to transmit a horizontally polarized electric field antenna signal (RF_out_H) and a vertically polarized electric field antenna signal (RF_out_V). The second pad 332e in the second bonding region BR2 is electrically connected to the chip 410 and the ground electrode 132.

[0161] Based on the above, the first ground structure 314, the first pad 331a and the first pad 331b are set in the first bonding area BR1, and the second ground structure 313, the second pad 332b, the second pad 332c, the second pad 332d and the second pad 332e are set in the second bonding area BR2, thereby reducing the interference of other signals to the high-frequency signal.

[0162] In other embodiments, the first bonding region BR1 and the second bonding region BR2 may also be in other shapes.

[0163] Figure 8 is a cross-sectional schematic diagram of an antenna device 1D according to an embodiment of the present invention. It must be noted here that: Figure 7 The implementation examples are used Figure 2 The component numbers and partial contents of the embodiments are the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. For the description of the omitted parts, please refer to the above embodiments, which will not be repeated here. Please refer to Figure 8 The antenna device 1D includes a transparent substrate 100 and a plurality of antenna units 10D disposed on the transparent substrate 100. The antenna units 10D are arranged in an array, for example, and light transmission regions TR are provided between the antenna units 10D.

[0164] Each antenna unit 10D includes an antenna electrode 110 , a ground electrode 132 , a thin film circuit structure 200D, a redistribution structure 300 , and a chip 410 .

[0165] In this embodiment, each antenna unit 10D includes a thin film transistor T disposed in a thin film circuit structure 200D. For example, in this embodiment, a gate dielectric layer 250 is further provided between the first dielectric layer 220 and the buffer layer 140. A plurality of semiconductor layers SM are further provided between the gate dielectric layer 250 and the buffer layer 140.

[0166] The first thin film conductive layer 210 is located on the gate dielectric layer 250 and includes a gate G overlapping the semiconductor layer SM. The first dielectric layer 220 covers the gate G. The second thin film conductive layer 230 is located on the first dielectric layer 220 and includes a plurality of source / drain electrodes SD. In the present embodiment, each thin film transistor T includes a corresponding semiconductor layer SM, a corresponding gate G, and a corresponding source / drain electrode SD. In the present embodiment, the thin film transistor T is a top gate thin film transistor, but the present invention is not limited thereto. In other embodiments, the thin film transistor T is a bottom gate thin film transistor, a double gate thin film transistor, or other types of thin film transistors.

[0167] The thin film transistor T is electrically connected to the chip 410 and the digital signal line 219 in the thin film circuit structure 200D. The thickness of the digital signal line 219 is less than the thickness of the signal line 334 (RF signal line). The digital signal line 219 is used to transmit any digital signal described in the previous embodiments.

[0168] In this embodiment, the redistribution structure 300 further includes pads P. The pads P are used to connect to an external flexible printed circuit, for example.

[0169] Fig. 9FIG. 1 is a schematic top view of an antenna device 1D according to an embodiment of the present invention. In this embodiment, the antenna device 1D includes a plurality of antenna units arrayed on a transparent substrate 100 . Fig. 9 The chip 410 in the antenna unit is shown, and other structures in the antenna unit are omitted. Fig. 9 In , a line segment can be used to represent a single signal line or multiple signal lines close together.

[0170] In this embodiment, the first thin film conductive layer 210 and / or the second thin film conductive layer 230 include one or more digital signal lines GL, DL, and are used to transmit digital signals to each antenna unit. Part of the digital signal line DL extends horizontally through multiple antenna units. Part of the digital signal line GL extends vertically through multiple antenna units. In this embodiment, the digital signal line GL is used, for example, to control the gate G of the thin film transistor T in the antenna unit (see Figure 8 ).

[0171] The radio frequency input signal (RF_in) is transmitted to the plurality of antenna units 10D via the signal line 334 in the second redistribution layer 330 .

[0172] The ground signal (AGND) and the ground signal (RF_GND) are transmitted to the plurality of antenna units through the first ground structure 314 and the second ground structure 313 in the first redistribution layer 310 , respectively.

[0173] The power signal (AVDD) is transmitted to the plurality of antenna units through the signal line 333 of the second redistribution layer 330 .

[0174] Fig.10 4 is a functional block diagram of an antenna device according to an embodiment of the present invention. In this embodiment, each antenna unit 10 includes a chip 410, and the chip 410 includes a BFIC.

[0175] In this embodiment, ground signals (e.g., AGND, RF_GND, etc.), power signals (e.g., AVDD, DVDD, etc.), RF signals (RF signal), RF enable signals (RF_en), reference voltage signals (Vref), and various circuit control signals (e.g., CS, CLK, SDI, SDO, PDI, etc.) are connected to the chip 410.

[0176] In this embodiment, the circuit control signal is provided to the signal control circuit module SCC and the memory circuit module MC in the chip 410. The signal control circuit module SCC provides a signal to the variable gain amplifier and phase shifter module VGPS.

[0177] In this embodiment, the RF signal is processed by a power divider and then provided to a variable gain amplifier and phase shifter module VGPS. The variable gain amplifier and phase shifter module VGPS provides a signal to a power amplifier and / or a low loss amplifier module PALNA.

[0178] The power amplifier and / or low-loss amplifier module PALNA provides a first antenna signal (eg, a horizontally polarized electric field antenna signal (RF_out_H)) and a second antenna signal (eg, a vertically polarized electric field antenna signal (RF_out_V)) to the antenna electrode 110 .

[0179] In some embodiments, other passive components PD, such as inductors, capacitors and / or resistors, may be additionally disposed in the antenna unit 10. The passive components are connected to the power amplifier and / or low-loss amplifier module PALNA of the chip 410.

[0180] In summary, the present invention reduces interference to high-frequency signals by separating pads for high-frequency signals from pads for low-frequency signals.

Claims

1. An antenna device, comprising: a transparent substrate; A plurality of antenna units are disposed on the transparent substrate, wherein each of the antenna units comprises: An antenna electrode is disposed on a first surface of the transparent substrate; A ground electrode is disposed on a second surface of the transparent substrate opposite to the first surface; a thin film circuit structure, located on the ground electrode and including a digital signal line; A redistribution structure is located on the thin film circuit structure and includes: a digital signal pad electrically connected to the digital signal line; An analog signal line and an analog signal pad electrically connected to the analog signal line; A radio frequency signal line and a radio frequency signal pad electrically connected to the radio frequency signal line; and an antenna signal pad electrically connected to the antenna electrode; and A chip is bonded to the digital signal pad, the analog signal pad, the RF signal pad and the antenna signal pad, wherein the digital signal pad and the analog signal pad are arranged in a first bonding area, and the RF signal pad and the antenna signal pad are arranged in a second bonding area separated from the first bonding area.

2. The antenna device as claimed in claim 1, wherein the rewiring structure comprises: A first grounding structure and a second grounding structure separated from each other; an insulating layer, located on the first grounding structure and the second grounding structure; as well as A shielding layer is located on the insulating layer and at least partially surrounds the antenna signal pad, wherein the shielding layer is electrically connected to the second grounding structure.

3. The antenna device as described in claim 2 further includes a plurality of first transfer structures, wherein the first grounding structure overlaps with the plurality of the first transfer structures in the first bonding area, and the second grounding structure overlaps the second bonding area, wherein at least a portion of the plurality of the first transfer structures are surrounded by the first grounding structure, and wherein the antenna signal pad includes a first conductive through-hole passing through the insulating layer. 4 . The antenna device as claimed in claim 3 , wherein the shielding layer comprises a plurality of second conductive vias passing through the insulating layer, wherein the plurality of second conductive vias are arranged around the first conductive via. 5 . The antenna device as claimed in claim 3 , wherein the digital signal pad and the analog signal pad are electrically connected to a plurality of the first transfer structures respectively.

6. The antenna device as described in claim 3, wherein the thin film circuit structure includes a first thin film conductive layer, a dielectric layer and a second thin film conductive layer deposited in sequence, wherein the second thin film conductive layer is electrically connected to the first thin film conductive layer through at least one contact portion located in the dielectric layer, wherein the inclination angle of the side wall of the contact portion is different from the inclination angle of the side wall of the first conductive through hole.

7. The antenna device as claimed in claim 1, wherein the rewiring structure comprises: A first grounding structure and a second grounding structure separated from each other, wherein the second grounding structure comprises a block portion overlapping the second bonding area and a wire portion extending outward from the block portion; as well as An insulating layer is located on the first grounding structure and the second grounding structure, wherein the RF signal line is located on the insulating layer and overlaps the wire portion of the second grounding structure, and the width of the wire portion of the second grounding structure is greater than the width of the RF signal line.

8. The antenna device as claimed in claim 1, wherein the thin film circuit structure comprises a thin film transistor, and the thin film transistor is electrically connected to the chip and the digital signal line, wherein the thickness of the digital signal line is smaller than the thickness of the radio frequency signal line.

9. An antenna device, comprising: a transparent substrate; A plurality of antenna units are disposed on the transparent substrate, wherein each of the antenna units comprises: An antenna electrode is disposed on a first surface of the transparent substrate; A ground electrode is disposed on a second surface of the transparent substrate opposite to the first surface; a thin film circuit structure located on the ground electrode; A redistribution structure is located on the thin film circuit structure and includes: A first grounding structure and a second grounding structure separated from each other and overlapping the grounding electrode; an insulating layer, located on the first grounding structure and the second grounding structure; and a first pad and a second pad located on the insulating layer, wherein the first pad overlaps a first opening of the first grounding structure, and the second pad overlaps a second opening of the second grounding structure, wherein the first grounding structure and the first pad overlap a first bonding area, and the second grounding structure and the second pad overlap a second bonding area separated from the first bonding area; and A chip overlaps the first bonding area and the second bonding area and is bonded to the first pad and the second pad.

10. The antenna device as claimed in claim 9, wherein the rewiring structure comprises: a first transfer structure located in the first opening, wherein the first pad is electrically connected to the first transfer structure; as well as A shielding layer is located on the insulating layer and at least partially surrounds the second pad, wherein the second pad has a first conductive via passing through the insulating layer, wherein the shielding layer has a plurality of second conductive vias passing through the insulating layer, wherein the plurality of second conductive vias are arranged around the first conductive via.

11. The antenna device as claimed in claim 9, wherein the second grounding structure comprises a block portion overlapping the second bonding area and a conductor portion extending outward from the block portion, wherein the redistribution structure further comprises: A radio frequency signal line is located on the insulating layer, wherein the radio frequency signal line overlaps the conductor part of the second grounding structure, and the width of the conductor part of the second grounding structure is greater than the width of the radio frequency signal line.

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