A three-port bidirectional supercapacitor power controller

Abstract

The present invention discloses a three-port bidirectional supercapacitor power controller, which relates to the field of electronic numerical control technology. The controller includes a sampling circuit, a main control circuit and a converter main topology; the converter main topology has three ports, and the three ports are respectively connected to the chassis, the capacitor group and the battery, wherein the chassis and the battery are respectively connected in parallel to the converter main topology input terminal, and the capacitor group is connected in parallel to the converter main topology output terminal; the sampling circuit is used to sample the voltage of the converter main topology input terminal and the converter main topology output terminal and the current of the three ports to obtain the sampling value; the main control circuit is used to calculate the topology efficiency according to the sampling value, and allocate the duty cycle for the two half-bridges of the converter main topology; the converter main topology controls the expected voltage according to the duty cycle, and switches the charge and discharge mode. The present invention can realize the bidirectional transmission of electric energy, which is convenient for energy management and chassis kinetic energy recovery.

Description

[0001] This application is a divisional application. The application number of the original application is 202410710709.4, the application date is June 4, 2024, and the name of the invention is "A three-port bidirectional supercapacitor power controller". Technical Field

[0002] The present invention relates to the technical field of electronic numerical control, and more particularly to a three-port bidirectional super capacitor power controller. Background Art

[0003] According to the RoboMaster competition rules, both teams need to install a referee system on their robots, which will detect the robot's "health", "chassis power", "projectile firing rate" and other information, and send it back to the server. The referee system will punish the robot's violations to ensure that the competition is fair and just.

[0004] During the competition, the chassis power of the robots of both teams will be limited within a certain range by the rules. Robots that exceed the limit will have their corresponding "health" deducted by the referee system. However, robots tend to consume higher power when maneuvering at high speeds, which can easily exceed the limit. This creates a contradiction between the robot's high-speed movement requirements and the chassis power limit. At the same time, when the robot is replenishing projectiles or shooting at fixed points, the chassis power will be far lower than the rule limit, resulting in energy waste, which in turn creates a need for energy storage and redistribution.

[0005] Therefore, designing a three-port bidirectional supercapacitor power controller to perform bidirectional constant power charging and discharging management on the supercapacitor and realize energy recovery during electric braking of the robot chassis is an urgent problem that technicians in this field need to solve. Summary of the invention

[0006] In view of this, the present invention provides a three-port bidirectional supercapacitor power controller to achieve bidirectional transmission of electric energy, thereby facilitating energy management and chassis kinetic energy recovery.

[0007] In order to achieve the above object, the present invention adopts the following technical solution:

[0008] A three-port bidirectional supercapacitor power controller, the controller comprising a sampling circuit, a main control circuit and a converter main topology;

[0009] The converter main topology has three ports, and the three ports are respectively connected to the chassis, the capacitor bank, and the battery, wherein the capacitor bank is connected in parallel to a port at one end of the converter main topology, and the chassis and the battery are respectively connected in parallel to two ports at the other end of the converter main topology;

[0010] The sampling circuit is used to sample the voltage at both ends of the main topology of the converter and the current at three ports to obtain sampling values;

[0011] The main control circuit is used to calculate the topology efficiency according to the sampled values ​​and allocate duty cycles to the two half-bridges of the main topology of the converter;

[0012] The converter main topology controls the expected voltage according to the duty cycle and switches the charging and discharging modes.

[0013] Preferably, the main topology of the converter consists of a BUCK half-bridge and a BOOST half-bridge, the two half-bridges are driven by half-bridge drivers respectively, and the main control circuit includes a high-resolution timer, and the half-bridge driver is driven by the high-resolution timer.

[0014] Preferably, the main control circuit is used to calculate the topology efficiency according to the sampled value and allocate the duty cycle to the two half-bridges of the main topology of the converter, including:

[0015] The main control circuit calculates the topological efficiency after digitally filtering the sampled values, constructs a current and voltage closed loop using a closed-loop algorithm, calculates the error and obtains the duty cycle output, and performs output compensation according to the topological efficiency and allocates the duty cycle for the two half-bridges of the main topology of the converter.

[0016] Preferably, the sampled values ​​are filtered to obtain capacitor voltage, capacitor current, chassis voltage, chassis current, battery voltage, and battery current;

[0017] The topological efficiency calculation formula is as follows:

[0018]

[0019]

[0020] Preferably, the current closed loop is to close the charging current and the discharging current on the capacitor side, including:

[0021] Calculate the expected current based on the charging power, discharging power and topology efficiency;

[0022] Comparing the capacitor current with the expected current using a closed-loop algorithm and calculating a current comparison value increment, and when the comparison value changes, the duty cycle changes;

[0023] The desired voltage output by the main topology of the converter is changed according to the duty cycle, and a voltage difference is formed between the desired voltage and the actual voltage of the capacitor group, thereby generating a charging current and a discharging current, and forming a current closed loop.

[0024] Preferably, the voltage closed loop acts in charging mode;

[0025] Comparing the capacitor voltage with the expected voltage using a closed-loop algorithm and calculating an output voltage comparison value increment to obtain a calculation result;

[0026] The calculation result and the current closed loop are subjected to a double-loop competition, and the minimum value wins.

[0027] Preferably, the duty cycle is a ratio of a half-bridge comparison value to a period of the high-resolution timer;

[0028] The calculation formula of the half-bridge comparison value is as follows:

[0029]

[0030] The total comparison value is the comparison value output by the closed-loop algorithm, and the period is the high-resolution timer period.

[0031] Preferably, the converter main topology controls the expected voltage according to the duty cycle to switch the charging and discharging mode, including:

[0032] If the expected voltage is higher than the actual voltage of the capacitor bank, current will flow from the chassis to the capacitor bank, which is a charging mode;

[0033] If the expected voltage is lower than the actual voltage of the capacitor group, current will flow from the capacitor group to the chassis, which is a discharge mode.

[0034] Preferably, the main control circuit is connected to the display circuit, and the main control circuit is also connected to the communication circuit to communicate with the host computer.

[0035] It can be seen from the above technical solutions that, compared with the prior art, the present invention discloses a three-port bidirectional supercapacitor power controller, which has the following beneficial effects:

[0036] 1. The chassis is not directly connected in parallel with the capacitor bank, which solves the problem of chassis undervoltage caused by capacitor bank discharge and voltage drop. At the same time, the battery and chassis are connected to the capacitor bank through a buckboost topology. Due to the bidirectional symmetry of the topology, bidirectional transmission of electric energy can be achieved, which is convenient for energy management and chassis kinetic energy recovery.

[0037] 2. The present invention only uses a single current loop and a single voltage loop to achieve bidirectional constant power control of the capacitor group; the current closed loop can directly control the output current, and has a faster response speed than the solution of closed loop for power. At the same time, in the charging state, a voltage closed loop is added to limit the charging current through the strategy of dual-loop competition to prevent overcharging of the capacitor; in the discharge state, the voltage loop will fail, and the system will be completely taken over by the current loop to control the discharge current and quickly establish the charge and discharge balance. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0039] Figure 1 This is the overall circuit structure diagram of the three-port bidirectional supercapacitor power controller proposed by the present invention;

[0040] Figure 2 A schematic diagram of energy flow of a three-port bidirectional supercapacitor power controller proposed in the present invention;

[0041] Figure 3 This is a hardware connection diagram of the three-port bidirectional supercapacitor power controller proposed in the present invention;

[0042] Figure 4 A schematic diagram of an OLED screen display interface provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0044] In the robomaster robot competition rules, the referee allows the use of supercapacitors with a total capacity of less than 2000J to provide additional power for the robot, but supercapacitors cannot be used without limit, and their charging power will also be regarded as part of the chassis power consumption. Therefore, designing a supercapacitor power controller has become a difficult problem to be solved. The controller proposed in the embodiment of the present invention maximizes the utilization rate of energy without exceeding the power, allowing the supercapacitor to follow the principle of "storing more and supplementing less". When the chassis energy consumption is low, the redundant energy is stored in the supercapacitor, and when the chassis power consumption exceeds the rule limit, the electric energy is released to the chassis as compensation, so as to improve the chassis maneuverability without exceeding the power.

[0045] The embodiment of the present invention discloses a three-port bidirectional supercapacitor power controller, referring to Figure 1 ,The controller includes a sampling circuit, a main control circuit and a converter main topology.

[0046] according to Figure 2 and Figure 3The converter main topology (i.e., DCDC topology) has three ports, which are respectively connected to the chassis, capacitor group, and battery (monitored by the referee system). The chassis and the battery are respectively connected in parallel to the two ports at one end of the converter main topology, and the capacitor group is connected in parallel to a port at the other end of the converter main topology.

[0047] The sampling circuit includes a current sampling circuit and a voltage sampling circuit. The current sampling circuit uses a rail-to-rail integrated operational amplifier to sample the voltage at both ends of the main topology, and the voltage sampling circuit uses a current sensing amplifier to sample the current of three ports to obtain a sampling value.

[0048] The main control circuit implements sampling value setting and filtering, topology efficiency calculation, voltage and current closed loop, and half-bridge duty cycle distribution based on MCU.

[0049] Specifically, the ADC sampling value is adjusted to the actual value, and digital filtering is performed to obtain the capacitor voltage, capacitor current, chassis voltage, chassis current, battery voltage, and battery current; the power at both ends of the topology is calculated based on the actual value after filtering, and the topology efficiency is calculated. The formula is as follows:

[0050]

[0051] The formation process of the current-voltage closed loop in this embodiment is as follows:

[0052] The current closed loop is to close the charging current and discharging current on the capacitor side. The current closed loop uses the current sensing amplifier chip to sample the high-side current and calculate the expected current based on the charging power, discharging power and topological efficiency. Specifically:

[0053] Expected charging power in charging mode = ideal topology power * topology efficiency;

[0054]

[0055] The incremental PID algorithm is used to compare the capacitor current with the expected current and calculate the current comparison value increment. When the comparison value changes, the duty cycle changes. The expected voltage output by the main topology of the converter is changed according to the duty cycle. A voltage difference is formed between the expected voltage and the actual voltage of the capacitor group, generating charging current and discharging current, thus forming a current closed loop.

[0056] The voltage closed loop only works when charging. The integrated operational amplifier is used to sample the capacitor bank voltage, and the incremental PID algorithm is used to compare the capacitor voltage with the expected voltage (capacitor full charge voltage) and calculate the output comparison value increment. The calculation result will compete with the current loop in a dual loop, and the minimum value wins.

[0057] The calculation result is the actual comparison value, that is, the previous comparison value + the calculation increment of this time (the comparison value calculation process is introduced in the subsequent allocation algorithm). The comparison value calculated by the voltage loop will be compared with the current loop, and the smaller result will be taken to limit the output. The winner of the dual-loop competition is the total comparison value, which is distributed to the two half-bridges according to the allocation algorithm described later.

[0058] The topology efficiency is sent to the closed-loop PID algorithm to calculate the error and obtain the duty cycle output. The real-time efficiency of the topology will be involved in the calculation of the loop target value, which can ensure that the target capacitor power is not affected by the topology power loss. Obtaining an accurate target value and coordinating it with the control algorithm can effectively avoid the overpower problem.

[0059] The embodiment of the present invention can realize bidirectional constant power control of the capacitor group by only using a single current loop and a single voltage loop. Before restarting the closed-loop control, the voltage at the capacitor end and the power supply voltage (the voltage at both ends of the topology) are detected first, and the open-loop duty cycle is calculated as the initial value of the incremental closed-loop algorithm, which can greatly reduce the time required for closed-loop convergence, thereby reducing the starting current, and can prevent voltage overshoot, eliminating the risk of overcurrent and overvoltage of the main topology switch device when the control board is powered on.

[0060] After the open-loop duty cycle is given, the interrupt is turned on and the closed-loop algorithm is run in the interrupt. The interrupt frequency is the switching frequency, which can achieve cycle-by-cycle control and improve the response speed of the system.

[0061] The current closed loop can directly control the output current, and has a faster response speed than the power closed loop solution. At the same time, when charging, a voltage closed loop is added to limit the charging current through a dual-loop competition strategy to prevent capacitor overcharging.

[0062] In the discharge state, the voltage loop will fail and the system will be completely taken over by the current loop to control the discharge current.

[0063] The main topology of the converter consists of a BUCK half-bridge and a BOOST half-bridge. The two half-bridges are driven by half-bridge drivers respectively, and the half-bridge drivers are driven by the MCU high-resolution timer. Specifically, the half-bridge driver receives the complementary PWM wave output by the MCU high-resolution timer, allocates duty cycle to the two half-bridges, and drives the main topology power elements to achieve energy conversion.

[0064] Furthermore, regarding the allocation of the half-bridge duty cycle, the two half-bridges are respectively controlled by two sets of complementary channels of the high-resolution timer, and the ratio of the half-bridge comparison value to the timer period is the half-bridge duty cycle.

[0065] Since the bootstrap capacitor of the half-bridge driver chip needs to be charged, the MOS tube cannot work at 100% duty cycle, so the maximum comparison value of the half-bridge is defined as: 0.95×cycle, and the minimum comparison value of the half-bridge is defined as: 0.05×cycle.

[0066] The comparison value calculated by PID is the "total comparison value" of the two half-bridges. When the calculated total comparison value is less than the maximum comparison value, the circuit is considered to be working in the BUCK state. At this time, in order to eliminate the influence of the BOOST half-bridge to the greatest extent, the half-bridge gain should be set to 1 as much as possible. According to the BOOST circuit gain The duty cycle is set to the minimum duty cycle, that is, the comparison value is: 0.05×cycle. The BUCK half-bridge comparison value is the calculated total comparison value.

[0067] When the calculated total comparison value increases, the duty cycle of the BUCK half-bridge also increases. When the total comparison value increases to close to the maximum comparison value, the gain α of the BUCK circuit is close to 1, which basically eliminates the influence of the BUCK half-bridge. If the output voltage is to continue to increase, the BOOST half-bridge needs to participate in the work. At this time, it is considered that the circuit is working in the BOOST state, and the comparison value of the BUCK half-bridge has increased to the maximum value, that is, 0.95×cycle, and cannot continue to increase. Therefore, the overflow comparison value is added to the BOOST half-bridge to continue to increase the output voltage. The overflow comparison value is: total comparison value-0.95×cycle. At this time, the comparison value of the BOOST half-bridge is the original comparison value plus the overflow comparison value, that is: 0.05×cycle+total comparison value-0.95×cycle.

[0068] The calculation method of the half-bridge comparison value can be obtained:

[0069]

[0070] This embodiment defines the ratio of the half-bridge comparison value to the timer period as the half-bridge duty cycle because, in general, two sets of complementary PWM signals are triggered by two comparison value registers, and the two registers control two half-bridges respectively. The output is set to 1 when the timer counts and is set to 0 when the comparison value is reached. However, such a PWM control method is not conducive to setting the sampling point. In the digital power supply system, the sampling point should be far away from the time point when the switching device is turned on and off. Therefore, the "analog center symmetry" PWM control method is used, that is, the sampling point is used as the symmetry point of the PWM waveform. Such a control method requires 4 comparison value registers to participate in the work. The comparison value registers CMP1 and CMP2 are responsible for the BUCK half-bridge. When the count reaches CMP1, the output is set to 1, and when the count reaches CMP2, the output is set to 0. The comparison value registers CMP3 and CMP4 are responsible for the BOOST half-bridge. When the count reaches CMP3, the output is set to 1, and when the count reaches CMP4, the output is set to 0. The timer output here refers to the control waveform of the upper bridge arm, and the waveform of the lower bridge arm is generated by complementing the waveform of the upper bridge arm and injecting it into the dead zone.

[0071] Since the BUCK half-bridge duty cycle is the duty cycle of the upper bridge arm, the setting value of the BUCK half-bridge comparison value register can be obtained:

[0072]

[0073] The BOOST half-bridge duty cycle is the duty cycle of the lower bridge arm, so the set value calculation formula is slightly different from the BUCK half-bridge:

[0074]

[0075] The main topology of the converter controls the desired voltage according to the duty cycle and switches the charge and discharge mode. The essence of building a current closed loop is to adjust the output voltage. The DCDC topology can achieve voltage conversion at both ends. If the desired voltage of DCDC is lower than the current capacitor voltage, the current will flow from the capacitor to the chassis to achieve discharge; if the desired output voltage of DCDC is higher than the current capacitor voltage, the current will flow from the chassis to the capacitor to achieve charging. Through the incremental PID algorithm, when the target current decreases to below the current current, the current error will be negative, the duty cycle will decrease, resulting in a decrease in the desired output voltage, and the system can quickly establish a discharge balance. Conversely, when the target current increases, the charging balance can also be quickly established.

[0076] Furthermore, the main control circuit is connected to the display circuit, and the main control circuit is also connected to the communication circuit to communicate with the host computer.

[0077] The embodiment of the present invention has a complete system in terms of information interaction, including a 0.96-inch OLED screen, two LED lamp beads, two buttons and two host computer interfaces. The lamp beads can indicate the working status or fault cause of the controller, as shown in Table 1.

[0078] Table 1 indicates the working status of the controller and the corresponding fault causes

[0079] LED1 is on...LED2 is on Normal operation LED1 is on...LED2 is off Input overvoltage LED1 off...LED2 on Input undervoltage LED1 is on...LED2 is off Input overcurrent

[0080] The OLED screen can display key information such as the controller's port parameters, working mode, current flow direction, etc. The OLED screen display interface diagram is as follows: Figure 4 As shown, Figure 4 The representative information is shown in Table 2.

[0081] Table 2 OLED screen display information

[0082]

[0083] The user can easily know from the screen that the capacitor bank is currently working in BOOST discharge mode, and can also send information such as the remaining voltage of the capacitor bank to the robot host computer through the CAN interface, so that the operator can check the working status of the capacitor bank through the host computer during the competition. In daily training and debugging, the UART interface can also be used to connect to the computer and observe the power curve through the serial port plotter. The controller firmware includes two protocols, "Firewater" and "Justfloat", which can adapt to most serial port software.

[0084] As an input medium, the buttons can be used to turn pages, or to directly set detailed target parameters, such as setting the referee system limit power, capacitor full charge voltage, etc., which can adapt to various types of supercapacitors and various robots in the competition, solving the pain point of needing to re-flash the firmware when the working conditions change. For the specific operation of its interactive logic and setting interface, refer to Table 3.

[0085] Table 3 Interaction logic and setting interface operation introduction

[0086]

[0087] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0088] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A three-port bidirectional supercapacitor power controller, characterized in that: The controller includes a sampling circuit, a main control circuit and a converter main topology; The converter main topology has three ports, and the three ports are respectively connected to the chassis, the capacitor bank, and the battery, wherein the capacitor bank is connected in parallel to a port at one end of the converter main topology, and the chassis and the battery are respectively connected in parallel to two ports at the other end of the converter main topology; The sampling circuit is used to sample the voltage at both ends of the main topology of the converter and the current at three ports to obtain sampling values; wherein the sampling circuit includes a current sampling circuit and a voltage sampling circuit, the current sampling circuit uses a rail-to-rail integrated operational amplifier to sample the voltage at both ends of the main topology, and the voltage sampling circuit uses a current sensing amplifier to sample the current at three ports to obtain sampling values; The main control circuit is used to calculate the topological efficiency according to the sampled values ​​and allocate the duty cycle to the two half-bridges of the main topology of the converter. Specifically, the main control circuit calculates the topological efficiency after digital filtering the sampled values, constructs a current and voltage closed loop using a closed-loop algorithm, calculates the error and obtains the duty cycle output, and performs output compensation according to the topological efficiency and allocates the duty cycle to the two half-bridges of the main topology of the converter. The converter main topology controls the expected voltage according to the duty cycle and switches the charging and discharging modes.

2. A three-port bidirectional supercapacitor power controller according to claim 1, characterized in that: The main topology of the converter consists of a BUCK half-bridge and a BOOST half-bridge, the two half-bridges are driven by half-bridge drivers respectively, and the main control circuit includes a high-resolution timer, and the half-bridge driver is driven by the high-resolution timer.

3. A three-port bidirectional supercapacitor power controller according to claim 1, characterized in that: After filtering the sampled values, capacitor voltage, capacitor current, chassis voltage, chassis current, battery voltage, and battery current are obtained; The topological efficiency calculation formula is as follows: ； 。 4. A three-port bidirectional supercapacitor power controller according to claim 3, characterized in that: The current closed loop is to close the charging current and discharging current on the capacitor side, including: Calculate the expected current based on the charging power, discharging power and topology efficiency; Comparing the capacitor current with the expected current using a closed-loop algorithm and calculating a current comparison value increment, and when the comparison value changes, the duty cycle changes; The desired voltage output by the main topology of the converter is changed according to the duty cycle, and a voltage difference is formed between the desired voltage and the actual voltage of the capacitor group, thereby generating a charging current and a discharging current, and forming a current closed loop.

5. A three-port bidirectional supercapacitor power controller according to claim 4, characterized in that: The voltage closed loop acts in charging mode; Comparing the capacitor voltage with the expected voltage using a closed-loop algorithm and calculating an output voltage comparison value increment to obtain a calculation result; The calculation result and the current closed loop are subjected to a double-loop competition, and the minimum value wins.

6. A three-port bidirectional supercapacitor power controller according to claim 2, characterized in that: The duty cycle is the ratio of the half-bridge comparison value to the high-resolution timer period; The calculation formula of the half-bridge comparison value is as follows: ； ； The total comparison value is the comparison value output by the closed-loop algorithm, and the period is the high-resolution timer period.

7. A three-port bidirectional supercapacitor power controller according to claim 2, characterized in that: The controller adopts a simulated central symmetric PWM control method, and uses the sampling point as the symmetric point of the PWM waveform; Four comparison value registers are used to work. Among them, the comparison value registers CMP1 and CMP2 are responsible for the BUCK half-bridge. When the count reaches CMP1, the output is set to 1, and when the count reaches CMP2, the output is set to 0; the comparison value registers CMP3 and CMP4 are responsible for the BOOST half-bridge. When the count reaches CMP3, the output is set to 1, and when the count reaches CMP4, the output is set to 0; Buck half-bridge comparison value register setting value: ； ； BOOST half-bridge comparison value register setting value: ； 。 8. A three-port bidirectional supercapacitor power controller according to claim 4, characterized in that: The converter main topology controls the expected voltage according to the duty cycle and switches the charging and discharging mode, including: If the expected voltage is higher than the actual voltage of the capacitor bank, current will flow from the chassis to the capacitor bank, which is a charging mode; If the expected voltage is lower than the actual voltage of the capacitor group, current will flow from the capacitor group to the chassis, which is a discharge mode.

9. A three-port bidirectional supercapacitor power controller according to claim 1, characterized in that: The main control circuit is connected to the display circuit, and the main control circuit is also connected to the communication circuit to communicate with the host computer.

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