Inverter hardware balance circuit control method, controller and inverter

Abstract

The invention discloses an inverter hardware balancing circuit control method, a controller and an inverter. The method comprises the following steps: calculating an opening duty ratio of a hardware balancing circuit based on a direct current positive and negative bus voltage difference; determining a limited duty ratio in real time based on the inductive current of the balancing circuit, outputting a fixed duty ratio as the limited duty ratio when the inductive current of the balancing circuit is greater than a preset proportion of a current protection threshold, and otherwise, calculating based on the inductive current of the balancing circuit to obtain a dynamic duty ratio in negative correlation with the inductive current of the balancing circuit as the limited duty ratio; performing amplitude limiting output on the calculated opening duty ratio of the hardware balancing circuit by using the limiting duty ratio; thus, based on the design of positive and negative bus voltage difference control and inductive current limiting duty ratio output, the balance of the positive and negative buses is adjusted, the overcurrent phenomenon is avoided, the balance capacity of the balance circuit is improved, meanwhile, the characteristics of complex control design and complex debugging are avoided, and the stability of the balance circuit is improved.

Description

Technical Field

[0001] The present invention relates to the field of inverter circuits, and in particular to an inverter hardware balancing circuit control method, a controller, and an inverter. Background Art

[0002] The hardware balancing circuit in the inverter is mainly used to ensure the voltage or current balance between the various components inside the inverter (such as capacitors, batteries, etc.), thereby improving the stability and reliability of the system. This circuit is particularly important, especially when using multiple strings of capacitors or battery packs, because imbalance may cause overvoltage or overcurrent in a component, thereby damaging the entire system. The hardware balancing circuit of the inverter is set in the front stage of the inverter circuit. Its control method generally uses positive and negative bus difference proportional control to adjust the positive and negative bus balance, or uses voltage (positive and negative bus difference) current dual closed-loop PI control to adjust the positive and negative bus voltage balance.

[0003] The first control method based on the positive and negative bus difference proportional control is simple and easy to implement, but it is prone to overcurrent. It is necessary to uniformly limit the duty cycle output of the balancing circuit to suppress overcurrent, but this sacrifices the balancing ability of the balancing circuit. The second control method based on voltage (positive and negative bus difference) current dual closed-loop PI control can eliminate overcurrent compared to the first method, but the design and debugging are complicated.

[0004] The above information disclosed in this Background section is included only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not form the prior art that is currently known to a person of ordinary skill in the art. Summary of the invention

[0005] The technical problem to be solved by the present invention is that, in view of the above-mentioned defects of the prior art such as easy overcurrent and complex design and debugging, a method, controller and inverter for controlling the hardware balancing circuit of an inverter are provided, which can avoid overcurrent and improve the balancing ability of the balancing circuit, avoid complex control design and debugging, and improve the stability of the balancing circuit.

[0006] The technical solution adopted by the present invention to solve its technical problem is:

[0007] On the one hand, a method for controlling an inverter hardware balancing circuit is constructed, the method comprising:

[0008] Obtaining a DC positive bus voltage, a DC negative bus voltage, and a balanced circuit inductor current;

[0009] The DC positive and negative bus voltages are calculated based on the DC positive bus voltage and the DC negative bus voltage to obtain a DC positive and negative bus voltage difference, and feedback control is performed based on the DC positive and negative bus voltage difference to obtain an on-duty ratio of the hardware balancing circuit;

[0010] Determining the limit duty cycle in real time based on the inductor current of the balancing circuit, including: when the inductor current of the balancing circuit is greater than a preset ratio of the current protection threshold, outputting a fixed duty cycle as the limit duty cycle; when the inductor current of the balancing circuit is not greater than the preset ratio of the current protection threshold, calculating a dynamic duty cycle negatively correlated with the inductor current of the balancing circuit as the limit duty cycle;

[0011] The calculated on-duty cycle of the hardware balancing circuit is limited and outputted using the limited duty cycle.

[0012] Further, in the inverter hardware balancing circuit control method of the present invention, the dynamic duty cycle negatively correlated with the inductor current of the balancing circuit is calculated based on the balancing circuit as the limiting duty cycle, specifically comprising: performing per-unit normalization processing on the inductor current of the balancing circuit in real time to obtain a dynamic per-unit value, and then substituting the per-unit value as an independent variable into a negatively correlated linear calculation formula to obtain the limiting duty cycle;

[0013] The negative correlation linear calculation formula is IL_Duty=k*I P.U +b, wherein IL_Duty represents the limit duty cycle, k and b are constants, k<0, 0<b<1.

[0014] Furthermore, in the inverter hardware balancing circuit control method of the present invention, the real-time per-unit normalization of the inductor current of the balancing circuit is performed to obtain a per-unit value, specifically based on the calculation formula I P.U =IL_Sample / Ir, where I P.U represents the per-unit value, IL_Sample represents the inductor current of the balancing circuit, and Ir represents the rated current.

[0015] Furthermore, in the inverter hardware balancing circuit control method described in the present invention, the fixed duty cycle is calculated based on the current protection threshold, and the calculation process of the fixed duty cycle is: the current protection threshold is normalized to obtain a per-unit value, and then the per-unit value is substituted as an independent variable into a negatively correlated linear calculation formula to obtain the limiting duty cycle.

[0016] Furthermore, in the inverter hardware balancing circuit control method described in the present invention, the use of the limiting duty cycle to limit the output of the calculated on-duty cycle of the hardware balancing circuit specifically includes: if the calculated on-duty cycle of the hardware balancing circuit is less than the limiting duty cycle, then directly controlling the switch tube that needs to be turned on in the hardware balancing circuit according to the calculated on-duty cycle of the hardware balancing circuit; if the calculated on-duty cycle of the hardware balancing circuit is not less than the limiting duty cycle, then directly controlling the switch tube that needs to be turned on in the hardware balancing circuit according to the limiting duty cycle.

[0017] Furthermore, in the inverter hardware balancing circuit control method described in the present invention, the feedback control calculation based on the DC positive and negative bus voltage difference to obtain the on-duty cycle of the hardware balancing circuit specifically includes: inputting the DC positive and negative bus voltage difference into a P controller, and the P controller multiplies the DC positive and negative bus voltage difference by a control coefficient to obtain and output the on-duty cycle of the hardware balancing circuit.

[0018] Further, in the inverter hardware balancing circuit control method described in the present invention, the hardware balancing circuit includes an energy storage circuit connected between the DC positive bus and the DC negative bus, a switch circuit connected between the DC positive bus and the DC negative bus, and an inductor connected between the energy storage circuit and the switch circuit;

[0019] The switch circuit includes a first switch tube and a second switch tube connected in series between a DC positive bus and a DC negative bus, the energy storage circuit includes a first capacitor and a second capacitor connected in series between the DC positive bus and the DC negative bus, and the inductor is connected between a connection node between the first switch tube and the second switch tube and a connection node between the first capacitor and the second capacitor; wherein the DC positive bus voltage refers to a voltage drop across the first capacitor, the DC negative bus voltage refers to a voltage drop across the second capacitor, and the balancing circuit inductor current refers to a current flowing through the inductor;

[0020] The method further includes: when the DC positive bus voltage is higher than the DC negative bus voltage, the first switch tube is turned on and the second switch tube is turned off; otherwise, the second switch tube is turned on and the first switch tube is turned off.

[0021] In a second aspect, a controller is constructed, which includes a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, the steps of the method described above are implemented.

[0022] In a third aspect, an inverter is constructed, which includes an inverter circuit, a hardware balancing circuit arranged in the front stage of the inverter circuit, and a controller, wherein the controller is used to execute the steps of the method as described above to control the switch tube in the hardware balancing circuit.

[0023] The inverter hardware balancing circuit control method, controller, and inverter of the present invention have the following beneficial effects: on the one hand, the present invention calculates the DC positive and negative bus voltage difference based on the DC positive bus voltage and the DC negative bus voltage, and performs feedback control based on the DC positive and negative bus voltage difference to calculate the turn-on duty cycle of the hardware balancing circuit; on the other hand, the limit duty cycle is determined according to the inductor current of the balancing circuit, and when the inductor current of the balancing circuit is greater than the preset proportion of the current protection threshold, a fixed duty cycle is output as the limit duty cycle, otherwise, a dynamic duty cycle negatively correlated with the inductor current of the balancing circuit is calculated based on the balancing circuit The duty cycle is used as the limit duty cycle; finally, the calculated turn-on duty cycle of the hardware balancing circuit is limited and output using the limit duty cycle; in this way, the present invention adjusts the positive and negative bus balance based on the design of positive and negative bus voltage difference control plus inductor current limit duty cycle output, avoids overcurrent, improves the balancing ability of the balancing circuit, and at the same time avoids the characteristics of complex control design and complex debugging, thereby improving the stability of the balancing circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below. Obviously, the drawings in the following description are only embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on the provided drawings without creative work:

[0025] Figure 1 It is a schematic diagram of the structure of the hardware balancing circuit;

[0026] Figure 2 is a flow chart of a method for controlling a hardware balancing circuit of an inverter according to the present invention;

[0027] Figure 3 It is a schematic diagram of the inverter hardware balancing circuit control method of the present invention;

[0028] Figure 4 2 is a graph showing the relationship between the limiting duty cycle IL_Duty and the balancing circuit inductor current IL_Sample. DETAILED DESCRIPTION

[0029] The general idea of ​​the present invention is: on the one hand, the DC positive and negative bus voltage difference is calculated based on the DC positive bus voltage and the DC negative bus voltage, and the turn-on duty cycle of the hardware balancing circuit is calculated based on the feedback control of the DC positive and negative bus voltage difference; on the other hand, the limit duty cycle is determined in real time based on the inductor current of the balancing circuit: when the inductor current of the balancing circuit is greater than the preset proportion of the current protection threshold, a fixed duty cycle is output as the limit duty cycle, otherwise a dynamic duty cycle negatively correlated with the inductor current of the balancing circuit is calculated based on the balancing circuit The duty cycle is used as the limit duty cycle; finally, the calculated turn-on duty cycle of the hardware balancing circuit is limited and output using the limit duty cycle; in this way, the present invention adjusts the positive and negative bus balance based on the design of positive and negative bus voltage difference control plus inductor current limit duty cycle output, avoids overcurrent, improves the balancing ability of the balancing circuit, and at the same time avoids the characteristics of complex control design and complex debugging, thereby improving the stability of the balancing circuit.

[0030] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Typical embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solutions of the present application, rather than limitations on the technical solutions of the present application. In the absence of conflict, the embodiments of the present invention and the technical features in the embodiments can be combined with each other.

[0031] Embodiment 1

[0032] Before introducing the method of the embodiment of the present invention, the inverter hardware balancing circuit is first introduced. Figure 1 The hardware balancing circuit includes an energy storage circuit connected between the DC positive bus and the DC negative bus, a switch circuit connected between the DC positive bus and the DC negative bus, and an inductor L connected between the energy storage circuit and the switch circuit. N The switch circuit is used to control the direction and time of energy flow, and the energy storage circuit is used to store energy. The switch circuit includes a first switch tube Q connected in series between the DC positive bus and the DC negative bus. 1N And the second switch tube Q 2N The energy storage circuit includes a first capacitor C connected in series between the DC positive bus and the DC negative bus 1N and the second capacitor C 2N , the inductance L N Connected to the first switch tube Q 1N And the second switch tube Q 2N The connection node O and the first capacitor C 1N and the second capacitor C 2NIt is understood that the method of the present invention is not limited to Figure 1 The circuit shown, Figure 1 Just to assist understanding, as long as the scheme includes an energy storage circuit and a switching circuit and an inductor is set between the energy storage circuit and the switching circuit, the method of the present invention can be used to control the turn-on time of the switching circuit in the hardware balancing circuit.

[0033] The method of the embodiment of the present invention mainly controls the opening time of the switch tube in the switch circuit: when the DC positive bus voltage is higher than the DC negative bus voltage, the first switch tube Q is opened. 1N Turn off the second switch tube Q 2N , otherwise turn on the second switch tube Q 2N Turn off the first switch Q 1N .

[0034] refer to Figure 2 , combined with Figure 3 The method of the embodiment of the present invention may be executed by a controller of an inverter, and the method includes:

[0035] S101: Obtaining a DC positive bus voltage, a DC negative bus voltage, and a balancing circuit inductor current;

[0036] The DC positive bus voltage, DC negative bus voltage and balanced circuit inductor current correspond to Figure 1 , 3 The method of the present invention needs to be implemented in conjunction with a voltage sampling circuit and a current sampling circuit. The voltage sampling circuit mainly needs to sample the DC positive bus voltage VdsBus_P and the DC negative bus voltage VdsBus_N. The DC positive bus voltage VdsBus_P refers to the first capacitor C 1N The voltage drop on the DC negative bus voltage VdsBus_N refers to the voltage drop of the second capacitor C 2N The current sampling circuit is mainly used to sample the balanced circuit inductor current IL_Sample, which refers to the current flowing through the inductor L N of current.

[0037] The DC positive bus voltage, DC negative bus voltage and balancing circuit inductor current are obtained here either by the controller analyzing and processing the sampling values ​​of the voltage and current according to the sampling circuit, or by other entities analyzing and processing the sampling values ​​of the voltage and current according to the sampling circuit and sending them to the controller. In short, there is no limitation on the specific method of obtaining the DC positive bus voltage, DC negative bus voltage and balancing circuit inductor current.

[0038] S102: Calculating a DC positive and negative bus voltage difference based on the DC positive bus voltage and the DC negative bus voltage, and performing feedback control calculation based on the DC positive and negative bus voltage difference to obtain an on-duty ratio of the hardware balancing circuit;

[0039] refer to Figure 3 Specifically, the DC positive bus voltage VdsBus_P is subtracted from the DC negative bus voltage VdsBus_N to obtain the DC positive and negative bus voltage difference △VdsBus. In this embodiment, the balancing circuit adopts pure proportional control, that is, the DC positive and negative bus voltage difference △VdsBus is input into the P controller, and the P controller multiplies the DC positive and negative bus voltage difference △VdsBus by the control coefficient Kp to obtain and output the opening duty cycle VdsBus_Duty of the hardware balancing circuit. The P controller here is only an example and is not used to limit the present invention.

[0040] S103: determining a limit duty cycle in real time based on the inductor current of the balancing circuit;

[0041] The duty cycle limit is represented by IL_Duty. According to the size of the inductor current in the balanced circuit, there are two cases to determine the duty cycle limit IL_Duty:

[0042] 1) When the balancing circuit inductor current IL_Sample is greater than a preset ratio of the current protection threshold, a fixed duty cycle is output as a duty cycle limit IL_Duty;

[0043] The preset ratio is represented by w, 0<w<1, and is adjusted and determined according to the situation. For example, in this embodiment, the preset ratio is determined to be 0.5.

[0044] In this embodiment, the fixed duty cycle is calculated based on the current protection threshold. Specifically, the calculation process of the fixed duty cycle is: the current protection threshold is normalized to obtain a per-unit value, and then the per-unit value is substituted as an independent variable into the negative correlation linear calculation formula to obtain the limited duty cycle IL_Duty. For example, assuming that the current protection threshold is IL_th, I P.U Indicates the per unit value, based on the calculation formula I P.U =IL_th / Ir The current protection threshold IL_th is normalized to obtain the normalized value I P.U , where Ir represents the rated current, the current protection threshold IL_th is less than the rated current Ir, and then I P.U Substituting the negative correlation linear calculation formula (1) below, the duty cycle limit IL_Duty can be calculated:

[0045] IL_Duty=k*I P.U +b(1);

[0046] Wherein, k and b are constants, k<0, 0<b<1. For example, in this embodiment, k is -1, b is 0.9, and b represents that the maximum duty cycle is limited.

[0047] In this case (IL_Sample>0.5*IL_th), the duty cycle limit IL_Duty is fixed.

[0048] 2) When the balancing circuit inductor current IL_Sample is not greater than a preset ratio of the current protection threshold, a dynamic duty cycle negatively correlated with the balancing circuit inductor current IL_Sample is calculated based on the balancing circuit inductor current IL_Sample to be used as a limiting duty cycle IL_Duty;

[0049] Specifically, based on the calculation formula I P.U =IL_Sample / Ir The inductor current IL_Sample of the balancing circuit is normalized in real time to obtain a dynamic normalized value I P.U , and then the per unit value I P.U Substituting the above-mentioned negative correlation linear calculation formula (1) as an independent variable, the duty cycle limit IL_Duty is obtained.

[0050] In this case (IL_Sample≤0.5*IL_th), the duty cycle limit IL_Duty is no longer fixed, but is linearly negatively correlated with IL_Sampl to prevent the current from fluctuating due to discontinuous duty cycle, which would affect the heat of the device over a long period of time.

[0051] It should be noted that, although the standardization processing method is adopted in this embodiment, other processing methods can actually be used, which is only an example here. The reference k and b in the calculation formula (1) can be determined in advance by debugging to take reasonable values. In addition, IL_Sampl and IL_Duty can also be other negatively correlated functional relationships, not necessarily linear. This embodiment proposes to design IL_Sampl and IL_Duty to be linearly negatively correlated in order to take into account the simplicity of the design scheme and the simplicity of debugging, but other negatively correlated functional relationships are also within the scope of the present invention.

[0052] S104: using the limited duty cycle to limit the calculated on-duty cycle of the hardware balancing circuit and output it.

[0053] Here, the limiting output can be understood as selecting the minimum value of the opening duty cycle VdsBus_Duty of the hardware balancing circuit calculated in step S102 and the limiting duty cycle IL_Duty in step S103 as the required duty cycle Duty for output. Specifically: if the opening duty cycle VdsBus_Duty is less than the limiting duty cycle IL_Duty, the switching tube that needs to be turned on in the hardware balancing circuit is directly controlled by the opening duty cycle VdsBus_Duty; if the opening duty cycle VdsBus_Duty is not less than the limiting duty cycle IL_Duty, the switching tube that needs to be turned on in the hardware balancing circuit is directly controlled by the limiting duty cycle IL_Duty. The focus of the present invention is how to determine the duty cycle. After determining the duty cycle, the specific wave generation process is a very mature technology in this field, so it will not be repeated here.

[0054] It should be noted that the numbers of the above steps S102 and S103 do not represent their order, and there is no logically necessary order restriction between steps S102 and S103.

[0055] Combine the following Figure 1 , 3 , introduces a specific application case of this embodiment. When the DC positive bus voltage VdsBus_P is high, the upper tube Q is turned on 11 Close the down tube Q 2N On the contrary, when the DC negative bus voltage VdsBus_N is high, the lower tube Q is turned on. 2N Close the upper tube Q 1N No matter which tube is turned on, the duty cycle of the tube is determined based on the following process:

[0056] 1) When the inductor current IL_Sample of the balancing circuit is less than 0.5 times the current protection threshold, linear limiting is performed to prevent the current from fluctuating due to discontinuous duty cycle, which may affect the heat of the device over a long period of time. Specifically, assuming that the maximum duty cycle is 90% for the limit b, the slope k is -1, and the corresponding inductor current IL_Sample is 0, then IL_Duty = -1.0*IL_Sample+0.9;

[0057] like Figure 4 As shown, it is a relationship diagram between the limited duty cycle IL_Duty and the balanced circuit inductor current IL_Sample. It can be seen that when IL_Sample does not exceed 0.5*IL_th, the limited duty cycle IL_Duty is linearly negatively correlated with IL_Sample. When IL_Sample is 0, the duty cycle Duty is the maximum value of 90%. As IL_Sample increases, the limited duty cycle IL_Duty gradually decreases.

[0058] 2) When the balancing circuit inductor current IL_Sample is greater than 0.5 times the current protection threshold (determined according to specific debugging), the duty cycle is limited to 40% (determined according to the current protection threshold).

[0059] like Figure 4 As shown, when IL_Sample exceeds 0.5*IL_th, the limit duty cycle IL_Duty is always stabilized at 40%.

[0060] 3) The DC positive and negative bus voltage difference △VdsBus is multiplied by the control coefficient Kp to obtain the duty cycle VdsBus_Duty, and then the inductor current duty cycle IL_Duty is limited in 1) or 2) to obtain the final output duty cycle.

[0061] In this embodiment, the DC positive and negative bus voltage difference is calculated based on the DC positive bus voltage and the DC negative bus voltage. On the one hand, feedback control is performed based on the DC positive and negative bus voltage difference to calculate the turn-on duty cycle of the hardware balancing circuit; on the other hand, the limit duty cycle is determined according to the inductor current of the balancing circuit. When the inductor current of the balancing circuit is greater than the preset ratio of the current protection threshold, a fixed duty cycle is output as the limit duty cycle. Otherwise, a dynamic duty cycle negatively correlated with the inductor current of the balancing circuit is calculated based on the balancing circuit The duty cycle is used as the limit duty cycle; finally, the calculated turn-on duty cycle of the hardware balancing circuit is limited and output using the limit duty cycle; in this way, the present invention adjusts the positive and negative bus balance based on the design of positive and negative bus voltage difference control plus inductor current limit duty cycle output, avoids overcurrent, improves the balancing ability of the balancing circuit, and at the same time avoids the characteristics of complex control design and complex debugging, thereby improving the stability of the balancing circuit.

[0062] A person skilled in the art may understand that all or part of the processes in the above-mentioned embodiment methods may be implemented by instructing related hardware through a computer program. The program may be stored in a computer-readable storage medium. When the program is executed, it may include the processes of the embodiments of the above-mentioned methods.

[0063] Embodiment 2

[0064] Based on the same inventive concept, the present invention also claims protection for a controller, which includes a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, the steps of the method described in Example 1 are implemented. The specific implementation process can refer to the relevant description of the above-mentioned method embodiment, which will not be repeated here.

[0065] It is to be understood that the scope of the present invention is not limited to the processors and memories clearly mentioned in the embodiments, and is not limited to a single processor or a single memory. As a non-limiting example, the present invention can be executed by one or more processors in an embodiment. Software instructions of one or more memories. The above description of the processor and memory is for clarity. However, in actual implementation, the boundaries of various modules may be fuzzy. Accordingly, unless explicitly required, the scope of the present invention is not limited by the mandatory boundaries between various hardware and / or software elements.

[0066] Embodiment 3

[0067] Based on the same inventive concept, the present invention also claims protection for an inverter, which includes an inverter circuit, a hardware balancing circuit, and a controller. The controller is used to execute the steps of the method described in Example 1 to control the switching tube in the hardware balancing circuit. The specific implementation process can refer to the relevant description of the above method embodiment and will not be repeated here.

[0068] Inverter circuits are common knowledge in the art, and are circuits used to convert direct current into alternating current. The present invention does not limit the specific circuit structure. Figure 1 The input end of the inverter circuit is connected to the energy storage circuit between the DC positive bus and the DC negative bus, that is, to the first capacitor C 1N and the second capacitor C 2N connection, which is used to connect the first capacitor C 1N and the second capacitor C 2N The hardware balancing circuit is set in the front stage of the inverter circuit, specifically controlling the first capacitor C 1N and the second capacitor C 2N It is understandable that the inverter of the present invention is not limited to Figure 1 The balanced circuit shown, Figure 1 Just to assist understanding, as long as the scheme includes an energy storage circuit and a switching circuit and an inductor is set between the energy storage circuit and the switching circuit, the method of the present invention can be used to control the turn-on time of the switching circuit in the hardware balancing circuit.

[0069] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0070] Terms containing ordinal numbers such as "first" and "second" used in this specification can be used to describe various constituent elements, but these constituent elements are not limited by these terms. The purpose of using these terms is only to distinguish one constituent element from other constituent elements. For example, without departing from the scope of the present invention, the first constituent element can be named as the second constituent element, and similarly, the second constituent element can also be named as the first constituent element. "Connected" or "connected" herein includes not only directly connecting two entities, but also indirectly connecting through other entities with beneficial improvement effects.

[0071] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A method for controlling an inverter hardware balancing circuit, characterized in that: The method comprises: Obtaining a DC positive bus voltage, a DC negative bus voltage, and a balanced circuit inductor current; The DC positive and negative bus voltages are calculated based on the DC positive bus voltage and the DC negative bus voltage to obtain a DC positive and negative bus voltage difference, and feedback control is performed based on the DC positive and negative bus voltage difference to obtain an on-duty ratio of the hardware balancing circuit; Determining the limit duty cycle in real time based on the inductor current of the balancing circuit, including: when the inductor current of the balancing circuit is greater than a preset ratio of the current protection threshold, outputting a fixed duty cycle as the limit duty cycle; when the inductor current of the balancing circuit is not greater than the preset ratio of the current protection threshold, calculating a dynamic duty cycle negatively correlated with the inductor current of the balancing circuit as the limit duty cycle; The calculated on-duty cycle of the hardware balancing circuit is limited and outputted using the limited duty cycle.

2. The inverter hardware balancing circuit control method according to claim 1, characterized in that: The said calculating based on the inductor current of the balancing circuit to obtain a negatively correlated dynamic duty cycle as the limited duty cycle specifically includes: performing real-time per-unit normalization processing on the inductor current of the balancing circuit to obtain a dynamic per-unit value, and then substituting the per-unit value as an independent variable into a negatively correlated linear calculation formula to obtain the limited duty cycle; The negative correlation linear calculation formula is IL_Duty=k*I P.U +b, wherein IL_Duty represents the limit duty cycle, k and b are constants, k<0, 0<b<1.

3. The inverter hardware balancing circuit control method according to claim 2, characterized in that: The real-time per-unit normalization of the inductor current of the balancing circuit is performed to obtain a per-unit value, specifically based on the calculation formula I P.U =IL_Sample / Ir, where I P.U represents the per-unit value, IL_Sample represents the inductor current of the balancing circuit, Ir represents the rated current, and the current protection threshold is less than the rated current.

4. The inverter hardware balancing circuit control method according to claim 1, characterized in that: The fixed duty cycle is calculated based on the current protection threshold.

5. The inverter hardware balancing circuit control method according to claim 4, characterized in that: The calculation process of the fixed duty cycle is: normalizing the current protection threshold to obtain a per-unit value, and then substituting the per-unit value as an independent variable into a negatively correlated linear calculation formula to obtain the limited duty cycle; The negative correlation linear calculation formula is IL_Duty=k*I P.U + b, where IL_Duty represents the limit duty cycle, I P.U Represents the per-unit value, k and b are constants, k<0, 0<b<1.

6. The inverter hardware balancing circuit control method according to claim 1, characterized in that: The step of limiting the calculated on-duty cycle of the hardware balancing circuit by using the limited duty cycle specifically includes: If the calculated on-duty cycle of the hardware balancing circuit is less than the limit duty cycle, the switch tube that needs to be turned on in the hardware balancing circuit is directly controlled by the calculated on-duty cycle of the hardware balancing circuit; if the calculated on-duty cycle of the hardware balancing circuit is not less than the limit duty cycle, the switch tube that needs to be turned on in the hardware balancing circuit is directly controlled by the limit duty cycle.

7. The inverter hardware balancing circuit control method according to claim 1, characterized in that: The feedback control calculation based on the DC positive and negative bus voltage difference to obtain the on-duty cycle of the hardware balancing circuit specifically includes: inputting the DC positive and negative bus voltage difference into a P controller, and the P controller multiplies the DC positive and negative bus voltage difference by a control coefficient to obtain and output the on-duty cycle of the hardware balancing circuit.

8. The inverter hardware balancing circuit control method according to claim 1, characterized in that: The hardware balancing circuit includes an energy storage circuit connected between the DC positive bus and the DC negative bus, a switch circuit connected between the DC positive bus and the DC negative bus, and an inductor connected between the energy storage circuit and the switch circuit; The switch circuit includes a first switch tube and a second switch tube connected in series between a DC positive bus and a DC negative bus, the energy storage circuit includes a first capacitor and a second capacitor connected in series between the DC positive bus and the DC negative bus, and the inductor is connected between a connection node between the first switch tube and the second switch tube and a connection node between the first capacitor and the second capacitor; wherein the DC positive bus voltage refers to a voltage drop across the first capacitor, the DC negative bus voltage refers to a voltage drop across the second capacitor, and the balancing circuit inductor current refers to a current flowing through the inductor; The method further includes: when the DC positive bus voltage is higher than the DC negative bus voltage, the first switch tube is turned on and the second switch tube is turned off; otherwise, the second switch tube is turned on and the first switch tube is turned off.

9. A controller, characterized in that: The method comprises a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, the steps of the method according to any one of claims 1 to 8 are implemented.

10. An inverter, characterized in that: It includes an inverter circuit, a hardware balancing circuit arranged in the front stage of the inverter circuit, and a controller, wherein the controller is used to execute the steps of the method described in any one of claims 1 to 8 to control the switch tube in the hardware balancing circuit.

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