Power supply circuit

Abstract

The invention relates to the technical field of integrated circuits, and discloses a power supply circuit which is characterized in that in order to reduce the use of an energy storage capacitor and reduce the cost of a chip, a voltage detection circuit detects the voltage of the energy storage capacitor to judge whether a charge pump needs to be started, and the voltage on the energy storage capacitor is charged to a higher voltage value by adopting PUMP; more electric charges are stored, and noise interference of the PUMP to the 1-Wire interface is reduced; when the charge pumps need to be started, the control circuit controls the charge pumps to be started in a time-sharing manner, so that the conditions of high power consumption and generation of a power consumption peak value caused by simultaneous starting of the charge pumps are avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a power supply circuit. Background Art

[0002] 1-Wire single-wire communication technology is a half-duplex, bidirectional serial bus standard and interface technology. Figure 1 As shown in the figure, the host only needs one port to communicate with the slave, and this interface also bears the task of obtaining power from the slave. In other words, one interface performs both power supply and communication tasks. This technology can save IO resources, has a simple structure and low cost, and is widely used in thermometers and hygrometers, device identification and authentication, batteries, storage and other fields.

[0003] However, in 1-Wire single-wire communication technology, since one interface is used for both power supply and communication, there is a modulated signal pulled down to ground in the communication stage, and the power supply is only provided by a pull-up resistor RPU of several hundred ohms to 1K ohms. Therefore, the power consumption fluctuation impact of the chip operation causes a large voltage drop and noise interference on the pull-up resistor RPU. This interference is so serious that it will affect the communication quality and reliability. Summary of the invention

[0004] In view of this, the present invention provides a power supply circuit to solve the problem of how to supply power to a chip while suppressing communication interference.

[0005] The present invention provides a power supply circuit, which is arranged in a chip. The host chip and the slave chip communicate via a 1-Wire single line. The 1-Wire communication line is connected to a power supply via a pull-up resistor. The charge pump circuit comprises: a voltage detection circuit, a control circuit, a charge pump circuit, an output circuit and an energy storage capacitor. The voltage detection circuit has a first end connected to a third end of the output circuit, a second end inputting a reference voltage, a third end being grounded, a fourth end being connected to the 1-Wire communication line, and a fifth end being connected to a first end of the control circuit. When the voltage division of the energy storage capacitor is higher than the reference voltage, the voltage detection circuit outputs a high level to the control circuit. When the voltage division of the energy storage capacitor is detected to be lower than the reference voltage, the voltage detection circuit outputs a low level to the control circuit. The control circuit has a second end inputting a clock signal, a third end inputting an enable signal, and a fourth end being connected to the first end of the charge pump circuit. When a low level is received, the voltage detection circuit outputs a high level to the control circuit. The invention relates to a charge pump circuit, wherein the first and second terminals of the charge pump circuit are connected to a 1-Wire communication line, and the second and third terminals of the charge pump circuit are connected to a 1-Wire communication line. The first and second ...

[0006] In order to reduce the use of energy storage capacitors and reduce chip costs, the voltage detection circuit of the present invention detects the voltage of the energy storage capacitor to determine whether the charge pump needs to be started, and uses the on-chip PUMP to charge the voltage on the energy storage capacitor to a higher voltage value, storing more charge, and reducing the noise interference of the PUMP on the 1-Wire interface; when the charge pump needs to be started, multiple charge pumps are controlled to start in time, thereby avoiding high power consumption and power consumption peaks caused by the simultaneous start of the charge pumps.

[0007] In an optional embodiment, the voltage detection circuit includes: a voltage divider circuit and a comparator, wherein the voltage divider circuit has a first end connected to the third end of the output circuit, a second end connected to the non-inverting input end of the comparator, and a second end grounded, and is used to divide the voltage of the energy storage capacitor; the comparator has an inverting input end inputting a reference voltage, and is used to output a high level to the control circuit when the divided voltage of the energy storage capacitor is higher than the reference voltage, and output a low level to the control circuit when the divided voltage of the energy storage capacitor is lower than the reference voltage.

[0008] In an optional embodiment, the voltage divider circuit includes: a first resistor and a second resistor, wherein the first resistor has a first end connected to the third end of the output circuit, and a second end connected to the first end of the second resistor and the in-phase input end of the comparator; the second resistor has a second end connected to ground.

[0009] In an optional embodiment, the control circuit includes: a clock control circuit and a delay control circuit, wherein the clock control circuit has a first end connected to the fifth end of the voltage detection circuit, a second end inputting a clock signal, and a third end connected to the first end of the delay control circuit, and is used to divide the clock signal when a high level or a low level is received to obtain a plurality of divided frequency signals; the delay control circuit has a second end inputting an enable signal, and a third end connected to the first end of the charge pump circuit, and is used to delay the plurality of divided frequency signals to obtain a plurality of time-sharing control signals, and output a set of time-sharing control signals with different delay times to the charge pump circuit based on the enable signal at the current moment.

[0010] In an optional embodiment, the clock control circuit includes: a first D flip-flop, a second D flip-flop, a first NOT gate, a second NOT gate, a third NOT gate, a first XOR gate and a second XOR gate, wherein the first D flip-flop has an input end connected to the output end of the first NOT gate, a reset end thereof inputs a clock signal, an output end thereof connected to the first input end of the first XOR gate, and a reverse output end thereof connected to the first end of the delay control circuit, and is used to divide the clock signal to obtain a first divided frequency signal; the second D flip-flop has an input end connected to the output end of the second NOT gate, and a reset end thereof inputs a clock signal, and an output end thereof connected to the first input end of the first XOR gate, and a reverse output end thereof connected to the first end of the delay control circuit, and is used to divide the clock signal to obtain a first divided frequency signal; the second D flip-flop has an input end connected to the output end of the second NOT gate, and a reset end thereof connected to the third XOR gate. The output end of the gate is connected, its output end is connected to the first input end of the second XOR gate, and its inverse output end is connected to the first end of the delay control circuit, which is used to divide the clock signal to obtain a second divided signal; the first divided signal and the second divided signal differ by half a clock cycle; the first XOR gate, its second input end is connected to the fifth end of the voltage detection circuit, and its output end is connected to the input end of the first NOT gate; the second XOR gate, its second input end is connected to the fifth end of the voltage detection circuit, and its output end is connected to the input end of the second NOT gate; the third NOT gate, its input end inputs the clock signal.

[0011] In an optional embodiment, the delay control circuit includes: a first delay circuit and a second delay circuit, wherein the first delay circuit, a first end of which inputs an enable signal, a second end of which is connected to the inverting output end of the first D flip-flop, and a third end of which is connected to the first end of the charge pump circuit, is used to delay the first frequency-divided signal to obtain multiple time-sharing control signals, and based on the enable signal at the current moment, only outputs one time-sharing control signal to the charge pump circuit, or does not output the time-sharing control signal to the charge pump circuit; the second delay circuit, a first end of which inputs an enable signal, a second end of which is connected to the inverting output end of the second D flip-flop, and a third end of which is connected to the first end of the charge pump circuit, is used to delay the second frequency-divided signal to obtain multiple time-sharing control signals, and based on the enable signal at the current moment, only outputs one time-sharing control signal to the charge pump circuit, or does not output the time-sharing control signal to the charge pump circuit.

[0012] In an optional embodiment, the charge pump circuit includes: a first charge pump sub-circuit and a second charge pump sub-circuit, wherein the first charge pump sub-circuit has a first end connected to the third end of the first delay circuit, a second end connected to the 1-Wire communication line, and a third end connected to the first end of the output circuit, and is used to enable a corresponding charge pump therein in sequence when a group timing control signal is received; the second charge pump sub-circuit has a first end connected to the third end of the second delay circuit, a second end connected to the 1-Wire communication line, and a third end connected to the first end of the output circuit, and is used to enable a corresponding charge pump therein in sequence when a group timing control signal is received.

[0013] In an optional embodiment, the first charge pump subcircuit and the second charge pump subcircuit both include: multiple charge pumps, the number of charge pumps included in each charge pump subcircuit is the same as the number of time-sharing control signals obtained by the connected first charge pump subcircuit or the second charge pump subcircuit, wherein the charge pump has an enable end connected to the third end of the first charge pump subcircuit or the third end of the second charge pump subcircuit, a second end connected to the 1-Wire communication line, and a third end connected to the first end of the output circuit.

[0014] In an optional embodiment, the output circuit includes: a first switching circuit and a second switching circuit, wherein the first switching circuit has a first end connected to the third end of the first charge pump sub-circuit, a second end inputting an enable signal, a third end connected to the first end of the chip built-in module and the voltage detection circuit, and a third end connected to the ground through a storage capacitor, and is used to select a corresponding path based on the enable signal at the current moment to connect the enabled charge pump to the energy storage capacitor; the second switching circuit has a first end connected to the third end of the second charge pump sub-circuit, a second end inputting an enable signal, a third end connected to the first end of the chip built-in module and the voltage detection circuit, and a third end connected to the ground through a storage capacitor, and is used to select a corresponding path based on the enable signal at the current moment to connect the enabled charge pump to the energy storage capacitor.

[0015] In an optional embodiment, the first switch circuit and the second switch circuit both include: multiple controllable switches, the number of controllable switches included in each switch circuit is the same as the number of charge pumps included in the connected first charge pump subcircuit or the second charge pump subcircuit, wherein the controllable switch has a first end connected to the third end of the first charge pump subcircuit or the third end of the second charge pump subcircuit, a second end inputting an enable signal, a third end connected to the first end of the chip built-in module and the voltage detection circuit, and a third end also grounded through a storage capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 It is a schematic diagram of 1-Wire communication technology;

[0018] Figure 2 is a composition diagram of a power supply circuit according to an embodiment of the present invention;

[0019] Figure 3 It is the interface and clock signal diagram of the communication stage in the -Wire communication technology;

[0020] Figure 4 is a specific circuit structure diagram of a power supply circuit according to an embodiment of the present invention;

[0021] Figure 5 is a timing diagram of a comparator clock and a PUMP clock according to an embodiment of the present invention;

[0022] Figure 6This is the PUMP internal clock timing diagram of an embodiment of the present invention. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0024] In this embodiment, a power supply circuit is provided. The power supply circuit is arranged in a chip. The host chip and the slave chip communicate via a 1-Wire single line. The 1-Wire communication line is connected to the power supply via a pull-up resistor. Figure 2 As shown, the charge pump circuit includes: a voltage detection circuit 1, a control circuit 2, a charge pump circuit 3, an output circuit 4 and an energy storage capacitor 5.

[0025] like Figure 2 As shown, the voltage detection circuit 1 has a first end connected to the third end of the output circuit 4, a second end inputting a reference voltage, a third end being grounded, a fourth end being connected to the 1-Wire communication line, and a fifth end being connected to the first end of the control circuit 2. When it is detected that the divided voltage of the energy storage capacitor 5 is higher than the reference voltage, the voltage detection circuit 1 outputs a high level to the control circuit 2, and when it is detected that the divided voltage of the energy storage capacitor 5 is lower than the reference voltage, the voltage detection circuit 1 outputs a low level to the control circuit 2.

[0026] Specifically, during the 1-Wire single-wire communication phase, the signals on the interface are as follows: Figure 3 As shown, when the interface is at a low level, the chip has no power supply. At this time, the stored charge on the energy storage capacitor 5 is completely needed to maintain the power consumption of the entire chip. When the chip power supply is low, the less the stored charge on the energy storage capacitor 5, the more difficult it is to support the power consumption of the entire chip, and a larger energy storage capacitor 5 is needed, but this will increase the cost of the chip. In order to reduce the use of the energy storage capacitor 5 and reduce the cost of the chip, a charge pump (PUMP) can be used to charge the voltage on the energy storage capacitor 5 to a higher voltage value to store more charge. In the communication stage, when the 1-Wire interface is at a high level, the PUMP starts and charges the energy storage capacitor 5. When the 1-Wire interface is at a low level, the PUMP stops and does not charge the energy storage capacitor 5. At this time, the energy storage capacitor 5 will discharge.

[0027] Based on the above analysis, in order to realize PUMP charging the energy storage capacitor 5, based on the loop control method, by setting the voltage detection circuit 1 to detect the voltage of the energy storage capacitor 5, that is, the voltage of the energy storage capacitor 5, the voltage detection circuit 1 compares the voltage of the energy storage capacitor 5 with the reference voltage, and according to different comparison results, the voltage detection circuit 1 outputs a high level or a low level to the control circuit 2, wherein, when the discharge voltage of the energy storage capacitor 5 is lower than the reference voltage, it indicates that the energy storage capacitor 5 needs to be charged, so the low level is used to drive the charge pump. Figure 2 As shown, the control circuit 2, whose second end inputs the clock signal, whose third end inputs the enable signal, and whose fourth end is connected to the first end of the charge pump circuit 3, is used for dividing the clock signal when receiving a low level, obtaining multiple frequency-divided signals, delaying the multiple frequency-divided signals for different times, obtaining multiple time-sharing control signals, and outputting a group of time-sharing control signals with different delay times to the charge pump circuit 3 based on the enable signal at the current moment; the periods and duty cycles of the multiple frequency-divided signals are the same, and the rising edge triggering times of two adjacent frequency-divided signals differ by a preset time. When it receives the high level, it does not output the time-sharing control signal.

[0028] Specifically, for most PUMP circuits, the power consumption is maximum during the first few clock cycles after the PUMP is started because the voltage of the internal capacitor node of the PUMP is established, resulting in a power consumption peak. Therefore, it is necessary to avoid starting all the PUMPs at the same time and to start the PUMPs in time through reasonable timing control.

[0029] Optionally, when the control circuit 2 receives a low level, the control circuit 2 divides the clock signal to obtain multiple divided signals, and the rising edge trigger time of two adjacent divided signals differs by a preset time. For example: when all the charge pumps are divided into two groups, the control circuit 2 divides the clock signal to obtain a first divided signal and a second divided signal. The first divided signal can drive one group of PUMPs, and the second divided signal can drive another group of PUMPs. Since the first divided signal differs from the second divided signal by half a clock cycle, the driving time of the two groups of charge pumps differs by half a clock cycle at the beginning.

[0030] It should be noted that the energy storage capacitor 5 here is actually a capacitor shared by each PUMP.

[0031] Furthermore, by delaying the first frequency-divided signal and the second frequency-divided signal for different time periods, multiple time-sharing control signals can be obtained. For example, by delaying the first frequency-divided signal by 0 microseconds, 0.1 microseconds, 0.2 microseconds, etc., multiple time-sharing control signals with different rising edge trigger times can be obtained. These time-sharing control signals can drive each PUMP of a group of charge pumps to start in time sequence, thereby preventing the PUMPs from starting at the same time.

[0032] Furthermore, in order to achieve that only one charge pump is started at each moment, that is, all time-sharing control signals are not output at the same time, the enable signal is set to enable only one time-sharing control signal to be output. It can be understood that if the charge pump is divided into two groups, the enable signal is also two, but this is only an example and is not limited to this.

[0033] like Figure 2 As shown, the charge pump circuit 3 has a second end connected to the 1-Wire communication line and a third end connected to the first end of the output circuit 4, and is used to enable a corresponding charge pump inside it when receiving a time-sharing control signal; the time-sharing control signal is used to control the charge pump to charge the energy storage capacitor 5.

[0034] Specifically, the charge pump circuit 3 has multiple PUMPs built in, and all the PUMPs can be divided into multiple groups. The number of each PUMP is set as needed, wherein the number of PUMP groups is the same as the number of time-sharing control signals, and the PUMPs are enabled and started in time-sharing.

[0035] like Figure 2 As shown, the output circuit 4 has a second end that inputs an enable signal, a third end that is connected to the chip's built-in module, and a third end that is also grounded via the energy storage capacitor 5, and is used to select the corresponding path based on the enable signal at the current moment to establish a connection between the enabled charge pump and the energy storage capacitor 5.

[0036] Specifically, in order to prevent the PUMP from absorbing the output charge when the power supply of the PUMP is suddenly restored, resulting in energy waste on the energy storage capacitor 5, the output circuit 4 is set to completely disconnect the disabled PUMP from the output end. Optionally, the output circuit 4 has multiple switch circuits built in, each switch circuit is connected to a PUMP, and each switch circuit is controlled by an enable signal so that the enabled PUMP is connected to the energy storage capacitor 5.

[0037] In some optional embodiments, such as Figure 4 As shown, the voltage detection circuit 1 includes: a voltage dividing circuit 11 and a comparator COMP.

[0038] like Figure 4 As shown, the voltage divider circuit has a first end connected to the third end of the output circuit 4, a second end connected to the non-inverting input end of the comparator, and a second end grounded, and is used to divide the voltage of the energy storage capacitor 5; the comparator, an inverting input end of which inputs a reference voltage, and is used to, when the divided voltage of the energy storage capacitor 5 is higher than the reference voltage, the voltage detection circuit 1 outputs a high level to the control circuit 2, and when the divided voltage of the energy storage capacitor 5 is lower than the reference voltage, the voltage detection circuit 1 outputs a low level to the control circuit 2.

[0039] Specifically, Figure 4In the embodiment, the voltage divider circuit inputs the voltage of the energy storage capacitor 5 (ie, PVDD), divides the PVDD to obtain a divided voltage (ie, VD_PVDD), and the comparator compares VD_PVDD with a reference voltage (ie, VREF).

[0040] In some optional embodiments, such as Figure 4 As shown, the voltage divider circuit includes: a first resistor R1 and a second resistor R2, wherein the first resistor has a first end connected to the third end of the output circuit 4, and a second end connected to the first end of the second resistor and the in-phase input end of the comparator; the second resistor has a second end connected to ground.

[0041] Optionally, Figure 4 The voltage divider circuit in the embodiment is composed of only two voltage divider resistors connected in series, but can also be composed of more resistors connected in series or in series-parallel. The specific voltage divider coefficient is determined by the resistors and is not limited here.

[0042] Specifically, resistors R1 and R2 divide the PVDD voltage to detect the voltage and output the divided voltage VD_PVDD. When VD_PVDD is higher than the reference voltage VREF, the comparator outputs VOUT_COMP at a high level; when VD_PVDD is lower than the reference voltage VREF, the comparator outputs VOUT_COMP at a low level. When VD_PVDD is lower than the reference voltage VREF, the PUMP circuit starts, otherwise the PUMP is in a dormant state.

[0043] In some optional embodiments, such as Figure 4 As shown, the control circuit 2 includes: a clock control circuit 21 and a delay control circuit 22.

[0044] like Figure 4 As shown, the clock control circuit has a first end connected to the fifth end of the voltage detection circuit 1, a second end inputting a clock signal, and a third end connected to the first end of the delay control circuit. When a high level or a low level is received, the clock signal is divided to obtain a plurality of divided signals.

[0045] Figure 4 In the embodiment, the clock control circuit is connected to the output end of the comparator, and when a low level is received, the low level is divided to obtain a plurality of divided signals, wherein adjacent divided signals differ by half a clock cycle. For example, when all PUMPs are divided into two groups, there are two divided signals, namely the first divided signal and the second divided signal, and the first divided signal differs from the second divided signal by half a clock cycle.

[0046] Optionally, when all PUMPs are divided into at least three groups, there are at least three frequency division signals. In order to separate each group of PUMPs at the initial enabling time, adjacent frequency division signals differ by a preset time period.

[0047] like Figure 4 As shown, the delay control circuit has an enable signal input at its second end and a third end connected to the first end of the charge pump circuit 3. It is used to delay multiple frequency-divided signals to obtain multiple time-sharing control signals, and based on the enable signal at the current moment, output a group of time-sharing control signals with different delay times to the charge pump circuit 3.

[0048] Figure 4 In the process, since the adjacent frequency division signals differ by a preset time period, and one frequency division signal drives a group of PUMPs, in order to enable the PUMPs in the group to start in time-sharing mode, each frequency division signal is delayed for different times to obtain multiple time-sharing control signals. For example, for one frequency division signal, 0 microseconds, 0.1 microseconds, and 0.2 microseconds are delayed respectively to obtain three time-sharing control signals with different trigger times.

[0049] In some optional embodiments, such as Figure 4 As shown, the clock control circuit includes: a first D flip-flop D1, a second D flip-flop D2, a first NOT gate IN1, a second NOT gate IN2, a third NOT gate IN3, a first XOR gate XOR1 and a second XOR gate XOR2.

[0050] like Figure 4 As shown, a first D flip-flop, whose input end is connected to the output end of the first NOT gate, whose reset end inputs the clock signal, whose output end is connected to the first input end of the first XOR gate, whose reverse output end is connected to the first end of the delay control circuit, is used to divide the clock signal to obtain a first divided frequency signal; a second D flip-flop, whose input end is connected to the output end of the second NOT gate, whose reset end is connected to the output end of the third NOT gate, whose output end is connected to the first input end of the second XOR gate, whose reverse output end is connected to the first end of the delay control circuit, is used to divide the clock signal to obtain a second divided frequency signal; the first divided frequency signal and the second divided frequency signal differ by half a clock cycle; a first XOR gate, whose second input end is connected to the fifth end of the voltage detection circuit 1, and whose output end is connected to the input end of the first NOT gate; a second XOR gate, whose second input end is connected to the fifth end of the voltage detection circuit 1, and whose output end is connected to the input end of the second NOT gate; a third NOT gate, whose input end inputs the clock signal.

[0051] Specifically, the clock control circuit has two built-in D flip-flops, each of which outputs a frequency division signal. It should be noted that the two D flip-flops correspond to the situation where the PUMP is divided into two groups, but multiple D flip-flops can also be set to correspond to the situation of multiple groups of PUMP.

[0052] Figure 4For the two PUMP groups, the clock control circuit input signal includes the comparator output VOUT_COMP and the clock CLK, and the output signal includes CLKA <0> and CLKB <0> , used as the clock control signal for PUMP operation. Figure 5 and Figure 6 As shown, CLK and CLKN are opposite to each other, CLKA <0> and CLKB <0> They are opposite to each other. <0> and CLKB <0> is the 2-frequency signal of CLK, and CLKA <0> With CLKB <0> Stagger CLK by half a clock cycle. <0> and CLKB <0> Control PUMPA separately <0> and PUMPB <0> The charging and discharging timing of the energy storage capacitor 5. In some optional embodiments, as Figure 4 As shown, the delay control circuit includes: a first delay circuit 221 and a second delay circuit 222 .

[0053] like Figure 4 As shown, the first delay circuit has a first end that inputs an enable signal, a second end that is connected to the reverse output end of the first D flip-flop, and a third end that is connected to the first end of the charge pump circuit 3, and is used to delay the first frequency-divided signal to obtain multiple time-sharing control signals, and based on the enable signal at the current moment, only outputs one time-sharing control signal to the charge pump circuit 3, or does not output a time-sharing control signal to the charge pump circuit 3.

[0054] like Figure 4 As shown, the second delay circuit has a first end that inputs an enable signal, a second end that is connected to the reverse output end of the second D flip-flop, and a third end that is connected to the first end of the charge pump circuit 3. It is used to delay the second frequency-divided signal to obtain multiple time-sharing control signals, and based on the enable signal at the current moment, only outputs one time-sharing control signal to the charge pump circuit 3, or does not output a time-sharing control signal to the charge pump circuit 3.

[0055] Specifically, Figure 4The two delay circuits correspond to the situation where PUMP is divided into two groups, and one delay circuit corresponds to one group of PUMP. Since the frequency division signal differs by a preset time at the beginning, the start time of each group is staggered at the beginning. In order to stagger the start time of PUMP in each group, each delay circuit delays the frequency division signal again for different times to obtain time-sharing control signals at different times. In some optional embodiments, the charge pump circuit 3 includes: a first charge pump subcircuit and a second charge pump subcircuit. Specifically, the first charge pump subcircuit, the first end of which is connected to the third end of the first delay circuit, the second end of which is connected to the 1-Wire communication line, and the third end of which is connected to the first end of the output circuit 4, is used to enable a corresponding charge pump inside it in sequence when a group of time-sharing control signals are received; the second charge pump subcircuit, the first end of which is connected to the third end of the second delay circuit, the second end of which is connected to the 1-Wire communication line, and the third end of which is connected to the first end of the output circuit 4, is used to enable a corresponding charge pump inside it in sequence when a group of time-sharing control signals are received.

[0056] Optionally, the first charge pump subcircuit and the second charge pump subcircuit both include: multiple charge pumps, the number of charge pumps included in each charge pump subcircuit is the same as the number of time-sharing control signals obtained by the connected first charge pump subcircuit or the second charge pump subcircuit, wherein the charge pump, its enable end is connected to the third end of the first charge pump subcircuit or the third end of the second charge pump subcircuit, its second end is connected to the 1-Wire communication line, and its third end is connected to the first end of the output circuit 4.

[0057] Figure 4 In the embodiment, the charge pump circuit 3 includes PUMPA<0:N> and PUMPB<0:N>, totaling 2N+2 sub-PUMPs, which are used to start the PUMP at different peak times or enable different numbers of PUMPs to adjust the charging capacity of the PUMP.

[0058] It should be noted that the number of PUMP groups can be set as needed and is not limited here.

[0059] Specifically, Figure 4 In the embodiment, the delay control circuit includes a first delay circuit and a second delay circuit, such as Figure 5As shown, the output signal CLKA<1:N> of the first delay circuit is used as the working clock of PUMPA<1:N>; the output signal CLKB<1:N> of the second delay circuit is used as the working clock of PUMPB<1:N>. At the same time, CLKA<1:N> is controlled by the enable signal EN_A<1:N>. Only when the corresponding bit of EN_A<1:N> is enabled, the corresponding CLKA<1:N> branch has a clock signal, and the corresponding module in PUMPA<1:N> works. Otherwise, corresponding to the bit of EN_A<1:N> that is not enabled, the corresponding CLKA<1:N> branch has no clock signal output, and the corresponding module in PUMPA<1:N> does not work. Similarly, CLKB<1:N> is controlled by the enable signal EN_B<1:N>. Only when the corresponding bit of EN_B<1:N> is enabled, the corresponding CLKB<1:N> branch has a clock signal, and the corresponding module in PUMPB<1:N> works. For the disabled bit of EN_B<1:N>, the corresponding CLKB<1:N> branch has no clock signal output, and the corresponding module in PUMPA<1:N> does not work.

[0060] The advantages of the above time-sharing control are: first, it plays a role in regulating the charging capacity of the energy storage capacitor 5 by PUMP, and at the same time it also regulates the size of the interference impact on the power supply VCC; second, Figure 5 As shown in the figure, the delay of each bit in CLKA<1:N> and CLKB<1:N> is different, which can make the start time of PUMPA<1:N> or PUMPB<1:N> staggered to avoid all PUMPs starting at the same time, causing instantaneous high power consumption and affecting communication quality.

[0061] In some optional embodiments, the output circuit 4 includes: a first switching circuit and a second switching circuit, wherein the first switching circuit, the first end of which is connected to the third end of the first charge pump sub-circuit, the second end of which is input with an enable signal, the third end of which is connected to the first end of the chip built-in module and the voltage detection circuit 1, and the third end of which is also grounded through the energy storage capacitor 5, and is used to select the corresponding path based on the enable signal at the current moment to connect the enabled charge pump to the energy storage capacitor 5; the second switching circuit, the first end of which is connected to the third end of the second charge pump sub-circuit, the second end of which is input with an enable signal, the third end of which is connected to the first end of the chip built-in module and the voltage detection circuit 1, and the third end of which is also grounded through the energy storage capacitor 5, and is used to select the corresponding path based on the enable signal at the current moment to connect the enabled charge pump to the energy storage capacitor 5.

[0062] Optionally, the first switch circuit and the second switch circuit both include: multiple controllable switches, the number of controllable switches included in each switch circuit is the same as the number of charge pumps included in the connected first charge pump sub-circuit or the second charge pump sub-circuit, wherein the controllable switch has a first end connected to the third end of the first charge pump sub-circuit or the third end of the second charge pump sub-circuit, a second end inputs an enable signal, a third end is connected to the chip built-in module, the first end of the voltage detection circuit 1, and the third end is also grounded through the energy storage capacitor 5.

[0063] It should be noted that the number of switch circuits is set as needed and is not limited here.

[0064] Specifically, Figure 4 In the output circuit 4, a total of 2N controllable switches SWA<1:N> and SWB<1:N> are included. When the corresponding PUMP is working, the corresponding controllable switches of SWA<1:N> and SWB<1:N> are turned on, otherwise they are turned off. Since even if PUMP is not enabled, if there is no controllable switch to completely cut off the connection between PUMP and the PVDD output power supply, in the 1-Wire communication stage, when the interface signal changes from a low level to a high level, the PUMP power supply is suddenly restored, which will absorb charge from the output terminal PVDD, resulting in energy waste on the energy storage capacitor 5. Therefore, it is necessary to completely disconnect the non-working PUMP from the output terminal PVDD through the SWA or SWB switch.

[0065] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A power supply circuit, characterized in that: The power supply circuit is arranged in the chip, the host chip and the slave chip communicate via a 1-Wire single line, the 1-Wire communication line is connected to the power supply via a pull-up resistor, the charge pump circuit comprises: a voltage detection circuit, a control circuit, a charge pump circuit, an output circuit and an energy storage capacitor, wherein, A voltage detection circuit, wherein a first end of the voltage detection circuit is connected to a third end of the output circuit, a second end of the voltage detection circuit is input with a reference voltage, a third end of the voltage detection circuit is grounded, a fourth end of the voltage detection circuit is connected with a 1-Wire communication line, and a fifth end of the voltage detection circuit is connected with a first end of the control circuit, and is used for outputting a high level to the control circuit when it is detected that the voltage divided by the energy storage capacitor is higher than the reference voltage, and outputting a low level to the control circuit when it is detected that the voltage divided by the energy storage capacitor is lower than the reference voltage; A control circuit, a second end of which inputs a clock signal, a third end of which inputs an enable signal, and a fourth end of which is connected to the first end of the charge pump circuit, and is used for, when receiving the low level, dividing the clock signal to obtain a plurality of divided frequency signals, delaying the plurality of divided frequency signals for different times to obtain a plurality of time-sharing control signals, and outputting a group of time-sharing control signals with different delay times to the charge pump circuit based on the enable signal at the current moment; the periods and duty cycles of the plurality of divided frequency signals are the same, and the rising edge triggering times of two adjacent divided frequency signals differ by a preset time; and when receiving the high level, not outputting the time-sharing control signal; A charge pump circuit, a second end of which is connected to the 1-Wire communication line, and a third end of which is connected to the first end of the output circuit, and is used to enable a corresponding charge pump inside it when receiving the time-sharing control signal; the time-sharing control signal is used to control the charge pump to charge the energy storage capacitor; The output circuit has a second end that inputs the enable signal, a third end that is connected to the chip built-in module, and a third end that is also grounded through an energy storage capacitor. It is used to select the corresponding path based on the enable signal at the current moment to connect the enabled charge pump to the energy storage capacitor.

2. The power supply circuit according to claim 1, characterized in that: The voltage detection circuit includes: a voltage divider circuit and a comparator, wherein: A voltage divider circuit, a first end of which is connected to the third end of the output circuit, a second end of which is connected to the non-inverting input end of the comparator, and a second end of which is grounded, and is used to divide the voltage of the energy storage capacitor; A comparator, whose inverting input terminal inputs the reference voltage, is used for the voltage detection circuit to output a high level to the control circuit when the divided voltage of the energy storage capacitor is higher than the reference voltage, and for the voltage detection circuit to output a low level to the control circuit when the divided voltage of the energy storage capacitor is lower than the reference voltage.

3. The power supply circuit according to claim 2, characterized in that: The voltage divider circuit includes: a first resistor and a second resistor, wherein: A first resistor, a first end of which is connected to the third end of the output circuit, and a second end of which is connected to the first end of the second resistor and the non-inverting input end of the comparator; The second resistor has a second end connected to the ground.

4. The power supply circuit according to claim 1, characterized in that: The control circuit includes: a clock control circuit and a delay control circuit, wherein: a clock control circuit, wherein a first end of the clock control circuit is connected to the fifth end of the voltage detection circuit, a second end of the clock control circuit is input with the clock signal, and a third end of the clock control circuit is connected with the first end of the delay control circuit, and is used for dividing the clock signal to obtain a plurality of divided frequency signals when receiving the high level or the low level; A delay control circuit, whose second end inputs the enable signal and whose third end is connected to the first end of the charge pump circuit, is used to delay the multiple frequency-divided signals to obtain multiple time-sharing control signals, and based on the enable signal at the current moment, output a group of time-sharing control signals with different delay times to the charge pump circuit.

5. The power supply circuit according to claim 4, characterized in that: The clock control circuit includes: a first D flip-flop, a second D flip-flop, a first NOT gate, a second NOT gate, a third NOT gate, a first XOR gate and a second XOR gate, wherein: A first D flip-flop, whose input end is connected to the output end of the first NOT gate, whose reset end inputs the clock signal, whose output end is connected to the first input end of the first XOR gate, and whose reverse output end is connected to the first end of the delay control circuit, and which is used to divide the clock signal to obtain a first divided frequency signal; a second D flip-flop, whose input end is connected to the output end of the second NOT gate, whose reset end is connected to the output end of the third NOT gate, whose output end is connected to the first input end of the second XOR gate, and whose reverse output end is connected to the first end of the delay control circuit, and which is used to divide the clock signal to obtain a second divided frequency signal; the first divided frequency signal and the second divided frequency signal differ by half a clock cycle; a first XOR gate, a second input terminal of which is connected to the fifth terminal of the voltage detection circuit, and an output terminal of which is connected to the input terminal of the first NOT gate; a second XOR gate, wherein a second input terminal of the second XOR gate is connected to the fifth terminal of the voltage detection circuit, and an output terminal of the second XOR gate is connected to the input terminal of the second NOT gate; The third NOT gate has an input terminal which inputs the clock signal.

6. The power supply circuit according to claim 5, characterized in that: The delay control circuit includes: a first delay circuit and a second delay circuit, wherein: A first delay circuit, a first end of which inputs the enable signal, a second end of which is connected to the inverting output end of the first D flip-flop, and a third end of which is connected to the first end of the charge pump circuit, and is used to delay the first frequency-divided signal to obtain a plurality of time-sharing control signals, and based on the enable signal at the current moment, output only one time-sharing control signal to the charge pump circuit, or output no time-sharing control signal to the charge pump circuit; A second delay circuit, whose first end inputs the enable signal, whose second end is connected to the inverting output end of the second D flip-flop, and whose third end is connected to the first end of the charge pump circuit, is used to delay the second frequency-divided signal to obtain multiple time-sharing control signals, and based on the enable signal at the current moment, only output one time-sharing control signal to the charge pump circuit, or do not output a time-sharing control signal to the charge pump circuit.

7. The power supply circuit according to claim 6, characterized in that: The charge pump circuit comprises: a first charge pump subcircuit and a second charge pump subcircuit, wherein: A first charge pump subcircuit, a first end of which is connected to the third end of the first delay circuit, a second end of which is connected to the 1-Wire communication line, and a third end of which is connected to the first end of the output circuit, and is used to sequentially enable a corresponding charge pump inside it when receiving the component timing control signal; The second charge pump sub-circuit has a first end connected to the third end of the second delay circuit, a second end connected to the 1-Wire communication line, and a third end connected to the first end of the output circuit. When receiving the group of time-sharing control signals, a corresponding charge pump inside it is enabled in turn.

8. The power supply circuit according to claim 7, characterized in that: The first charge pump subcircuit and the second charge pump subcircuit both include: a plurality of charge pumps, the number of charge pumps included in each charge pump subcircuit is the same as the number of time-sharing control signals obtained by the connected first charge pump subcircuit or the second charge pump subcircuit, wherein: The charge pump has an enable terminal connected to the third terminal of the first charge pump subcircuit or the third terminal of the second charge pump subcircuit, a second terminal connected to the 1-Wire communication line, and a third terminal connected to the first terminal of the output circuit.

9. The power supply circuit according to claim 8, characterized in that: The output circuit includes: a first switch circuit and a second switch circuit, wherein: A first switch circuit, a first end of which is connected to a third end of the first charge pump subcircuit, a second end of which inputs the enable signal, a third end of which is connected to the first end of the chip built-in module and the voltage detection circuit, and a third end of which is also grounded through an energy storage capacitor, and is used to select a corresponding path based on the enable signal at the current moment to connect the enabled charge pump to the energy storage capacitor; A second switch circuit, a first end of which is connected to the third end of the second charge pump subcircuit, a second end of which inputs the enable signal, a third end of which is connected to the first end of the chip built-in module and the voltage detection circuit, and a third end of which is also grounded through an energy storage capacitor. It is used to select the corresponding path based on the enable signal at the current moment to connect the enabled charge pump to the energy storage capacitor.

10. The power supply circuit according to claim 9, characterized in that: The first switch circuit and the second switch circuit each include: a plurality of controllable switches, the number of controllable switches included in each switch circuit is the same as the number of charge pumps included in the first charge pump subcircuit or the second charge pump subcircuit connected thereto, wherein: A controllable switch, wherein the first end is connected to the third end of the first charge pump subcircuit or the third end of the second charge pump subcircuit, the second end is input with the enable signal, the third end is connected to the first end of the chip built-in module and the voltage detection circuit, and the third end is also grounded through the energy storage capacitor.

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