Three-phase inverter drive circuit and three-phase inverter circuit

Abstract

The invention provides a three-phase inverter drive circuit and a three-phase inverter circuit. The three-phase inverter drive circuit is connected with a three-phase inverter bridge; the three-phase inverter drive circuit comprises a drive chip, a signal generation module and an adjustable dead time module, and the output end of the drive chip is connected with the control end of the signal generation module through the adjustable dead time module. The output end of the signal generation module is connected with the grid electrode of an inversion switch tube in the three-phase inversion bridge. The dead zone time is adjusted by setting the dead zone time adjusting module, so that the dead zone time can be adjusted based on actual needs, the dead zone time can be matched with the actual situation of the three-phase inverter bridge, and the signal generating module controls the conducting state of the inverter switch tube based on the dead zone time, so that the switching-on state of the three-phase inverter bridge can be matched with the actual situation of the three-phase inverter bridge. Therefore, the inverter switch tubes of the same phase are not switched on at the same time, and short circuit is avoided.

Description

Technical Field

[0001] The present invention relates to the field of circuits, and in particular to a three-phase inverter drive circuit and a three-phase inverter circuit. Background Art

[0002] In a three-phase inverter circuit, a dead time needs to be set to avoid a short circuit caused by two switches on the same phase bridge arm being turned on at the same time. The existing dead time is controlled by software, and the specific setting of the dead time is determined when the software is burned. When a program setting error occurs or the circuit ages, the dead time set by the software will not be able to meet the interlocking requirements of the switch tubes, and will still cause a short circuit problem. Summary of the invention

[0003] The main purpose of the present invention is to propose a three-phase inverter drive circuit and a three-phase inverter circuit, aiming to solve the problem that the dead time set by the software in the prior art cannot meet the interlocking requirements of the switch tube and cause a short circuit.

[0004] To achieve the above-mentioned object, the present invention provides a three-phase inverter drive circuit, which is connected to a three-phase inverter bridge; the three-phase inverter drive circuit includes a drive chip, a signal generation module and an adjustable dead time module, the adjustable dead time module includes a plurality of dead time units, the output end of the drive chip is connected to the control end of the signal generation module through the dead time unit, and the output end of the signal generation module is connected to the gate of the inverter switch tube in the three-phase inverter bridge; the dead time unit includes a logic gate and an adjustable delay response subunit, the first input end of the logic gate is connected to the output end of the drive chip, the input end of the adjustable delay response subunit is connected to the input end of the drive chip, and the output end of the adjustable delay response subunit is connected to the second input end of the logic gate; wherein: The driving chip is used to output a driving signal for the inverter switch tube of the three-phase inverter bridge; The signal generating module is used to output a control level corresponding to the driving signal to the inverter switch tube of the three-phase inverter bridge to control the conduction state of the inverter switch tube; The adjustable dead time module is used to adjust the dead time, and within the set dead time, maintain the logic gate outputting a driving signal indicating that the inverter switch tube is in the off state to the signal generation module through the adjustable delay response subunit.

[0005] Optionally, the signal generating module includes a plurality of signal generating units; wherein: For each phase bridge arm of the three-phase inverter bridge, the first output end of the driving chip is connected to the control end of the first signal generating unit, and the output end of the first signal generating unit is connected to the control end of the first inverter switch tube; The second output end of the driving chip is connected to the control end of the dead time unit, the output end of the dead time unit is connected to the control end of the second signal generating unit, and the output end of the second signal generating unit is connected to the control end of the second inverter switch tube.

[0006] Optionally, the logic gate is a NOR gate, and the adjustable delay response subunit includes a first resistor and a first capacitor; wherein: The first input end of the NOR gate is connected to the second output end of the driving chip as the input end of the dead time unit, the first input end of the NOR gate is also connected to the second input end of the NOR gate through the first resistor, the second input end of the NOR gate is also grounded through the first capacitor, and the output end of the NOR gate is connected to the control end of the second signal generating unit as the output end of the dead time unit.

[0007] Optionally, the adjustable delayed response subunit further includes an adjustable resistor; wherein: The adjustable resistor is connected in parallel with the first resistor, and a control end of the adjustable resistor is connected to the driving chip.

[0008] Optionally, the signal generating module includes a plurality of signal generating units, and the signal generating unit includes a first triode and a second triode; wherein: The base of the first transistor and the base of the second transistor serve as the control end of the signal generating unit, the collector of the first transistor is connected to the power supply, the emitter of the first transistor serves as the output end of the signal generating unit, the emitter of the first transistor is connected to the emitter of the second transistor, and the collector of the second transistor is grounded.

[0009] Optionally, the three-phase inverter drive circuit further includes a plurality of overcurrent detection modules, a plurality of delay modules and a plurality of voltage limiting modules; for each phase bridge arm of the three-phase inverter bridge, the detection end of the overcurrent detection module is connected to the input end and the output end of the three-phase inverter bridge, the output end of the overcurrent detection module is connected to the overcurrent detection end of the drive chip, the overcurrent detection module is also connected to the control end of the voltage limiting module through the delay module, and the output end of the voltage limiting module is connected to the gate of the inverter switch tube of the three-phase inverter bridge; wherein: The overcurrent detection module is used to detect the overcurrent of the three-phase inverter bridge and send an overcurrent signal to the driving chip when an overcurrent is detected; The delay module is used to drive the voltage limiting module to work within a preset delay time when the overcurrent detection module detects overcurrent; The voltage limiting module is used to reduce the gate voltage of the inverter switch tube; The driving chip is used to control all the inverter switches of the three-phase inverter bridge to turn off after the overcurrent detection module detects that the overcurrent reaches a preset delay time.

[0010] Optionally, the overcurrent detection module includes a first diode, a second diode, a first voltage regulator diode, a second resistor, a third resistor, a third transistor and an optical coupler; wherein: The cathode of the first diode is connected to the positive input end of the bridge arm, and the anode of the first diode is connected to the cathode of the first voltage stabilizing diode; the cathode of the second diode is connected to the output end of the bridge arm, and the anode of the second diode is connected to the cathode of the first voltage stabilizing diode; The anode of the first voltage stabilizing diode is connected to the base of the third transistor, the emitter of the third transistor is grounded, the collector of the third transistor is connected to the negative electrode of the optocoupler, the anode of the optocoupler is connected to the power supply through the delay module, the emitter of the optocoupler is grounded, the collector of the optocoupler is connected to the overcurrent detection end of the driving chip as the output end of the overcurrent detection module, and the collector of the optocoupler is also connected to the power supply through the third resistor.

[0011] Optionally, the delay module includes a fourth resistor, a fifth resistor, a second capacitor, a second voltage zener diode and a third voltage zener diode; wherein: The first end of the second capacitor is connected to the power supply, the second end of the second capacitor is connected to the positive electrode of the optocoupler through the fourth resistor, the fifth resistor is connected to the second capacitor in parallel, the second voltage regulator diode is connected in reverse parallel to the second capacitor, the positive electrode of the second voltage regulator diode is connected to the negative electrode of the third voltage regulator diode, and the positive electrode of the third voltage regulator diode is connected to the control end of the voltage limiting module as the output end of the delay module.

[0012] Optionally, the voltage limiting module includes a fourth triode, a sixth resistor, a third diode and a fourth diode; wherein: The base of the fourth transistor is connected to the anode of the third voltage-stabilizing diode as the control end of the voltage limiting module, the collector of the fourth transistor is grounded through the sixth resistor, the emitter of the fourth transistor is connected to the cathode of the third diode and the cathode of the fourth diode respectively, the anode of the third diode is connected to the gate of the first inverter switch tube of the three-phase inverter bridge as the output end of the voltage limiting module, and the anode of the fourth diode is connected to the gate of the second inverter switch tube of the three-phase inverter bridge as the output end of the voltage limiting module.

[0013] In addition, to achieve the above objectives, the present invention also provides a three-phase inverter circuit, which includes a three-phase inverter drive circuit and a three-phase inverter bridge, and the three-phase inverter drive circuit is configured as the three-phase inverter drive circuit described above.

[0014] The present invention proposes a three-phase inverter drive circuit and a three-phase inverter circuit, wherein the three-phase inverter drive circuit is connected to a three-phase inverter bridge; the three-phase inverter drive circuit comprises a drive chip, a signal generating module and an adjustable dead time module, wherein the output end of the drive chip is connected to the control end of the signal generating module through the adjustable dead time module, and the output end of the signal generating module is connected to the gate of the inverter switch tube in the three-phase inverter bridge; wherein: the drive chip is used to output a drive signal for the inverter switch tube of the three-phase inverter bridge; the signal generating module is used to output a control level corresponding to the drive signal to the inverter switch tube of the three-phase inverter bridge to control the conduction state of the inverter switch tube; the adjustable dead time module is used to adjust the dead time, and within the set dead time, output a drive signal indicating that the inverter switch tube is in the off state to the signal generating module. The dead time is adjusted by setting an adjustable dead time module, so that the dead time can be adjusted based on actual needs, so that the dead time can match the actual situation of the three-phase inverter bridge, and the signal generation module controls the conduction state of the inverter switch tube based on the dead time, so as to ensure that the inverter switch tubes of the same phase are not turned on at the same time to avoid short circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0016] Figure 1 A functional module diagram of an embodiment of a three-phase inverter drive circuit of the present invention; Figure 2 It is a structural schematic diagram of an adjustable dead time module in a three-phase inverter drive circuit of the present invention; Figure 3 is a timing diagram of a driving signal in a three-phase inverter driving circuit of the present invention; Figure 4 It is a schematic diagram of the overall structure of the three-phase inverter drive circuit of the present invention; Figure 5 It is a schematic diagram of the structure of the overcurrent protection part in the three-phase inverter drive circuit of the present invention.

[0017] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings in conjunction with the embodiments.

[0018] Description of Figure Numbers: DETAILED DESCRIPTION

[0019] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0022] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0023] The present invention provides a three-phase inverter drive circuit, which is applied to a three-phase inverter circuit. Figure 1 , Figure 1This is a functional module diagram of an embodiment of a three-phase inverter drive circuit of the present invention. In this embodiment, the three-phase inverter drive circuit is connected to a three-phase inverter bridge 200; the three-phase inverter drive circuit includes a driver chip 110, a signal generation module 130 and an adjustable dead time module 120, the adjustable dead time module 120 includes a plurality of dead time units, the output end of the driver chip 110 is connected to the control end of the signal generation module 130 through the dead time unit, and the output end of the signal generation module 130 is connected to the gate of the inverter switch tube in the three-phase inverter bridge 200; the dead time unit includes a logic gate and an adjustable delay response subunit, the first input end of the logic gate is connected to the output end of the driver chip 110, the input end of the adjustable delay response subunit is connected to the input end of the driver chip 110, and the output end of the adjustable delay response subunit is connected to the second input end of the logic gate; wherein: The driving chip 110 is used to output a driving signal for the inverter switch tube of the three-phase inverter bridge 200; The signal generating module 130 is used to output a control level corresponding to the driving signal to the inverter switch tube of the three-phase inverter bridge 200 to control the conduction state of the inverter switch tube; The adjustable dead time module 120 is used to adjust the dead time, and within the set dead time, maintain the logic gate outputting a driving signal indicating that the inverter switch tube is in the off state to the signal generation module 130 through the adjustable delay response subunit.

[0024] The three-phase inverter bridge 200 is used to invert the input DC voltage into three-phase AC voltages of U, V, and W; Figure 1 C01 and C02 are input bus capacitors; the specific structure of the three-phase inverter bridge 200 can be set based on actual needs. In this embodiment, the inverter switch tube of the three-phase inverter bridge 200 is an IGBT.

[0025] The driving chip 110 outputs a driving signal; the driving signal is used to indicate the conduction state of the corresponding inverter switch tube; specifically, the three-phase inverter bridge 200 includes six basic inverter switch tubes; the driving chip 110 outputs six driving signals, and the driving signals correspond to the inverter switch tubes one by one; the driving signal output by the driving chip 110 reaches the signal generating module 130 through the adjustable dead time module 120, and the signal generating module 130 controls the conduction state of the corresponding inverter switch tube based on the specific driving signal.

[0026] The adjustable dead time module 120 is used to adjust the dead time applied to the three-phase inverter bridge 200. At the same time, within the set dead time, the output of the drive signal indicating the off state is maintained, so that the state of the corresponding inverter switch tube remains in the off state, thereby realizing the interlocking effect of the dead time and avoiding the two inverter switches of the same phase bridge arm from being turned on at the same time.

[0027] Generally, the dead time is set with the rising edge of the driving signal as the starting point, and when the driving signal is at a high level, indicating that the corresponding inverter switch tube is turned on, for example; it can be understood that when the state of the inverter switch tube has not changed, the conduction state of the two inverter switch tubes on the same phase bridge arm is one on and the other off, such as the first inverter switch tube T1 is turned on and the second inverter switch tube T2 is turned off, and if it is necessary to change the state of the inverter switch tube, that is, to turn the first inverter switch tube T1 off and the second inverter switch tube T2 on, if the first inverter switch tube T1 is not turned off in time, the second inverter switch tube T2 is already turned on, a short circuit will occur. Therefore, at this time, the dead time should be set at the second inverter switch The first inverter switch T1 is turned on for a period of time at the beginning of the rising edge of the driving signal of the first inverter switch T2, thereby delaying the conduction of the second inverter switch T2, ensuring that the second inverter switch T2 is turned on only after the first inverter switch T1 is turned off, to avoid the occurrence of a short circuit; when the circuit ages, the time for the first inverter switch T1 to change from on to off may be extended, so the original dead time may not be able to cover the state change of the first inverter switch T1, and the adjustable dead time module 120 in this embodiment can adjust the dead time, so that the dead time can be adjusted to cover the state change of the first inverter switch T1, ensuring that the first inverter switch T1 can be turned off within the dead time, to adapt to different usage scenarios. The first inverter switch T1 changes from off to on, and the second inverter switch T2 changes from on to off in the same way, which will not be repeated.

[0028] The signal generating module 130 is used to directly control the conduction state of the inverter switch tube; for example, when the gate of the inverter switch tube is at a high level, the inverter switch tube is turned on, and when the gate of the inverter switch tube is at a low level, the inverter switch tube is turned off; that is, when the signal generating module 130 receives a driving signal indicating conduction, it sends a high level to the inverter switch tube, and when the signal generating module 130 receives a driving signal indicating shutdown, it sends a low level to the inverter switch tube.

[0029] In this embodiment, the dead time is adjusted by setting an adjustable dead time module 120, so that the dead time can be adjusted based on actual needs, so that the dead time can match the actual situation of the three-phase inverter bridge 200, and the signal generation module 130 controls the conduction state of the inverter switch tube based on the dead time, so as to ensure that the inverter switch tubes of the same phase are not turned on at the same time to avoid short circuit.

[0030] Furthermore, the signal generating module 130 includes a plurality of signal generating units; wherein: For each phase bridge arm of the three-phase inverter bridge 200, the first output end of the driver chip 110 is connected to the control end of the first signal generating unit 131, and the output end of the first signal generating unit 131 is connected to the control end of the first inverter switch tube T1; The second output end of the driving chip 110 is connected to the control end of the dead time unit 121, the output end of the dead time unit 121 is connected to the control end of the second signal generating unit 132, and the output end of the second signal generating unit 132 is connected to the control end of the second inverter switch tube T2.

[0031] It can be understood that each inverter switch tube in the three-phase inverter bridge 200 needs to be driven; therefore, in this embodiment, multiple signal generating units are provided, each signal generating unit receives a driving signal, and the output end of each signal generating unit is respectively connected to an inverter switch tube; it can be understood that for a signal generating unit, the driving signal it receives corresponds to the connected inverter switch tube.

[0032] In the three-phase inverter bridge 200, each phase bridge arm includes two inverter switch tubes; in this embodiment, the inverter switch tube arranged in the upper bridge arm is the first inverter switch tube T1, and the inverter switch tube arranged in the lower bridge arm is the second inverter switch tube T2; the signal generating unit connected to the first inverter switch tube T1 is the first signal generating unit 131, and the signal generating unit connected to the second inverter switch tube T2 is the second signal generating unit 132.

[0033] The signal generating unit corresponding to the first inverter switch tube T1 is directly connected to the driving chip 110; the signal generating unit corresponding to the second inverter switch tube T2 is connected to the driving chip 110 through the dead time unit 121; that is, the driving signal received by the second inverter switch tube T2 is processed by the dead time unit 121 and then output.

[0034] It should be noted that, in this embodiment, the driving signal output by the driving chip 110 has been set with the dead time processing by software. Even without the dead time unit 121, the dead time can be realized only by the driving signal itself. However, on this basis, the dead time unit 121 is set in this embodiment, so that the effect of the dead time can be further guaranteed. At the same time, since the dead time of the dead time unit 121 is adjustable, when the dead time set by the software cannot achieve interlocking, the interlocking of the first inverter switch tube T1 and the second inverter switch tube T2 can be guaranteed by setting a suitable dead time. Therefore, on this basis, in this embodiment, the dead time unit 121 is set only for the second inverter switch tube T2. Compared with the solution in which the dead time unit 121 is set for all inverter switches, the delay effect of the dead time unit 121 on the driving of the three-phase inverter bridge 200 can be reduced, and the influence on the driving accuracy of the three-phase inverter bridge 200 can be avoided.

[0035] It should be noted that, in other embodiments, a dead time unit 121 may be provided for each inverter switch tube.

[0036] Furthermore, the logic gate is a NOR gate ON, and the adjustable delay response subunit includes a first resistor R1 and a first capacitor C1; wherein: The first input end of the NOR gate ON is connected to the second output end of the driving chip 110 as the input end of the dead time unit 121, the first input end of the NOR gate ON is also connected to the second input end of the NOR gate ON through the first resistor R1, the second input end of the NOR gate ON is also grounded through the first capacitor C1, and the output end of the NOR gate ON is connected to the control end of the second signal generating unit 132 as the output end of the dead time unit 121.

[0037] The NOR gate ON will output a high level only when both input terminals are at a low level.

[0038] The driver chip 110 outputs a high level signal to the first input terminal of the NOR gate ON. At this time, the NOR gate ON outputs a low level signal to the second signal generating unit 132. At the same time, the high level signal output by the driver chip 110 charges the first capacitor C1 through the first resistor R1.

[0039] The output of the driving chip 110 is converted from a high level to a low level signal. At this time, the first input end of the NOR gate ON is at a low level, and the second end is at a high level due to the effect of the first capacitor C1. Therefore, the NOR gate ON still maintains the output low level to the second signal generating unit 132; thereafter, the first capacitor C1 is discharged through the first resistor R1. When the first capacitor C1 is discharged, the two input ends of the NOR gate ON are both at a low level, and the NOR gate ON changes to output a high level to the second signal generating unit 132.

[0040] It should be noted that, in the present embodiment, when the driving signal output by the driving chip 110 to the dead time unit 121 is at a low level, it indicates that the second inverter switch tube T2 is turned on; when the driving signal output by the driving chip 110 to the dead time unit 121 is at a high level, it indicates that the second inverter switch tube T2 is turned off; and when the driving signal directly output by the driving chip 110 to the first signal generating unit 131 is at a high level, it indicates that the first inverter switch tube T1 is turned on; when the driving signal directly output by the driving chip 110 to the first signal generating unit 131 is at a low level, it indicates that the second inverter switch tube T2 is turned off.

[0041] According to the capacitor charging and discharging formula:

[0042] Among them, U is the capacitor voltage; U0 is the charging power supply voltage, which is the driving signal in this embodiment; t is time, τ=RC, wherein R is the charging and discharging resistance, which is the first resistor R1 in this embodiment, and C is the capacitance of the first capacitor C1.

[0043] For example, the closing level of the NOR gate ON, that is, the voltage recognized as a low level, is 1.3V; when the high level of the driving signal is 5V, the voltage at the second input end of the NOR gate ON needs to be reduced to 1.3 / 5≈0.26 U0 to be recognized as a low level. From the above formula, the time t required for the capacitance to decrease to 0.26 U0 can be obtained. d for:

[0044] It can be seen that for capacitor charging and discharging, the resistance value of the resistor and the capacitance value of the capacitor will affect the charging and discharging speed of the capacitor; and the charging and discharging speed of the capacitor will affect the arrival time of the low level of the second input terminal of the NOR gate ON. The faster the charging and discharging speed of the capacitor, the earlier the low level of the second input terminal of the NOR gate ON arrives, that is, the shorter the set dead time, and the slower the charging and discharging speed of the capacitor, the later the low level of the second input terminal of the NOR gate ON arrives, that is, the longer the set dead time; therefore, the dead time can be adjusted by adjusting the values ​​of the first resistor R1 and the first capacitor C1; for example, the user can select a first resistor R1 with a suitable resistance value or a first capacitor C1 with a suitable capacitance value to replace the original first resistor R1 or the first capacitor C1 according to actual needs to adjust the dead time.

[0045] In other embodiments, the logic gate may also be of other types, such as an AND gate; when the logic gate is an AND gate, when the driver chip outputs a high level, when the driving signal output by the driver chip 110 to the dead time unit 121 is a low level, it indicates that the second inverter switch tube T2 is turned off; when the driving signal output by the driver chip 110 to the dead time unit 121 is a high level, it indicates that the second inverter switch tube T2 is turned on; The AND gate outputs a high level only when both input terminals are high.

[0046] The driving chip 110 outputs a low level signal to the first input terminal of the AND gate. At this time, the AND gate outputs a low level signal to the second signal generating unit 132. At the same time, the first capacitor C1 is discharged through the first resistor R1.

[0047] The output of the driving chip 110 is converted from a low level to a high level signal. At this time, the first input terminal of the AND gate is at a high level, and the second terminal is at a low level due to the effect of the first capacitor C1. Therefore, the AND gate still maintains outputting a low level to the second signal generating unit 132; thereafter, the first capacitor C1 is charged through the first resistor R1. When the first capacitor C1 is charged, both input terminals of the AND gate are at a high level, and the AND gate switches to outputting a high level to the second signal generating unit 132.

[0048] Furthermore, the adjustable delay response subunit further includes an adjustable resistor RT; wherein: The adjustable resistor RT is connected in parallel with the first resistor R1 , and a control end of the adjustable resistor RT is connected to the driving chip 110 .

[0049] In this embodiment, an adjustable resistor RT is provided in parallel with the first resistor R1; when the resistance value of the adjustable resistor RT changes, the parallel resistance value of the first resistor R1 and the adjustable resistor RT will change, thereby changing the set dead time. In this embodiment, the dead time can be adjusted more conveniently by providing the adjustable resistor RT.

[0050] The specific type of the adjustable resistor RT can be set based on actual needs, such as a voltage-controlled resistor.

[0051] Furthermore, the signal generating module 130 includes a plurality of signal generating units, and the signal generating units include a first transistor Q1 and a second transistor Q2; wherein: The base of the first transistor Q1 and the base of the second transistor Q2 serve as the control end of the signal generating unit, the collector of the first transistor Q1 is connected to the power supply, the emitter of the first transistor Q1 serves as the output end of the signal generating unit, the emitter of the first transistor Q1 is connected to the emitter of the second transistor Q2, and the collector of the second transistor Q2 is grounded.

[0052] In this embodiment, the first transistor Q1 is an NPN transistor, and the second transistor Q2 is a PNP transistor.

[0053] When the input drive signal is at a high level, the first transistor Q1 is turned on and the second transistor Q2 is turned off. At this time, the voltage of the power supply is transmitted to the gate of the corresponding inverter switch tube through the first transistor Q1 to control the inverter switch tube to turn on.

[0054] When the input driving signal is at a low level, the first transistor Q1 is turned off and the second transistor Q2 is turned on. At this time, the gate of the inverter switch tube is grounded through the second transistor Q2, and the corresponding inverter switch tube is turned off.

[0055] Furthermore, the three-phase inverter drive circuit further includes a plurality of overcurrent detection modules 140, a plurality of delay modules 150 and a plurality of voltage limiting modules 160; for each phase bridge arm of the three-phase inverter bridge 200, the detection end of the overcurrent detection module 140 is connected to the input end and the output end of the three-phase inverter bridge 200, the output end of the overcurrent detection module 140 is connected to the overcurrent detection end of the drive chip 110, the overcurrent detection module 140 is also connected to the control end of the voltage limiting module 160 through the delay module 150, and the output end of the voltage limiting module 160 is connected to the gate of the inverter switch tube of the three-phase inverter bridge 200; wherein: The overcurrent detection module 140 is used to detect the overcurrent of the three-phase inverter bridge 200 and send an overcurrent signal to the driver chip 110 when an overcurrent is detected; The delay module 150 is used to drive the voltage limiting module 160 to work within a preset delay time when the overcurrent detection module 140 detects an overcurrent; The voltage limiting module 160 is used to reduce the gate voltage of the inverter switch tube; The driving chip 110 is used to control all the inverter switches of the three-phase inverter bridge 200 to turn off after the overcurrent detection module 140 detects that the overcurrent reaches a preset delay time.

[0056] Existing overcurrent protection methods are easily affected by circuit environment fluctuations, resulting in misjudgment of overcurrent protection and affecting the normal operation of the circuit. To solve this problem, an overcurrent detection module 140, a delay module 150, and a voltage limiting module 160 are provided in this embodiment.

[0057] The overcurrent condition of the three-phase inverter bridge 200 is detected by the overcurrent detection module 140. When the three-phase inverter bridge 200 is monitored to have an overcurrent, the inverter switch tubes in the three-phase inverter bridge 200 are not directly turned off, but the gate voltage of each inverter switch tube is first reduced by the voltage limiting module 160, so as to limit the current while preventing direct shutdown due to misjudgment, thereby affecting the normal operation of the three-phase inverter bridge 200; at the same time, the driver chip 110 monitors the overcurrent condition. When the overcurrent is continuously detected for a period of time, that is, the preset delay time, it is considered that the circuit does have an overcurrent problem. At this time, all the inverter switch tubes are controlled to be turned off to avoid overcurrent damaging the circuit.

[0058] Furthermore, the overcurrent detection module 140 includes a first diode D1, a second diode D2, a first voltage regulator diode ZD1, a second resistor R2, a third resistor R3, a third transistor Q3 and an optical coupler U1; wherein: The cathode of the first diode D1 is connected to the positive input end of the bridge arm, and the anode of the first diode D1 is connected to the cathode of the first voltage stabilizing diode ZD1; the cathode of the second diode D2 is connected to the output end of the bridge arm, and the anode of the second diode D2 is connected to the cathode of the first voltage stabilizing diode ZD1; The anode of the first voltage stabilizing diode ZD1 is connected to the base of the third transistor Q3, the emitter of the third transistor Q3 is grounded, the collector of the third transistor Q3 is connected to the negative electrode of the optocoupler U1, the anode of the optocoupler U1 is connected to the power supply through the delay module 150, the emitter of the optocoupler U1 is grounded, the collector of the optocoupler U1 is connected to the overcurrent detection end of the driving chip 110 as the output end of the overcurrent detection module 140, and the collector of the optocoupler U1 is also connected to the power supply through the third resistor R3.

[0059] When there is no overcurrent in the circuit, the first diode D1 and the second diode D2 are not conducting, the reverse voltage of the first voltage stabilizing diode ZD1 cannot trigger breakdown, the base of the third transistor Q3 is at a low level, the third transistor Q3 is turned off, the optocoupler U1 is not conducting, and due to the pull-up effect of the third resistor R3, the optocoupler U1 outputs a high level to the driver chip 110. The base of the third transistor Q3 is grounded through a capacitor, which can filter out circuit interference.

[0060] When overcurrent occurs in the circuit, the first diode D1 and / or the second diode D2 is broken down, the first voltage stabilizing diode ZD1 is broken down, the base of the third transistor Q3 is at a high level, the third transistor Q3 is turned on, the cathode of the optocoupler U1 is grounded through the third transistor Q3, the optocoupler U1 is turned on, the emitter of the optocoupler U1 is grounded, and the optocoupler U1 outputs a low level to the driver chip 110.

[0061] When the driver chip 110 receives a high level output by the optocoupler U1, it considers that there is no overcurrent; when the driver chip 110 receives a low level output by the optocoupler U1, it considers that there is an overcurrent and starts timing. When the timing time reaches the preset delay time, all the inverter switches of the three-phase inverter bridge 200 are controlled to be turned off.

[0062] Furthermore, the delay module 150 includes a fourth resistor R4, a fifth resistor R5, a second capacitor C2, a second voltage zener diode ZD2 and a third voltage zener diode ZD3; wherein: The first end of the second capacitor C2 is connected to the power supply, the second end of the second capacitor C2 is connected to the positive electrode of the optocoupler U1 through the fourth resistor R4, the fifth resistor R5 is connected to the second capacitor C2 in parallel, the second voltage regulator diode ZD2 is connected to the second capacitor C2 in reverse parallel, the positive electrode of the second voltage regulator diode ZD2 is connected to the negative electrode of the third voltage regulator diode ZD3, and the positive electrode of the third voltage regulator diode ZD3 is connected to the control end of the voltage limiting module 160 as the output end of the delay module 150.

[0063] When there is no overcurrent in the circuit, since the optical coupler U1 is not conducting, the second capacitor C2 cannot be charged, and the delay module 150 is equivalent to not working.

[0064] After the overcurrent occurs in the circuit, the voltage of the power supply sequentially passes through the fifth resistor R5, the fourth resistor R4, the optical coupler U1, the third transistor Q3, and the ground to form a loop, and the optical coupler U1 is turned on; at the same time, the second capacitor C2 starts to charge, and the voltage of the second capacitor C2 gradually increases. When the voltage of the second capacitor C2 increases to the breakdown voltage of the second voltage zener diode ZD2, the second voltage zener diode ZD2 is broken down. At this time, as the voltage of the second capacitor C2 continues to increase, the voltage received by the voltage limiting module 160 also gradually increases; when it continues to increase to the breakdown voltage of the third voltage zener diode ZD3, the third voltage zener diode ZD3 is broken down, and the voltage of the voltage limiting module 160 no longer increases; After the current is converted from overcurrent to normal, the second capacitor C2 is discharged through the fifth resistor R5, the voltage of the second capacitor C2 gradually decreases, and the second zener diode ZD2 and the third zener diode ZD3 also return to the cut-off state.

[0065] Furthermore, the voltage limiting module 160 includes a fourth transistor Q4, a sixth resistor R6, a third diode D3 and a fourth diode D4; wherein: The base of the fourth transistor Q4 is connected to the anode of the third voltage regulator diode ZD3 as the control end of the voltage limiting module 160, the collector of the fourth transistor Q4 is grounded through the sixth resistor R6, the emitter of the fourth transistor Q4 is connected to the cathode of the third diode D3 and the cathode of the fourth diode D4 respectively, the anode of the third diode D3 is connected to the gate of the first inverter switch tube T1 of the three-phase inverter bridge 200 as the output end of the voltage limiting module 160, and the anode of the fourth diode D4 is connected to the gate of the second inverter switch tube T2 of the three-phase inverter bridge 200 as the output end of the voltage limiting module 160.

[0066] When there is no overcurrent in the circuit, the fourth transistor Q4 is not conducting.

[0067] After the circuit has an overcurrent, after the second voltage stabilizing diode ZD2 breaks down, the base voltage of the fourth triode Q4 increases with the increase of the second capacitor C2, so that the emitter voltage of the fourth triode Q4 increases synchronously, so that the Vge of the inverter switch tube becomes smaller, thereby limiting the gate voltage of the inverter switch tube; and after the third voltage stabilizing diode ZD3 breaks down, the base voltage of the fourth triode Q4 no longer increases with the increase of the second capacitor C2, so that the emitter voltage of the fourth triode Q4 no longer increases, so that the Vge of the inverter switch tube no longer decreases; After the current is converted from overcurrent to normal, as the second voltage stabilizing diode ZD2, the third voltage stabilizing diode ZD3, and the third triode Q3 are restored to be cut off, the gate voltage of the inverter switch tube is restored to the initial state.

[0068] The overall principle of overcurrent protection in this embodiment is described below: When there is no overcurrent in the circuit, the first diode D1 and the second diode D2 are not conducting, the reverse voltage of the first voltage stabilizing diode ZD1 cannot trigger breakdown, the base of the third transistor Q3 is at a low level, the third transistor Q3 is turned off, the optocoupler U1 is not conducting, and due to the pull-up effect of the third resistor R3, the optocoupler U1 outputs a high level to the driving chip 110; the second capacitor C2 cannot be charged, and the delay module 150 is equivalent to not working; the fourth transistor Q4 is not conducting.

[0069] When overcurrent occurs in the circuit, the first diode D1 and / or the second diode D2 is broken down, the first voltage stabilizing diode ZD1 is broken down, the base of the third transistor Q3 is at a high level, the third transistor Q3 is turned on, the cathode of the optocoupler U1 is grounded through the third transistor Q3, the optocoupler U1 is turned on, the emitter of the optocoupler U1 is grounded, and the optocoupler U1 outputs a low level to the driver chip 110; the voltage of the power supply sequentially passes through the fifth resistor R5, the fourth resistor R4, the optocoupler U1, the third transistor Q3, and the ground to form a loop, and the optocoupler U1 is turned on; at the same time, the second capacitor C2 starts to charge, and the voltage of the second capacitor C2 gradually increases. When the voltage of the second capacitor C2 increases to the second voltage stabilizing diode C2, the base of the third transistor Q3 is turned on, and the cathode of the optocoupler U1 is grounded through the third transistor Q3. The optocoupler U1 is turned on, and the emitter of the optocoupler U1 is grounded. The optocoupler U1 outputs a low level to the driver chip 110; the voltage of the power supply passes through the fifth resistor R5, the fourth resistor R4, the optocoupler U1, the third transistor Q3, and the ground to form a loop, and the optocoupler U1 is turned on; at the same time, the second capacitor C2 starts to charge, and the voltage of the second capacitor C2 gradually increases. When the voltage of the second capacitor C2 increases to the second voltage stabilizing diode C2, the base of the third transistor Q3 is turned on, and the base of the third transistor Q3 is turned on. When the breakdown voltage of the diode ZD2 reaches the breakdown voltage of the diode ZD2, the second voltage zener diode ZD2 is broken down. At this time, the base voltage of the fourth triode Q4 increases with the increase of the second capacitor C2. Therefore, the emitter voltage of the fourth triode Q4 increases synchronously, so that the Vge of the inverter switch tube becomes smaller, thereby limiting the gate voltage of the inverter switch tube; when it continues to increase to the breakdown voltage of the third voltage zener diode ZD3, the third voltage zener diode ZD3 is broken down, and the base voltage of the fourth triode Q4 no longer increases with the increase of the second capacitor C2. Therefore, the emitter voltage of the fourth triode Q4 no longer increases, so that the Vge of the inverter switch tube no longer decreases; When the driver chip 110 receives a high level output by the optocoupler U1, it considers that there is no overcurrent; when the driver chip 110 receives a low level output by the optocoupler U1, it considers that there is an overcurrent and starts timing. When the timing time reaches the preset delay time, all the inverter switches of the three-phase inverter bridge 200 are controlled to be turned off.

[0070] After the current is converted from overcurrent to normal, the second capacitor C2 is discharged through the fifth resistor R5, the voltage generated by the second capacitor C2 gradually decreases, and the second voltage zener diode ZD2 and the third voltage zener diode ZD3 also return to the cut-off state. As the second voltage zener diode ZD2, the third voltage zener diode ZD3, and the third transistor Q3 return to cut-off, the gate voltage of the inverter switch tube returns to the initial state.

[0071] The present invention also protects a three-phase inverter circuit, which includes a three-phase inverter drive circuit and a three-phase inverter bridge 200. The structure of the three-phase inverter drive circuit can refer to the above embodiment and will not be repeated here. As a matter of course, since the three-phase inverter circuit of this embodiment adopts the technical solution of the above three-phase inverter drive circuit, the three-phase inverter circuit has all the beneficial effects of the above three-phase inverter drive circuit.

[0072] It should be noted that, in this article, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "includes a..." does not exclude the presence of other identical elements in the process, method, article or system including the element. The serial numbers of the above-mentioned embodiments of the present invention are for description only and do not represent the advantages and disadvantages of the embodiments.

[0073] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A three-phase inverter drive circuit, characterized in that: The three-phase inverter drive circuit is connected to the three-phase inverter bridge; the three-phase inverter drive circuit includes a drive chip, a signal generation module and an adjustable dead time module, the adjustable dead time module includes a plurality of dead time units, the output end of the drive chip is connected to the control end of the signal generation module through the dead time unit, and the output end of the signal generation module is connected to the gate of the inverter switch tube in the three-phase inverter bridge; the dead time unit includes a logic gate and an adjustable delay response subunit, the first input end of the logic gate is connected to the output end of the drive chip, the input end of the adjustable delay response subunit is connected to the input end of the drive chip, and the output end of the adjustable delay response subunit is connected to the second input end of the logic gate; wherein: The driving chip is used to output a driving signal for the inverter switch tube of the three-phase inverter bridge; The signal generating module is used to output a control level corresponding to the driving signal to the inverter switch tube of the three-phase inverter bridge to control the conduction state of the inverter switch tube; The adjustable dead time module is used to adjust the dead time, and within the set dead time, maintain the logic gate outputting a driving signal indicating that the inverter switch tube is in the off state to the signal generation module through the adjustable delay response subunit.

2. The three-phase inverter drive circuit according to claim 1, characterized in that: The signal generation module includes a plurality of signal generation units; wherein: For each phase bridge arm of the three-phase inverter bridge, the first output end of the driving chip is connected to the control end of the first signal generating unit, and the output end of the first signal generating unit is connected to the control end of the first inverter switch tube; The second output end of the driving chip is connected to the control end of the dead time unit, the output end of the dead time unit is connected to the control end of the second signal generating unit, and the output end of the second signal generating unit is connected to the control end of the second inverter switch tube.

3. The three-phase inverter drive circuit according to claim 2, characterized in that: The logic gate is a NOR gate, and the adjustable delay response subunit includes a first resistor and a first capacitor; wherein: The first input end of the NOR gate is connected to the second output end of the driving chip as the input end of the dead time unit, the first input end of the NOR gate is also connected to the second input end of the NOR gate through the first resistor, the second input end of the NOR gate is also grounded through the first capacitor, and the output end of the NOR gate is connected to the control end of the second signal generating unit as the output end of the dead time unit.

4. The three-phase inverter drive circuit according to claim 3, characterized in that: The adjustable delayed response subunit also includes an adjustable resistor; wherein: The adjustable resistor is connected in parallel with the first resistor, and a control end of the adjustable resistor is connected to the driving chip.

5. The three-phase inverter drive circuit according to claim 1, characterized in that: The signal generation module includes a plurality of signal generation units, each of which includes a first triode and a second triode; wherein: The base of the first transistor and the base of the second transistor serve as the control end of the signal generating unit, the collector of the first transistor is connected to the power supply, the emitter of the first transistor serves as the output end of the signal generating unit, the emitter of the first transistor is connected to the emitter of the second transistor, and the collector of the second transistor is grounded.

6. The three-phase inverter drive circuit according to claim 1, characterized in that: The three-phase inverter drive circuit further includes a plurality of overcurrent detection modules, a plurality of delay modules and a plurality of voltage limiting modules; for each phase bridge arm of the three-phase inverter bridge, the detection end of the overcurrent detection module is connected to the input end and the output end of the three-phase inverter bridge, the output end of the overcurrent detection module is connected to the overcurrent detection end of the drive chip, the overcurrent detection module is also connected to the control end of the voltage limiting module through the delay module, and the output end of the voltage limiting module is connected to the gate of the inverter switch tube of the three-phase inverter bridge; wherein: The overcurrent detection module is used to detect the overcurrent of the three-phase inverter bridge and send an overcurrent signal to the driver chip when an overcurrent is detected; The delay module is used to drive the voltage limiting module to work within a preset delay time when the overcurrent detection module detects overcurrent; The voltage limiting module is used to reduce the gate voltage of the inverter switch tube; The driving chip is used to control all the inverter switches of the three-phase inverter bridge to turn off after the overcurrent detection module detects that the overcurrent reaches a preset delay time.

7. The three-phase inverter drive circuit according to claim 6, characterized in that: The overcurrent detection module includes a first diode, a second diode, a first voltage regulator diode, a second resistor, a third resistor, a third transistor and an optical coupler; wherein: The cathode of the first diode is connected to the positive input end of the bridge arm, and the anode of the first diode is connected to the cathode of the first voltage stabilizing diode; the cathode of the second diode is connected to the output end of the bridge arm, and the anode of the second diode is connected to the cathode of the first voltage stabilizing diode; The anode of the first voltage stabilizing diode is connected to the base of the third transistor, the emitter of the third transistor is grounded, the collector of the third transistor is connected to the negative electrode of the optocoupler, the anode of the optocoupler is connected to the power supply through the delay module, the emitter of the optocoupler is grounded, the collector of the optocoupler is connected to the overcurrent detection end of the driving chip as the output end of the overcurrent detection module, and the collector of the optocoupler is also connected to the power supply through the third resistor.

8. The three-phase inverter drive circuit according to claim 7, characterized in that: The delay module includes a fourth resistor, a fifth resistor, a second capacitor, a second voltage stabilizing diode and a third voltage stabilizing diode; wherein: The first end of the second capacitor is connected to the power supply, the second end of the second capacitor is connected to the positive electrode of the optocoupler through the fourth resistor, the fifth resistor is connected to the second capacitor in parallel, the second voltage regulator diode is connected in reverse parallel to the second capacitor, the positive electrode of the second voltage regulator diode is connected to the negative electrode of the third voltage regulator diode, and the positive electrode of the third voltage regulator diode is connected to the control end of the voltage limiting module as the output end of the delay module.

9. The three-phase inverter drive circuit according to claim 8, characterized in that: The voltage limiting module includes a fourth triode, a sixth resistor, a third diode and a fourth diode; wherein: The base of the fourth transistor is connected to the anode of the third voltage-stabilizing diode as the control end of the voltage limiting module, the collector of the fourth transistor is grounded through the sixth resistor, the emitter of the fourth transistor is connected to the cathode of the third diode and the cathode of the fourth diode respectively, the anode of the third diode is connected to the gate of the first inverter switch tube of the three-phase inverter bridge as the output end of the voltage limiting module, and the anode of the fourth diode is connected to the gate of the second inverter switch tube of the three-phase inverter bridge as the output end of the voltage limiting module.

10. A three-phase inverter circuit, characterized in that: The three-phase inverter circuit comprises a three-phase inverter drive circuit and a three-phase inverter bridge, and the three-phase inverter drive circuit is configured as a three-phase inverter drive circuit as claimed in any one of claims 1 to 9.

Images