Inverter parallel single bus active carrier phase synchronization method

Abstract

The invention discloses an inverter parallel single bus active carrier phase synchronization method. A host sends a carrier synchronization signal to a slave through a synchronization signal line at a carrier counting zero point; the slave reads numerical values in the basic calibration register, the time deviation register and the period register while receiving the carrier synchronization signal, and calculates a deviation value delta psi of carrier phases of the current slave and the host; and compensating the period deviation in the period register through the deviation value delta psi, so that the carrier counting zero point of the slave is aligned with the carrier counting zero point of the host. An existing hardware system does not need to be expanded, extra hardware cost is not increased, and the hardware size is not expanded. And the carrier wave difference of different master and slave controllers can be dynamically compensated according to an established parallel operation system. The carrier synchronization of the host and the slave is realized in a carrier phase deviation period, the synchronization speed is high, the precision is high, the synchronization can be locked after synchronization, and the condition of carrier synchronization failure in the operation process is avoided. And the stability is excellent.

Description

Technical Field

[0001] The invention relates to a single bus active carrier phase synchronization method for parallel inverters, belonging to the technical field of parallel inverter synchronization control. Background Art

[0002] With the development of the photovoltaic industry, the increase in market demand for energy storage, and the emergence of usage scenarios with different power ranges and scalable power, the demand for multiple parallel inverters is increasing. Therefore, the use of multiple inverters in parallel has become an inevitable trend in the development of the inverter industry.

[0003] However, when the inverters are used in parallel, there will be high-frequency circulating currents due to the asynchronous controller carriers. The high-frequency circulating current coupling in the system will affect the stability of the system and also have an impact on the load. Therefore, it is necessary to eliminate the high-frequency circulating currents in the system.

[0004] The main methods for suppressing high-frequency circulating currents are active circulating current suppression and passive circulating current suppression. Although the passive solution is simple to implement, it will increase the size and cost of the system, and its stability is not as good as that of the active circulating current suppression method. Compared with the passive suppression method, the carrier phase shift modulation method in the active suppression method has the advantages of high stability, fast synchronization speed, and low cost.

[0005] Traditional active circulating current suppression clearly states that the main source of carrier difference is the clock source of the inverter controller, that is, the difference in crystal oscillator. There is a certain difference between the actual oscillation frequency of the crystal oscillator and its nominal value, resulting in a large deviation in synchronization control. Summary of the invention

[0006] The purpose of the present invention is to solve the above-mentioned deficiencies in the prior art, and to propose a single-bus active carrier phase synchronization method for inverters in parallel, aiming at the problems of high cost of traditional passive circulating current and large active suppression synchronization deviation.

[0007] In order to achieve the above object, the technical solution adopted by the present invention is: A single bus active carrier phase synchronization method for inverter parallel connection, comprising a host and several slaves, wherein the host is connected to any of the slaves through a synchronization signal line, the host and any of the slaves are provided with a control management module ECAP, any of the control management module ECAP is provided with a carrier register EPWM, and the carrier register EPWM is provided with a basic calibration register, a time deviation register, and a period register; The host sends a carrier synchronization signal to the slave through the synchronization signal line at the carrier count zero point; The slave reads the values ​​in the basic calibration register, time deviation register, and period register while receiving the carrier synchronization signal, and calculates the deviation value ΔΨ of the carrier phase between the current slave and the host; The period deviation in the period register is compensated by the deviation value ΔΨ, so that the carrier count zero point of the slave is aligned with the carrier count zero point of the host.

[0008] Preferably, a deviation value ΔΨ between the carrier phases of the slave and the master is calculated; ; The TBCTR is the carrier count value read by the slave after receiving the carrier synchronization signal as the basic calibration value of the carrier phase difference between the master and the slave; The HW_Delay_CNT is a count value of the time delay caused by the carrier synchronization signal in the communication transmission obtained by the test; The TSCTR is used to introduce an interrupt to the control management module ECAP and record the time deviation caused by the interference of program operation when the slave receives the carrier synchronization signal.

[0009] Preferably, the S1 host reference voltage is at the carrier count zero point; The S2 host is at the zero point interrupt of the carrier register EPWM; S3 meets the conditions of step S1 and step S2, and the host sends a carrier synchronization signal to the slave through the synchronization signal line; S4 slave receives the carrier synchronization signal sent by the host; S5 slave reads TBCTR in the basic calibration register; S6 slave reads the assigned time delay count value HW_Delay_CNT; The S7 slave reads the TSCTR in the time deviation register; S8 calculates the deviation value ΔΨ of the master and slave; S9 compensates the carrier deviation value ΔΨ by operating the slave period register TBPRD.

[0010] The beneficial effects of the present invention are mainly reflected in: 1. No need to expand the existing hardware system, no additional hardware costs, and no increase in hardware volume.

[0011] 2. The carrier differences between different master and slave controllers can be dynamically compensated according to the established parallel system.

[0012] 3. The carrier synchronization of the master and slave is achieved within one carrier phase deviation cycle. Not only is the synchronization speed fast and the accuracy high, but the synchronization can also be locked to avoid the failure of carrier synchronization during operation.

[0013] 4. It increases the stability when multiple inverters are connected in parallel, and has a higher market promotion value. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings: Figure 1 It is a structural schematic diagram of a single bus active carrier phase synchronization method for inverters in parallel according to the present invention.

[0015] Figure 2 It is a flow chart of a single bus active carrier phase synchronization method for inverters in parallel according to the present invention.

[0016] Figure 3 It is a schematic diagram of generating a synchronization signal period of a single bus active carrier phase synchronization method for inverters in parallel according to the present invention.

[0017] Figure 4 It is a schematic diagram of dynamic adjustment of the single bus active carrier phase synchronization method of the inverters in parallel of the present invention.

[0018] Figure 5 It is a high-frequency circulating current waveform diagram of active carrier phase synchronization in the prior art.

[0019] Figure 6 It is a high-frequency circulating current waveform diagram during the intervention process of the active carrier phase synchronization method of the present invention.

[0020] Figure 7 It is a high-frequency circulating current waveform diagram after the active carrier phase synchronization method of the present invention is introduced. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] The present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant inventions, rather than to limit the inventions. It should also be noted that, for ease of description, only the parts related to the relevant inventions are shown in the accompanying drawings. It should be noted that, in the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0023] The present invention provides a single bus active carrier phase synchronization method for inverters in parallel, such as Figure 1As shown, it includes a host and several slaves. The host is connected to communicate with any of the slaves through a synchronization signal line. The host and any of the slaves are equipped with a control management module ECAP. Any of the control management modules ECAP is equipped with a carrier register EPWM. The carrier register EPWM is equipped with a basic calibration register, a time deviation register, and a period register.

[0024] The host sends a carrier synchronization signal to the slave through the synchronization signal line at the carrier count zero point.

[0025] The slave reads the values ​​in the basic calibration register, the time deviation register, and the period register while receiving the carrier synchronization signal, and calculates the deviation value ΔΨ of the carrier phase between the current slave and the host.

[0026] The period deviation in the period register is compensated by the deviation value ΔΨ, so that the carrier count zero point of the slave is aligned with the carrier count zero point of the host.

[0027] Specific implementation process and principle description: The source of carrier difference is mainly the clock source on the inverter controller, that is, the difference in crystal oscillators. The actual oscillation frequency of the crystal oscillator is different from its nominal value. Take the crystal oscillator with a nominal value of 30MHz and a frequency deviation of ±20ppm as an example. When the carrier frequency of the controller is 20kHz (single-side count 5000 in up and down counting mode), the deviation of the carrier frequency is ±0.4Hz. That is, the maximum carrier phase deviation of 360° can be achieved within a period of 2.5s, that is, the performance of a high-frequency circulating current in a low-frequency period.

[0028] The present invention determines the identities of a master and a slave in a parallel system, and the master sends a carrier synchronization signal to the slave through a single synchronization signal line at the carrier count zero point. The slave reads the carrier count value while receiving the synchronization signal, and determines the difference in carrier phase between the current slave and the master through the carrier count value. At the same time, the carrier zero point of the slave is aligned with the carrier zero point of the master by modifying the period value within the current carrier period of the slave, thereby achieving carrier synchronization between the master and the slave.

[0029] In a specific embodiment, a deviation value ΔΨ between the carrier phases of the slave and the master is calculated; .

[0030] like Figure 3 As shown, this embodiment realizes carrier synchronization of the slave by performing carrier phase shift in a time window with a small duty cycle, so the host sends a synchronization signal at the zero-crossing point with the smallest duty cycle of each reference voltage cycle.

[0031] TBCTR is the carrier count value read by the slave after receiving the carrier synchronization signal as the basic calibration value of the carrier phase difference between the master and the slave, that is, the TBCTR value in the EPWM register.

[0032] HW_Delay_CNT is the time delay count value caused by the carrier synchronization signal in the communication transmission obtained by the test; the time delay caused by the synchronization signal in the hardware device is obtained through multiple tests and converted into the count value HW_Delay_CNT with the same dimension as TBCTR and TSCTR. In some actual tests, the value is in the range of 2000~15000. The general value is in the range of 6600±1000.

[0033] TSCTR is used to introduce the interrupt of the control management module ECAP and record the time deviation caused by the interference of program operation when the slave receives the carrier synchronization signal. The interrupt of ECAP is introduced to record the time deviation caused by the interference of other programs when the slave receives the synchronization signal (that is, the TSCTR value in the ECAP register) to eliminate the abnormality of carrier phase calculation caused by program interference.

[0034] like Figure 4 As shown, after receiving the synchronization signal, the slave adds the carrier deviation value to the slave EPWM carrier cycle value TBPRD through the deviation value calculated by the above formula to realize carrier phase shift, and dynamically adjusts the carrier synchronization through the movement of each cycle.

[0035] In a specific embodiment, referring to Figure 1 As shown, the following steps are included: The host reference voltage is at the carrier count zero point; The host is at the zero point interrupt of the carrier register EPWM; If the conditions of step S1 and step S2 are met, the host sends a carrier synchronization signal to the slave through the synchronization signal line; The slave receives the carrier synchronization signal sent by the master; The slave reads TBCTR in the basic calibration register; The slave reads the assigned time delay count value HW_Delay_CNT; The slave reads TSCTR in the time deviation register; Calculate the deviation value ΔΨ of the master and slave; The slave is at the zero point interrupt of the carrier register EPWM; By operating the slave period register TBPRD, the carrier deviation value ΔΨ is compensated.

[0036] like Figure 5As shown, CH1: host branch output side current 20.0A / Div; CH2: slave branch output side current 20.0A / Div; before this carrier synchronization method is used, the high-frequency circulating current value is relatively large, and this is the waveform of the no-load high-frequency circulating current on the inverter output side before this method is used.

[0037] like Figure 6 As shown, CH1: host branch output side current 20.0A / Div; CH2: slave branch output side current 20.0A / Div; these are high-frequency circulating current waveforms during the carrier synchronization process after the intervention of this method.

[0038] like Figure 7 As shown in the figure, CH1: host branch output side current 20.0A / Div; CH2: slave branch output side current 20.0A / Div; are the high-frequency circulating current waveforms after the intervention of this method, that is, after carrier synchronization. The difference can be clearly compared. Before using this method, the effective value of the high-frequency circulating current is higher. After using this method, the high-frequency circulating current is significantly reduced.

[0039] From the above description, it can be found that there is no need to expand the existing hardware system, increase additional hardware costs, and expand the hardware volume. The carrier differences of different master and slave controllers can be dynamically compensated according to the established parallel system. The carrier synchronization of the master and slave is achieved within a carrier phase deviation cycle. Not only is the synchronization speed fast and the accuracy high, but it can also be locked after synchronization to avoid the failure of carrier synchronization during operation. The stability of multiple inverters in parallel is increased, which has a high market promotion value.

[0040] The term "comprise" or any other similar term is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus / device that includes a list of elements includes not only those elements but also other elements not expressly listed, or also includes elements inherent to such process, method, article, or apparatus / device.

[0041] So far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.

Claims

1. A single bus active carrier phase synchronization method for inverter parallel connection, comprising a host and several slaves, wherein the host is connected to any of the slaves through a synchronization signal line, wherein the host and any of the slaves are provided with a control management module ECAP, wherein any of the control management module ECAP is provided with a carrier register EPWM, wherein the carrier register EPWM is provided with a basic calibration register, a time deviation register, and a period register, wherein: The host sends a carrier synchronization signal to the slave through the synchronization signal line at the carrier count zero point; The slave reads the values ​​in the basic calibration register, time deviation register, and period register while receiving the carrier synchronization signal, and calculates the deviation value ΔΨ of the carrier phase between the current slave and the host; The period deviation in the period register is compensated by the deviation value ΔΨ, so that the carrier count zero point of the slave is aligned with the carrier count zero point of the host.

2. The single bus active carrier phase synchronization method for inverters in parallel according to claim 1, characterized in that: Calculate the carrier phase deviation ΔΨ between the slave and the master; ； The TBCTR is the carrier count value read by the slave after receiving the carrier synchronization signal as the basic calibration value of the carrier phase difference between the master and the slave; The HW_Delay_CNT is a count value of the time delay caused by the carrier synchronization signal in the communication transmission obtained by the test; The TSCTR is used to introduce an interrupt to the control management module ECAP and record the time deviation caused by the interference of program operation when the slave receives the carrier synchronization signal.

3. The single bus active carrier phase synchronization method for inverters in parallel according to claim 2, characterized in that: The S1 host reference voltage is at the carrier count zero point; The S2 host is at the zero point interrupt of the carrier register EPWM; S3 meets the conditions of step S1 and step S2, and the host sends a carrier synchronization signal to the slave through the synchronization signal line; S4 slave receives the carrier synchronization signal sent by the host; S5 slave reads TBCTR in the basic calibration register; S6 slave reads the assigned time delay count value HW_Delay_CNT; The S7 slave reads the TSCTR in the time deviation register; S8 calculates the deviation value ΔΨ of the master and slave; S9 compensates the carrier deviation value ΔΨ by operating the slave period register TBPRD.

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