Harmonic current suppression method and device, computer equipment, medium and program product

Abstract

The invention relates to a harmonic current suppression method and device, computer equipment, a medium and a program product. The method is applied to a mixed frequency parallel system comprising a low-frequency unit and a high-frequency unit, and comprises the following steps: filtering a first part of harmonic waves generated by the low-frequency unit and the high-frequency unit at a power grid side; performing pulse width modulation on the low-frequency unit, and reducing a second part of harmonic waves generated by the low-frequency unit; and performing multiple quasi-proportional resonance control on the high-frequency unit, and compensating a third part of harmonic waves generated by the low-frequency unit. Therefore, some specific sub-harmonics can be selectively eliminated, an optimal output voltage waveform is generated at a lower switching frequency, current harmonics are remarkably reduced, high efficiency and low cost are effectively considered, the advantages of a power device are played to the maximum extent, and the system performance is improved while the dynamic performance and the power density of the system are improved. The size of a passive filter element is reduced, the control bandwidth of the system is increased, the control complexity of the converter is reduced, and the output performance of the hybrid frequency parallel system is improved.

Description

Technical Field

[0001] The present application relates to the field of power electronics technology, and in particular to a harmonic current suppression method, device, computer equipment, computer-readable storage medium, and computer program product. Background Art

[0002] In order to alleviate the contradiction between converter efficiency and power quality and make the output power quality meet the relevant grid connection standards, a variety of solutions have emerged. Among them, the mixed frequency parallel system of Si IGBT (based on traditional silicon-based insulated gate bipolar transistor) and SiC MOSFET (new silicon carbide-based metal-oxide semiconductor field effect transistor) directly connects high-current Si IGBT devices and low-current SiC MOSFET devices in parallel to form a hybrid switch. This mixed frequency parallel system breaks through the switching frequency limit of SiIGBT and the rated current limit of SiC MOSFET, and reduces the system cost, providing a feasible idea for high-quality, high-efficiency and large-capacity power conversion.

[0003] At present, the mixed frequency parallel technology has been gradually applied to many types of converters such as bidirectional DC-DC (direct current-direct current) converters, PFC (Power Factor Correction), and single-phase inverters.

[0004] However, mixed frequency parallel connection technology is mostly used in simple topologies such as chopper circuits or single-phase inverter circuits. For complex topologies such as three-phase inverters, when mixed frequency parallel connection schemes are applied, there are often problems such as complex control methods, many system output current harmonics, and poor output voltage waveforms. Summary of the invention

[0005] Based on this, it is necessary to provide a harmonic current suppression method, device, computer equipment, computer-readable storage medium and computer program product that can be applied to a mixed frequency parallel system and can effectively reduce multiple current harmonics of low-frequency units and high-frequency units and improve the quality of the output voltage waveform in response to the above-mentioned technical problems.

[0006] In a first aspect, the present application provides a harmonic current suppression method, which is applied to a mixed frequency parallel system including a low frequency unit and a high frequency unit, comprising:

[0007] filtering out the first part of harmonics generated by the low-frequency unit and the high-frequency unit on the grid side; wherein the low-frequency unit comprises: a converter based on Si IGBT, and the high-frequency unit comprises: a converter based on SiC MOSFET;

[0008] Performing pulse width modulation on the low-frequency unit to reduce the second part of harmonics generated by the low-frequency unit itself;

[0009] The high frequency unit is subjected to multiple quasi-proportional resonance control, and the third part of harmonics generated by the low frequency unit is compensated.

[0010] In one of the embodiments, the first part of harmonics includes: 23rd to 256th harmonics generated by the low frequency unit and the high frequency unit;

[0011] The second part of harmonics includes: 3rd to 13th harmonics generated by the low-frequency unit;

[0012] The third part of harmonics includes: 3rd to 23rd harmonics generated by the low-frequency unit.

[0013] In one of the embodiments, filtering out the first part of harmonics generated by the low-frequency unit and the high-frequency unit on the grid side includes:

[0014] respectively determining harmonic frequencies generated by the low-frequency unit and the high-frequency unit;

[0015] The parameters of the grid-side LC filter are determined according to the harmonic frequencies generated by the low-frequency unit and the high-frequency unit, and the first part of the harmonics generated by the low-frequency unit and the high-frequency unit are filtered out by the LC filter.

[0016] In one embodiment, the pulse width modulation of the low frequency unit to reduce the second part of harmonics generated by the low frequency unit itself includes:

[0017] Obtain five switching angles of the first 1 / 4 cycle of the phase voltage output by the low-frequency unit bridge arm;

[0018] Using the five switching angles as reference quantities, the switching angles of the A-phase, B-phase, and C-phase bridge arms of the low-frequency unit are determined respectively;

[0019] According to the switching angles of the A-phase, B-phase and C-phase bridge arms of the low-frequency unit, a first switching signal for controlling two power devices of the A-phase, B-phase and C-phase bridge arms is generated, wherein the on-off timing of the first switching signal is selected to eliminate the 5th, 7th, 11th and 13th harmonics generated by the low-frequency unit itself.

[0020] In one embodiment, the step of obtaining five switching angles of the first 1 / 4 cycle of the phase voltage output by the low-frequency unit bridge arm includes:

[0021] Determine the modulation signal amplitude and the modulation signal initial phase angle of the low frequency unit;

[0022] Determine the three-phase modulation signal of the low-frequency unit according to the modulation signal amplitude and the modulation signal initial phase angle;

[0023] The Gaussian fitting method is used to fit the trajectory of the switching angle of the phase voltage output by the low-frequency unit bridge arm changing with the three-phase modulation signal of the low-frequency unit, and five switching angles of the first 1 / 4 cycle of the phase voltage output by the low-frequency unit bridge arm are obtained.

[0024] In one embodiment, the performing multiple quasi-proportional resonance control on the high frequency unit includes:

[0025] respectively determining the three-phase modulation signals of the high-frequency unit;

[0026] A three-phase modulation signal of a high-frequency unit is processed using a sinusoidal pulse width modulation strategy or a space vector pulse width modulation strategy, and a second switching signal for a power device in the high-frequency unit is output. The on-off timing of the second switching signal is selected to compensate for the 5th, 7th, 11th, 13th, 17th, 19th, and 23rd harmonics generated by the low-frequency unit.

[0027] In a second aspect, the present application further provides a harmonic current suppression device, which is applied to a mixed frequency parallel system including a low frequency unit and a high frequency unit, comprising:

[0028] A filtering module, used for filtering out the first part of harmonics generated by the low-frequency unit and the high-frequency unit on the grid side; wherein the low-frequency unit comprises: a converter based on Si IGBT, and the high-frequency unit comprises: a converter based on SiC MOSFET;

[0029] A pulse width modulation module, used for performing pulse width modulation on the low frequency unit to reduce the second part of harmonics generated by the low frequency unit itself;

[0030] The resonance control and compensation module is used to perform multiple quasi-proportional resonance control on the high-frequency unit and compensate for the third part of the harmonics generated by the low-frequency unit.

[0031] In a third aspect, the present application further provides a computer device, which is applied to a mixed frequency parallel system including a low frequency unit and a high frequency unit, and includes a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0032] filtering out the first part of harmonics generated by the low-frequency unit and the high-frequency unit on the grid side; wherein the low-frequency unit comprises: a converter based on Si IGBT, and the high-frequency unit comprises: a converter based on SiC MOSFET;

[0033] Performing pulse width modulation on the low-frequency unit to reduce the second part of harmonics generated by the low-frequency unit itself;

[0034] The high frequency unit is subjected to multiple quasi-proportional resonance control, and the third part of harmonics generated by the low frequency unit is compensated.

[0035] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, which is applied to a mixed frequency parallel system including a low frequency unit and a high frequency unit, and when the computer program is executed by a processor, the following steps are implemented:

[0036] filtering out the first part of harmonics generated by the low-frequency unit and the high-frequency unit on the grid side; wherein the low-frequency unit comprises: a converter based on Si IGBT, and the high-frequency unit comprises: a converter based on SiC MOSFET;

[0037] Performing pulse width modulation on the low-frequency unit to reduce the second part of harmonics generated by the low-frequency unit itself;

[0038] The high frequency unit is subjected to multiple quasi-proportional resonance control, and the third part of harmonics generated by the low frequency unit is compensated.

[0039] In a fifth aspect, the present application further provides a computer program product, which is applied to a mixed frequency parallel system including a low frequency unit and a high frequency unit, and includes a computer program, and when the computer program is executed by a processor, the following steps are implemented:

[0040] filtering out the first part of harmonics generated by the low-frequency unit and the high-frequency unit on the grid side; wherein the low-frequency unit comprises: a converter based on Si IGBT, and the high-frequency unit comprises: a converter based on SiC MOSFET;

[0041] Performing pulse width modulation on the low-frequency unit to reduce the second part of harmonics generated by the low-frequency unit itself;

[0042] The high frequency unit is subjected to multiple quasi-proportional resonance control, and the third part of harmonics generated by the low frequency unit is compensated.

[0043] The above-mentioned harmonic current suppression method, device, computer equipment, computer-readable storage medium and computer program product are applied to a mixed frequency parallel system including a low-frequency unit and a high-frequency unit, and the first part of the harmonics generated by the low-frequency unit and the high-frequency unit are filtered out on the grid side; wherein the low-frequency unit includes: a converter based on Si IGBT, and the high-frequency unit includes: a converter based on SiC MOSFET; thereby, most of the harmonics generated by the low-frequency unit and the high-frequency unit can be eliminated on the grid side. The low-frequency unit is pulse-width modulated to reduce the second part of the harmonics generated by the low-frequency unit itself; thereby, the specific harmonics generated by the low-frequency unit can be effectively reduced. The high-frequency unit is subjected to multiple quasi-proportional resonance control, and the third part of the harmonics generated by the low-frequency unit is compensated. This can selectively eliminate certain specific harmonics, generate the optimal output voltage waveform at a lower switching frequency, significantly reduce current harmonics, achieve an effective balance between high efficiency and low cost, maximize the advantages of power devices, and reduce the size of passive filtering components while improving the dynamic performance and power density of the system. It increases the control bandwidth of the system, reduces the control complexity of the converter, and improves the output performance of the mixing system. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments of the present application or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0045] Figure 1 A topological diagram of an application system of a harmonic current suppression method in an embodiment;

[0046] Figure 2 Schematic diagram of a flow chart of a harmonic current suppression method in one embodiment;

[0047] Figure 3 A schematic diagram of harmonic elimination in a current harmonic suppression method for a mixed frequency parallel system in one embodiment;

[0048] Figure 4 A schematic diagram of the SHEPWM principle in a control method for a mixed frequency parallel system in an embodiment;

[0049] Figure 5 A schematic diagram of the trajectories of five switch angles changing with modulation signals in a control method for a mixed frequency parallel system in one embodiment;

[0050] Figure 6 This is a frequency response comparison chart of commonly used controllers;

[0051] Figure 7 A simulated output current waveform diagram of a mixed frequency parallel system in one embodiment;

[0052] Figure 8 A comparison diagram of THD content of simulated output current of a mixed frequency parallel system in one embodiment.

[0053] Fig. 9 is a structural block diagram of a harmonic current suppression device in one embodiment;

[0054] Fig.10 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0056] The harmonic current suppression method provided in the embodiment of the present application can be applied to Figure 1 In the mixed frequency parallel system shown in FIG. The mixed frequency parallel system includes a converter based on Si IGBT (traditional silicon-based insulated gate bipolar transistor) and a converter based on SiC MOSFET (new silicon carbide-based metal-oxide semiconductor field effect transistor). Exemplarily, a large-capacity three-phase Si IGBT low frequency unit (Low frequency unit, LFU) and a small-capacity three-phase SiCMOSFET high frequency unit (High frequency unit, HFU) are connected in parallel to form a Figure 1 The circuit structure shown in the figure, L L and L H They are high-frequency unit filter inductance and low-frequency unit filter inductance, i L and i H Corresponding to the inductance L L and L H The current on the high-frequency unit and the low-frequency unit; L g and C f The grid-side LC filter is formed, u C is the system capacitor voltage, i C is the system capacitance current; i g is the grid-connected current, u g is the grid voltage; the common DC bus voltage is U dc ; N' is the imaginary midpoint of the DC power supply, and N is the midpoint of the load.

[0057] Exemplarily, the low-frequency unit and high-frequency unit connected in parallel can operate independently or in coordination. When an open-circuit fault occurs in the high-frequency unit, the low-frequency unit works alone to provide fault tolerance; under light-load conditions within the safe operating range of the device, the high-frequency unit can work alone to improve efficiency. Under other operating conditions, the low-frequency unit and the high-frequency unit share a common DC power supply and work in coordination. The low-frequency unit processes high power at an extremely low switching frequency, and the high-frequency unit compensates for the switching ripple generated by the low-frequency unit to achieve a trade-off between efficiency and power quality. Since the principle of the low-frequency unit and the high-frequency unit working alone is the same as the working principle of the traditional three-phase bridge converter, the following will only explain in detail how to suppress system current harmonics when the low-frequency unit and the high-frequency unit work in coordination.

[0058] Exemplarily, the first part of harmonics generated by the low-frequency unit and the high-frequency unit can be filtered out on the grid side; pulse width modulation can be performed on the low-frequency unit to reduce the second part of harmonics generated by the low-frequency unit itself; multiple quasi-proportional resonance control can be performed on the high-frequency unit to compensate for the third part of harmonics generated by the low-frequency unit.

[0059] In an exemplary embodiment, Figure 2 As shown, a harmonic current suppression method is provided, which is applied to Figure 1 The system in is taken as an example to illustrate, including the following steps 201 to 203. Among them:

[0060] Step 201: filter out the first part of harmonics generated by the low-frequency unit and the high-frequency unit on the grid side.

[0061] The low-frequency unit includes: a converter based on Si IGBT, and the high-frequency unit includes: a converter based on SiCMOSFET.

[0062] In this embodiment, the harmonic frequencies generated by the low-frequency unit and the high-frequency unit are first determined respectively; according to the harmonic frequencies generated by the low-frequency unit and the high-frequency unit, the parameters of the grid-side LC filter are determined, and the first part of the harmonics generated by the low-frequency unit and the high-frequency unit are filtered out by the LC filter.

[0063] Exemplarily, the first part of harmonics includes: 23rd to 256th harmonics generated by the low-frequency unit and the high-frequency unit.

[0064] Step 202: pulse width modulation is performed on the low frequency unit to reduce the second part of harmonics generated by the low frequency unit itself.

[0065] The second part of harmonics includes: 3rd to 13th harmonics generated by the low-frequency unit.

[0066] Exemplarily, five switching angles of the first 1 / 4 cycle of the phase voltage output by the bridge arm of the low-frequency unit are obtained; the five switching angles are used as reference quantities to respectively determine the switching angles of the A-phase, B-phase, and C-phase bridge arms of the low-frequency unit; based on the switching angles of the A-phase, B-phase, and C-phase bridge arms of the low-frequency unit, a first switching signal for controlling two power devices of the A-phase, B-phase, and C-phase bridge arms is generated, wherein the selection of the on-off moment of the first switching signal is used to eliminate the 5th, 7th, 11th, and 13th harmonics generated by the low-frequency unit itself.

[0067] In this embodiment, the modulation signal amplitude and the initial phase angle of the modulation signal of the low-frequency unit are determined; according to the modulation signal amplitude and the initial phase angle of the modulation signal, the three-phase modulation signal of the low-frequency unit is determined; and the Gaussian fitting method is used to fit the trajectory of the switching angle of the phase voltage output by the bridge arm of the low-frequency unit as the three-phase modulation signal of the low-frequency unit changes, and the five switching angles of the first 1 / 4 cycle of the phase voltage output by the bridge arm of the low-frequency unit are obtained.

[0068] Exemplarily, the amplitude M of the low-frequency unit modulation signal and the initial phase angle Δθ of the modulation signal are first calculated, and the calculation formula is as follows:

[0069]

[0070] In the formula, and Respectively represent the d-axis modulation signal and q-axis modulation signal of the low-frequency unit; U dc Indicates the output voltage.

[0071] Secondly, based on the obtained M and Δθ, calculate the low-frequency unit a-phase modulation signal b-phase modulation signal C phase modulation signal The calculation formula is as follows:

[0072]

[0073] Where ω is the grid-connected voltage angular frequency.

[0074] Finally, according to the obtained a-phase modulation signal b-phase modulation signal C phase modulation signal The switching angles of the A-phase, B-phase, and C-phase bridge arms of the low-frequency unit are calculated to control the on and off of the two power devices of the A-phase, B-phase, and C-phase bridge arms respectively.

[0075] Exemplarily, the five switching angles of the first 1 / 4 cycle of the output phase voltage of the low-frequency unit bridge arm are recorded as α1, α2, α3, α4, and α5, respectively. The Gaussian fitting method is used to fit the trajectories of the five switching angles changing with the modulation signal, and the following formula is obtained:

[0076]

[0077] Where: m is the low-frequency unit modulation signal; α k is the kth switching angle among the five switching angles.

[0078] When k = 1:

[0079] When n=1, a1=21.3, b1=-0.3641, c1=1.244;

[0080] When n=2, a2=0, b2=0.2745, c2=0.0003583;

[0081] When n=3, a3=3.937, b3=0.9583, c3=0.6273;

[0082] When k = 2:

[0083] When n=1, a1=3.193, b1=1.144, c1=0.2337;

[0084] When n=2, a2=8.636, b2=0.989, c2=0.5303;

[0085] When n=3, a3=20, b3=0.1601, c3=1.217;

[0086] When k = 3:

[0087] When n=1, a1=40.41, b1=-0.2299, c1=1.235;

[0088] When n=2, a2=11.7, b2=0.9276, c2=0.5762;

[0089] When n=3, a3=3.576, b3=1.141, c3=0.2539;

[0090] When k = 4:

[0091] When n=1, a1=5.435, b1=1.108, c1=0.1701;

[0092] When n=2, a2=16.44, b2=1.023, c2=0.4966;

[0093] When n=3, a3=40.48, b3=0.1932, c3=1.245;

[0094] When k = 5:

[0095] When n=1, a1=59.54, b1=-0.09161, c1=1.263;

[0096] When n=2, a2=17.91, b2=0.9769, c2=0.5182;

[0097] When n=3, a3=5.673, b3=1.105, c3=0.1828;

[0098] Combined with the obtained a-phase modulation signal b-phase modulation signal C phase modulation signal And formula (3) can calculate the switching angles of the A-phase, B-phase, and C-phase bridge arms of the low-frequency unit respectively, thereby controlling the on and off of the two power devices of the A-phase, B-phase, and C-phase bridge arms respectively to eliminate the 5th, 7th, 11th, and 13th harmonics generated by the Si IGBT low-frequency unit itself.

[0099] Exemplarily, the a-phase modulation signal u is obtained by combining * La And formula (3), calculate the switching angle of the A-phase bridge arm of the Si IGBT low-frequency unit, and control the on and off of the two IGBTs in the A-phase bridge arm. Combined with the obtained b-phase modulation signal u * Lb And formula (3), calculate the switching angle of the B phase and bridge arm of the Si IGBT low-frequency unit, and control the on and off of the two IGBTs in the B phase bridge arm. Combined with the obtained C phase modulation signal u * Lc And formula (3), calculate the switching angle of the C-phase bridge arm of the Si IGBT low-frequency unit, and control the on and off of the two IGBTs in the C-phase bridge arm.

[0100] Step 203 , performing multiple quasi-proportional resonance control on the high frequency unit, and compensating for the third part of harmonics generated by the low frequency unit.

[0101] Exemplarily, the third part of harmonics includes: 3rd to 23rd harmonics generated by the low-frequency unit.

[0102] In this embodiment, the three-phase modulation signal of the high-frequency unit is determined respectively; the three-phase modulation signal of the high-frequency unit is processed using a sinusoidal pulse width modulation strategy or a space vector pulse width modulation strategy, and a second switching signal for a power device in the high-frequency unit is output, and the on-off timing of the second switching signal is selected to compensate for the 5th, 7th, 11th, 13th, 17th, 19th, and 23rd harmonics generated by the low-frequency unit.

[0103] Exemplarily, the high frequency unit a phase modulation signal is calculated according to the following formulas (4)-(6): b-phase modulation signal C phase modulation signal

[0104]

[0105] Among them, the mQPR controller (composite quasi-proportional resonant current controller) can make the specified frequency signal reach high gain, thereby realizing small error control. The mQPR consists of the fundamental wave controller H1 and the harmonic compensator H2, as shown in formula (5):

[0106] G mQPR (s)=H1(s)+H2(s) (5)

[0107]

[0108] In the formula, i Href(a) 、i Href(b) 、i Href(c) Respectively represent the current reference values ​​of phase A, phase B, and phase C of the high-frequency unit; i H(a) 、i H(b) 、i H(c) Respectively represent the current sampling values ​​of phase A, phase B, and phase C of the high-frequency unit; K Hp K is the proportional coefficient of the fundamental wave controller; HR1 and K HRn are the resonance coefficients of the fundamental wave and the nth harmonic respectively; ω1 and ω n are the angular frequencies of the fundamental wave and the nth harmonic, ξ1 and ξ n are the correlation coefficients between the corresponding frequency cutoff frequency and the resonant frequency.

[0109] For example, n=5, 7, 11, 13, 17, 19, 23 are taken respectively. Figure 6 The frequency domain characteristics of common controllers such as PI controller (integral controller), PR controller (proportional resonant controller), QPR controller (quasi-proportional resonant controller) and mQPR controller are shown in Figure 1. Figure 6 It can be seen that the mQPR controller has a large gain at the fundamental frequency and the selected harmonic frequency, so it can track complex signals with multiple frequencies superimposed, and is suitable for the scenarios in the embodiments of the present application.

[0110] Exemplarily, when multiple quasi-proportional resonant control is adopted, the a-phase modulation signal is processed using an SPWM (sinusoidal pulse width modulation technique) strategy or an SVPWM (space vector pulse width modulation) strategy. b-phase modulation signal C phase modulation signal The second switching signal of the high frequency unit is output to compensate for the 5th, 7th, 11th, 13th, 17th, 19th and 23rd harmonics generated by the low frequency unit.

[0111] For example, Figure 3 As shown, the current harmonics of the mixed frequency parallel system of Si IGBT and SiC MOSFET are suppressed by the following three methods: (1) HFU adopts multiple quasi proportional resonance (mQPR) control to compensate the 3rd to 23rd harmonics generated by LFU; (2) LFU adopts selective harmonic elimination (SHE) PWM control to reduce the 3rd to 13th harmonics generated by itself, so as to reduce the capacity demand of HFU; (3) The grid-side LC filter filters out the 23rd to 256th harmonics generated by LFU and HFU. In a three-phase three-wire system under normal grid conditions, the harmonics of multiples of 3 in the output line voltage of the inverter bridge arm can be automatically offset, so this embodiment only focuses on 6k±1 (k=1,2,3,…) harmonics (it should be noted that in a three-phase symmetrical system of three-phase three-wire system, even harmonics and harmonics of integer multiples of three are not included).

[0112] For example, SHEPWM (Specific Harmonic Elimination Pulse Width Modulation) technology is a PWM strategy with application prospects in high-power low-switching frequency converters. This strategy uses the switching angle as a reference variable and selectively eliminates certain specific harmonics by calculating and reasonably selecting the switching moment position. SHEPWM technology can generate the optimal output voltage waveform at a lower switching frequency, thereby reducing current harmonics and improving control performance.

[0113] For example, Figure 4 The figure shows the voltage waveform of phase A output by the LFU bridge arm. The voltages of phases B and C lag behind phase A by 120° and 240° respectively. Figure 4 It can be seen that the voltage waveform of phase A output by the LFU bridge arm is an even function symmetrical about π / 2 and 3π / 2, and an odd function symmetrical about π. Due to the above symmetric relationship, the bridge arm switching angle only needs to be solved for the first 1 / 4 cycle, that is, α1, α2…α N There are N controllable switch angles in total. Since the phase voltage signal satisfies the Dirichlet condition, it can be expressed in Fourier series form:

[0114]

[0115] Wherein, ω′ is the fundamental angular frequency of the phase voltage signal, ω′=100π.

[0116] Due to the odd symmetry and 1 / 4 period symmetry of the phase voltage signal, the coefficients of the DC component, cosine component and even sine component in the Fourier decomposition are zero, that is:

[0117]

[0118] The odd-order sinusoidal component coefficients can be expressed as:

[0119]

[0120] Where n is the order of the fundamental wave and each harmonic, α k is the kth switching angle among the N switching angles in the interval [0,π / 2], and the size of each switching angle should satisfy the condition: 0°≤α1<α2…<α N ≤90°.

[0121] When there are N controllable switch angles, (N-1) harmonics can be eliminated through the SHEPWM strategy. To eliminate the 5th, 7th, 11th, and 13th harmonics, let there be 5 switch angles in 1 / 4 period (here, it is worth mentioning that by substituting the five switch angles into the Fourier function, the coefficients corresponding to the 5th, 7th, 11th, and 13th harmonics are calculated to be 0. Therefore, these harmonics can be suppressed), the following SHEPWM harmonic elimination equations can be written:

[0122]

[0123] In the formula, m is the modulation signal. By solving (11), the switching action time can be obtained. Figure 5 The switching angle trajectory obtained is shown in FIG. 1 as a function of the modulation signal m.

[0124] Furthermore, the Gaussian fitting method is used to fit the trajectory of the switching angle changing with the modulation signal. The general expression of n-dimensional Gaussian fitting is shown in formula (3).

[0125] In formula (3), n=3 is taken (here n=3 is taken as an example. The value of n depends on the specific situation. The larger n is, the more accurate the fitting effect is; the smaller n is, the simpler the fitted function expression is), and α1~α5 are fitted. The fitting curve is shown as follows: Figure 5 , the fitting coefficients are shown in Table 1.

[0126] Table 1 Fitting parameters of the switching angle trajectory changing with the modulation signal

[0127] <![CDATA[α1(m)]]> <![CDATA[α2(m)]]> <![CDATA[α3(m)]]> <![CDATA[α4(m)]]> <![CDATA[α5(m)]]> <![CDATA[a1]]> 21.3 3.191 40.41 5.435 59.54 <![CDATA[a2]]> 0 8.636 11.7 16.44 17.91 <![CDATA[a3]]> 3.937 20 3.576 40.48 5.673 <![CDATA[b1]]> -0.3641 1.144 -0.2299 1.108 -0.09161 <![CDATA[b2]]> 0.2745 0.989 0.9276 1.023 0.9769 <![CDATA[b3]]> 0.9583 0.1601 1.141 0.1932 1.105 <![CDATA[c1]]> 1.244 0.2337 1.235 0.1701 1.263 <![CDATA[c2]]> 0.0003583 0.5303 0.5762 0.4966 0.5182 <![CDATA[c3]]> 0.6273 1.217 0.2539 1.245 0.1828

[0128] For example, to verify the effectiveness of the present invention, the mixing system is simulated using the suppression method of the present invention. The simulation waveform is as follows: Figure 7 , 8The simulation parameters are shown in Table 2. Initially, only the main unit operates independently. At t=0.5s, the high-frequency unit is connected, and the two units operate jointly. Before the auxiliary unit is connected, the total output current waveform of the grid-connected converter is distorted and the harmonic content is high. After the high-frequency unit is connected, the output current THD (abbreviation of total harmonic distortion in English, which means total harmonic distortion in Chinese, is used to reflect the quality of the output current waveform. After using the mixed frequency parallel system, THD is reduced, indicating that the waveform quality is improved) content is reduced from 6.02% to 2.30%. It can be seen from the preliminary verification and comparative analysis of the simulation that the mixing system can achieve high efficiency and low cost effectively, maximize the advantages of power devices, and reduce the volume of passive filter components while improving the dynamic performance and power density of the system, increase the control bandwidth of the system, reduce the control complexity of the converter, and improve the output performance of the mixed frequency parallel system.

[0129] Table 2 Mixed frequency parallel system parameters

[0130] symbol meaning Numeric symbol meaning Numeric <![CDATA[V dc ]]> DC side voltage 1500V <![CDATA[L g ]]> Grid inductance 2mH <![CDATA[L f,L ]]> Low frequency unit filter 3.5mH <![CDATA[R g ]]> Grid resistance 0.5Ω <![CDATA[L f,H ]]> High frequency unit filter 1mH <![CDATA[C f ]]> Filter capacitor 15μF <![CDATA[f s,L ]]> Main unit switching frequency 1kHz <![CDATA[f s,H ]]> Auxiliary unit switching frequency 35kHz <![CDATA[i qref ]]> Q-axis rated current 0A <![CDATA[i gdref ]]> D-axis rated current 500A K Power allocation factor 0.75 <![CDATA[R d ]]> Damping resistor 5.5Ω

[0131] The method in this embodiment can be applied to a mixed frequency parallel system. Compared with the converter of all-SiC devices and the converter of all-Si devices, the mixed frequency parallel system achieves the beneficial effect of substantially the same conversion efficiency but greatly reducing its manufacturing cost. In terms of key parameter design, the selection of the power distribution ratio and switching frequency of the high / low frequency unit is crucial to maximizing the advantages of the mixed frequency parallel system. In terms of control strategy, the low frequency unit adopts specific harmonic elimination PWM control to reduce the 3rd to 13th harmonics generated by itself to reduce the capacity demand for the high frequency unit; the grid-side LC filter filters out the 23rd to 256th harmonics generated by the low frequency unit and the high frequency unit. Multiple quasi-proportional resonance mQPR control is adopted to compensate for the 3rd to 23rd harmonics generated by the low frequency unit; the purpose of compensating the low frequency current ripple generated by the low frequency unit by the high frequency unit is achieved, thereby increasing the frequency of the output current ripple and reducing the size and weight of the filter.

[0132] The above-mentioned harmonic current suppression method, device, computer equipment, computer-readable storage medium and computer program product are applied to a mixed frequency parallel system including a low-frequency unit and a high-frequency unit, and the first part of the harmonics generated by the low-frequency unit and the high-frequency unit are filtered out on the grid side; wherein the low-frequency unit includes: a converter based on Si IGBT, and the high-frequency unit includes: a converter based on SiC MOSFET; thereby, most of the harmonics generated by the low-frequency unit and the high-frequency unit can be eliminated on the grid side. The low-frequency unit is pulse-width modulated to reduce the second part of the harmonics generated by the low-frequency unit itself; thereby, the specific harmonics generated by the low-frequency unit can be effectively reduced. The high-frequency unit is subjected to multiple quasi-proportional resonance control, and the third part of the harmonics generated by the low-frequency unit is compensated. This can selectively eliminate certain specific harmonics, generate the optimal output voltage waveform at a lower switching frequency, significantly reduce current harmonics, achieve an effective balance between high efficiency and low cost, maximize the advantages of power devices, and reduce the size of passive filtering components while improving the dynamic performance and power density of the system. It increases the control bandwidth of the system, reduces the control complexity of the converter, and improves the output performance of the mixing system.

[0133] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0134] Based on the same inventive concept, the embodiment of the present application also provides a harmonic current suppression device for implementing the harmonic current suppression method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more harmonic current suppression device embodiments provided below can refer to the limitations of the harmonic current suppression method above, and will not be repeated here.

[0135] In an exemplary embodiment, Fig. 9 As shown, a harmonic current suppression device is provided, which is applied to a mixed frequency parallel system including a low frequency unit and a high frequency unit, and includes: a filtering module 901, a pulse width modulation module 902 and a resonance control and compensation module 903, wherein:

[0136] A filter module 901 is used to filter out the first part of harmonics generated by the low-frequency unit and the high-frequency unit on the grid side; wherein the low-frequency unit includes: a converter based on Si IGBT, and the high-frequency unit includes: a converter based on SiCMOSFET;

[0137] A pulse width modulation module 902 is used to perform pulse width modulation on the low frequency unit to reduce the second part of harmonics generated by the low frequency unit itself;

[0138] The resonance control and compensation module 903 is used to perform multiple quasi-proportional resonance control on the high-frequency unit and compensate for the third part of the harmonics generated by the low-frequency unit.

[0139] In one of the embodiments, the first part of harmonics includes: 23rd to 256th harmonics generated by the low frequency unit and the high frequency unit;

[0140] The second part of harmonics includes: 3rd to 13th harmonics generated by the low-frequency unit;

[0141] The third part of harmonics includes: 3rd to 23rd harmonics generated by the low-frequency unit.

[0142] In one embodiment, the filtering module 901 is specifically used for:

[0143] respectively determining harmonic frequencies generated by the low-frequency unit and the high-frequency unit;

[0144] The parameters of the grid-side LC filter are determined according to the harmonic frequencies generated by the low-frequency unit and the high-frequency unit, and the first part of the harmonics generated by the low-frequency unit and the high-frequency unit are filtered out by the LC filter.

[0145] In one embodiment, the pulse width modulation module 902 is specifically configured to:

[0146] Obtain five switching angles of the first 1 / 4 cycle of the phase voltage output by the low-frequency unit bridge arm;

[0147] Using the five switching angles as reference quantities, the switching angles of the A-phase, B-phase, and C-phase bridge arms of the low-frequency unit are determined respectively;

[0148] According to the switching angles of the A-phase, B-phase and C-phase bridge arms of the low-frequency unit, a first switching signal for controlling two power devices of the A-phase, B-phase and C-phase bridge arms is generated, wherein the on-off timing of the first switching signal is selected to eliminate the 5th, 7th, 11th and 13th harmonics generated by the low-frequency unit itself.

[0149] In one embodiment, the step of obtaining five switching angles of the first 1 / 4 cycle of the phase voltage output by the low-frequency unit bridge arm includes:

[0150] Determine the modulation signal amplitude and the modulation signal initial phase angle of the low frequency unit;

[0151] Determine the three-phase modulation signal of the low-frequency unit according to the modulation signal amplitude and the modulation signal initial phase angle;

[0152] The Gaussian fitting method is used to fit the trajectory of the switching angle of the phase voltage output by the low-frequency unit bridge arm changing with the three-phase modulation signal of the low-frequency unit, and five switching angles of the first 1 / 4 cycle of the phase voltage output by the low-frequency unit bridge arm are obtained.

[0153] In one embodiment, the resonance control and compensation module 903 is specifically used to:

[0154] respectively determining the three-phase modulation signals of the high-frequency unit;

[0155] A three-phase modulation signal of a high-frequency unit is processed using a sinusoidal pulse width modulation strategy or a space vector pulse width modulation strategy, and a second switching signal for a power device in the high-frequency unit is output. The on-off timing of the second switching signal is selected to compensate for the 5th, 7th, 11th, 13th, 17th, 19th, and 23rd harmonics generated by the low-frequency unit.

[0156] Each module in the above harmonic current suppression device can be implemented in whole or in part by software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module.

[0157] In an exemplary embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as shown in FIG. Fig.10 As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. The processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store control strategy data. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a harmonic current suppression method is implemented.

[0158] Those skilled in the art will understand that Fig.10 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0159] In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above-mentioned method embodiments when executing the computer program.

[0160] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0161] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0162] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0163] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0164] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0165] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A method for suppressing harmonic current, characterized in that: Applied to a mixed frequency parallel system including a low frequency unit and a high frequency unit, the method comprises: filtering out the first part of harmonics generated by the low-frequency unit and the high-frequency unit on the grid side; wherein the low-frequency unit comprises: a converter based on Si IGBT, and the high-frequency unit comprises: a converter based on SiC MOSFET; Performing pulse width modulation on the low-frequency unit to reduce the second part of harmonics generated by the low-frequency unit itself; The high frequency unit is subjected to multiple quasi-proportional resonance control, and the third part of harmonics generated by the low frequency unit is compensated.

2. The method according to claim 1, characterized in that The first part of harmonics includes: 23 to 256 harmonics generated by the low frequency unit and the high frequency unit; The second part of harmonics includes: 3rd to 13th harmonics generated by the low-frequency unit; The third part of harmonics includes: 3rd to 23rd harmonics generated by the low-frequency unit.

3. The method according to claim 1, characterized in that The filtering out the first part of harmonics generated by the low-frequency unit and the high-frequency unit on the grid side includes: respectively determining harmonic frequencies generated by the low-frequency unit and the high-frequency unit; The parameters of the grid-side LC filter are determined according to the harmonic frequencies generated by the low-frequency unit and the high-frequency unit, and the first part of the harmonics generated by the low-frequency unit and the high-frequency unit are filtered out by the LC filter.

4. The method according to claim 1, characterized in that: The pulse width modulation is performed on the low frequency unit to reduce the second part of harmonics generated by the low frequency unit itself, including: Obtain five switching angles of the first 1 / 4 cycle of the phase voltage output by the low-frequency unit bridge arm; Using the five switching angles as reference quantities, the switching angles of the A-phase, B-phase, and C-phase bridge arms of the low-frequency unit are determined respectively; According to the switching angles of the A-phase, B-phase and C-phase bridge arms of the low-frequency unit, a first switching signal for controlling two power devices of the A-phase, B-phase and C-phase bridge arms is generated, wherein the on-off timing of the first switching signal is selected to eliminate the 5th, 7th, 11th and 13th harmonics generated by the low-frequency unit itself.

5. The method according to claim 4, characterized in that The step of obtaining five switching angles of the first 1 / 4 cycle of the phase voltage output by the low-frequency unit bridge arm includes: Determine the modulation signal amplitude and the modulation signal initial phase angle of the low frequency unit; Determine the three-phase modulation signal of the low-frequency unit according to the modulation signal amplitude and the modulation signal initial phase angle; The Gaussian fitting method is used to fit the trajectory of the switching angle of the phase voltage output by the low-frequency unit bridge arm changing with the three-phase modulation signal of the low-frequency unit, and five switching angles of the first 1 / 4 cycle of the phase voltage output by the low-frequency unit bridge arm are obtained.

6. The method according to any one of claims 1 to 5, characterized in that: The performing multiple quasi-proportional resonance control on the high frequency unit comprises: respectively determining the three-phase modulation signals of the high-frequency unit; A three-phase modulation signal of a high-frequency unit is processed using a sinusoidal pulse width modulation strategy or a space vector pulse width modulation strategy, and a second switching signal for a power device in the high-frequency unit is output. The on-off timing of the second switching signal is selected to compensate for the 5th, 7th, 11th, 13th, 17th, 19th, and 23rd harmonics generated by the low-frequency unit.

7. A harmonic current suppression device, characterized in that: Applicable to a mixed frequency parallel system including a low frequency unit and a high frequency unit, the device comprises: A filtering module, used for filtering out the first part of harmonics generated by the low-frequency unit and the high-frequency unit on the grid side; wherein the low-frequency unit comprises: a converter based on SiIGBT, and the high-frequency unit comprises: a converter based on SiC MOSFET; A pulse width modulation module, used for performing pulse width modulation on the low frequency unit to reduce the second part of harmonics generated by the low frequency unit itself; The resonance control and compensation module is used to perform multiple quasi-proportional resonance control on the high-frequency unit and compensate for the third part of the harmonics generated by the low-frequency unit.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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