Voltage controlled oscillator circuit

Abstract

The invention provides a voltage-controlled oscillator circuit, and the circuit comprises a four-stage differential ring oscillator which is used for outputting a preset number of differential output signals with the same frequency in a clock period; a first end of the voltage-to-current module is electrically connected with a first power line, a second end is used for inputting a control signal, a third end is used for inputting an adjusting voltage, a current output end of the voltage-to-current module is electrically connected with a first input end of the four-stage differential ring oscillator, and the voltage-to-current module is used for providing a driving current for the four-stage differential ring oscillator; the clock signal input end of the driving circuit is electrically connected with the clock signal output end of the four-stage differential ring oscillator, and the driving circuit is used for performing alignment output on the differential output signals and improving the clock driving capability of the differential output signals. According to the circuit, the requirement of a chip for a high-speed clock when the chip works at high frequency is met, the power consumption of the chip in the using process is reduced, the performance of the chip is improved, and meanwhile the design area of the chip is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor chips, and in particular to a voltage-controlled oscillator circuit. Background Art

[0002] Voltage Controlled Oscillator (VCO) is a special electronic module that controls the oscillation frequency of the VCO output signal through Vcon (regulating voltage) to generate the periodic clock signal required by the chip. Due to the miniaturization of electronic products, the capacity of the battery is limited, so the power consumption of the VCO inside the chip is a problem, and energy cannot be consumed excessively. Due to the complexity of the functions of electronic products, the circuit modules required by the chip are also increasing, and the problem of power consumption is more prominent. As the number of functional modules of the chip increases without changing the design architecture, the area of ​​the chip will inevitably increase, which is inconsistent with the miniaturization of current electronic products. With the development of electronic technology, users have higher and higher requirements for the smoothness of human-computer interaction, which results in the frequency signal generated by the VCO not meeting the high frequency requirements of the chip during operation. Summary of the invention

[0003] The main purpose of the present application is to provide a voltage-controlled oscillator circuit to at least solve the problem that the voltage-controlled oscillator in the prior art cannot balance the three performance aspects of high frequency, low power consumption and small chip design area.

[0004] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a voltage-controlled oscillator circuit is provided, comprising: a four-stage differential ring oscillator, the four-stage differential ring oscillator is used to output a preset number of differential output signals of the same frequency within one clock cycle, and the phase shifts of two adjacent differential output signals are the same; a voltage-to-current module, the first end of the voltage-to-current module is electrically connected to the first power line, the second end of the voltage-to-current module is used to input a control signal, the third end of the voltage-to-current module is used to input a regulating voltage, the current output end of the voltage-to-current module is electrically connected to the first input end of the four-stage differential ring oscillator, and the voltage-to-current module is used to provide a driving current to the four-stage differential ring oscillator; a driving circuit, the clock signal input end of the driving circuit is electrically connected to the clock signal output end of the four-stage differential ring oscillator, and the driving circuit is used to align the differential output signals and improve the clock driving capability of the differential output signals.

[0005] Optionally, the four-stage differential ring oscillator includes four cascaded delay units, a pair of differential output signals output by the delay unit of the previous stage is a pair of differential input signals input by the delay unit of the next stage, a pair of differential input signals of the delay unit of the first stage is a pair of differential output signals of the delay unit of the last stage, a pair of differential input signals are respectively a first input clock signal and a second input clock signal, a pair of differential output signals are respectively a first output clock signal and a second output clock signal, a phase difference between the first input clock signal and the first output clock signal is 45°, and a phase difference between the second input clock signal and the second output clock signal is 45°.

[0006] Optionally, the delay unit includes: a first master delay structure, the first master delay structure is composed of multiple switching devices, and the input end of the first master delay structure is used to input the first input clock signal; a second master delay structure, the second master delay structure is composed of multiple switching devices, and the input end of the second master delay structure is used to input the second input clock signal; a first slave delay structure, the first slave delay structure is composed of multiple switching devices, the input end of the first slave delay structure is electrically connected to the output end of the first master delay structure, the output end of the first slave delay structure is electrically connected to the output end of the second master delay structure and is used to output the second output clock signal; a second slave delay structure, the second slave delay structure is composed of multiple switching devices, the input end of the second slave delay structure is electrically connected to the output end of the second master delay structure, the output end of the second slave delay structure is electrically connected to the output end of the first master delay structure and is used to output the first output clock signal.

[0007] Optionally, the first master delay structure, the second master delay structure, the first slave delay structure and the second slave delay structure are all composed of N basic delay structures connected in parallel, the first master delay structure and the second master delay structure have the same number of paths, the first slave delay structure and the second slave delay structure have the same number of paths, and the basic delay structure includes: a first switch device, a first end of the first switch device is used to be electrically connected to the current output end of the voltage-to-current module, and a control end of the first switch device is used to input a first control signal; a second switch device, a first end of the second switch device is electrically connected to the second end of the first switch device, and the control end of the first switch device is used to input a first control signal; A second switch device, the control end of which is used to be electrically connected to the input end of the basic delay structure, and the second end of the second switch device is used to be electrically connected to the output end of the basic delay structure; a third switch device, the first end of the third switch device is respectively electrically connected to the second end of the second switch device and the output end of the basic delay structure, and the control end of the third switch device is respectively electrically connected to the control end of the second switch device and the input end of the basic delay structure; a fourth switch device, the first end of the fourth switch device is electrically connected to the second end of the third switch device, the control end of the fourth switch device is used to input a second control signal, and the second end of the fourth switch device is grounded.

[0008] Optionally, the voltage-to-current module is composed of M optimized current mirror structures connected in parallel, and the optimized current mirror structure includes: a fifth switching device, a first end of the fifth switching device is electrically connected to the first power line, and a control end of the fifth switching device is used to input a third control signal; a resistance module, a first end of the resistance module is electrically connected to the second end of the fifth switching device; a sixth switching device, a first end of the sixth switching device is electrically connected to the second end of the resistance module, a control end of the sixth switching device is used to input the regulating voltage, and a second end of the sixth switching device is electrically connected to the first input end of the four-stage differential ring oscillator.

[0009] Optionally, the fifth switching device and the sixth switching device are both PMOS.

[0010] Optionally, the driving circuit includes an input circuit and an output circuit, and the input circuit of the driving circuit includes: a first switching unit, the first switching unit is composed of a plurality of switching devices, the first input end of the first switching unit is used to input the first output clock signal, the second input end of the first switching unit is used to input the second output clock signal, and the output end of the first switching unit is used to output the first output signal, the potential of the first output clock signal is opposite to the potential of the second output clock signal, and the potential of the first output signal is the same as the potential of the first output clock signal; a second switching unit, the second switching unit is composed of a plurality of switching devices, the first input end of the second switching unit is used to input the first output clock signal, the second input end of the second switching unit is used to input the second output clock signal, and the output end of the second switching unit is used to output the second output signal, and the potential of the second output signal is the same as the potential of the second output clock signal.

[0011] Optionally, the first switch unit includes: a seventh switch device, a first end of the seventh switch device is grounded, and a control end of the seventh switch device is used to input the first output clock signal; an eighth switch device, a first end of the eighth switch device is grounded, and a control end of the eighth switch device is used to input the second output clock signal, and a second end of the eighth switch device is used to output the first output signal; a ninth switch device, a first end of the ninth switch device, a control end of the ninth switch device and a second end of the seventh switch device are electrically connected, and a second end of the ninth switch device is electrically connected to a second power line; a tenth switch device, a first end of the tenth switch device is electrically connected to a second end of the eighth switch device, a control end of the tenth switch device is electrically connected to a control end of the ninth switch device, and a second end of the tenth switch device is electrically connected to the second power line.

[0012] Optionally, the second switch unit includes: an eleventh switch device, a first end of the eleventh switch device is grounded, and a control end of the eleventh switch device is used to input the second output clock signal; a twelfth switch device, a first end of the twelfth switch device is grounded, a control end of the twelfth switch device is used to input the first output clock signal, and a second end of the twelfth switch device is used to output the second output signal; a thirteenth switch device, a first end of the thirteenth switch device, a control end of the thirteenth switch device and a second end of the eleventh switch device are electrically connected, and a second end of the thirteenth switch device is electrically connected to a second power line; a fourteenth switch device, a first end of the fourteenth switch device is electrically connected to the second end of the twelfth switch device, a control end of the fourteenth switch device is electrically connected to the control end of the thirteenth switch device, and a second end of the fourteenth switch device is electrically connected to the second power line.

[0013] Optionally, the output circuit of the driving circuit includes: a first inverter, wherein the input end of the first inverter is used to input the first output signal; a second inverter, wherein the input end of the second inverter is used to input the second output signal; a third inverter, wherein the input end of the third inverter is electrically connected to the output end of the first inverter, and the output end of the third inverter is used to output the first target clock signal; a fourth inverter, wherein the input end of the fourth inverter is electrically connected to the output end of the second inverter, and the output end of the fourth inverter is used to output the second target clock signal; a fifth inverter, wherein the input end of the fifth inverter is electrically connected to the output end of the second inverter and the input end of the fourth inverter, respectively, and the output end of the fifth inverter is electrically connected to the output end of the first inverter and the input end of the third inverter, respectively; a sixth inverter, wherein the input end of the sixth inverter is electrically connected to the output end of the first inverter and the input end of the third inverter, respectively, and the output end of the sixth inverter is electrically connected to the output end of the second inverter and the input end of the fourth inverter, respectively.

[0014] Applying the technical solution of the present application, the above-mentioned voltage-controlled oscillator circuit includes a four-stage differential ring oscillator, wherein the four-stage differential ring oscillator is used to output a preset number of differential output signals of the same frequency within one clock cycle, and the phase shifts of two adjacent differential output signals are the same; a voltage-to-current module, wherein a first end of the voltage-to-current module is electrically connected to a first power line, a second end of the voltage-to-current module is used to input a control signal, a third end of the voltage-to-current module is used to input a regulating voltage, a current output end of the voltage-to-current module is electrically connected to a first input end of the four-stage differential ring oscillator, and the voltage-to-current module is used to provide a driving current to the four-stage differential ring oscillator; and a driving circuit, wherein a clock signal input end of the driving circuit is electrically connected to a clock signal output end of the four-stage differential ring oscillator, and the driving circuit is used to align the differential output signals and improve the clock driving capability of the differential output signals. This circuit solves the chip's need for a high-speed clock when operating at a high frequency, greatly improving the chip's efficiency when sampling data, which is equivalent to increasing the chip's clock frequency at work, and reducing the chip's power consumption during use, thereby improving the chip's performance and reducing the chip's design area. This solves the problem in the prior art that the voltage-controlled oscillator cannot balance the three performance aspects of high frequency, low power consumption, and small chip design area. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0016] Figure 1 A schematic structural diagram of a voltage-controlled oscillator circuit provided in an embodiment of the present application is shown;

[0017] Figure 2 A schematic structural diagram of a four-stage differential ring oscillator provided in an embodiment of the present application is shown;

[0018] Figure 3 A schematic structural diagram of a delay unit provided in an embodiment of the present application is shown;

[0019] Figure 4 A schematic structural diagram of a basic delay structure provided in an embodiment of the present application is shown;

[0020] Figure 5 A schematic structural diagram of a multi-channel basic delay structure provided in an embodiment of the present application is shown;

[0021] Figure 6 A schematic structural diagram of an optimized current mirror structure provided in an embodiment of the present application is shown;

[0022] Figure 7 A schematic structural diagram of a multi-channel optimized current mirror structure provided in an embodiment of the present application is shown;

[0023] Figure 8 A schematic structural diagram of an input circuit of a driving circuit provided in an embodiment of the present application is shown;

[0024] Fig. 9 A schematic structural diagram of an output circuit of a driving circuit provided in an embodiment of the present application is shown;

[0025] Fig.10 A schematic structural diagram of another voltage-controlled oscillator circuit provided in an embodiment of the present application is shown.

[0026] The above drawings include the following reference numerals:

[0027] 10. Four-stage differential ring oscillator; 11. Basic delay structure; 20. Voltage-to-current module; 21. Optimized current mirror structure; 30. Driving circuit; 31. First switch unit; 32. Second switch unit; D1. First delay unit; D2. Second delay unit; D3. Third delay unit; D4. Fourth delay unit; a1. First master delay structure; a2. Second master delay structure; b1. First slave delay structure; b2. Second slave delay structure; PM1. First switch device; PM2. Second switch device; NM1. Third switch device; NM2, the fourth switch device; PM31, the fifth switch device; Res, the resistance module; PM32, the sixth switch device; NM4, the seventh switch device; NM5, the eighth switch device; PM4, the ninth switch device; PM5, the tenth switch device; NM6, the eleventh switch device; NM7, the twelfth switch device; PM6, the thirteenth switch device; PM7, the fourteenth switch device; a3, the first inverter; a4, the second inverter; a5, the third inverter; a6, the fourth inverter; b3, the fifth inverter; b4, the sixth inverter. DETAILED DESCRIPTION

[0028] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0029] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0030] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0031] As introduced in the background technology, all chips require a stable periodic signal, such as the clock signal required inside the chip. In addition to accessing the periodic signal from the outside, the chip can also generate a periodic signal inside the chip. In the prior art, due to the miniaturization of electronic products, the capacity improvement of the battery is limited, and the power consumption problem of the VCO inside the chip arises. Energy cannot be consumed excessively, and due to the complexity of the functions of electronic products, the circuit modules required for the chip are also increasing, and the power consumption problem is more prominent. The increase in the number of functional modules of the chip will inevitably increase the area of ​​the chip without changing the design architecture. In order to solve the problem that the voltage-controlled oscillator in the prior art cannot balance the three aspects of high frequency, low power consumption and small chip design area, the embodiment of the present application provides a voltage-controlled oscillator circuit.

[0032] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0033] Figure 1 is a schematic diagram of the structure of a voltage-controlled oscillator circuit according to an embodiment of the present application. Figure 1 As shown, the voltage-controlled oscillator circuit includes: a four-stage differential ring oscillator 10, the four-stage differential ring oscillator 10 is used to output a preset number of differential output signals of the same frequency within one clock cycle, and the phase shifts of two adjacent differential output signals are the same; a voltage-to-current module 20, the first end of the voltage-to-current module 20 is electrically connected to the first power line, the second end of the voltage-to-current module 20 is used to input a control signal, the third end of the voltage-to-current module 20 is used to input a regulating voltage, the current output end of the voltage-to-current module 20 is electrically connected to the first input end of the four-stage differential ring oscillator 10, and the voltage-to-current module 20 is used to provide a driving current to the four-stage differential ring oscillator 10; a driving circuit 30, the clock signal input end of the driving circuit 30 is electrically connected to the clock signal output end of the four-stage differential ring oscillator 10, and the driving circuit 30 is used to align the differential output signals and improve the clock driving capability of the differential output signals.

[0034] The voltage-controlled oscillator circuit of the present application comprises a four-stage differential ring oscillator, wherein the four-stage differential ring oscillator is used to output a preset number of differential output signals of the same frequency within one clock cycle, and the phase shifts of two adjacent differential output signals are the same; a voltage-to-current module, wherein the first end of the voltage-to-current module is electrically connected to the first power line, the second end of the voltage-to-current module is used to input a control signal, the third end of the voltage-to-current module is used to input an adjustment voltage, the current output end of the voltage-to-current module is electrically connected to the first input end of the four-stage differential ring oscillator, and the voltage-to-current module is used to provide a driving current to the four-stage differential ring oscillator; and a driving circuit, wherein the clock signal input end of the driving circuit is electrically connected to the clock signal output end of the four-stage differential ring oscillator, and the driving circuit is used to align the output of the differential output signals and improve the clock driving capability of the differential output signals. This circuit solves the chip's need for a high-speed clock when operating at a high frequency, greatly improving the chip's efficiency when sampling data, which is equivalent to increasing the chip's clock frequency at work, and reducing the chip's power consumption during use, thereby improving the chip's performance and reducing the chip's design area. This solves the problem in the prior art that the voltage-controlled oscillator cannot balance the three performance aspects of high frequency, low power consumption, and small chip design area.

[0035] Among them, since a byte of electronic data is 8 bits, a clock signal is required for each bit of data during serial transmission. Under the same data transmission rate, the smaller the number of stages, the greater the requirements for circuit design. On the contrary, the larger the number of stages, the more devices are used, and the mutual parasitic effects between devices will also increase, which will increase the complexity of the design. A byte has 8 bits, and the divisors of 8 are 1, 2, 4, and 8. The first stage cannot form an oscillation, but the second stage can form an oscillation, with low utilization rate. The eight-stage stage has many stages and a large area, which is not easy to match, so this design uses a four-stage structure. The four-stage structure can generate 4 sets of differential co-frequency clock signals in one cycle, and one byte, that is, 8 bits of data, can be sampled in two cycles, which improves the clock sampling speed and reduces the design difficulty.

[0036] The clock frequency of the circuit is in a contradictory relationship with the power consumption. The higher the clock frequency, the greater the power consumption of the circuit. In the prior art, the circuit often uses only one clock signal output by the VCO. The higher the frequency, the greater the power consumption. However, this embodiment uses four pairs of differential clock signals output by the VCO to sample data. At the same data transmission rate, this embodiment can use one-fourth of the clock, thereby achieving the effect of reducing power consumption.

[0037] In some instances, such as Figure 2As shown, the four-stage differential ring oscillator includes four cascaded delay units, namely, a first delay unit D1, a second delay unit D2, a third delay unit D3 and a fourth delay unit D4, a pair of the differential output signals output by the previous delay unit is a pair of differential input signals input by the next delay unit, a pair of the differential input signals of the first delay unit is a pair of differential output signals of the last delay unit, a pair of differential input signals are a first input clock signal and a second input clock signal, a pair of differential output signals are a first output clock signal and a second output clock signal, a phase difference between the first input clock signal and the first output clock signal is 45°, and a phase difference between the second input clock signal and the second output clock signal is 45°.

[0038] The delay unit can adjust the delay time of the circuit by controlling the level of the input signal to charge and discharge the parasitic capacitor, thereby achieving the delay effect and generating the clock frequency required by the circuit.

[0039] Each stage of the four-stage differential ring oscillator must be matched well, that is, the position of each stage of the four-stage differential ring oscillator must be close, the direction of the devices must be consistent, the connections between them must be consistent, and the surrounding environment must be as consistent as possible. Only in this way can we ensure that the output high-speed clock signals are in step with each other and the phase difference is 45 degrees. The four-stage differential ring oscillator has a total of 4 delay_cells. In order to achieve the best matching effect, first design a delay_cell, and then the other three delay cells reuse this delay_cell. Figure 2 As shown, D1, D2, D3 and D4 are the same module, which is reused 4 times to ensure that the duration of the high and low levels of the clock signal is the same.

[0040] Each delay unit has a pair of differential input signals and a pair of differential output signals; the phase shift between the input signal and the output signal of each delay unit is 45 degrees; each delay unit needs a control signal to control the speed of the delay, that is, the delay unit can determine the frequency of the generated clock signal. The clock used in high frequency can control the delay to be faster, and the power consumption will also increase; the slow delay is the clock used in low frequency applications, which can achieve the effect of reducing power consumption. Among them, the MOS tubes selected in the delay unit are of equal width, which is conducive to source and drain sharing to reduce the chip design area.

[0041] The above embodiment adopts the architecture of a four-stage differential ring oscillator. Each stage has a pair of differential input signals and a pair of differential output signals. The output of the first stage is reversely connected to the input of the second stage, the output of the second stage is reversely connected to the input of the third stage, the output of the third stage is reversely connected to the input of the fourth stage, and the output of the fourth stage is directly connected to the input of the first stage. The differential input signal pair is phase-shifted by 180 degrees (that is, in reverse), and each stage is phase-shifted by 45 degrees. Eight high-speed clock signals with the same frequency and a phase shift of 45 degrees can be generated in one clock cycle. This embodiment solves the demand for high-speed clocks when the chip works at high frequencies. Each stage uses the same delay_cell (delay unit), and the four delay_cell (delay unit) layouts can be reused to make the physical structure matching performance of the chip better. In addition to a pair of differential input signals and a pair of differential output signals, each delay_cell (delay unit) also has a power supply signal, a ground signal and some control signals. When the four-stage differential ring oscillator works at high frequency, the IRDrop (voltage drop) of the power supply and ground signal has a great influence on the performance of the VCO (Voltage Controlled Oscillator). Therefore, the power supply and ground signal lines of this embodiment should use high-layer thick metal connections. The control signal is used to control the access module of the delay_cell (delay unit), so as to achieve the effect of reducing the power consumption of the chip. The differential input and output make the differential signal pairs of input and output naturally reverse, the input differential signal phase is reversed (phase shifted 180 degrees), and the output differential signal pair is also reversed (phase shifted 180 degrees). This embodiment adopts a four-stage loop to design each stage of the output signal phase shifted 45 degrees according to the formula 360° / 2N (N=4). In this way, within one clock cycle, the VCO (Voltage Controlled Oscillator) can provide the chip with 8 groups of high-speed clock signals of the same frequency with a phase shift of 45 degrees, which greatly improves the efficiency of the chip when sampling data, which is equivalent to increasing the clock frequency of the chip at work.

[0042] In some instances, such as Figure 3As shown, the delay unit includes: a first master delay structure a1, the first master delay structure a1 is composed of a plurality of switch devices, the input end of the first master delay structure a1 is used to input the first input clock signal, that is, the input end of the first master delay structure a1 is the i port of the delay unit; a second master delay structure a2, the second master delay structure a2 is composed of a plurality of switch devices, the input end of the second master delay structure a2 is used to input the second input clock signal, that is, the input end of the second master delay structure is the ib port of the delay unit; a first slave delay structure b1, the first slave delay structure b1 is composed of a plurality of switch devices, the first slave delay structure The input end of the structure b1 is electrically connected to the output end of the above-mentioned first master delay structure a1, and the output end of the above-mentioned first slave delay structure b1 is electrically connected to the output end of the above-mentioned second master delay structure a2 and is used to output the above-mentioned second output clock signal, that is, it is connected to the qb port of the delay unit; the second slave delay structure b2, the above-mentioned second slave delay structure b2 is composed of a plurality of switching devices, the input end of the above-mentioned second slave delay structure b2 is electrically connected to the output end of the above-mentioned second master delay structure a2, and the output end of the above-mentioned second slave delay structure b2 is electrically connected to the output end of the above-mentioned first master delay structure a1 and is used to output the above-mentioned first output clock signal, that is, it is connected to the q port of the delay unit.

[0043] Among them, Figure 3 As shown, i and ib are differential input signals, and q and qb are differential output signals. Delay units a1 and a2 receive differential input signals i and ib, and output differential signals q and qb. The input signal i and the output signal q have a phase difference of 45 degrees, and the input signal ib and the output signal qb have a phase difference of 45 degrees. According to the start-up requirements of the ring oscillator, the input and output of the main delay structures a1 and a2 must be reversed, and the input and output of the slave delay structures b1 and b2 must also reversely align the output signals. The delay unit uses differential input and differential output, and uses an axisymmetric design scheme. The main delay structures a1 and a2 are multiplexed units, and the slave delay structures b1 and b2 are also multiplexed units.

[0044] In some instances, such as Figure 4As shown, the first main delay structure a1, the second main delay structure a2, the first slave delay structure b1 and the second slave delay structure b2 are all composed of N-path parallel basic delay structures 11, the first main delay structure a1 and the second main delay structure a2 have the same number of paths, the first slave delay structure b1 and the second slave delay structure b2 have the same number of paths, and the basic delay structure 11 includes: a first switch device PM1, a first end of the first switch device PM1 is used to be electrically connected to the current output end of the voltage-to-current module 20, and a control end of the first switch device PM1 is used to input a first control signal; a second switch device PM2, a first end of the second switch device PM2 is electrically connected to the second end of the first switch device PM1, and the second switch The control end of the device PM2 is used to be electrically connected to the input end of the above-mentioned basic delay structure 11, and the second end of the above-mentioned second switching device PM2 is used to be electrically connected to the output end of the above-mentioned basic delay structure 11; the third switching device NM1, the first end of the above-mentioned third switching device NM1 is respectively electrically connected to the second end of the above-mentioned second switching device PM2 and the output end of the above-mentioned basic delay structure 11, and the control end of the above-mentioned third switching device NM1 is respectively electrically connected to the control end of the above-mentioned second switching device PM2 and the input end of the above-mentioned basic delay structure 11; the fourth switching device NM2, the first end of the above-mentioned fourth switching device NM2 is electrically connected to the second end of the above-mentioned third switching device NM1, the control end of the above-mentioned fourth switching device NM2 is used to input the second control signal, and the second end of the above-mentioned fourth switching device NM2 is grounded.

[0045] Among them, under the premise of considering the chip performance, the design area of ​​the chip is also optimized to a certain extent. The bottom layers of the master delay structure a1, a2 and the slave delay structure b1 and b2 use the same Base delay structure, such as Figure 4 As shown. The first switch device PM1 and the second switch device PM2 are both PMOS, and the third switch device NM1 and the fourth switch device NM2 are both NMOS. PM1 and PM2 are connected in series, and NM1 and NM2 are connected in series. The S (Source) terminal of PM1 is connected to the power supply VDD2, and the S (Source) terminal of NM2 is connected to the power supply GND2. PM1 and NM2 are switch tubes, the G (gate) terminal of PM1 is connected to the control signal s_pb1, and the G (gate) terminal of NM2 is connected to the control signal s_nb1, which controls whether the Base (base) delay structure is connected. PM2 and NM1 form an inverter structure, the G (Gate) terminal of PM2 is connected to the G (Gate) terminal of NM1 to input the signal in, and the D (Drain) terminal of PM2 is connected to the D (Drain) terminal of NM1 to output the signal out. The output signal out is opposite to the input signal in (phase shifted by 180 degrees), forming a ring oscillator.

[0046] In addition, the basic delay structure of multiple parallel connections is as follows Figure 5 As shown, control signals s_pb1 to s_pbn connect each PMOS (P-channel Metal Oxide Semiconductor) switch tube. Each input signal in is connected together, and each output signal out is connected together. Control signals s_nb1 to s_nbn connect each NMOS (N-channel Metal Oxide Semiconductor) switch tube. The access of each Base (base) delay structure is controlled by control signals s_pb1...s_pbn and s_nb1...s_nbn. A larger inverter structure is formed to control the frequency of the oscillation signal output by the VCO (Voltage Controlled Oscillator) at the source. a1 and a2 must be the same, and b1 and b2 must be the same, so that the duration of the high and low levels of the generated clock signal will be consistent. a1, a2 and b1, b2 can be different, and the same structure is used to match the physical layout of the device. If the devices are of the same size and structure, the matching will be better.

[0047] In addition, the access of the basic delay structure is determined by the discrimination signal received by the chip. The delay structure composed of the basic delay structure is always connected, but some basic delay structures will be turned off according to demand. When the front end detects that it is a low-frequency application (such as displaying a picture), the control signals s_pb1...s_pbn and s_nb1...s_nbn of the switch tube do not have to be turned on. When the front end detects that it is a high-frequency application (such as displaying high-definition and smooth video), the control signals s_pb1...s_pbn and s_nb1...s_nbn of the switch tube will be turned on more, or even all of them.

[0048] In some instances, such as Figure 6 As shown, the voltage-to-current module is composed of M optimized current mirror structures 21 connected in parallel, and the optimized current mirror structure 21 includes: a fifth switch device PM31, a first end of the fifth switch device PM31 is electrically connected to the first power line, and a control end of the fifth switch device PM31 is used to input a third control signal; a resistor module Res, a first end of the resistor module Res is electrically connected to a second end of the fifth switch device PM31; a sixth switch device PM32, a first end of the sixth switch device PM32 is electrically connected to a second end of the resistor module Res, a control end of the sixth switch device PM32 is used to input the adjustment voltage, and a second end of the sixth switch device PM32 is electrically connected to a first input end of the four-stage differential ring oscillator 10.

[0049] The energy (power supply VDD2) of the four-stage differential ring oscillator comes from the output Icon of the v2i (voltage-to-current) module controlled by Vcon (regulation voltage). The v2i (voltage-to-current) module is composed of multiple current mirror-like structures. The current mirror-like structure of v2i is shown in Figure 6 As shown. PM31 is connected to PM32 through a resistor, the S (Source) terminal of PM31 is connected to the power supply VDD1, and the G (Gate) terminal of PM31 is connected to the control signal s_pa1 to control whether the current mirror structure is connected. The G (Gate) terminal of PM32 is connected to Vcon (regulation voltage), and the D (Drain) terminal of PM32 is used as the output of the v2i (Voltage-to-Current) module. The output of each channel is connected together and the signal is defined as Icon. The output signal Icon of the v2i (Voltage-to-Current) module is connected to the power supply VDD2 of the four-stage differential ring oscillator to provide it with energy.

[0050] In addition, the v2i (voltage-to-current) module is composed of multiple current mirror structures. Figure 7 As shown. Each current mirror-like structure is accessed by the PM31 switch tube, and the resistor Res adjusts the overdrive voltage Vgs-Vth (gate-source voltage-threshold voltage) of each amplifier tube PM32. The G (Gate) terminals of each PM32 are connected together, and this node is defined as Vcon (adjustment voltage). The D (Drain) terminals of each PM32 are connected together, and this node is defined as Icon (output current). Vcon (adjustment voltage) adjusts the output signal Icon of the v2i (Voltage-to-Current) module to control the four-stage differential ring oscillator to output a periodic oscillation signal.

[0051] In some instances, such as Figure 6 As shown, the fifth switching device PM31 and the sixth switching device PM32 are both PMOS.

[0052] The Vcon (regulation voltage) of the VCO (voltage controlled oscillator) controls the energy supply of the power supply to the four-stage differential ring oscillator through the G (gate) terminal of the PMOS (P-channel Metal Oxide Semiconductor) tube. The PMOS (P-channel Metal Oxide Semiconductor) tube to which the Vcon (regulation voltage) is connected adopts a multiplexing form, and the VCO (voltage controlled oscillator) can be adjusted at any time. In the low-frequency application of the chip, the clock frequency can be directly reduced at the source of the clock signal, thereby reducing the energy consumption of the chip.

[0053] In some embodiments, the driving circuit includes an input circuit and an output circuit, such as Figure 8 As shown, the input circuit of the above-mentioned driving circuit includes: a first switch unit 31, the above-mentioned first switch unit 31 is composed of a plurality of switch devices, the first input end of the above-mentioned first switch unit 31 is used to input the above-mentioned first output clock signal, the second input end of the above-mentioned first switch unit 31 is used to input the above-mentioned second output clock signal, the output end of the above-mentioned first switch unit 31 is used to output the first output signal, the potential of the above-mentioned first output clock signal is opposite to the potential of the above-mentioned second output clock signal, and the potential of the above-mentioned first output signal is the same as the potential of the above-mentioned first output clock signal; a second switch unit 32, the above-mentioned second switch unit 32 is composed of a plurality of switch devices, the first input end of the above-mentioned second switch unit 32 is used to input the above-mentioned first output clock signal, the second input end of the above-mentioned second switch unit 32 is used to input the above-mentioned second output clock signal, and the output end of the above-mentioned second switch unit 32 is used to output the second output signal, and the potential of the above-mentioned second output signal is the same as the potential of the above-mentioned second output clock signal.

[0054] The output of the four-stage differential ring oscillator of this embodiment is composed of the differential input signal of each stage (also the differential output signal of each stage), a total of 8 (4 pairs of differential signals) oscillation signals of the same frequency and phase shifted by 45 degrees, forming the clock signal required by the chip. The output clock signals are ckp0, ckn0, ckp45, ckn45, ckp90, ckn90, ckp135, ckn135. ckp0 and ckn0 are a pair of differential signals, ckp45 and ckn45 are a pair of differential signals, ckp90 and ckn90 are a pair of differential signals, and ckp135 and ckn135 are a pair of differential signals. ckp180 feedback is connected to ckn0, and ckn180 feedback is connected to ckp0. The entire loop constitutes a positive feedback and meets the starting condition AF>=1 (loop gain is greater than or equal to 1).

[0055] Since the driving capability of the eight oscillation signals directly output by the four-stage differential ring oscillator is generally poor, they cannot be directly used as the clock signal of the chip. This embodiment designs an axisymmetric driving circuit to make the four pairs of differential oscillation signals have stronger clock driving capability.

[0056] In some instances, such as Figure 8 As shown, the first switch unit 31 includes: a seventh switch device NM4, a first end of the seventh switch device NM4 is grounded, and a control end of the seventh switch device NM4 is used to input the first output clock signal; an eighth switch device NM5, a first end of the eighth switch device NM5 is grounded, a control end of the eighth switch device NM5 is used to input the second output clock signal, and a second end of the eighth switch device NM5 is used to output the first output signal; a ninth switch device PM4, a first end of the ninth switch device PM4, a control end of the ninth switch device PM4 is electrically connected to the second end of the seventh switch device NM4, and a second end of the ninth switch device PM4 is electrically connected to the second power line; a tenth switch device PM5, a first end of the tenth switch device PM5 is electrically connected to the second end of the eighth switch device NM5, a control end of the tenth switch device PM5 is electrically connected to the control end of the ninth switch device PM4, and a second end of the tenth switch device PM5 is electrically connected to the second power line.

[0057] The seventh switch device NM4 and the eighth switch device NM5 are both NMOS, and the ninth switch device PM4 and the tenth switch device PM5 are both PMOS.

[0058] In some instances, such as Figure 8As shown, the second switch unit 32 includes: an eleventh switch device NM6, a first end of the eleventh switch device NM6 is grounded, and a control end of the eleventh switch device NM6 is used to input the second output clock signal; a twelfth switch device NM7, a first end of the twelfth switch device NM7 is grounded, a control end of the twelfth switch device NM7 is used to input the first output clock signal, and a second end of the twelfth switch device NM7 is used to output the second output signal; a thirteenth switch device PM6, a first end of the thirteenth switch device PM6, a control end of the thirteenth switch device PM6 is electrically connected to the second end of the eleventh switch device NM6, and a second end of the thirteenth switch device PM6 is electrically connected to the second power line; a fourteenth switch device PM7, a first end of the fourteenth switch device PM7 is electrically connected to the second end of the twelfth switch device NM7, a control end of the fourteenth switch device PM7 is electrically connected to the control end of the thirteenth switch device PM6, and a second end of the fourteenth switch device PM7 is electrically connected to the second power line.

[0059] The eleventh switch device NM6 and the twelfth switch device NM7 are both NMOS, and the thirteenth switch device PM6 and the fourteenth switch device PM7 are both PMOS.

[0060] Among them, inputs ina and inb are connected to a pair of differential oscillation signals output by the four-stage differential ring oscillator. When ina is at a high potential, inb is connected to a low potential. At this time, NM4 and NM7 are turned on, and NM5 and NM6 are turned off. When NM4 is turned on, PM4 will also be turned on. Since PM4 and PM5 are in a mirror relationship, PM5 will also be turned on. When NM6 is turned off, PM6 will also be turned off. Since PM6 and PM7 are in a mirror relationship, PM7 will also be turned off. As a result, NM5 is turned off, PM5 is turned on, and the output signal Inap is a high level. NM7 is turned on, PM7 is turned off, and the output signal Inbp is a low level. On the contrary, if ina is at a low potential, inb is connected to a high potential. Then NM5 is turned on, PM5 is turned off, and the output signal Inap is a low level. NM7 is turned off, PM7 is turned on, and the output signal Inbp is a high level. Signals Inap and Inbp improve the driving capability of the oscillation circuit.

[0061] In some instances, such as Fig. 9As shown, the output circuit of the driving circuit includes: a first inverter a3, the input end of the first inverter a3 is used to input the first output signal; a second inverter a4, the input end of the second inverter a4 is used to input the second output signal; a third inverter a5, the input end of the third inverter a5 is electrically connected to the output end of the first inverter a3, and the output end of the third inverter a5 is used to output the first target clock signal; a fourth inverter a6, the input end of the fourth inverter a6 is electrically connected to the output end of the second inverter a4, and the output end of the fourth inverter a6 is used to output the second target clock signal. a fifth inverter b3, wherein the input end of the fifth inverter b3 is electrically connected to the output end of the second inverter a4 and the input end of the fourth inverter a6, respectively, and the output end of the fifth inverter b3 is electrically connected to the output end of the first inverter a3 and the input end of the third inverter a5, respectively; a sixth inverter b4, wherein the input end of the sixth inverter b4 is electrically connected to the output end of the first inverter a3 and the input end of the third inverter a5, respectively, and the output end of the sixth inverter b4 is electrically connected to the output end of the second inverter a4 and the input end of the fourth inverter a6, respectively.

[0062] The output structure of the driving circuit is composed of 6 inv (inverter). Input in8 is connected to Inap of the driving input structure, and input in8b is connected to Inbp of the driving input structure. Signal in8 reaches the output end out8 through a3 and a5, and signal in8b reaches the output end out8b through a4 and a6. b3 and b4 form a latch structure to align the differential clock signal for output.

[0063] In some embodiments, the specific circuit diagram of the voltage controlled oscillator circuit is as follows: Fig.10As shown, the control signals corresponding to the four delay_cells are connected together to form signals sa_pb<1:n>, sa_nb<1:n>, sb_pb<1:n> and sb_nb<1:n>. sa_pb<1:n> and sa_nb<1:n> are control signals of the master delay structure, and sb_pb<1:n> and sb_nb<1:n> are control signals of the slave delay structure. s_pa<1:n> is a control signal of a multi-channel current mirror module. The present invention improves the operating frequency of the chip by designing a clock signal that can generate 8 clock signals of the same frequency with a phase shift of 45 degrees in one clock cycle and sampling 8 data signals in one clock cycle. This design uses logic signals sa_pb<1:n>, sa_nb<1:n>, sb_pb<1:n> and sb_nb<1:n> to control the output frequency of vco_core (four-stage differential ring oscillator), thereby achieving the effect of reducing power consumption. This design uses Vcon (adjusting voltage) to adjust the output signal Icon of v2i (voltage-to-current), so that the frequency output of vco_core (four-stage differential ring oscillator) is more stable and accurate, and the reliability of the chip's clock signal is improved. This design uses transistors of equal width and minimum length, while reducing effects such as STI (Shallow Trench Isolation) and WPE (Well Proximity Effect), it improves the performance of the chip and reduces the design area of ​​the chip.

[0064] Among them, the above embodiment is a core module VCO (Voltage Controlled Oscillator) chip of PLL (Phase Locked Loop) in serial SerDes (SERializer-DESerializer) communication technology widely used in mainstream TDM (Time Division Multiplexing) and P2P (Point-to-Point) communication technologies. A chip has different requirements for clock frequency in different working modes, and the higher the frequency, the greater the power consumption. This embodiment selectively turns on and off the PMOS (P-channel Metal Oxide Semiconductor) tube controlled by Vcon (regulating voltage). In addition to the highest frequency working mode, the chip reduces the clock frequency of the chip by turning off the switch tube. Instead of reducing the frequency through the commonly used DIV (Divider). The present invention reduces the power consumption of the chip during use. In addition, the CMOS (Complementary Metal-Oxide-Semiconductor Transistor) tube in the circuit of this embodiment adopts a minimum length, equal width, and source-drain shared structure. The influence of STI (Shallow Trench Isolation) and WPE (Well Proximity Effect) on the chip is avoided. The present invention improves the performance of the chip and reduces the chip design area at the same time.

[0065] This embodiment uses a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) tube with the minimum length and consistent width in the device selection. The S (Source) and D (Drain) of such a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) tube can be shared, and dummy (virtual CMOS) tubes can be added on both sides. The chip designed with this structure occupies the smallest area and has the best matching. The use of source-drain sharing can also reduce the impact of STI (Shallow Trench Isolation) and WPE (Well Proximity Effect) and other effects on this design module. This design reduces the resistance used in the chip and further reduces the design area of ​​the chip.

[0066] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0067] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0068] 1) The voltage-controlled oscillator circuit of the present application includes a four-stage differential ring oscillator, which is used to output a preset number of differential output signals of the same frequency within one clock cycle, and the phase shifts of two adjacent differential output signals are the same; a voltage-to-current module, wherein the first end of the voltage-to-current module is electrically connected to the first power line, the second end of the voltage-to-current module is used to input a control signal, the third end of the voltage-to-current module is used to input an adjustment voltage, the current output end of the voltage-to-current module is electrically connected to the first input end of the four-stage differential ring oscillator, and the voltage-to-current module is used to provide a driving current to the four-stage differential ring oscillator; a driving circuit, wherein the clock signal input end of the driving circuit is electrically connected to the clock signal output end of the four-stage differential ring oscillator, and the driving circuit is used to align the differential output signals and improve the clock driving capability of the differential output signals. This circuit solves the chip's need for a high-speed clock when operating at a high frequency, greatly improving the chip's efficiency when sampling data, which is equivalent to increasing the chip's clock frequency at work, and reducing the chip's power consumption during use, thereby improving the chip's performance and reducing the chip's design area. This solves the problem in the prior art that the voltage-controlled oscillator cannot balance the three performance aspects of high frequency, low power consumption, and small chip design area.

[0069] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A voltage-controlled oscillator circuit, characterized in that: include: A four-stage differential ring oscillator, wherein the four-stage differential ring oscillator is used to output a preset number of differential output signals of the same frequency within one clock cycle, and the phase shifts of two adjacent differential output signals are the same; a voltage-to-current module, wherein a first end of the voltage-to-current module is electrically connected to a first power line, a second end of the voltage-to-current module is used to input a control signal, a third end of the voltage-to-current module is used to input a regulating voltage, a current output end of the voltage-to-current module is electrically connected to a first input end of the four-stage differential ring oscillator, and the voltage-to-current module is used to provide a driving current to the four-stage differential ring oscillator; A driving circuit, wherein a clock signal input terminal of the driving circuit is electrically connected to a clock signal output terminal of the four-stage differential ring oscillator, and the driving circuit is used to align the output of the differential output signal and improve the clock driving capability of the differential output signal.

2. The oscillator circuit according to claim 1, characterized in that The four-stage differential ring oscillator includes four cascaded delay units, a pair of differential output signals output by the delay unit of the previous stage is a pair of differential input signals input by the delay unit of the next stage, a pair of differential input signals of the delay unit of the first stage is a pair of differential output signals of the delay unit of the last stage, a pair of differential input signals are respectively a first input clock signal and a second input clock signal, a pair of differential output signals are respectively a first output clock signal and a second output clock signal, a phase difference between the first input clock signal and the first output clock signal is 45°, and a phase difference between the second input clock signal and the second output clock signal is 45°.

3. The oscillator circuit according to claim 2, characterized in that The delay unit comprises: A first main delay structure, wherein the first main delay structure is composed of a plurality of switch devices, and an input end of the first main delay structure is used to input the first input clock signal; A second main delay structure, wherein the second main delay structure is composed of a plurality of switch devices, and an input end of the second main delay structure is used to input the second input clock signal; a first slave delay structure, wherein the first slave delay structure is composed of a plurality of switch devices, an input end of the first slave delay structure is electrically connected to an output end of the first master delay structure, and an output end of the first slave delay structure is electrically connected to an output end of the second master delay structure and is used to output the second output clock signal; A second slave delay structure, wherein the second slave delay structure is composed of a plurality of switch devices, an input end of the second slave delay structure is electrically connected to an output end of the second master delay structure, and an output end of the second slave delay structure is electrically connected to an output end of the first master delay structure and is used to output the first output clock signal.

4. The oscillator circuit according to claim 3, characterized in that The first master delay structure, the second master delay structure, the first slave delay structure and the second slave delay structure are all composed of N-path parallel basic delay structures, the first master delay structure and the second master delay structure have the same number of paths, the first slave delay structure and the second slave delay structure have the same number of paths, and the basic delay structure includes: a first switch device, wherein a first end of the first switch device is used to be electrically connected to a current output end of the voltage-to-current module, and a control end of the first switch device is used to input a first control signal; a second switch device, wherein a first end of the second switch device is electrically connected to a second end of the first switch device, a control end of the second switch device is used to be electrically connected to an input end of the basic delay structure, and a second end of the second switch device is used to be electrically connected to an output end of the basic delay structure; a third switch device, wherein a first end of the third switch device is electrically connected to the second end of the second switch device and the output end of the basic delay structure, and a control end of the third switch device is electrically connected to the control end of the second switch device and the input end of the basic delay structure; A fourth switch device, wherein a first end of the fourth switch device is electrically connected to a second end of the third switch device, a control end of the fourth switch device is used to input a second control signal, and a second end of the fourth switch device is grounded.

5. The oscillator circuit according to claim 1, characterized in that The voltage-to-current module is composed of M optimized current mirror structures connected in parallel, and the optimized current mirror structure includes: a fifth switch device, wherein a first end of the fifth switch device is electrically connected to the first power line, and a control end of the fifth switch device is used to input a third control signal; a resistance module, wherein a first end of the resistance module is electrically connected to a second end of the fifth switch device; A sixth switch device, wherein a first end of the sixth switch device is electrically connected to a second end of the resistor module, a control end of the sixth switch device is used to input the regulating voltage, and a second end of the sixth switch device is electrically connected to a first input end of the four-stage differential ring oscillator.

6. The oscillator circuit according to claim 5, characterized in that The fifth switching device and the sixth switching device are both PMOS.

7. The oscillator circuit according to claim 2, characterized in that The driving circuit comprises an input circuit and an output circuit, wherein the input circuit of the driving circuit comprises: a first switch unit, the first switch unit is composed of a plurality of switch devices, a first input end of the first switch unit is used to input the first output clock signal, a second input end of the first switch unit is used to input the second output clock signal, an output end of the first switch unit is used to output a first output signal, a potential of the first output clock signal is opposite to a potential of the second output clock signal, and a potential of the first output signal is the same as a potential of the first output clock signal; A second switch unit, the second switch unit is composed of a plurality of switch devices, the first input end of the second switch unit is used to input the first output clock signal, the second input end of the second switch unit is used to input the second output clock signal, the output end of the second switch unit is used to output a second output signal, and the potential of the second output signal is the same as the potential of the second output clock signal.

8. The oscillator circuit according to claim 7, characterized in that The first switch unit comprises: a seventh switch device, wherein a first terminal of the seventh switch device is grounded, and a control terminal of the seventh switch device is used to input the first output clock signal; an eighth switch device, wherein a first terminal of the eighth switch device is grounded, a control terminal of the eighth switch device is used to input the second output clock signal, and a second terminal of the eighth switch device is used to output the first output signal; a ninth switch device, wherein a first end of the ninth switch device and a control end of the ninth switch device are electrically connected to a second end of the seventh switch device, and a second end of the ninth switch device is electrically connected to a second power line; A tenth switching device, wherein a first end of the tenth switching device is electrically connected to a second end of the eighth switching device, a control end of the tenth switching device is electrically connected to a control end of the ninth switching device, and a second end of the tenth switching device is electrically connected to the second power line.

9. The oscillator circuit according to claim 7, characterized in that The second switch unit comprises: an eleventh switch device, a first terminal of the eleventh switch device being grounded, and a control terminal of the eleventh switch device being used for inputting the second output clock signal; a twelfth switch device, wherein a first terminal of the twelfth switch device is grounded, a control terminal of the twelfth switch device is used to input the first output clock signal, and a second terminal of the twelfth switch device is used to output a second output signal; a thirteenth switch device, wherein a first end of the thirteenth switch device and a control end of the thirteenth switch device are electrically connected to a second end of the eleventh switch device, and a second end of the thirteenth switch device is electrically connected to a second power line; A fourteenth switching device, wherein a first end of the fourteenth switching device is electrically connected to a second end of the twelfth switching device, a control end of the fourteenth switching device is electrically connected to a control end of the thirteenth switching device, and a second end of the fourteenth switching device is electrically connected to the second power line.

10. The oscillator circuit according to claim 7, characterized in that The output circuit of the driving circuit comprises: A first inverter, wherein an input terminal of the first inverter is used to input the first output signal; a second inverter, wherein an input terminal of the second inverter is used to input the second output signal; a third inverter, wherein an input end of the third inverter is electrically connected to an output end of the first inverter, and an output end of the third inverter is used to output a first target clock signal; a fourth inverter, wherein an input end of the fourth inverter is electrically connected to an output end of the second inverter, and an output end of the fourth inverter is used to output a second target clock signal; a fifth inverter, wherein an input terminal of the fifth inverter is electrically connected to an output terminal of the second inverter and an input terminal of the fourth inverter respectively, and an output terminal of the fifth inverter is electrically connected to an output terminal of the first inverter and an input terminal of the third inverter respectively; A sixth inverter, wherein the input end of the sixth inverter is electrically connected to the output end of the first inverter and the input end of the third inverter respectively, and the output end of the sixth inverter is electrically connected to the output end of the second inverter and the input end of the fourth inverter respectively.

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