Distributed feedback in amplified signal path

Abstract

The invention relates to distributed feedback in an amplified signal path. An apparatus includes: a signal path including a plurality of inverters connected in series, the plurality of inverters including: a first inverter having a first input and having a first output; a second inverter having a second input coupled to the first output of the first inverter and having a second output; and a third inverter having a third input coupled to the second output of the second inverter and having a third output. The apparatus also includes a first feedback path coupling the second output of the second inverter to the first input of the first inverter, the first feedback path including a fourth inverter; and a second feedback path coupling the third output of the third inverter to the second input of the second inverter, the second feedback path including a fifth inverter.

Description

[0001] CROSS REFERENCE TO RELATED APPLICATIONS

[0002] This application is a non-provisional application claiming priority to U.S. Provisional Patent Application No. 63 / 522,331, filed on June 21, 2023, entitled “DISTRIBUTED FEEDBACK IN SCALE UP SIGNAL PATHS,” which is incorporated herein by reference. Technical Field

[0003] Embodiments of the present disclosure generally relate to the field of semiconductor memory devices. More specifically, embodiments of the present disclosure relate to modification of signal paths of electronic devices (eg, memory devices). Background Art

[0004] Generally speaking, an electronic device (e.g., a semiconductor device, a memory chip, a microprocessor chip, an image chip, etc.) may include one or more signal paths. These signal paths may transmit data signals, clock signals, etc. However, when transmitting signals along the signal paths of the electronic device, degradation of the signal may occur. Likewise, in some cases, amplification of the signal strength may be desired in addition and / or alternatively. In order to alleviate this degradation and / or provide an increase in the signal strength of the signal in the electronic device, enhancement of the signal strength may be performed. However, when the signal enhancement is performed, errors may be introduced into the data.

[0005] Embodiments of the present disclosure may address one or more of the issues set forth above. Summary of the invention

[0006] According to aspects of the present disclosure, a device is provided. The device includes: a signal path including a plurality of inverters connected in series, the plurality of inverters including: a first inverter having a first input and having a first output; a second inverter having a second input coupled to the first output of the first inverter and having a second output; and a third inverter having a third input coupled to the second output of the second inverter and having a third output; a first feedback path coupling the second output of the second inverter to the first input of the first inverter, the first feedback path including a fourth inverter; and a second feedback path coupling the third output of the third inverter to the second input of the second inverter, the second feedback path including a fifth inverter.

[0007] According to another aspect of the present disclosure, a device is provided. The device includes: a signal path including a plurality of inverters connected in series to define a plurality of intermediate nodes, each intermediate node being disposed between two corresponding adjacent inverters of the plurality of inverters; and a plurality of feedback paths, each feedback path connecting a corresponding one of the plurality of intermediate nodes to another node of the plurality of intermediate nodes, each of the plurality of feedback paths including at least one inverter as a feedback inverter; wherein each loop path closed using a corresponding portion of the signal path and a corresponding one of the plurality of feedback paths includes an odd number of inverters.

[0008] According to another aspect of the present disclosure, a method is provided. The method includes: transmitting a signal along a signal path including a plurality of inverters connected in series to increase the capacitive driving capability of the signal, wherein a first inverter among the plurality of inverters includes a first input and a first output, wherein a second inverter among the plurality of inverters includes a second input coupled to the first output of the first inverter and the second inverter includes a second output, wherein a third inverter among the plurality of inverters includes a third input coupled to the second output of the second inverter and the third inverter includes a third output; feeding back a first feedback signal from the second output of the second inverter to the first input of the first inverter along a first feedback path including a fourth inverter and connecting the second output of the second inverter to the first input of the first inverter; and feeding back a second feedback signal from the third output of the third inverter to the second input of the second inverter along a second feedback path including a fifth inverter and connecting the third output of the third inverter to the second input of the second inverter. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Various aspects of the present disclosure may be better understood upon reading the following detailed description and upon reference to the drawings, in which:

[0010] Figure 1 is a simplified block diagram illustrating certain features of a memory device according to an embodiment of the present disclosure;

[0011] Figure 2 Describe the embodiment according to the present disclosure Figure 1 A block diagram of a first embodiment of an inverter chain of a memory device;

[0012] Figure 3 Describe the embodiment according to the present disclosure Figure 1 A block diagram of a second embodiment of an inverter chain of a memory device;

[0013] Figure 4 Describe the embodiment according to the present disclosure Figure 1 A block diagram of a third embodiment of an inverter chain of a memory device of FIG. 1 ; and

[0014] Figure 5 Describe the embodiment according to the present disclosure Figure 1 A block diagram of a fourth embodiment of an inverter chain of a memory device. DETAILED DESCRIPTION

[0015] One or more specific embodiments will be described below. In order to provide a concise description of these embodiments, not all features of the actual implementation are described in the specification. It should be understood that in the development of any such actual implementation, as in any engineering or design project, many implementation-specific decisions must be made to achieve the developer's specific goals, such as complying with system-related and business-related constraints that may vary from one implementation to another. In addition, it should be understood that such development work can be complex and time-consuming, but will still be a routine task of design, fabrication, and manufacturing for a person of ordinary skill in the art who has the benefit of this disclosure.

[0016] An electronic device includes any number of signal paths that allow transmission of corresponding signals (e.g., clock signals, data signals, etc.). Similarly, there are situations where it is desirable to amplify (e.g., provide bandwidth extension of) a signal transmitted along a signal path (i.e., increase the amount of current available to drive or switch a capacitor at a particular speed along the signal path). One technique for amplifying a signal transmitted along a signal path is to utilize an inverter chain along the signal path. However, including an inverter chain along the signal path may introduce errors into the signal transmitted along the path, such as inter-symbol interference (ISI) errors in the signal. Therefore, in some embodiments, a feedback path may be introduced into the inverter chain to reduce signal errors, such as ISI. However, in other embodiments, the use of multiple feedback paths disposed throughout the inverter chain may be implemented to further reduce signal errors in the amplified signal.

[0017] Now turn to the diagram, Figure 1 is a simplified block diagram illustrating certain features of memory device 10. Specifically, Figure 1The block diagram of is a functional block diagram illustrating certain functionality of the memory device 10. According to one embodiment, the memory device 10 may be a random access memory (RAM) device, a dynamic RAM (DRAM) device, a static RAM (SRAM) device (including a double data rate SRAM device), a flash memory, a double data rate type four synchronous dynamic random access memory (DDR4 SDRAM) device, a double data rate type five synchronous dynamic random access memory (DDR5 SDRAM) device, or a NAND memory device. Although the memory device 10 is described herein, it should be noted that alternative electronic devices (e.g., application specific integrated circuits) may be utilized in place of the memory device 10. In fact, the techniques and devices described herein with respect to amplification of a signal may be applied to any electronic device that implements amplification of a signal along a signal path.

[0018] The memory device 10 may include a number of memory partitions 12, each memory partition 12 including one or more arrays (i.e., memory arrays). Depending on the application and design of the overall system, various configurations, organizations, and sizes of memory partitions 12 on the memory device 10 may be utilized. The memory device 10 may also include a command interface 14 and an input / output (I / O) interface 16. The command interface 14 is configured to provide a number of signals from an external device, such as a processor or controller (e.g., memory controller 18) external to the memory device 10. In some embodiments, the bus 20 (or a signal path or another group of signal paths) may allow bidirectional transmission of signals between the command interface 14 and the processor or controller (e.g., memory controller 18), either individually or in combination. Likewise, the bus 22 (or a signal path or another group of signal paths) may allow bidirectional transmission of signals including, for example, data signals, between the I / O interface 16 and, for example, a processor or controller (e.g., memory controller 18), either individually or in combination. Thus, a processor or controller, such as memory controller 18 , may provide various signals to memory device 10 to facilitate the transmission and receipt of data to be written to or read from memory device 10 .

[0019] As will be appreciated, the command interface 14 may include a plurality of circuits, such as a clock input circuit 24 and a command address input circuit 26, for example, to ensure proper handling of received signals. The command interface 14 may receive one or more clock signals from an external device, such as a processor or controller (e.g., a memory controller 18 or a register clock driver (RCD) for a dual in-line memory module), for example, at the clock input circuit 24. Likewise, the command interface 14 receives commands (e.g., read commands, write commands, etc.) that may be typed on the positive edge of the clock signal, as well as data that is typically transmitted or received on both the positive and negative clock edges. In some embodiments, commands may have a variable clock length (e.g., one or more clocks for receiving commands).

[0020] The clock input circuit 24 receives one or more clock signals and transmits an internal clock signal CLK therefrom (e.g., based on the received one or more clock signals). In some embodiments, the internal clock signal CLK is supplied to an internal clock generator 28 (e.g., a delay locked loop (DLL)) along a path 30. The internal clock generator 28 generates a phase-controlled internal clock signal (LCLK) based on the received internal clock signal CLK. In some embodiments, for example, the clock adjustment circuit 30 is operable to adjust the internal clock signal CLK so that it has a frequency different from the phase-controlled internal clock signal LCLK. The phase-controlled internal clock signal LCLK is supplied to the I / O interface 16, for example, and is used as a timing signal for determining the output timing of the read data.

[0021] The internal clock signal CLK may also be provided to various other components within the memory device 10 and may be used to generate various additional internal clock signals. For example, the internal clock signal CLK may be provided to a command decoder 32. The command decoder 32 may receive command signals from a command bus 34 and may decode the command signals to provide various internal commands. For example, the command decoder 32 may provide command signals to the internal clock generator 28 via a bus 36 to coordinate the generation of the phase-controlled internal clock signal LCLK.

[0022] Furthermore, the command decoder 32 may decode commands, such as read commands, write commands, mode register set commands, activate commands, etc., and provide access to the specific memory partition 12 corresponding to the command via the bus path 38. As will be appreciated, the memory device 10 may include various other decoders, such as row decoders and column decoders, to facilitate access to the memory partitions 12. In one embodiment, each memory partition 12 includes a control block 40 that provides the necessary decoding, such as row decoders and column decoders, as well as other features such as timing control and data control to facilitate execution of commands to and from the memory partitions 12.

[0023] The memory device 10 performs operations such as read commands and write commands based on command / address signals received from an external device such as a processor and / or by a memory controller 18. In one embodiment, the command / address signals are clocked to the command interface 14 using a clock signal. The command interface 14 may include a command address input circuit 26 configured to receive and transmit commands to provide access to the memory partitions 12, such as through a command decoder 32. Additionally, the command interface 14 may receive a memory select signal that enables the memory device 10 to process commands on the incoming command / address signals. Access to a particular memory partition 12 within the memory device 10 may be encoded in the command.

[0024] In addition, command interface 14 may be configured to receive a number of other command signals. For example, during power-up, a reset command may be used to reset command interface 14, status registers, state machines, etc. Various signals for facilitating testing memory device 10 may also be provided. For example, a test signal may be used to place memory device 10 in a test mode for connectivity testing. Command interface 14 may also be used to provide an alarm signal or another warning signal to a system processor or controller for certain errors that may be detected. However, in some embodiments, I / O interface 16 may additionally or alternatively be used to transmit an alarm signal, such as a thermal alarm.

[0025] By transmitting and receiving data signals through the I / O interface 16, data can be sent to and from the memory device 10 using the command and timing signals discussed above. More specifically, data can be sent to or retrieved from the memory partitions 12 via a data path 41 that includes a plurality of bidirectional data buses. Data I / O signals are typically transmitted to and received from the I / O interface 16 in one or more bidirectional data buses. For some memory devices, such as DDR5 SDRAM memory devices, the I / O signals may be divided into upper and lower bytes; however, other memory device types do not require such a division.

[0026] As will be appreciated, various other components such as power supply circuits (for receiving external VDD and VSS signals), read / write amplifiers (for amplifying signals during read / write operations), temperature sensors (for sensing the temperature of memory device 10), etc. may also be incorporated into memory device 10. Thus, it should be understood that providing Figure 1 The block diagram is merely intended to highlight certain functional features of the memory device 10 to facilitate the subsequent detailed description.

[0027] In some embodiments, the memory device 10 may be disposed in a host device (physically integrated into or otherwise connected to the host device), or otherwise coupled to the host device. The host device may include any of a desktop computer, a laptop computer, a pager, a cellular phone, a personal organizer, a portable audio player, a control circuit, a camera, etc. The host device may also be a network node, such as a router, a server, or a client (e.g., one of the computers of the previously described types). The host device may be some other type of electronic device, such as a copier, a scanner, a printer, a game console, a television, a set-top video distribution or recording system, a cable box, a personal digital media player, a factory automation system, an automotive computer system, or a medical device. (Like many other terms used herein, the terms used to describe these various examples of the system may share some references and thus should not be narrowly interpreted by virtue of the other items listed.)

[0028] Thus, the host device may be a processor-based device that may include a processor, such as a microprocessor, that controls system functions and processing of requests in the host. In addition, any host processor may include multiple processors that share system control. The host processor may be coupled directly or indirectly to additional system elements of the host so that the host processor controls the operation of the host by executing instructions that may be stored within the host or external to the host.

[0029] The memory device 10 may benefit from having signals that are amplified. For example, memory signals in the memory partition 12 that are transmitted to the output driver may be amplified before being received by the output driver. Similarly, the CLK and / or LCLK may similarly be amplified before being transmitted to various elements of the memory device 10. One technique to provide scaling of signals of the memory device 10 (or, for example, another electronic device where similar scaling of signals may be desired) is to implement a chain of inverters along the respective signal paths. Examples of potential inverter chains that may be utilized are described below.

[0030] Figure 2 An embodiment of an inverter chain 42 that operates to amplify a signal received at an input 44 (e.g., a pin, connection, or line) is described. As illustrated, the inverter chain 42 includes an inverter 46, an inverter 48, an inverter 50, and an inverter 52 disposed in series. Although four inverters 46, 48, 50, and 52 are illustrated, it should be noted that a greater or lesser number of inverters may be utilized in the inverter chain 42. Further, it should be noted that an even number of inverters 46, 48, 50, and 52 are illustrated so that any signal received at the input 44 and transmitted at the output 54 (e.g., a pin, connection, or line) is not inverted. However, in some embodiments, for example, when an inverted output signal at the output 54 is desired, an odd number of inverters may be utilized in the inverter chain 42.

[0031] As illustrated, the inverter chain 42 is a scaled inverter chain with a corresponding fan-out at the output 54. For example, the fan-out at the output 54 may be the amount of drive or switching current at the output 54 relative to the capacitance driven at the input 44. The number and size of the inverters 46, 48, 50, and 52 may be selected to produce a desired drive or switching current at the output 54 for a given capacitance at the input 44, and in some embodiments, the fan-out of each of the inverters 46, 48, 50, and 52 may be evenly distributed across the inverters 46, 48, 50, and 52. Alternatively, the fan-out of the inverters 46, 48, 50, and 52 may be increased, for example, for each of the inverters 46, 48, 50, and 52 in the inverter chain 42. In this way, the inverter chain 42 operates to amplify the signal received at the input 44 (i.e., by the increase in capacitive drive capability provided by the inverter chain 42). However, when amplifying the signal received at input 44, there may be some amount of accompanying signal degradation in the resulting signal generated and transmitted from output 54. These errors may include, for example, inter-symbol interference (ISI) errors and / or other errors in the signal. Therefore, in some embodiments, a feedback path may be introduced into the inverter chain to reduce signal errors, such as ISI.

[0032] Figure 3 An embodiment of an inverter chain 56 is illustrated that operates similarly to the inverter chain 42 in that the inverter chain 56 operates to amplify the signal received at the input 44. As illustrated, the inverter chain 56 includes the inverter 46, the inverter 48, the inverter 50, and the inverter 52 disposed in series, and while four inverters 46, 48, 50, and 52 are illustrated, it should be noted that a greater or lesser number of inverters may be utilized in the inverter chain 56. Furthermore, it should be noted that while an even number of inverters 46, 48, 50, and 52 are illustrated so that any signal received at the input 44 and transmitted at the output 54 is not inverted, in some embodiments, for example, when an inverted output signal at the output 54 is desired, an odd number of inverters may be utilized in the inverter chain 56.

[0033] As illustrated, inverter chain 56 is a scaled inverter chain with a corresponding fan-out at output 54, whereby the number and size of inverters 46, 48, 50, and 52 may be selected to produce a desired capacitive drive capability at output 54 for a given capacitance at input 44. Additionally, in some embodiments, the fan-out of each of inverters 46, 48, 50, and 52 may be evenly distributed across inverters 46, 48, 50, and 52. Alternatively, the fan-out of inverters 46, 48, 50, and 52 may be increased, for example, for each of inverters 46, 48, 50, and 52 in inverter chain 56. In this manner, inverter chain 42 operates to amplify the signal received at input 44 (i.e., by the increase in capacitance provided by inverter chain 56).

[0034] In addition, the inverter chain 56 additionally includes another inverter 58 disposed in the feedback path 60. As illustrated, the feedback path 60 is coupled to the output 62 of the final inverter (i.e., inverter 52) in the inverter chain 56, and is coupled to the input 64 of the same final inverter (i.e., inverter 52), with the inverter 58 disposed therebetween. In some embodiments, the size of the inverter 58 may be selected based on, for example, the amount of desired error reduction in the signal output from the output 54, area constraints, and / or other considerations. However, the size of the inverter 52 coupled to the feedback path 60 and / or the fan-out of the inverter 58 may be selected based on the fan-out of the inverter 52 coupled to the feedback path 60. That is, the inverter 58 may be selected according to the scaling factor applied to the inverter 52 coupled to the feedback path 60. In operation, the selection and utilization of the inverter 58 in the feedback path 60 may operate to reduce errors in the signal output from the output 54.

[0035] As illustrated, the inclusion of a feedback path 60 at a node (e.g., at output 62 of inverter 52) strengthens the signal input to inverter 52, and inverter chain 56 is operable to provide amplification of the signal while reducing associated errors. However, additional embodiments may be utilized to achieve similar or better results with respect to error reduction associated with an amplification path.

[0036] Figure 4 An embodiment of an inverter chain 66 is illustrated that operates similarly to inverter chain 56 in that inverter chain 66 operates to amplify a signal received at input 44. As illustrated, inverter chain 66 includes inverter 46, inverter 48, inverter 50, and inverter 52 disposed in series, and while four inverters 46, 48, 50, and 52 are illustrated, it should be noted that a greater or lesser number of inverters may be utilized in inverter chain 66. Further, it should be noted that while an even number of inverters 46, 48, 50, and 52 are illustrated so that any signal received at input 44 and transmitted at output 54 is not inverted, in some embodiments, for example, when an inverted output signal at output 54 is desired, an odd number of inverters may be utilized in inverter chain 66.

[0037] As illustrated, inverter chain 66 is a scaled inverter chain with a corresponding fan-out at output 54, whereby the number and size of inverters 46, 48, 50, and 52 may be selected to produce a desired capacitive drive capability at output 54 for a given capacitance at input 44. Additionally, in some embodiments, the fan-out of each of inverters 46, 48, 50, and 52 may be evenly distributed across inverters 46, 48, 50, and 52. Alternatively, the fan-out of inverters 46, 48, 50, and 52 may be increased, for example, for each of inverters 46, 48, 50, and 52 in inverter chain 66. In this manner, inverter chain 42 operates to amplify the signal received at input 44 (i.e., by the increase in capacitance provided by inverter chain 66).

[0038] Inverter chain 66 additionally includes feedback path 68, feedback path 70, feedback path 72, and feedback path 74, whereby feedback path 68 includes inverter 76 disposed therein, feedback path 70 includes inverter 78 disposed therein, feedback path 72 includes inverter 80 disposed therein, and feedback path 74 includes inverter 82 and inverter 84 disposed therein. Additionally, feedback path 68 is coupled to output 86 of inverter 48 and input 88 of inverter 46. Feedback path 70 is coupled to output 90 of inverter 50 and input 92 of inverter 48. Feedback path 72 is coupled to output 62 of inverter 52 and input 94 of inverter 50, and feedback path 74 is coupled to output 62 of inverter 52 and input 96 of inverter 52. In this manner, each of feedback path 68, feedback path 70, feedback path 72, and feedback path 74 operates as part of distributed feedback along inverter chain 66.

[0039] The inclusion of feedback path 68, feedback path 70, feedback path 72, and feedback path 74 imposes a de-emphasis behavior (i.e., de-emphasizes the low frequency content of the signal transmitted from output 54 while equalizing or otherwise improving the signal quality of the signal transmitted from output 54) in inverter chain 66. This imposition of de-emphasis behavior in inverter chain 66 is accomplished by including an odd number of inverters in feedback path 68, feedback path 70, feedback path 72, and feedback path 74.

[0040] For example, inverter chain 66 may be utilized in memory device 10 to couple memory signals that have been transmitted to gates of reduced size (i.e., to increase memory density that can be used for a given amount of available space) to amplify signals from the memory gates to output drivers to drive signals from, for example, memory device 10 to another chip. In this embodiment, a large number of inverters (e.g., ten or more inverters, each having the size characteristics of inverters 46, 48, 50, and 52) may be used in a pre-driver chain to, for example, drive a load coupled to the pre-driver chain. Similar examples may apply to clock transmissions.

[0041] By using inverter chain 66 as the above-mentioned pre-driver chain to distribute the feedback mechanism (e.g., using multiple feedback loops or paths, such as feedback path 68, feedback path 70, feedback path 72, and feedback path 74), the number of gates in the pre-driver chain can be reduced by using feedback elements (e.g., inverter 76, inverter 78, inverter 80, inverter 82, and inverter 84) in feedback paths 68, feedback paths 70, feedback paths 72, and feedback paths 74 (i.e., inverter chain 66 can operate using inverters 46, 48, 50, and 52 instead of a larger number of additional inverters in inverter chain 66 connected in series with inverters 46, 48, 50, and 52). Additionally, the size of the feedback elements (e.g., inverter 76, inverter 78, inverter 80, inverter 82, and inverter 84) is physically smaller than the chain inverters (e.g., inverters 46, 48, 50, and 52 and any additional inverters in series therewith that would be utilized). Thus, by utilizing the feedback elements (e.g., inverter 76, inverter 78, inverter 80, inverter 82, and inverter 84), the chain inverters (e.g., inverters 46, 48, 50, and 52 and any additional inverters in series therewith) may be removed, thereby achieving a total footprint of inverter chain 66 that is smaller than that of inverter chain 66 that would be utilized. Figure 2 or Figure 3 A reduction of the inverter chain in a form similar to that described in any of the above.

[0042] Additionally, the removal of the chain inverters reduces the delay from the path through the chain inverters (caused by the chain inverters) and removes a buffer stage from the path through the chain inverters. Thus, the use of feedback elements (e.g., inverter 76, inverter 78, inverter 80, inverter 82, and inverter 84) not only reduces the delay of inverter chain 66 relative to taking the same approach as Figure 2 or Figure 3 The silicon area (i.e., footprint) of an inverter chain of a form similar to that described in any of the above embodiments is reduced, and the use of a distributed feedback mechanism (e.g., feedback elements inverter 76, inverter 78, inverter 80, inverter 82, and inverter 84 and their respective feedback paths 68, feedback path 70, feedback path 72, and feedback path 74) also enables inverter chain 66 to be more compact than that of a conventional inverter chain. Figure 2 or Figure 3 The speed increase of an inverter chain of a form similar to that described in any of the above embodiments and the power savings due to removing the larger chain inverters and replacing them with smaller feedback elements (e.g., inverter 76, inverter 78, inverter 80, inverter 82, and inverter 84) that draw less power than the larger chain inverters. In addition, removing stages along the forward path reduces sensitivity to power supply fluctuations and temperature drifts, as those sensitivities are typically associated with time delays through any particular circuit.

[0043] exist Figure 4 In the chain inverter 66 illustrated in FIG. 1 , there is a fan-out (e.g., an amplification factor relative to the next stage) for chain inverters 46, 48, 50, and 52. As previously mentioned, the fan-out may be constant (e.g., four). Thus, for example, with respect to capacitance, inverter 46 may be a 1X inverter, inverter 48 may be a 4X inverter, inverter 50 may be a 16X inverter, and inverter 52 may be 64X, such that the resulting capacitive gain at output 54 relative to input 44 is 64 times greater in magnitude (i.e., the capacitance at output 54 is 64 times greater than the capacitance at input 44). The feedback elements (e.g., inverter 76, inverter 78, inverter 80, inverter 82, and inverter 84) scale with the same growth as their associated chain inverters 46, 48, 50, and 52. Thus, inverter 76 is a IX inverter, inverter 78 is a 4X inverter, inverter 80 is a 16X inverter, inverter 82 is a 16X inverter, and inverter 84 is a 64X inverter. However, each of inverters 76, 78, 80, 82, and 84 is associated with a feedback scaling factor that causes each of inverters 76, 78, 80, 82, and 84 to be at least 10 times smaller, 20 times smaller, 30 times smaller, or another value smaller than its associated chain inverters 46, 48, 50, and 52 (e.g., chain inverters 46, 48, 50, and 52 in respective feedback paths 68, 70, 72, and 74 associated with each of inverters 46, 48, 50, and 52). For example, flexibility in fan-out and feedback scaling between stages may be advantageous when the interconnect contributes non-uniformity to the capacitance seen at any stage. That is, while a fixed fan-out scaling through the forward chain (e.g., four times larger) and a fixed feedback scaling throughout the chain (e.g., ten times larger) may be employed in some embodiments, the actual feedback scaling may, for example, vary from feedback path to feedback path.

[0044] As further illustrated, each of feedback path 68, feedback path 70, feedback path 72, and feedback path 74 has an odd number (i.e., three) of inverters therein. Feedback path 68 includes inverter 46, inverter 48, and inverter 76. Feedback path 70 includes inverter 48, inverter 50, and inverter 78. Feedback path 72 includes inverter 50, inverter 52, and inverter 80. Finally, feedback path 74 includes (by comparison) three inverters, but only one of them is a main inverter as inverter 52, with the remaining two inverters acting as two feedback inverters (i.e., inverter 82 and inverter 84). In this way, in some embodiments, each of feedback path 68, feedback path 70, feedback path 72, and feedback path 74 operates in a manner similar to a ring oscillator. Additionally, it should be noted that in some embodiments, feedback inverter 82 and feedback inverter 84 are amplified, which can be beneficial because it reduces (or minimizes) the capacitive loading imposed on the output node by adding a feedback path while still providing full feedback strength at the input of the final stage (i.e., the input of inverter 52).

[0045] Furthermore, while each of feedback path 68, feedback path 70, feedback path 72, and feedback path 74 includes an odd number (i.e., three) of inverters therein, other odd numbers are contemplated (e.g., one, five, etc.). Likewise, in some embodiments, one or more of inverter 46, inverter 48, inverter 50, and inverter 52 may not have a corresponding feedback path associated therewith, while the remainder have an odd number of inverters associated therewith. Additionally, in some embodiments, an odd number of feedback elements may be disposed at a single node between any of inverter 46, inverter 48, inverter 50, and inverter 52 (e.g., chain inverters) without including any chain inverters in the feedback paths.

[0046] In one embodiment whereby there is an odd number of inverters for any given feedback path 68, 70, 72, and 74, the respective feedback elements (e.g., inverter 76, inverter 78, inverter 80, inverter 82, and inverter 84) operate to produce a signal that is the opposite of the potential received signal at the respective feedback path 68, 70, 72, and 74. This causes the individual amplitudes received at each of inputs 88, 92, 94, and 96 to be reduced in proportion to the size of inverter 76, inverter 78, inverter 80, inverter 82, and inverter 84 relative to their associated chain inverters 46, 48, 50, and 52 (due to the operation of inverter 76, inverter 78, inverter 80, inverter 82, and inverter 84). This produces a de-emphasis behavior in the inverter chain 66 (e.g., de-emphasizes low frequency content of the signal transmitted from the output 62 while maintaining high frequency content of the signal to counter the typical roll-off of the bandwidth limited circuit elements of the inverter chain 66). However, unlike the chain inverter 56, the de-emphasis behavior in the inverter chain 66 is distributed across the entirety of the inverter chain 66 rather than just at one single node, which is operable to improve voltage margins along the entire chain inverter 66 and does not require large error correction by one inverter at a single node.

[0047] As mentioned above, the size of the feedback elements (e.g., inverter 76, inverter 78, inverter 80, inverter 82, and inverter 84) may be physically smaller relative to their associated chain inverters 46, 48, 50, and 52. However, in some embodiments, this may lead to problems with implementing the inverters (e.g., inverter 76) in the first feedback loop (i.e., feedback loop 68); that is, the desired size of inverter 76 may not be achievable. Therefore, the following description is related to Figure 4 The inverter chain 66 operates similarly to another embodiment of an embodiment of an inverter chain.

[0048] Figure 5 An embodiment of the inverter chain 98 is described. The inverter chain 98 is connected to Figure 4 The inverter chain 66 of FIG. 4 operates similarly in that the inverter chain 98 operates to amplify the signal received at the input 44. However, unlike the inverter chain 98 including the feedback path 68 having the inverter 76 therein, FIG. Figure 4 Compared with the inverter chain 66, Figure 5Inverter 98 of FIG. 1 includes a feedback path 100 including a resistor 102. This may occur, for example, when the desired size of inverter 76 may not be achievable (e.g., less than the size allowed in a given set of process design specifications). In this case, replacement of resistor 102 in place of the feedback inverter in the first feedback loop (e.g., feedback path 100) may be implemented. In some embodiments, resistor 102 may have a resistance of, for example, approximately 1000 ohms, 2000 ohms, 3000 ohms, 5000 ohms, or another value, and resistor 102 may operate to ensure similar de-emphasis benefits in the small early stages of the main path (i.e., along inverters 46, 48, 50, and 52).

[0049] Additionally, a similar replacement may be additionally implemented in another feedback loop (e.g., replacing inverter 78 in feedback path 70 with a resistor similar to feedback path 100). In this additional embodiment, each resistor is associated with a particular stage, so if two stages receive resistor feedback, there are two resistors with a shared node connected between the main line inverter stages, and opposite ends of the resistors connected to the input of the first stage and the output of the second stage, respectively. Furthermore, in some embodiments, transistor-based transmission gates may be connected in series with the resistor feedback to remove them from the main path when the path is powered down. This may assist in minimizing leakage current in the powered down state. In this way, the use of resistors is similar to Figure 4 The feedback inverters of may operate similarly to how they are implemented as, for example, tri-stateable inverters (eg, so that they may also be selectively disabled as desired).

[0050] Although the present disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the present disclosure is not intended to be limited to the specific forms disclosed. Rather, the present disclosure is intended to cover all modifications, equivalents, and alternatives that fall within the spirit and scope of the present disclosure as defined by the following claims.

[0051] The technology presented and claimed herein is cited and applied to physical and concrete examples of a practical nature that can significantly improve the art and are therefore not abstract, intangible or purely theoretical. In addition, if any claim attached at the end of this specification contains one or more elements designated as "means for [performing] [the function] ..." or "steps for [performing] [the function] ...", it is intended that such elements be interpreted in accordance with 35 U.S.C. 112(f). However, for any claim containing elements designated in any other manner, it is intended that such elements not be interpreted in accordance with 35 U.S.C. 112(f).

Claims

1. A device comprising: A signal path comprising a plurality of inverters connected in series, the plurality of inverters comprising: a first inverter having a first input and having a first output; A second inverter having a second input coupled to the first output of the first inverter and having a second output; and A third inverter having a third input coupled to the second output of the second inverter and having The third output; a first feedback path coupling the second output of the second inverter to the first input of the first inverter, the first feedback path comprising a fourth inverter; and A second feedback path couples the third output of the third inverter to the second input of the second inverter, the second feedback path comprising a fifth inverter.

2. The device of claim 1, wherein a size of the fourth inverter is based on a scaled size of the first inverter. 3 . The apparatus of claim 1 , wherein a first size of the fourth inverter is at most one-thirtieth of a second size of the first inverter. 4 . The device of claim 1 , wherein a size of the fifth inverter is based on a scaled size of the second inverter. 5 . The apparatus of claim 1 , wherein a first size of the fifth inverter is at most one-thirtieth of a second size of the second inverter. 6 . The apparatus of claim 1 , wherein the plurality of inverters connected in series include a sixth inverter having a fourth input coupled to the third output of the third inverter and having a fourth output.

7. The device of claim 6, comprising a third feedback path connecting the fourth output of the fourth inverter to the third input of the third inverter, the third feedback path comprising a seventh inverter.

8. The device of claim 7, wherein a size of the seventh inverter is based on a scaled size of the third inverter. 9 . The apparatus of claim 7 , wherein a first size of the seventh inverter is at most one-thirtieth of a second size of the third inverter.

10. The device of claim 7, comprising a fourth feedback path connecting the fourth output of the fourth inverter to the fourth input of the fourth inverter, the fourth feedback path comprising an eighth inverter and a ninth inverter.

11. The device of claim 10, wherein a size of the eighth inverter is based on a scaled size of the third inverter. 12 . The apparatus of claim 10 , wherein a first size of the eighth inverter is at most one-thirtieth of a second size of the third inverter.

13. The device of claim 10, wherein a size of the ninth inverter is based on a scaled size of the sixth inverter.

14. The apparatus of claim 10, wherein a first size of the ninth inverter is at most one-thirtieth of a second size of the sixth inverter.

15. An apparatus comprising: a signal path comprising a plurality of inverters connected in series to define a plurality of intermediate nodes, each intermediate node being disposed between corresponding adjacent two inverters of the plurality of inverters; and a plurality of feedback paths, each feedback path connecting a corresponding one of the plurality of intermediate nodes to another one of the plurality of intermediate nodes, each of the plurality of feedback paths comprising at least one inverter as a feedback inverter; Each loop path in which is closed using a corresponding portion of the signal path and a corresponding one of the plurality of feedback paths includes an odd number of inverters.

16. The apparatus of claim 15, wherein a size of the feedback inverter in each loop path is based on a second size of at least one inverter in the loop path.

17. The apparatus of claim 15, wherein a size of each feedback inverter in each loop path is smaller than a second size of at least one inverter in the loop path.

18. The device of claim 15, wherein each inverter of the plurality of inverters in the signal path comprises a common fan-out value.

19. The apparatus of claim 15, comprising a first inverter disposed in series with the plurality of inverters, wherein the first inverter comprises a first input and a first output, wherein the first output of the first inverter is coupled to a second output of a second inverter of the plurality of inverters connected in series; and An initial feedback path connects the first output of the first inverter to the first input of the first inverter, the initial feedback path comprising a resistor.

20. A method comprising: transmitting a signal along a signal path including a plurality of inverters connected in series to increase a capacitive drive capability of the signal, wherein a first inverter of the plurality of inverters includes a first input and a first output, wherein a second inverter of the plurality of inverters includes a second input coupled to the first output of the first inverter and the second inverter includes a second output, wherein a third inverter of the plurality of inverters includes a third input coupled to the second output of the second inverter and the third inverter includes a third output; feeding back a first feedback signal from the second output of the second inverter to the first input of the first inverter along a first feedback path including a fourth inverter and connecting the second output of the second inverter to the first input of the first inverter; and A second feedback signal from the third output of the third inverter is fed back to the second input of the second inverter along a second feedback path including a fifth inverter and connecting the third output of the third inverter to the second input of the second inverter.

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