RTC clock measurement and control circuit and method based on battery

Abstract

The invention discloses a battery-based RTC clock measurement and control circuit and method, and relates to the technical field of clock electronics. Compared with a previous RTC chip, the problem that an existing quartz crystal RTC chip is poor in RTC clock precision is solved; and data loss and time abnormity are caused by system interruption due to an abnormal power failure phenomenon. A bias circuit is designed in combination with a bipolar junction transistor, the accuracy and stability of power management are effectively improved, a clock monitoring circuit is designed based on the capacitor charging and discharging principle, and accurate detection of clock signals is achieved; a current-adjustable Pearls oscillator is designed, power consumption optimization and dynamic path adjustment of the oscillator are realized, and the power consumption of an RTC system is greatly reduced. Aiming at the abnormal power failure condition of the RTC system, an emergency power supply scheme combined with a 3V button battery or a high-capacity capacitor is provided and is seamlessly integrated with a configurable crystal oscillator. When abnormal power failure occurs, the system can be rapidly switched to an emergency power supply mode, and the continuity and stability of a system clock are maintained.

Description

Technical Field

[0001] The present invention relates to the field of clock electronic technology, and in particular to a battery-based RTC clock measurement and control circuit and method. Background Art

[0002] In recent years, with the rapid development of Internet of Things technology, real-time clock (RTC) chips have been widely used in the field of electronic equipment. Internet of Things chips are generally powered by batteries. In order to ensure that the chips can work stably and effectively for a long time, higher requirements are put forward for the power consumption, voltage resistance, high temperature resistance, and anti-interference of the chips. As an indispensable key component in the field of Internet of Things, when the Internet of Things system is in a dormant state, the RTC chip and part of the control battery work. The power consumption of RTC directly affects the standby time of the system to a large extent.

[0003] Since the RTC chip is generally based on a quartz crystal as the clock source, the quartz crystal will cause problems such as poor RTC clock accuracy and high power consumption under the influence of temperature and power supply voltage. In the IoT system, the level standards of the RTC power supply in different circuits are also different, and the RTC circuit needs to have higher compatibility and versatility. As the working circuit in the system sleep state, abnormal power failure of RTC will cause abnormal operation of the entire system. It is necessary not only to ensure high-precision recording of RTC under normal conditions, but also to quickly activate the built-in emergency power supply mechanism in the event of abnormal power failure, maintain the continuous operation of key clock functions, and avoid data loss and time anomalies caused by system interruptions.

[0004] In order to solve the above problems, the present invention proposes a battery-based RTC clock measurement and control method and circuit to meet the RTC clock calibration requirements in various environments of the Internet of Things system, ensure the accuracy of the system clock in the event of abnormal power failure of the system, and have low power consumption. Summary of the invention

[0005] The purpose of the present invention is to provide a battery-based RTC clock measurement and control circuit and method to solve the problems raised in the background technology:

[0006] The existing technology generally uses quartz crystal as the RTC chip clock source. Under the influence of temperature and power supply voltage, it will cause problems such as poor RTC clock accuracy and high power consumption; and abnormal power failure can easily cause system interruption, resulting in data loss and time anomalies.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions:

[0008] A battery-based RTC clock measurement and control circuit, including a bias circuit, a clock monitoring circuit, a low-power control circuit and a power switching circuit;

[0009] The output end of the bias circuit is connected to the input end of the clock monitoring circuit; the second inverter output end of the clock monitoring circuit is connected to the switch signal input end of the Pierce oscillator of the low power control circuit; the output end of the mirror current source of the low power control circuit is connected to the input end of the comparator of the power switching circuit;

[0010] The low power consumption control circuit includes a sixth NMOS transistor N6 to an eleventh NMOS transistor N6 to N11, a sixth PMOS transistor P6 to an eleventh PMOS transistor P6 to P11, a feedback resistor R f ; A first oscillator capacitor C1, a second oscillator capacitor C2 and a crystal oscillator;

[0011] The drain of the seventh PMOS tube P7 is connected to the first control voltage V bias1 The gate of the seventh PMOS tube P7 is connected to the gate of the sixth NMOS tube N6 and the state input terminal, the drain of the sixth NMOS tube N6 is grounded, the source of the seventh PMOS tube P7 and the source of the sixth NMOS tube N6 are connected to the gate of the eighth PMOS tube N8, the gate of the ninth PMOS tube P9 and the gate of the tenth PMOS tube P10, the drain of the eighth PMOS tube P8, the drain of the ninth PMOS tube P9 and the drain of the tenth PMOS tube P10 are connected to the power supply V DD The source of the eighth PMOS tube P8 is connected to the first end of the first control signal terminal CT0, the source of the ninth PMOS tube P9 is connected to the first end of the second control signal terminal CT1, the source of the tenth PMOS tube P10 is connected to the first end of the third control signal terminal CT2, the second end of the first control signal terminal CT0, the second end of the second control signal terminal CT1 and the second end of the third control signal terminal CT2 are all connected to the drain of the eleventh PMOS tube P11, and the gate of the eleventh PMOS tube P11 is connected to the feedback resistor R f The first end, the first end of the first oscillator capacitor C1, the first end of the crystal oscillator and the gate of the eleventh NMOS tube N11; the source of the eleventh PMOS tube P11 is connected to the feedback resistor R f The second end, the second end of the crystal oscillator, the first end of the second oscillator capacitor C2 and the source of the eleventh NMOS transistor N11, the second end of the first oscillator capacitor C1 and the second end of the second oscillator capacitor C2 are all grounded;

[0012] The drain of the seventh NMOS tube N7 is connected to the second control voltage V bias2 The gate of the seventh NMOS tube N7 is connected to the gate and state input terminal of the sixth PMOS tube P6, and the drain of the sixth PMOS tube P6 is connected to the power supply V DD, the source of the seventh NMOS tube N7 and the source of the sixth PMOS tube P6 are connected to the gate of the eighth NMOS tube N8, the gate of the ninth NMOS tube N9 and the gate of the tenth NMOS tube N10, the drain of the eighth NMOS tube N8, the drain of the ninth NMOS tube N9 and the drain of the tenth NMOS tube N10 are grounded, the source of the eighth NMOS tube N8 is connected to the first end of the first control signal terminal CT0, the source of the ninth NMOS tube N9 is connected to the first end of the second control signal terminal CT1, the source of the tenth NMOS tube N10 is connected to the first end of the third control signal terminal CT2, the second end of the first control signal terminal CT0, the second end of the second control signal terminal CT1 and the second end of the third control signal terminal CT2 are all connected to the drain of the eleventh NMOS tube N11;

[0013] The power switching circuit includes a first control resistor R1, a second control resistor R2, a voltage follower and a comparator; the first control resistor R1 is connected to a power source V DD The second end of the first control resistor R1 and the first end of the second control resistor R2 are connected to the positive input end of the voltage follower, the second end of the second control resistor R2 is grounded, the output end of the voltage follower is connected to its negative input end and the positive input end of the comparator, the negative input end of the comparator is provided with a 1.2V reference voltage through a bandgap reference circuit, and the comparator is also connected to the positive input end of the comparator through the power supply V H The comparator output is input to the power supply gating logic unit through level shifting, and the power supply gating logic unit is also connected to the power supply V DD and power supply V BAK , the power supply gate logic unit output gate power supply V S The LDO circuit is also connected to the external control EN18 pin and the backup voltage V CORE Pin.

[0014] Preferably, the clock monitoring circuit includes a first inverter INV1, a first switch sw1, a second switch sw2, a first monitoring capacitor C1, a second monitoring capacitor C2, a monitoring resistor R, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3 and a second inverter INV2;

[0015] The first end of the first inverter INV1 is an input end, connected to the first end of the first switch sw1, the second end of the first inverter INV1 is connected to the first end of the second switch sw2, the third end of the first switch sw1 is connected to the second end of the second switch sw2, the second end of the first switch sw1 is connected to the second end of the monitoring resistor R and the first end of the first monitoring capacitor C1, and the first end of the monitoring resistor R is connected to the power supply V DDThe first monitoring capacitor C1 is connected to the drain of the first MOS tube M1, and the second monitoring capacitor C1 is grounded; the third terminal of the second switch sw2 is connected to the source of the third MOS tube M3, the first terminal of the second monitoring capacitor C2 and the gate of the second MOS tube M2, the drain of the third MOS tube M3, the second terminal of the second monitoring capacitor C2 and the drain of the second MOS tube M2 are grounded, the source of the second MOS tube M2 is connected to the source of the first MOS tube M1 and the first terminal of the second inverter INV2, and the second terminal of the second inverter INV2 is the output terminal.

[0016] Preferably, the built-in reference capacitor C0 and the built-in inductor L M 、Built-in capacitor C M and built-in resistor R M , the built-in inductor L M 、Built-in capacitor C M and built-in resistor R M Firstly connect them in series, and then connect them in parallel with the built-in reference capacitor C0 to obtain the crystal oscillator;

[0017] The comparator in the power switching circuit adopts a hysteresis comparator and outputs a control signal through a power gating logic unit.

[0018] Preferably, the EN18 pin is used to enable 1.8V standard power supply and to realize external control; when the EN18 pin is pulled low externally, the LDO circuit is disabled, and the V CORE The pin provides voltage.

[0019] A battery-based RTC clock measurement and control method is applied to the battery-based RTC clock measurement and control circuit as described above, and comprises the following steps:

[0020] S1: Control the bias circuit and the clock monitoring circuit. The bias circuit uses a bipolar junction transistor to reduce the error during the startup process. The clock monitoring circuit uses the capacitor charging and discharging principle to control the clock monitoring circuit to detect the clock signal.

[0021] S2: The low power consumption control circuit adopts the digital circuit control technology of the current adjustable Pierce oscillator to realize the ultra-low power consumption control of the RTC clock measurement and control circuit;

[0022] S3: In case of abnormal power outage, the power switching circuit uses the auxiliary power system to perform emergency power failure processing.

[0023] Preferably, in S1, the implementation process of using a bipolar junction transistor in the bias circuit to reduce the error during the startup process is:

[0024] S101: By formula Calculate the reference voltage V ref With the power supply voltage VDD There is a proportional relationship between them, where R1 and R2 are the equivalent resistance values ​​of the reference voltage and the power supply voltage respectively;

[0025] S102: Set the reference voltage V ref The equivalent resistance R1 and the power supply voltage V DD The equivalent resistor R2 is replaced by a bipolar junction transistor with the base and collector short-circuited; through the formula The reference voltage V ref Transformed to the power supply voltage V DD The form of weak correlation, where T is the absolute temperature; k is the Boltzmann constant; q is the charge constant; I S is the reverse saturation current, R is the resistance of resistors R1 and R2 in parallel;

[0026] S103: By formula Calculate the signal sensitivity and use the formula The signal sensitivity is converted into is the signal sensitivity;

[0027] S104: Calculate the signal sensitivity values ​​of the bipolar junction transistor before and after replacement, and select a bipolar junction transistor whose sensitivity after replacement is lower than that before replacement, so as to reduce the error in the startup process.

[0028] Preferably, in S1, the process of controlling the clock monitoring circuit is specifically as follows:

[0029] The first inverter INV1 is used to output a clock signal and its inverted signal to control the first switch sw1 and the second switch sw2 respectively, ensuring that the states of the two are complementary; driven by the clock signal, the two switches are turned on alternately to control the charging process of the first monitoring capacitor C1 and the second monitoring capacitor C2 respectively; during the charging and discharging process, when the first switch sw1 is turned on, the power supply charges the first monitoring capacitor C1 through the first switch sw1; when the second switch sw2 is turned on, the second monitoring capacitor C2 starts to charge, and at the same time, the third MOS tube M3 in the clock monitoring circuit provides a pull current to discharge the second monitoring capacitor C2. The calculation formula for the charge amount Q charged in the second monitoring capacitor C2 by the circuit in a single cycle is as follows: Wherein, Q1 is the charge amount charged to the first monitoring capacitor C1 in a single cycle; Q2 is the pull current I through the third MOS tube M3 in a single cycle. L The amount of released charge; τ is the period; η is the duty cycle.

[0030] Preferably, in S2, based on the traditional Pierce oscillator, the feedback resistor R fThe two ends of the crystal oscillator are respectively connected in parallel with an eleventh NMOS tube N11 and an eleventh PMOS tube P11, and the eleventh NMOS tube N11 and the eleventh PMOS tube P11 are used as reverse amplification cores to form a reverse amplifier, and provide gain for the reverse amplifier;

[0031] Through an adjustable current bias mechanism, the on and off of a plurality of MOS tubes are controlled by a switch control signal; three NMOS tubes and three PMOS tubes are used as mirror current sources, and the width-to-length ratios of the three NMOS tubes and the three PMOS tubes are all set to a ratio of 1:2:4, so as to provide a dynamically adjustable bias current for the reverse amplifier; the three NMOS tubes include an eighth NMOS tube N8 to a tenth NMOS tube N10, and the three PMOS tubes include an eighth PMOS tube P8 to a tenth PMOS tube P10;

[0032] At the same time, a state flag signal M is introduced; the state flag signal M refers to the signal of the state input terminal; when the state flag signal M is at a low level, it indicates that the oscillator is in the start-up stage. At this time, by setting the switch control signal to a high level, the sixth NMOS tube N6 and the sixth PMOS tube P6 switches at the input terminal of the state flag signal M are turned on, the seventh NMOS tube N7 and the seventh PMOS tube P7 are turned off, and the gate potentials of the three PMOS tubes are configured to be zero, so as to realize the supply of the maximum variable current, thereby accelerating the start-up process;

[0033] Until the oscillation is stable, the state flag signal M jumps to a high level, the sixth NMOS tube N6 and the sixth PMOS tube P6 are turned off, the seventh NMOS tube N7 and the seventh PMOS tube P7 are turned on, and the gates of the three PMOS tubes are adjusted to the first control voltage V bias1 , reducing the current supply, so that the oscillator enters a stable oscillation state with low power consumption; the mirror current source composed of the three NMOS tubes and the three PMOS tubes has a current ratio that follows the binary increasing principle. By adjusting the control switch control signal, each current source is gradually turned off to achieve a gradual reduction in the current of the inverting amplifier.

[0034] Preferably, the implementation process of S3 is as follows: in response to abnormal power failure, the power supply V DD Power supply; circuit at V DD When power is off, the power switching circuit automatically switches to the power supply V powered by the 1mF capacitor BAK powered, while the power supply V DD After power is restored, it automatically switches back to power supply V DD powered by.

[0035] Preferably, the power switching circuit in S3 uses a resistor voltage divider network to DDAfter voltage division and signal driving capability enhancement through voltage follower, the voltage is input to the comparator, which compares the voltage division result with a stable 1.2V reference voltage and controls the power supply gating logic unit according to the comparison result to realize power supply V DD With power supply V BAK Automatic switching between.

[0036] Compared with the prior art, the present invention provides a battery-based RTC clock measurement and control circuit and method, which has the following beneficial effects:

[0037] The bias circuit designed by the present invention is combined with a bipolar junction transistor to effectively improve the accuracy and stability of power management. Based on the principle of capacitor charging and discharging, a clock monitoring circuit is designed to achieve accurate detection of clock signals. A current-adjustable Pierce oscillator is designed to optimize the oscillator power consumption and dynamically adjust the path, greatly reducing the power consumption of the RTC system. In response to abnormal power outages in the RTC system, the present invention proposes an emergency power supply solution that combines a 3V button battery or a large-capacity capacitor, and seamlessly integrates it with a configurable crystal oscillator. When an abnormal power outage occurs, the system can quickly switch to the emergency power supply mode and maintain the continuous stability of the system clock. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 The clock monitoring circuit diagram mentioned in Embodiment 1 of the present invention;

[0039] Figure 2 The low power consumption control circuit diagram mentioned in Embodiment 1 of the present invention;

[0040] Figure 3 This is a block diagram of the power switching circuit mentioned in Embodiment 1 of the present invention;

[0041] Figure 4 This is a flow chart of the method mentioned in Example 2 of the present invention;

[0042] Figure 5 The Pierce oscillator starting waveform diagram mentioned in Embodiment 3 of the present invention;

[0043] Figure 6 This is a simulation waveform diagram of the standby capacitor charging circuit mentioned in Embodiment 3 of the present invention;

[0044] Figure 7 This is a waveform diagram of a power failure emergency processing circuit under battery power supply conditions mentioned in Embodiment 3 of the present invention;

[0045] Figure 8 This is the overall layout of the RTC circuit mentioned in Example 3 of the present invention. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0047] The bias circuit designed by the present invention is combined with a bipolar junction transistor to effectively improve the accuracy and stability of power management. Based on the principle of capacitor charging and discharging, a clock monitoring circuit is designed to achieve accurate detection of clock signals; a current-adjustable Pierce oscillator is designed to optimize the oscillator power consumption and dynamically adjust the path, greatly reducing the power consumption of the RTC system. In response to abnormal power outages in the RTC system, the present invention proposes an emergency power supply solution that combines a 3V button battery or a large-capacity capacitor, and seamlessly integrates it with a configurable crystal oscillator. When an abnormal power outage occurs, the system can quickly switch to the emergency power supply mode and maintain the continuous stability of the system clock. Specifically including the following contents.

[0048] Embodiment 1:

[0049] See also Figure 1-3 , this embodiment provides a battery RTC clock measurement and control circuit, including: a bias circuit, a clock monitoring circuit, a low power consumption control circuit and a power switching circuit;

[0050] The output end of the bias circuit is connected to the input end of the clock monitoring circuit; the INV2 output end of the clock monitoring circuit is connected to the switch signal input end of the Pierce oscillator of the low power control circuit; the output end of the mirror current source of the low power control circuit is connected to the input end of the comparator of the power switching circuit;

[0051] The clock monitoring circuit includes a first inverter INV1, a first switch sw1, a second switch sw2, a first monitoring capacitor C1, a second monitoring capacitor C2, a monitoring resistor R, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3 and a second inverter INV2;

[0052] The first end of INV1 is the input end, connected to the first end of sw1, the second end of INV1 is connected to the first end of sw2, the third end of sw1 is connected to the second end of sw2, the second end of sw1 is connected to the second end of R and the first end of the first monitoring capacitor C1, and the first end of R is connected to the power supply V DD The third terminal of sw2 is connected to the source of M3, the first terminal of the second monitoring capacitor C2 and the gate of M2, the drain of M3, the second terminal of the second monitoring capacitor C2 and the drain of M2 are grounded, the source of M2 is connected to the source of M1 and the first terminal of INV2, and the second terminal of INV2 is the output terminal;

[0053] During the charging and discharging process, when sw1 is turned on, the power supply charges the first monitoring capacitor C1 through sw1; when sw2 is turned on, the second monitoring capacitor C2 starts to be charged, and M3 provides a pull current to discharge the second monitoring capacitor C2; by adjusting the capacity of the first monitoring capacitor C1 and the second monitoring capacitor C2 and the pull current of M3, the net charge amount of the second monitoring capacitor C2 in each cycle can be accurately controlled.

[0054] The low power consumption control circuit includes a sixth NMOS transistor N6 to an eleventh NMOS transistor N6 to N11, a sixth PMOS transistor P6 to an eleventh PMOS transistor P6 to P11, a feedback resistor R f ; The first oscillator capacitor C1, the second oscillator capacitor C2 and the crystal oscillator; The crystal oscillator connects C0 and L M , C M and R M Obtained in parallel.

[0055] The drain of P7 is connected to the first control voltage V bias1 , P7 gate is connected to N6 gate and state input terminal M, N6 drain is grounded, P7 source and N6 source are connected to P8 gate, P9 gate and P10 gate, P8 drain, P9 drain and P10 drain are connected to power supply V DD , the source of P8 is connected to the first terminal of CT0, the source of P9 is connected to the first terminal of CT1, the source of P10 is connected to the first terminal of CT2, the second terminals of CT0, CT1 and CT2 are all connected to the drain of P11, and the gate of P11 is connected to R f The first terminal, the first terminal of the first oscillator capacitor C1, the first terminal of the crystal oscillator and the gate of N11; the source of P11 is connected to R f The second end, the second end of the crystal oscillator, the first end of the second oscillator capacitor C2 and the source of N11, the second end of the first oscillator capacitor C1 and the second end of the second oscillator capacitor C2 are all grounded;

[0056] The drain of N7 is connected to the second control voltage V bias2 , N7 gate is connected to P6 gate and state input terminal M, P6 drain is connected to power supply V DD , the source of N7 and the source of P6 are connected to the gate of N8, the gate of N9 and the gate of N10, the drain of N8, the drain of N9 and the drain of N10 are grounded, the source of N8 is connected to the first terminal of CT0, the source of N9 is connected to the first terminal of CT1, the source of N10 is connected to the first terminal of CT2, the second terminal of CT0, the second terminal of CT1 and the second terminal of CT2 are all connected to the drain of N11;

[0057] P11 and N11 are used as the reverse amplifier core to form the reverse amplifier, which is mainly used to provide the necessary gain for the reverse amplifier. P8~P10 and N8~N10 are used as mirror current sources to provide dynamically adjustable bias current for the reverse amplifier;

[0058] The power switching circuit includes a first control resistor R1, a second control resistor R2, a voltage follower and a comparator; the first terminal of R1 is connected to the power supply V DD The second end of R1 and the first end of R2 are connected to the positive input of the voltage follower, the second end of R2 is grounded, the output of the voltage follower is connected to its negative input and the positive input of the comparator, the negative input of the comparator is provided with a 1.2V reference voltage through a bandgap reference circuit, and the comparator is also connected to the power supply V H The comparator output is input to the power supply gating logic unit through level shifting, and the power supply gating logic unit is also connected to the power supply V DD and power supply V BAK , the power supply gate logic unit output gate power supply V S The LDO circuit is also connected to the external control EN18 pin and the backup voltage V CORE Pin.

[0059] In order to prevent frequent switching caused by power supply voltage fluctuations, a hysteresis comparator is used in the power supply switching circuit. Due to the operating voltage domain limitation of the hysteresis comparator, when the high level is lower than V DD and V BAK The higher one is 0.6V. Directly controlling the switch tube may cause leakage or current backflow problems. The logic circuit is introduced to optimize the control signal of the switch tube to ensure that the switch tube can be completely cut off or turned on under any power supply conditions, thereby avoiding the occurrence of current backflow.

[0060] As a key pin of the chip, the EN18 pin is not only used to enable the 1.8V standard power supply, but also has an external control function; when the EN18 pin is pulled low externally, the LDO circuit is disabled, and the V CORE The pins provide voltage for the configurable oscillator, interface circuits, timing circuits, and associated registers, thereby taking full advantage of the low power consumption characteristics of the crystal oscillator.

[0061] Embodiment 2:

[0062] Reference Figure 1-4 A battery-based RTC clock measurement and control method is applied to the battery-based RTC clock measurement and control circuit described in Example 1, and includes the following steps:

[0063] S1: Control the bias circuit and clock monitoring circuit of the system. The bias circuit uses a reverse proportional MOS tube to reduce the error during the startup process; the clock monitoring circuit uses the principle of capacitor charging and discharging to control the clock monitoring circuit to detect the clock signal. The details are as follows:

[0064] The ideal reference voltage is generally replaced by a voltage source or a current source. The reference voltage is based on the bias circuit of the basic voltage divider circuit and is calculated by the following formula:ref With the power supply voltage V DD The proportional relationship between: Among them, R1 and R2 are the equivalent resistance values ​​of the reference voltage and the power supply voltage respectively;

[0065] In order to weaken the interference of the power supply voltage on the reference voltage, the equivalent resistor R1 of the reference voltage and the equivalent resistor R2 of the power supply voltage are replaced by bipolar junction transistors with base and collector short-circuited; the core of the improvement is to use the characteristics of active devices to transform the reference voltage into a form that is weakly related to the power supply voltage. Calculating the proportional relationship between the reference voltage and the power supply voltage helps to understand the quantitative relationship between the two, so as to better predict and control the output of the circuit. Through quantitative analysis of sensitivity: After using bipolar junction transistor, the reference voltage V ref For power supply voltage V DD The sensitivity of the reference voltage is significantly reduced, thereby enhancing the stability of the reference voltage: represents partial derivative.

[0066] Where, T is the absolute temperature; k is the Boltzmann constant; q is the charge constant; I S is the reverse saturation current, and R is the resistance of resistors R1 and R2 in parallel; the sensitivity values ​​before and after the use of bipolar junction transistors are calculated, and combined with the actual circuit simulation and delay test results, to determine whether the bipolar junction transistor can reduce the influence of the power supply voltage on the reference voltage. For example, if the sensitivity is 0.5 when the bipolar junction transistor is not used, it means that the reference voltage changes by 0.5V for every 1V change in the power supply voltage; and after the bipolar junction transistor is used, the sensitivity is 0.1, that is, the reference voltage only changes by 0.1V for every 1V change in the power supply voltage. This shows that the bipolar junction transistor can effectively reduce the influence of the power supply voltage on the reference voltage, thereby reducing the error during the startup process.

[0067] The above formula can more intuitively understand that the use of bipolar junction transistors can effectively reduce the impact of the power supply voltage on the reference voltage and reduce the error during the startup process.

[0068] Reference Figure 1 The clock monitoring circuit is designed based on the principle of capacitor charging and discharging, and the functional requirements are achieved through a specially designed circuit structure. The clock signal and its inverted signal output by the inverter INV1 are used to control the two switches (sw1 and sw2) respectively to ensure that the two states are complementary. Driven by the clock signal, the two switches are turned on alternately to control the charging process of the first monitoring capacitor C1 and the second monitoring capacitor C2.

[0069] During the charging and discharging process, when sw1 is turned on, the power supply charges the first monitoring capacitor C1 through sw1; when sw2 is turned on, the second monitoring capacitor C2 starts to charge, and M3 provides a pull current to discharge the second monitoring capacitor C2. By adjusting the capacity of the first monitoring capacitor C1 and the second monitoring capacitor C2 and the pull current of M3, the net charge amount of the second monitoring capacitor C2 in each cycle can be accurately controlled. The calculation of the charge amount Q charged in the second monitoring capacitor C2 by the circuit in a single cycle is as follows: Wherein, Q1 is the charge amount charged to the first monitoring capacitor C1 in a single cycle; Q2 is the pull current I through M3 in a single cycle L The amount of released charge; τ is the period; η is the duty cycle.

[0070] By adjusting the initial voltage of the second monitoring capacitor C2 or the start-up voltage of M2, it can be ensured that the cumulative increase in the voltage at point A is not enough to trigger the conduction of M2 in the first three clock cycles, thereby achieving a startup delay. The capacity of the first monitoring capacitor C1 needs to be large enough to ensure that under normal circumstances, each cycle can provide sufficient net charge for the second monitoring capacitor C2; the pull current of M3 adjusts the discharge rate of the second monitoring capacitor C2, and the performance of the detection clock can be further improved by adjusting its value. The clock monitoring mechanism in the design process achieves accurate detection of the oscillator output clock by cleverly utilizing the principle of capacitor charging and discharging, combined with precise circuit parameter settings.

[0071] S2: The low power control circuit uses the digital circuit control technology of the current adjustable Pierce oscillator to achieve ultra-low power control of the RTC clock measurement and control circuit; the details are as follows:

[0072] Reference Figure 2 , based on the traditional Pierce oscillator, an improved Pierce oscillator circuit architecture is designed. Through the adjustable current bias mechanism, a series of switch control signals are selected to control the on and off of the MOS switch;

[0073] MOS tubes P8~P10 and N8~N10 are used as mirror current sources, and their width-to-length ratio is set to 1:2:4, which is used to provide dynamically adjustable bias current for the reverse amplifier. At the same time, a key state flag signal M is introduced. When M is low, it indicates that the oscillator is in the start-up stage. At this time, by setting CT0~CT2 to a high level, setting N6 and P6 switches to conduct, turning off N7 and P7, and configuring the gate potential of P8~P10 to zero, the maximum variable current supply is achieved, thereby accelerating the start-up process;

[0074] Until the oscillation is stable, the state flag signal M jumps to a high level, the N6 and P6 switches are turned off, the N7 and P7 switches are turned on, and the gates of P8 to P10 are adjusted to V bias, effectively reducing the current supply and allowing the oscillator to enter a stable oscillation state with low power consumption.

[0075] The current ratio of the mirror current source composed of P8~P10 and N8~N10 follows the binary increasing principle. By finely adjusting the control signals CT0~CT2, each current source is gradually turned off to achieve a gradual reduction in the current of the inverting amplifier, thereby effectively reducing the power consumption of the overall circuit without affecting the oscillation stability.

[0076] S3: In case of abnormal power failure, the power switching circuit uses an auxiliary power system powered by a 3V button battery or a 1mF capacitor to handle power failure emergencies.

[0077] Reference Figure 3 , for a wide voltage range (2.5V~5.5V, typical value is 3.3V) of V DD The power failure emergency processing circuit of the auxiliary power system powered by a 3V button battery or a 1mF capacitor ensures that the RTC clock circuit can continue to work stably when either power supply is valid. DD Automatically switches to V BAK powered, while at V BAK After power is restored, it automatically switches back to V DD powered by.

[0078] The core of the power switching principle is to use a resistor divider network to DD After voltage division and signal driving capability enhancement through voltage follower, the signal is input into a comparator with hysteresis characteristics. The comparator compares the voltage division result with a stable 1.2V reference voltage and controls the power supply gating logic according to the comparison result to achieve V DD With V BAK Intelligent switching between

[0079] EN18 is used to enable the 1.8V standard power supply and also has an external control function. When EN18 is pulled low externally, the LDO circuit is disabled and the V CORE The pins provide voltage for the configurable oscillator, interface circuits, timing circuits, and associated registers, thereby taking full advantage of the low power consumption characteristics of the crystal oscillator.

[0080] Embodiment 3:

[0081] The Cadence EDA platform is used to analyze the transient state of the RTC system bias circuit. Through transient analysis of the circuit, it can be started quickly and accurately when the power supply voltage is 1.8V and the temperature is in the range of -50℃ to 100℃.

[0082] By adjusting the simulation parameters, setting the flag signal M to an inactive state (i.e., set to 0), and setting the variable current to the maximum value, the transient behavior of the Pierce oscillator in the start-up phase is simulated and analyzed. The simulation results are shown in Figure 5 As shown. Under the TT process condition of 25°C and driven by a 1.8V power supply voltage, the oscillator quickly completes the start-up process in about 112 milliseconds and outputs a stable full-amplitude sine wave signal. After the oscillator is working stably, the measured data shows that the crystal oscillator itself consumes only about 248.9mA of current, and the total current of the entire RTC circuit is only 290.6mA. Table 1 shows the power consumption values ​​of common traditional design circuits. The results show that the method adopted by the present invention is more advantageous in reducing power consumption.

[0083] Table 1 Performance indicators of different crystal oscillator circuits

[0084]

[0085] In addition, during the simulation verification of the entire circuit, a BR2330A button battery is used as the power supply battery (a CR2032 button battery can also be used for simulation verification), and a 1mF capacitor is used to provide continuous and stable voltage support for the RTC circuit. In the case of abnormal power failure in the above two power supply methods, the simulation results are as follows Figure 6 shown.

[0086] In order to analyze the efficiency of the backup capacitor charging mechanism, the main power supply V DD Set to 5.5V, and V BAK A 1mF energy storage capacitor is connected. Simulation V DD In the scenario where the voltage rises rapidly to 5.5V within 10ms, V BC The signal is activated at 5 seconds, triggering the charging process. During the entire 100-second simulation period, V BC After the signal is activated, the capacitor starts to charge with an initial current of about 160A, and it takes about 22 seconds to reach the preset 3.63V threshold, at which point the charging circuit automatically shuts down. This cycle fully demonstrates the charging circuit's ability to accurately control the charging cycle and threshold.

[0087] Reference Figure 7 The performance of the battery-powered mode is tested by the power-off emergency handling circuit. A 3V button battery BR2330A is used as the backup power supply, and a 600Ω equivalent resistor is used to simulate the load condition. Under the standard environment of 25℃, the simulation time is set to 400ms, covering V DD The simulation results show that as V DD From 0V to 5.5V, when the threshold is reached, VDD 2.6V, and starts to provide power support for the circuit. CORE The voltage quickly stabilizes at 1.8V. Then, at V BAK The voltage reaches 3V, V DD Starts to decrease when V DD When it drops to about 2.5V, the power supply switches to V BAK , during this process V CORE Although the voltage fluctuated briefly, it quickly returned to stability.

[0088] The layout design of the real-time clock RTC is constructed in the Virtuoso Layout Editor environment of the Cadence software platform. The clock chip used is the RX8111CE chip of Epson (other models of Epson chips, such as RA8000CE, RA8900CE, etc., can also be used); the size of the RTC design layout in the present invention is 780um*1016um, and the overall layout of the design is as follows Figure 8 As shown, during the layout design process, the RTC wiring method was optimized, which effectively reduced the delay in the signal transmission process and improved the synchronization and accuracy of the clock signal.

[0089] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A battery-based RTC clock measurement and control circuit, characterized in that: Including bias circuit, clock monitoring circuit, low power control circuit and power switching circuit; The output end of the bias circuit is connected to the input end of the clock monitoring circuit; the second inverter output end of the clock monitoring circuit is connected to the switch signal input end of the Pierce oscillator of the low power control circuit; the output end of the mirror current source of the low power control circuit is connected to the input end of the comparator of the power switching circuit; The low power consumption control circuit includes a sixth NMOS transistor N6 to an eleventh NMOS transistor N11, a sixth PMOS transistor P6 to an eleventh PMOS transistor P11, a feedback resistor R f ; A first oscillator capacitor C1, a second oscillator capacitor C2 and a crystal oscillator; The drain of the seventh PMOS tube P7 is connected to the first control voltage V bias1 , the gate of the seventh PMOS tube P7 is connected to the gate of the sixth NMOS tube N6 and the state input terminal; the drain of the sixth NMOS tube N6 is grounded, the source of the seventh PMOS tube P7 and the source of the sixth NMOS tube N6 are connected to the gate of the eighth PMOS tube N8, the gate of the ninth PMOS tube P9 and the gate of the tenth PMOS tube P10, the drain of the eighth PMOS tube P8, the drain of the ninth PMOS tube P9 and the drain of the tenth PMOS tube P10 are connected to the power supply V DD The source of the eighth PMOS tube P8 is connected to the first end of the first control signal terminal CT0, the source of the ninth PMOS tube P9 is connected to the first end of the second control signal terminal CT1, the source of the tenth PMOS tube P10 is connected to the first end of the third control signal terminal CT2, the second end of the first control signal terminal CT0, the second end of the second control signal terminal CT1 and the second end of the third control signal terminal CT2 are all connected to the drain of the eleventh PMOS tube P11, and the gate of the eleventh PMOS tube P11 is connected to the feedback resistor R f The first end, the first end of the first oscillator capacitor C1, the first end of the crystal oscillator and the gate of the eleventh NMOS tube N11; the source of the eleventh PMOS tube P11 is connected to the feedback resistor R f The second end, the second end of the crystal oscillator, the first end of the second oscillator capacitor C2 and the source of the eleventh NMOS transistor N11, the second end of the first oscillator capacitor C1 and the second end of the second oscillator capacitor C2 are all grounded; The drain of the seventh NMOS tube N7 is connected to the second control voltage V bias2 The gate of the seventh NMOS tube N7 is connected to the gate and state input terminal of the sixth PMOS tube P6, and the drain of the sixth PMOS tube P6 is connected to the power supply V DD , the source of the seventh NMOS tube N7 and the source of the sixth PMOS tube P6 are connected to the gate of the eighth NMOS tube N8, the gate of the ninth NMOS tube N9 and the gate of the tenth NMOS tube N10, the drain of the eighth NMOS tube N8, the drain of the ninth NMOS tube N9 and the drain of the tenth NMOS tube N10 are grounded, the source of the eighth NMOS tube N8 is connected to the first end of the first control signal terminal CT0, the source of the ninth NMOS tube N9 is connected to the first end of the second control signal terminal CT1, the source of the tenth NMOS tube N10 is connected to the first end of the third control signal terminal CT2, the second end of the first control signal terminal CT0, the second end of the second control signal terminal CT1 and the second end of the third control signal terminal CT2 are all connected to the drain of the eleventh NMOS tube N11; The power switching circuit includes a first control resistor R1, a second control resistor R2, a voltage follower and a comparator; the first control resistor R1 is connected to a power source V DD The second end of the first control resistor R1 and the first end of the second control resistor R2 are connected to the positive input end of the voltage follower, the second end of the second control resistor R2 is grounded, the output end of the voltage follower is connected to its negative input end and the positive input end of the comparator, the negative input end of the comparator is provided with a 1.2V reference voltage through a bandgap reference circuit, and the comparator is also connected to the positive input end of the comparator through the power supply V H The comparator output is input to the power supply gating logic unit through level shifting, and the power supply gating logic unit is also connected to the power supply V DD and power supply V BAK , the power supply gate logic unit output gate power supply V S The LDO circuit is also connected to the external control EN18 pin and the backup voltage V CORE Pin.

2. A battery-based RTC clock measurement and control circuit according to claim 1, characterized in that: The clock monitoring circuit includes a first inverter INV1, a first switch sw1, a second switch sw2, a first monitoring capacitor C1, a second monitoring capacitor C2, a monitoring resistor R, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3 and a second inverter INV2; The first end of the first inverter INV1 is an input end, connected to the first end of the first switch sw1, the second end of the first inverter INV1 is connected to the first end of the second switch sw2, the third end of the first switch sw1 is connected to the second end of the second switch sw2, the second end of the first switch sw1 is connected to the second end of the monitoring resistor R and the first end of the first monitoring capacitor C1, and the first end of the monitoring resistor R is connected to the power supply V DD and the drain of the first MOS tube M1, and the second end of the first monitoring capacitor C1 is grounded; the third end of the second switch sw2 is connected to the source of the third MOS tube M3, the first end of the second monitoring capacitor C2 and the gate of the second MOS tube M2, the drain of the third MOS tube M3, the second end of the second monitoring capacitor C2 and the drain of the second MOS tube M2 are grounded, the source of the second MOS tube M2 is connected to the source of the first MOS tube M1 and the first end of the second inverter INV2, and the second end of the second inverter INV2 is the output end.

3. A battery-based RTC clock measurement and control circuit according to claim 1, characterized in that: The crystal oscillator includes a built-in reference capacitor C0, a built-in inductor L M 、Built-in capacitor C M and built-in resistor R M , the built-in inductor L M 、Built-in capacitor C M and built-in resistor R M Firstly connect them in series, and then connect them in parallel with the built-in reference capacitor C0 to obtain the crystal oscillator; The comparator in the power switching circuit adopts a hysteresis comparator and outputs a control signal through a power gating logic unit.

4. A battery-based RTC clock measurement and control circuit according to claim 3, characterized in that: The EN18 pin is used to enable the 1.8V standard power supply and to implement external control; when the EN18 pin is pulled low externally, the LDO circuit is disabled and the V CORE The pin provides voltage.

5. A battery-based RTC clock measurement and control method, characterized in that: The battery-based RTC clock measurement and control circuit is applied to any one of claims 1 to 4, and comprises the following steps: S1: Control the bias circuit and the clock monitoring circuit. The bias circuit uses a bipolar junction transistor to reduce the error during the startup process. The clock monitoring circuit uses the capacitor charging and discharging principle to control the clock monitoring circuit to detect the clock signal. S2: The low power consumption control circuit adopts the digital circuit control technology of the current adjustable Pierce oscillator to realize the ultra-low power consumption control of the RTC clock measurement and control circuit; S3: In case of abnormal power outage, the power switching circuit uses the auxiliary power system to perform emergency power failure processing.

6. A battery-based RTC clock measurement and control method according to claim 5, characterized in that: In S1, the bias circuit uses a bipolar junction transistor to reduce the error during the startup process as follows: S101: By formula Calculate the reference voltage V ref With the power supply voltage V DD The proportional relationship between them, where R1 and R2 are the reference voltage V ref and the power supply voltage V DD The equivalent resistance value of S102: Set the reference voltage V ref The equivalent resistance R1 and the power supply voltage V DD The equivalent resistor R2 is replaced by a bipolar junction transistor with the base and collector short-circuited; through the formula The reference voltage V ref Transformed to the power supply voltage V DD The form of weak correlation, where T is the absolute temperature; k is the Boltzmann constant; q is the charge constant; I S is the reverse saturation current, R is the resistance of resistors R1 and R2 in parallel; S103: By formula Calculate the signal sensitivity and use the formula The signal sensitivity is converted into is the signal sensitivity; S104: Calculate the signal sensitivity values ​​of the bipolar junction transistor before and after replacement, and select a bipolar junction transistor whose sensitivity after replacement is lower than that before replacement, so as to reduce the error in the startup process.

7. A battery-based RTC clock measurement and control method according to claim 6, characterized in that: In S1, the process of controlling the clock monitoring circuit is as follows: The first inverter INV1 is used to output a clock signal and its inverted signal to control the first switch sw1 and the second switch sw2 respectively, ensuring that the states of the two are complementary; driven by the clock signal, the two switches are turned on alternately to control the charging process of the first monitoring capacitor C1 and the second monitoring capacitor C2 respectively; during the charging and discharging process, when the first switch sw1 is turned on, the power supply charges the first monitoring capacitor C1 through the first switch sw1; when the second switch sw2 is turned on, the second monitoring capacitor C2 starts to charge, and at the same time, the third MOS tube M3 in the clock monitoring circuit provides a pull current to discharge the second monitoring capacitor C2. The calculation formula for the charge amount Q charged in the second monitoring capacitor C2 by the circuit in a single cycle is as follows: Wherein, Q1 is the charge amount charged to the first monitoring capacitor C1 in a single cycle; Q2 is the pull current I through the third MOS tube M3 in a single cycle. L The amount of released charge; τ is the period; η is the duty cycle.

8. A battery-based RTC clock measurement and control method according to claim 7, characterized in that: The S2, the feedback resistor R f The two ends of the crystal oscillator are respectively connected in parallel with an eleventh NMOS tube N11 and an eleventh PMOS tube P11, and the eleventh NMOS tube N11 and the eleventh PMOS tube P11 are used as reverse amplification cores to form a reverse amplifier, and provide gain for the reverse amplifier; Through an adjustable current bias mechanism, the on and off of a plurality of MOS tubes are controlled by a switch control signal; three NMOS tubes and three PMOS tubes are used as mirror current sources, and the width-to-length ratios of the three NMOS tubes and the three PMOS tubes are all set to a ratio of 1:2:4, so as to provide a dynamically adjustable bias current for the reverse amplifier; the three NMOS tubes include an eighth NMOS tube N8 to a tenth NMOS tube N10, and the three PMOS tubes include an eighth PMOS tube P8 to a tenth PMOS tube P10; At the same time, a state flag signal M is introduced, and the state flag signal M refers to the signal at the state input end; when the state flag signal M is at a low level, it indicates that the oscillator is in the start-up stage. At this time, by setting the switch control signal to a high level, the sixth NMOS tube N6 and the sixth PMOS tube P6 switches at the input end of the state flag signal M are turned on, and the seventh NMOS tube N7 and the seventh PMOS tube P7 are turned off. At the same time, the gate potentials of the three PMOS tubes are configured to be zero, so as to realize the supply of the maximum variable current, thereby accelerating the start-up process; Until the oscillation is stable, the state flag signal M jumps to a high level, the sixth NMOS tube N6 and the sixth PMOS tube P6 are turned off, the seventh NMOS tube N7 and the seventh PMOS tube P7 are turned on, and the gates of the three PMOS tubes are adjusted to the first control voltage V bias1 , reducing the current supply, so that the oscillator enters a stable oscillation state with low power consumption; the mirror current source composed of the three NMOS tubes and the three PMOS tubes has a current ratio that follows the binary increasing principle. By adjusting the control switch control signal, each current source is gradually turned off to achieve a gradual reduction in the current of the inverting amplifier.

9. A battery-based RTC clock measurement and control method according to claim 8, characterized in that: The implementation process of S3 is as follows: In case of abnormal power failure, the power supply V DD Power supply; the circuit is powered by V DD When power is off, the power switching circuit automatically switches to the power supply V powered by the 1mF capacitor BAK powered, and at the power supply V DD Automatically switches back to power supply V after power is restored DD powered by.

10. A battery-based RTC clock measurement and control method according to claim 9, characterized in that: The power switching circuit in S3 uses a resistor voltage divider network to DD After voltage division and signal driving capability enhancement through voltage follower, the voltage is input to the comparator, which compares the voltage division result with a stable 1.2V reference voltage and controls the power supply gating logic unit according to the comparison result to realize power supply V DD With power supply V BAK Automatic switching between.

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