Method for improving spurious suppression of phase-locked loop based on digital mode
By modifying the phase-detection current output of the phase-locked loop in a vector network analyzer and modifying the loop bandwidth equivalently, the contradiction between frequency hopping speed and stray suppression performance is solved, and better stray suppression effect and fast locking are achieved. In fact, the entire process is controlled by the program, avoiding hardware modifications.
Patent Information
- Application Number
- CN202411141542.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-20
- Publication Date
- 2024-12-24
AI Technical Summary
The prior art is difficult to improve the frequency hopping speed and stray suppression performance in vector network analyzers at the same time. It usually requires a compromise choice of loop bandwidth, which cannot achieve better frequency hopping speed and stray suppression performance, and the cost of modifying hardware parameters is high. And complicated.
By modifying the phase-detection current output of the phase-locked loop, the loop bandwidth is equivalently modified, and the digital register configuration algorithm is used to flexibly control the loop bandwidth, and the control algorithm is optimized to achieve fast phase-locking and ideal stray suppression effects. There is no need for the entire process Hardware modification.
It realizes flexible control of loop bandwidth without changing the hardware circuit, improves stray suppression effect, and ensures frequency hopping speed, significantly improves stray suppression performance, such as increasing from 19dB to 39dB, with significant results.
Smart Images
Figure CN119182399A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the field of testing technology, and in particular relates to a method for improving spurious suppression of a phase-locked loop based on a digital method. Background Art
[0002] As users' requirements for the measurement accuracy of vector network analyzers continue to increase, and functions such as spectrum testing and THz spread spectrum testing continue to be enriched, vector network analyzers require that the spurious suppression indicators of the excitation source and local oscillator source continue to improve while achieving fast scanning. However, frequency hopping speed and spurious suppression are usually contradictory.
[0003] Modifying the phase-locked loop bandwidth can improve boundary spurious. In an actual phase-locked loop circuit, the most direct way to modify the loop bandwidth is to modify the loop filter. The loop filter is generally composed of components such as resistors and capacitors. Modifying the hardware parameters will be costly. The key is that reducing the loop bandwidth will increase the phase-locking time, affect the frequency hopping speed, and cannot simultaneously meet the requirements of the vector network analyzer excitation source and local oscillator source for scanning speed and spurious suppression.
[0004] The fractional phase-locked loop of the traditional vector network analyzer excitation source and local oscillator source generally adopts a fixed loop filter, with a relatively fixed loop bandwidth, a small loop bandwidth, good spurious suppression, and a relatively slow frequency hopping speed. The loop bandwidth is large, the frequency modulation speed is fast, but the spurious suppression is relatively poor, and the frequency hopping speed and spurious suppression are contradictory. In this case, we can only choose a compromise loop bandwidth based on the vector network analyzer user test requirements and product performance indicators, taking into account both the frequency hopping speed and spurious suppression performance, with a faster frequency hopping speed and a better spurious suppression level.
[0005] If the existing solution attempts to increase the loop bandwidth and improve the frequency hopping speed, the spurious suppression will inevitably deteriorate. On the other hand, if the loop bandwidth is reduced and the spurious suppression effect is improved, the frequency hopping speed will inevitably be reduced.
[0006] The prior art has the following deficiencies:
[0007] 1. The existing technology generally changes the loop bandwidth by modifying the hardware parameters of the loop filter to achieve the purpose of improving spurious suppression, which is relatively complex and has a certain cost;
[0008] 2. The existing technology generally selects the loop bandwidth by compromise, adopts a fixed loop filter, and takes both the frequency hopping speed and the spurious suppression performance into consideration, but cannot achieve a better frequency hopping speed and spurious suppression performance. Summary of the invention
[0009] In view of the above technical problems existing in the prior art, the present invention proposes a method for improving the spurious suppression of a phase-locked loop based on a digital method, which has a reasonable design, overcomes the shortcomings of the prior art, and has a good effect.
[0010] In order to achieve the above object, the present invention adopts the following technical solution:
[0011] A method for improving spurious suppression of a phase-locked loop based on a digital method comprises the following steps:
[0012] Step 1: Set a large phase-comparison current to increase the loop bandwidth;
[0013] Step 2: Set new frequency data;
[0014] Step 3: Wait for phase lock;
[0015] Step 4: After capture, switch to a small phase-comparison current;
[0016] Step 5: Wait for the loop to stabilize;
[0017] Step 6: Collect measurement data after stabilization, and then execute step 1.
[0018] Preferably, the loop gain can be modified by modifying the phase-comparison current output of the phase-locked loop, which is equivalent to modifying the loop bandwidth.
[0019] Beneficial technical effects brought by the present invention:
[0020] The present invention proposes a method of reducing the phase-locked current and improving the spurious by modifying the digital register and a register configuration algorithm that takes into account the phase-locked speed and spurious suppression of the phase-locked loop; by optimizing the configuration of the phase-locked loop phase detector digital register, the phase-locked current output of the phase detector is reduced, the loop gain is equivalently reduced, and thus the loop bandwidth is equivalently reduced, so as to achieve the purpose of improving the sideband spurious. In a digital way, the control algorithm is optimized, and the flexible control of the loop bandwidth during the phase-locked process can ensure fast phase locking and achieve a relatively ideal spurious suppression effect. The entire control process is completed by the program without modifying the hardware circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 is a flow chart of the method of the present invention;
[0022] Figure 2 This is a schematic diagram of the spurious suppression curve of the fractional phase-locked loop 16.0001GHz before optimization;
[0023] Figure 3 Schematic diagram of the optimized fractional phase-locked loop 16.0001GHz spurious suppression curve. DETAILED DESCRIPTION
[0024] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:
[0025] The present invention proposes a method for improving the spurious suppression of a phase-locked loop by optimizing the control algorithm and flexibly configuring the phase detector register in a digital manner without changing the loop filter of the phase-locked loop. Figure 1 shown.
[0026] The fractional phase-locked loop phase detector provides a way to modify the phase current in the form of a digital register. By modifying the phase current output of the phase detector, the loop gain can be modified, which is equivalent to modifying the loop bandwidth. After testing, reducing the phase current value can achieve the purpose of improving the sideband spurious.
[0027] Reducing the phase-lock current essentially reduces the loop bandwidth. The problem with reducing the loop bandwidth is that the phase-lock time is prolonged, affecting the frequency hopping speed. The phase-lock time includes the capture time and the stabilization time. The capture speed, such as pull-in, sweep frequency, or capture with the help of the frequency detector, can be improved by widening the loop bandwidth.
[0028] The specific solutions are as follows:
[0029] Use a large phase-locked current to increase the loop bandwidth and enable the phase-locked loop to capture quickly;
[0030] Set new frequency data and wait for phase lock (capture time);
[0031] After capture, switch to a small phase-comparison current, reduce the loop bandwidth, and wait for the loop to reach a stable state;
[0032] After stabilization, the measurement data is collected, and then a large phase-locked current is set to increase the loop bandwidth, set new frequency data, and repeat the cycle.
[0033] By optimizing the control algorithm in a digital way, the flexible control of the loop bandwidth during the phase-locking process ensures fast phase-locking and an ideal state for spurious suppression. Figure 2 , Figure 3 As shown in the figure, the spurious suppression of the fractional phase-locked loop output 16.0001GHz was only 19dB before optimization. After optimization by the above method, the spurious suppression reached 39dB, an improvement of about 20dB, with obvious effect, and the frequency hopping speed was not affected. The entire control process is completed by the program without modifying the hardware circuit.
[0034] The present invention reduces the phase detector current output of the phase detector by optimizing the configuration of the digital register of the phase detector of the phase-locked loop, equivalently reduces the loop gain, thereby equivalently reducing the loop bandwidth, and achieving the purpose of improving the sideband spurious. In a digital way, the control algorithm is optimized, and the flexible control of the loop bandwidth during the phase-locking process can not only ensure fast phase locking, but also achieve a relatively ideal spurious suppression effect. The entire control process is completed by the program without modifying the hardware circuit.
[0035] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by technicians in this technical field within the essential scope of the present invention should also fall within the protection scope of the present invention.
Claims
1. A method for improving spurious suppression of a phase-locked loop based on a digital method, characterized in that: The steps include: Step 1: Set a large phase-comparison current to increase the loop bandwidth; Step 2: Set new frequency data; Step 3: Wait for phase lock; Step 4: After capture, switch to a small phase-comparison current; Step 5: Wait for the loop to stabilize; Step 6: Collect measurement data after stabilization, and then execute step 1.
2. The method for improving spurious suppression of a phase-locked loop based on a digital method according to claim 1, characterized in that: By modifying the phase-locked loop's phase-comparison current output, the loop gain can be modified, which is equivalent to modifying the loop bandwidth.