Delay detection method and device

Abstract

The invention provides a delay detection method, and relates to the technical field of communication, and the method comprises the steps: starting a switch matrix after a preset period after a first NIC sends a detection code and a detection message, and enabling a second NIC to receive an incomplete detection message at the beginning. And under the condition that the second NIC receives the incomplete detection message, the first NIC sends a longer detection code, so that the second NIC is more likely to receive the complete detection message. When the second NIC receives the complete detection message, the delay between the first NIC and the switch can be obtained according to the digit of the detection code sent by the first NIC and the preset period. Compared with the scheme of a special measuring instrument, the embodiment of the invention can realize delayed online detection, and the detection efficiency and accuracy are improved.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and more specifically, to a delay detection method, apparatus, computing device, computer program product, and computer-readable storage medium. Background Art

[0002] The communication system may include multiple network interface cards (NICs), switches, and controllers. Among them, the NIC can be used to connect to user devices or servers, convert traffic data into optical signals or electrical signals for exchange with the switch. For example, the switch may include a switch matrix, and by controlling the corresponding switches in the switch matrix to turn on or off, different transmission links are mapped to achieve many-to-many transmission. The controller can control the time when the NIC sends data and the opening and closing of the switch matrix to achieve the switching of the transmission link.

[0003] It is important to accurately measure the delay between NIC and switch. For example, in order to prevent the subsequent data of the messages of each transmission link from being lost due to the change of the switch matrix when part of the message passes through the switch, the messages of all transmission links need to pass through the switch within a slice cycle. In other words, the slice cycle needs to be set large enough to cover the time for each transmission link to transmit the message. However, the delays of each transmission link are often different. If the message of the transmission link with high delay is sent later and the message of the transmission link with low delay is sent first, when these two messages are transmitted simultaneously in the link, the slice cycle must cover both the link that is sent first and transmits faster, and the link that is sent later and transmits slower, thereby increasing the slice cycle. On the contrary, sending the message of the transmission link with high delay first and the message of the transmission link with low delay later can reduce the slice cycle, so that more messages can be sent in the same time.

[0004] However, the related technical solutions only use dedicated measuring instruments to perform "offline measurement" on the delay of the connection line between the NIC and the switch, which cannot accurately measure the delay between the NIC and the switch in actual application scenarios.

[0005] Therefore, how to accurately detect the latency between NIC and switch is an urgent problem to be solved. Summary of the invention

[0006] The present application provides a delay detection method, which can accurately detect the delay between NIC and switch.

[0007] In a first aspect, a delay detection method is provided, comprising: controlling a first network interface card (NIC) to continuously send a first detection code and a first detection message to a second NIC through a switch matrix of a switch at a first moment, wherein the first detection code is sent before the first detection message; starting the switch matrix at a preset period from the first moment, wherein the switch matrix is ​​closed after the second NIC receives the first detection message; in a case where the second NIC receives an incomplete first detection message, controlling the first network interface card NIC to continuously send a second detection code and a second detection message to the second NIC through the switch matrix of the switch at a second moment, wherein the number of bits of the second detection code is greater than the number of bits of the first detection code, and the length of the second detection message is equal to the length of the first detection message; starting the switch matrix at a preset period from the second moment, wherein the switch matrix is ​​closed after the second NIC receives the second detection message; in a case where the second NIC receives a complete second detection message, determining the delay between the first NIC and the switch according to the number of bits of the second detection code and the preset period.

[0008] In an embodiment of the present application, after the first NIC sends a detection code and a detection message, the switch matrix is ​​turned on after a preset period, so that the second NIC initially receives an incomplete detection message. In the case where the second NIC receives an incomplete detection message, the first NIC sends a longer detection code so that the second NIC is more likely to receive a complete detection message. When the second NIC receives a complete detection message, the delay between the first NIC and the switch can be obtained based on the number of bits of the detection code sent by the first NIC this time and the preset period. Compared with the solution of a dedicated measuring instrument, the embodiment of the present application can realize "online detection" of delay and improve detection efficiency and accuracy.

[0009] In combination with the first aspect, in some implementations of the first aspect, the switch matrix includes an optical switch matrix.

[0010] The method provided in the embodiment of the present application can be applied to an optical switch with an optical switch matrix. The delay detection method has a wide range of application scenarios and strong applicability.

[0011] In combination with the first aspect, in certain implementations of the first aspect, determining the delay between the first NIC and the switch based on the number of bits of the second detection code and the preset period includes: determining the additional delay caused by adding the second detection code based on the number of bits of the second detection code; and determining the delay between the first NIC and the switch based on the additional delay and the preset period.

[0012] In the embodiment of the present application, accurate detection of delay is achieved based on the additional delay caused by sending the detection code and the preset period.

[0013] In combination with the first aspect, in some implementations of the first aspect, determining the delay between the first NIC and the switch according to the number of bits of the second detection code and the preset period includes: determining the delay between the first NIC and the switch according to the following formula:

[0014] T delay =ΔT switch -ΔT n ;

[0015] Among them, T delay is the delay between the first NIC and the switch, ΔT switch is the preset period, ΔT n is that additional delay.

[0016] In the embodiment of the present application, accurate detection of delay is achieved based on the additional delay caused by sending the detection code and the preset period.

[0017] In combination with the first aspect, in certain implementations of the first aspect, determining the additional delay caused by adding the second detection code based on the number of bits of the second detection code includes: determining the additional delay based on the number of bits of the second detection code and the rate at which the first NIC sends the second detection code.

[0018] The embodiment of the present application can determine the additional delay according to the number of bits of the detection code and the sending rate of the first NIC, thereby achieving accurate detection of the delay between the first NIC and the switch.

[0019] In combination with the first aspect, in some implementations of the first aspect, a difference between the number of bits of the second detection code and the number of bits of the first detection code is 1.

[0020] In the embodiment of the present application, the number of bits of the detection code added each time can be 1, so as to achieve picosecond level detection and improve the accuracy of delay detection.

[0021] In combination with the first aspect, in certain implementations of the first aspect, the method further includes: when the second NIC receives an incomplete second detection message, controlling the first NIC to send a third detection code and a third detection message to the second NIC through the switch matrix of the switch at a third moment, wherein the number of bits of the third detection code is greater than the number of bits of the second detection code, and the length of the third detection message is equal to the length of the first detection message; turning on the switch matrix at an interval of the preset period from the third moment, wherein the switch matrix is ​​turned off after the second NIC receives the third detection message; and determining the delay between the first NIC and the switch based on the number of bits of the third detection code and the preset period when the second NIC receives the complete third detection message.

[0022] By continuously increasing the length of the detection code until the second NIC can receive the complete detection message, the detection method provided in the embodiment of the present application can accurately detect the delay between the first NIC and the switch.

[0023] In combination with the first aspect, in certain implementations of the first aspect, the number of bits of 0 and 1 in the second detection code is similar.

[0024] In the embodiment of the present application, the number of bits of 0 and 1 in the detection code is similar, which can achieve a balance between 0 and 1 in the link, thereby reducing the bit error rate of the NIC.

[0025] In combination with the first aspect, in certain implementations of the first aspect, the second detection message includes an indication field, which is used to indicate the number of bits of the second detection code, wherein the method further includes: determining the number of bits of the second detection code based on the second detection message.

[0026] The detection message may include an indication field, which may indicate the number of bits of the detection code before the detection message, thereby facilitating delay calculation and improving detection efficiency.

[0027] In a second aspect, an embodiment of the present application provides a delay detection device, which includes a module for implementing the first aspect or any possible implementation method of the first aspect.

[0028] In a third aspect, a computing device is provided, including a processor and a memory, wherein the processor is used to execute instructions stored in the memory so that the computing device executes the delay detection method of the first aspect or any possible implementation of the first aspect.

[0029] According to a fourth aspect, a computer program product comprising instructions is provided. When the instructions are executed by a computing device, the computing device executes the delay detection method of the first aspect or any possible implementation of the first aspect.

[0030] In a fifth aspect, a computer-readable storage medium is provided, comprising computer program instructions. When the computer program instructions are executed by a computing device, the computing device executes the delay detection method of the first aspect or any possible implementation of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic block diagram of the architecture of a switching network provided in an embodiment of the present application.

[0032] Figure 2 It is a schematic diagram of message transmission provided in an embodiment of the present application.

[0033] Figure 3 It is a schematic flow chart of a delay detection method provided in an embodiment of the present application.

[0034] Figure 4 It is a schematic diagram of a delay detection method provided in an embodiment of the present application.

[0035] Figure 5 It is a schematic flowchart of another delay detection method provided in an embodiment of the present application.

[0036] Figure 6 It is a schematic block diagram of a delay detection device provided in an embodiment of the present application.

[0037] Figure 7 It is a schematic block diagram of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] The technical solution in this application will be described below in conjunction with the accompanying drawings.

[0039] The present application will present various aspects, embodiments or features around a system that may include multiple devices, components, modules, etc. It should be understood and appreciated that each system may include additional devices, components, modules, etc., and / or may not include all of the devices, components, modules, etc. discussed in conjunction with the figures. In addition, combinations of these schemes may also be used.

[0040] In addition, in the embodiments of the present application, words such as "exemplary" and "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the word "exemplary" is intended to present concepts in a concrete way.

[0041] The business scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Ordinary technicians in this field can know that with the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0042] References to "one embodiment" or "some embodiments" etc. described in this specification mean that a particular feature, structure or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. appearing in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0043] Figure 1 1 is a schematic block diagram of an architecture of a switching network provided in an embodiment of the present application. In the diagram, a controller 110 is connected to multiple network interface cards (NICs) 120, a switch 130, and multiple NICs 140. Multiple NICs 120 are connected to multiple NICs 140 via switches 130. Each NIC is connected to the switch 130 via a connection line 150.

[0044] In some embodiments, NIC 120 may send a message to NIC 140 through switch 130. NIC 120 and NIC 140 may be the same NIC or the same group of NICs, and NIC 140 may also send a message to NIC 120 through switch 130.

[0045] In some embodiments, the controller 110 can control the time synchronization of the high-precision clocks of various parts in the switching network 100 to enable various parts to work at the same rhythm. In some embodiments, the controller 110 can also control the time when the NIC 120 sends data and the switching time of the switch matrix in the switch 130.

[0046] The switch 130 may include a switch matrix. For example, the switch 130 may include an optical switch matrix. In this case, the switch 130 may also be referred to as an optical switch or an optical switch matrix, and the connection line 150 may be an optical fiber. The optical switch matrix may perform the function of optical packet switching.

[0047] It should be noted that the present application does not limit the specific type of the switch. For example, the switch 130 may also include an electrical switch matrix. In this case, the switch 130 may be called an electrical switch.

[0048] The NIC can be used to connect to user equipment or servers, convert traffic data into optical signals and send them to the switch 110 for switching. The optical switch may include an optical switch matrix, and the corresponding optical switches are turned on or off by the control signal input by the controller 110, so that different optical paths can be generated, thereby realizing many-to-many transmission according to different optical paths.

[0049] NIC may include a fabric interface circuit (FIC) and an optical / electrical module (OE). FIC may implement communication from a user network interface to a switching network interface, and FIC may include an upstream processing unit (iFIC) and a downstream processing unit (eFIC). OE may convert optical signals on a transmission link into electrical signals, or may convert electrical signals on a transmission link into optical signals. For example, in an optical switching matrix scenario, NIC 120 includes an iFIC, and OE sends optical signals converted from electrical signals to the optical switching matrix at the output end of the iFIC for optical switching, and NIC 140 includes an eFIC, and OE converts optical signals into electrical signals at the eFIC and outputs them outside the switching network 100.

[0050] In order to prevent the subsequent data loss due to the change of the switch matrix when the messages of each transmission link partially pass through the switch, the messages of all transmission links need to pass through the switch within a slice period. In other words, the slice period needs to be set large enough to cover the time for each transmission link to transmit the message and the delay of each transmission link.

[0051] However, the delays of various transmission links are often different. If the message of the transmission link with high delay is sent later and the message of the transmission link with low delay is sent first, when these two messages are transmitted simultaneously in the link, the slicing period must cover both the link that is sent first and transmits faster and the link that is sent later and transmits slower, thereby increasing the slicing period. On the contrary, sending the message of the transmission link with high delay first and the message of the transmission link with low delay later can reduce the slicing period, thereby sending more messages in the same time.

[0052] Figure 2 1 is a schematic diagram of a message transmission provided in an embodiment of the present application. Assuming that the length (ie, data volume) of the message sent by each link is the same, the connection line 150 ( Figure 2The number of packets on the NIC 120 (not shown) indicates that the NIC 120 can send this number of packets to the switch 130 within a period of time. Figure 2 As shown in (a), during this period, there are three slice periods 210, and each transmission link can transmit a message in each slice period 210. However, the delay of each transmission link is different, and each NIC 120 does not make effective adjustments. Therefore, in addition to sending the message, each slice period 210 also includes the time for waiting for other links to delay.

[0053] like Figure 2 As shown in (b), by obtaining the delay of each link, the messages to be sent by each link can be "aligned", for example, the link with high delay is controlled to send the message first, and the link with low delay is controlled to send the message later. It can be seen that there are four slicing periods 220 after alignment. That is to say, in the same time, without message alignment, a link can only transmit 3 messages. After message alignment, a link can transmit 4 messages, thus significantly improving the efficiency of the communication system. From another perspective, the slicing period covers the link that sends first but transmits slower, and the link that sends later but transmits faster, thereby reducing the slicing period.

[0054] In some embodiments, the intervals between messages sent by various links are different, but the intervals between messages sent within a link are the same, so as long as the first message is aligned, the following messages will also be aligned.

[0055] However, to achieve Figure 2 To achieve the effect shown, it is necessary to first accurately obtain the delay of each link. Specifically, it is necessary to accurately detect the delay of each NIC 120 sending a message to the switch 130.

[0056] The related technical solution approximates the delay of NIC 120 sending messages to switch 130 to the delay of measuring line 150, and uses a dedicated measuring instrument to measure the delay of connecting line 150. However, the use of a dedicated measuring instrument to intelligently implement the "offline measurement" of connecting line 150 cannot compensate for the link delay changes caused by environmental changes. Each time a dedicated measuring instrument is used for measurement, the connecting line 150 needs to be reconnected to the dedicated measuring instrument, which affects the efficiency of the measurement. In addition, in the scenario where the connecting line 150 is an optical fiber, the delay of the switching network 100 is also affected by each single board, optical module and optical fiber connector. The delay between NIC 110 and switch 130 in the actual switching network 100 cannot be simply replaced by the delay of the optical fiber.

[0057] Figure 3 It is a schematic flow chart of a delay detection method provided in an embodiment of the present application. Figure 3The illustrated method 300 is capable of accurately detecting the latency between the NIC and the switch.

[0058] The method 300 may be executed by any device having a computing function (such as a delay detection device), for example, Figure 1 The controller 110 executes.

[0059] S310, controlling the first NIC to continuously send a first detection code and a first detection message to the second NIC through a switch matrix of a switch at a first moment, wherein the first detection code is sent before the first detection message.

[0060] The first NIC may be a NIC at the transmitting end, and it is understood that there is often more than one NIC at the transmitting end. The first NIC in the embodiment of the present application is only a NIC that method 300 focuses on when performing delay detection. Obviously, repeating method 300 can detect delays between multiple NICs and switches. The second NIC may be a NIC at the receiving end, and it is understood that there is often more than one NIC at the receiving end.

[0061] The first moment is a point in time. For example, the delay detection device or controller 110 may send control information to the first NIC, notifying the first NIC to send a detection code and a detection message at the first moment. The first NIC may parse the control information and extract the first moment. In some embodiments, the first NIC may include a real time clock (RTC), and when the RTC reaches the first moment, the first NIC sends the first detection code and the first detection message. For example, the first NIC may include a serializing / deserializing circuitry (SerDes) interface, and the first NIC sends the first detection code and the first detection message through the SerDes interface.

[0062] The SerDes interface is a high-speed serial interface that can send a large amount of data bit by bit at a rate of up to tens to hundreds of Gbps. After the receiving end receives the data, it can restore the data from the sending end bit by bit.

[0063] The first detection message may be a message constructed by the first NIC, which is not limited in the present application. For example, the first detection message may also be a message indicated by the delay detection device or the controller 110 .

[0064] The first detection message may include a message header and a check bit. The message header may be used to identify the first detection message, and the check bit may be used to check the integrity of the first detection message. The first detection message may also include other fields. For example, the second NIC may identify the first detection message through the message header, and may check the integrity of the first detection message through the check bit.

[0065] The first detection code is used to detect the delay, and the specific detection method will be described later. For example, the first detection code can be a binary number of a certain number of bits, such as a pseudo-random binary sequence (PRBS) or any other form of binary number. For example, it can be a sequence similar to "010101...".

[0066] “Continuously sending” means that the first detection code and the first detection message are adjacent. It can also be understood that there is no time interval between sending the first detection code and the first detection message, and no other data is sent.

[0067] In some embodiments, the first detection message may include an indication field, which is used to indicate the number of digits (or bits) of the first detection code. For example, the number of digits of the first detection code can be encapsulated in the first detection message. For example, the indication field can be located behind the message header field. In some embodiments, the indication field can also be called a message sequence number field. For example, the first detection message can be constructed by the first NIC, and the number of digits of the first detection code can be 1. In this case, the first NIC can encapsulate the number of digits in the first detection message when constructing the first detection message. In this way, the second NIC can determine the number of digits of the first detection code by parsing the first detection message.

[0068] In some embodiments, the switch matrix comprises an optical switch matrix.

[0069] The meaning of the switch matrix can be found in the above text and will not be described here in detail. In addition, the present application does not limit the switch matrix, for example, the switch matrix may also include an electrical switch matrix.

[0070] When the switch matrix includes an optical switch matrix, the switch may also be called an optical switch or an optical switching matrix. If the first NIC sends the first detection code and the first detection message in the form of electrical signals, an optical module may be used to convert the electrical signals into optical signals, and the optical signals may be transmitted to the optical switching matrix.

[0071] The method provided in the embodiment of the present application can be applied to an optical switch with an optical switch matrix. The delay detection method has a wide range of application scenarios and strong applicability.

[0072] S320, starting from the first moment at a preset period, turning on the switch matrix, wherein the switch matrix is ​​turned off after the second NIC receives the first detection message.

[0073] The preset period can be a pre-set interval. The first NIC sends the first detection code and the first detection message at the first moment, and the switch matrix is ​​turned on after the preset period from the first moment. Therefore, the first detection code may not be sent to the second NIC, and part of the first detection message may not be sent to the second NIC. By reasonably setting the preset period, a larger delay can be "artificially" created, and then by adjusting the detection code, the delay of the transmission link can be detected.

[0074] The switch matrix can be closed after the second NIC receives the first detection message. For example, a certain time window can be set according to the length of the first detection message, so that at least the first detection message itself can pass through the switch completely. In other words, the time window is at least longer than the length of the first detection message. In some embodiments, the time window can be set larger. In addition to allowing the first detection message to pass through the switch completely, it can also allow the first detection code part before the first detection message to pass through the switch, or it can also allow the padding data part after the first detection message to pass through the switch. It can be understood that the padding data can be a sequence similar to "010101······", or it can be a PRBS code, etc. The padding data can maintain the stability of the transmission link (such as a link with a SerDes port).

[0075] S330, when the second NIC receives the incomplete first detection message, control the first network interface card NIC to continuously send a second detection code and a second detection message to the second NIC through the switch matrix of the switch at a second moment, wherein the number of bits of the second detection code is greater than the number of bits of the first detection code, and the length of the second detection message is equal to the length of the first detection message.

[0076] As described above, since the switch matrix is ​​turned on at a preset interval from the first moment, the second NIC is likely to receive an incomplete first detection message. In some embodiments, the first detection message may include a check bit, and the second NIC determines whether the first detection message is complete by checking the check bit, and the second NIC sends the result of the determination to the delay detection device or the controller 110. In other embodiments, the delay detection device may obtain the check bit of the first detection message, and the delay detection device determines whether the first detection message is complete.

[0077] The second moment may be a moment after the first moment. It is understandable that the switch matrix has been turned off at the second moment, and therefore needs to be turned on again.

[0078] The process of controlling the first network interface card NIC to continuously send the second detection code and the second detection message to the second NIC through the switch matrix of the switch at the second moment can refer to the above description, which is not repeated here.

[0079] The length of the second detection message is equal to the length of the first detection message. In some embodiments, the second detection message is substantially the same as the first detection message, so that the first NIC or the delay detection device or the controller 110 does not need to reconstruct the second detection message, reducing the burden on system operation. For example, in the case where the detection message can indicate the number of bits of the detection code, the second detection message and the first detection message can differ only in the indication field, the indication field of the first detection message is used to indicate the number of bits of the first detection code, and the indication field of the second detection message is used to indicate the number of bits of the second detection code. For another example, in the case where the detection message does not indicate the number of bits of the detection code, the data of each field in the second detection message can be the same as the first detection message.

[0080] The number of digits of the second detection code is greater than that of the first detection code. In other words, the second detection code may be longer than the first detection code, or the number of digits of the second detection code may be more than that of the first detection code.

[0081] In some embodiments, the number of bits of the second detection code may be one more bit width of the user side of the SerDes than the first detection code. For example, the user side bit width of the SerDes may be 32 bits, and the number of bits of the second detection code is 32 bits more than the number of bits of the first detection code. In this way, the number of bits of the second detection code may be adjusted on the user side of the SerDes, thereby increasing the applicability of the detection method.

[0082] In some other embodiments, the difference between the number of bits of the second detection code and the number of bits of the first detection code is 1. In other words, the second detection code has 1 bit more than the first detection code.

[0083] For example, assuming that the rate of the SerDes port is 25 Gbps and the user-side bit width of the SerDes is 32 bits. If the number of bits of the detection code is adjusted using the user-side bit width of the SerDes as the granularity, the calculated delay is a multiple of 1.28 nanoseconds, so the delay can be accurate to the nanosecond level. If the number of bits of the detection code is adjusted using 1 bit as the granularity, the calculated delay is a multiple of 40 picoseconds, thus achieving picosecond-level detection.

[0084] In the embodiment of the present application, the number of bits of the detection code added each time can be 1, achieving picosecond level detection and improving the accuracy and precision of delay detection.

[0085] In some embodiments, the second detection code may be any random sequence.

[0086] In some other embodiments, the number of bits of 0 and 1 in the second detection code is similar.

[0087] For example, the second detection code may be a sequence similar to “010101······” or a PRBS code.

[0088] In the embodiment of the present application, the number of bits of 0 and 1 in the detection code is similar, which can achieve a balance between 0 and 1 in the link, thereby reducing the bit error rate of the NIC.

[0089] S340, starting from the second moment and at an interval of the preset period, turning on the switch matrix, wherein the switch matrix is ​​turned off after the second NIC receives the second detection message.

[0090] It should be noted that the preset period here is the same as the preset period in S320. Since the second NIC has not received the complete detection message, the number of bits of the detection code is increased so that the second NIC is more likely to receive the complete detection message.

[0091] S350: When the second NIC receives the complete second detection message, determine the delay between the first NIC and the switch according to the number of bits of the second detection code and the preset period.

[0092] In an embodiment of the present application, after the first NIC sends a detection code and a detection message, the switch matrix is ​​turned on after a preset period, so that the second NIC initially receives an incomplete detection message. In the case where the second NIC receives an incomplete detection message, the first NIC sends a longer detection code so that the second NIC is more likely to receive a complete detection message. When the second NIC receives a complete detection message, the delay between the first NIC and the switch can be obtained based on the number of bits of the detection code sent by the first NIC this time and the preset period. Compared with the solution of a dedicated measuring instrument, the embodiment of the present application can realize "online detection" of delay and improve detection efficiency and accuracy.

[0093] In some embodiments, the preset period can be converted into a number of bits according to how many bits of data can be sent in the preset period, and the delay between the first NIC and the switch can be determined according to the number of bits converted from the preset period and the number of bits of the detection code.

[0094] In other embodiments, the delay between the first NIC and the switch is determined based on the number of bits of the second detection code and the preset period, including: determining the additional delay caused by adding the second detection code based on the number of bits of the second detection code; and determining the delay between the first NIC and the switch based on the additional delay and the preset period.

[0095] Figure 4It is a schematic diagram of a delay detection method provided in an embodiment of the present application. Figure 4 The arrows below the left and right images in indicate the time axis.

[0096] See also Figure 4 In the left figure, at the sending time 410 (for example, the first moment), the first NIC can send a first detection code 430, a first detection message and padding data 450 to the second NIC. Figure 4 In the right figure, at the start time 420, the switch matrix is ​​turned on. It can be seen that part of the data of the first detection message should have reached the second NIC through the switch matrix before the start time 420, but because the start time 420 is after this part of the data, this part of the data does not reach the second NIC. Therefore, the second NIC does not receive the complete first detection message.

[0097] It can be understood that the difference between the start time 420 and the sending time 410 is the aforementioned predetermined period. Figure 4 This is merely illustrative and does not constitute a limitation of this application. Figure 4 This is only for ease of understanding and does not mean that the first detection message and the second detection message are sent at the same time at the sending time 410. In fact, more detection messages and detection codes may be sent before the first detection message, and more detection messages and detection codes may be sent after the second detection message when the second detection message cannot pass through the switch completely to reach the second NIC.

[0098] See also Figure 4 In the left figure, at the sending time 410 (e.g., the second moment), the first NIC can send the second detection code 440, the second detection message and the padding data 450 to the second NIC. Since the second detection code 440 is longer than the first detection code 430, the second detection message can pass through the switch completely to the second NIC.

[0099] Increasing the amount of data sent will cause a delay, which is referred to as "extra delay". In some embodiments, the extra delay can be calculated based on the data transmission rate. For example, assuming that the rate of the SerDes port is 25 Gbps, each additional bit of data will increase the extra delay by 40 nanoseconds. Figure 4 The first detection code 430 is shorter than the second detection code 440, which can intuitively indicate that the additional delay corresponding to the first detection code 430 is less than the additional delay corresponding to the second detection code 440. It should be noted that the "increase" and "extra delay" here are relative to not sending a detection code, rather than relative to a shorter detection code.

[0100] For example, it may be determined that the delay between the first NIC and the switch is the difference between a preset period and the additional delay.

[0101] Further, determining the delay between the first NIC and the switch according to the number of bits of the second detection code and the preset period may include: determining the delay between the first NIC and the switch according to the following formula:

[0102] T delay =ΔT switch -ΔT n ;

[0103] Among them, T delay is the delay between the first NIC and the switch, ΔT switch is the preset period, ΔT n is that additional delay.

[0104] In the embodiment of the present application, accurate detection of delay is achieved based on the additional delay caused by sending the detection code and the preset period.

[0105] In some embodiments, determining the additional delay caused by adding the second detection code according to the number of bits of the second detection code includes: determining the additional delay according to the number of bits of the second detection code and the rate at which the first NIC sends the second detection code.

[0106] For example, assuming that the rate at which the first NIC sends the second detection code is 25 Gbps and the number of bits of the second detection code is 10 bits of data, it can be determined that the additional delay is 400 nanoseconds.

[0107] The embodiment of the present application can determine the additional delay according to the number of bits of the detection code and the sending rate of the first NIC, thereby achieving accurate detection of the delay between the first NIC and the switch.

[0108] In some embodiments, the second detection message includes an indication field, and the indication field is used to indicate the number of bits of the second detection code, wherein the method further includes: determining the number of bits of the second detection code according to the second detection message.

[0109] The detection message may include an indication field, which may indicate the number of bits of the detection code before the detection message, thereby facilitating delay calculation and improving detection efficiency.

[0110] In some embodiments, the controller 110 or the delay detection device may control the second NIC to determine the number of bits of the second detection code. In other embodiments, the controller 110 or the delay detection device may obtain the second detection message to determine the number of bits of the second detection code.

[0111] It should be noted that the above describes a situation where the second NIC receives a complete detection message after receiving an incomplete detection message. In fact, before S310, the first NIC may have sent many detection codes and detection messages, and these detection codes are shorter than the first detection code, and these detection messages are the same length as the first detection message. After the second NIC receives the incomplete first detection message, it may also receive an incomplete second detection message. The following describes a situation where the second NIC receives an incomplete second detection message.

[0112] Alternatively, the method further includes: when the second NIC receives an incomplete second detection message, controlling the first NIC to send a third detection code and a third detection message to the second NIC through the switch matrix of the switch at a third moment, wherein the number of bits of the third detection code is greater than the number of bits of the second detection code, and the length of the third detection message is equal to the length of the first detection message; turning on the switch matrix at an interval of the preset period from the third moment, wherein the switch matrix is ​​turned off after the second NIC receives the third detection message; and determining the delay between the first NIC and the switch according to the number of bits of the third detection code and the preset period when the second NIC receives the complete third detection message.

[0113] That is to say, when the second NIC receives an incomplete second detection message, the embodiment of the present application can control the first NIC to send a longer detection code and detection message again. If the detection message sent this time can be completely received by the second NIC, the delay is determined based on the detection code sent this time.

[0114] It is understandable that if the detection message sent this time still cannot be completely received by the second NIC, longer detection codes and detection messages may continue to be sent.

[0115] By continuously increasing the length of the detection code until the second NIC can receive the complete detection message, the detection method provided in the embodiment of the present application can accurately detect the delay between the first NIC and the switch.

[0116] The above describes the method of detecting delay. The following describes the application of delay by taking "message alignment" as an example.

[0117] Method 300 is executed on multiple transmission links (e.g., multiple links between the first NIC and the switch), and the delays of the multiple transmission links can be obtained. In some embodiments, the maximum delay among the delays of the multiple transmission links can be taken as a reference point, and the delay of each transmission link can be subtracted from the maximum delay to obtain the delay compensation of each transmission link in the multiple transmission links. According to the delay compensation of each transmission link in the multiple transmission links, message alignment can be achieved.

[0118] For example, according to the delay compensation of the transmission link, the number of data bits corresponding to the delay compensation can be determined. Before each message is sent on the transmission link, the number of data bits corresponding to the delay compensation can be filled. By performing a filling operation on each of the multiple transmission links, the alignment of the messages of the multiple transmission links can be achieved.

[0119] In some embodiments, the plurality of second NICs may calculate the delay of the corresponding transmission link. The second NICs send the delay of the transmission link to the controller 110, and the controller 110 calculates the delay of the transmission link according to the delay of each transmission link (eg, T Delay_1 ~T Delay_n ), determine the maximum delay among the delays of these transmission links (e.g., T Delay_max ). The controller 110 subtracts the delay of each transmission link from the maximum delay to obtain the delay compensation of each transmission link. The controller 110 sends the delay compensation to the corresponding first NIC respectively. In this way, before sending the message, the first NIC can align the message according to the delay compensation sent by the controller 110, for example, fill the message with data corresponding to the number of bits of delay compensation. The filled data can be a sequence similar to "010101······", or a PRBS code, etc., or any sequence.

[0120] The present application does not limit the specific method of aligning messages according to delay compensation. For example, in addition to the aforementioned data of the corresponding number of bits of delay compensation filled in front of the message, it can also be adjusted by the system clock of the field programmable gate array (FPGA) (for example, the high delay compensation is sent first, and the low delay compensation is sent later), and other methods can also be used for adjustment. For example, the integer part of the delay compensation greater than the FPGA system clock is adjusted by the system clock, and the remaining decimal part is adjusted by filling the corresponding number of bits of data.

[0121] In some embodiments, the above delay detection and message alignment scheme can be executed periodically, so that the delay of the transmission link can be regularly refreshed so that the messages at the switch inlet are always aligned. Compared with the scheme using a dedicated measuring instrument, the embodiment provided by the present application can effectively reduce the difficulty of networking and can compensate for the changes in transmission link delay caused by environmental changes.

[0122] When the above delay detection and message alignment scheme is applied to the scenario of the optical switching matrix, the delay of the transmission link can be corrected in real time according to the situation of the transmission link without interrupting the service, thereby improving the efficiency of data exchange.

[0123] Figure 5is a schematic flow chart of another delay detection method provided in an embodiment of the present application. The method 500 may be executed by the delay detection device or the controller 110 .

[0124] S510, controlling the first NIC to continuously send a detection code and a detection message to the second NIC through a switch matrix of the switch, wherein the detection code is sent before the detection message.

[0125] S520, turning on the switch matrix after a predetermined period.

[0126] S530: Control the second NIC to determine whether the detection message received by the second NIC is complete.

[0127] If the second NIC receives a complete detection message, S540 is executed. If the second NIC receives an incomplete detection message, S550 is executed.

[0128] S540: Determine a delay according to the predetermined period and the number of bits of the detection code.

[0129] After executing S540 , the method 500 may end.

[0130] S550, increase the number of bits of the detection code.

[0131] For example, 1 bit may be added, or the number of bits of the user-side bit width of the SerDes may be increased, for example, to 32 bits.

[0132] In some embodiments, due to a possible failure of the delay detection device or the controller 110, when the second NIC receives the complete detection message for the first time, S540 is not executed for calculation. In order to increase the robustness of the detection method provided in the embodiment of the present application, a judgment may be added between S530 and S540.

[0133] For example, after S530 is executed, if the second NIC receives a complete detection message, S540 is not executed, but it is determined whether the second NIC received a complete detection message last time. If the second NIC did not receive a complete detection message last time, S540 is executed. If the second NIC also received a complete detection message last time, the number of bits of the detection code is reduced, and steps S510, S520, etc. are executed, that is, a cycle is re-entered.

[0134] The method embodiments of the present application are described in detail above. The device embodiments of the present application are described below. The device embodiments correspond to the method embodiments, so the parts not described in detail can refer to the previous method embodiments. The device can implement any possible implementation of the above method.

[0135] Figure 6A schematic block diagram of a delay detection device provided in an embodiment of the present application is shown.

[0136] Figure 6 As shown, the delay detection device 600 includes: a control module 610, which is used to control the first NIC to continuously send a first detection code and a first detection message to the second NIC through the switch matrix of the switch at a first moment, wherein the first detection code is sent before the first detection message; the control module 610 is also used to turn on the switch matrix at a preset interval from the first moment, wherein the switch matrix is ​​turned off after the second NIC receives the first detection message; when the second NIC receives an incomplete first detection message, the control module 610 is also used to control the first network interface card NIC to send a first detection code and a first detection message to the second NIC through the switch matrix at a second moment. The switch matrix of the switch continuously sends a second detection code and a second detection message to the second NIC, wherein the number of bits of the second detection code is greater than the number of bits of the first detection code, and the length of the second detection message is equal to the length of the first detection message; the control module 610 is also used to turn on the switch matrix at intervals of the preset period from the second moment, wherein the switch matrix is ​​turned off after the second NIC receives the second detection message; the processing module 630 is used to determine the delay between the first NIC and the switch according to the number of bits of the second detection code and the preset period when the second NIC receives the complete second detection message.

[0137] The control module 610 and the processing module 630 can be implemented by software or hardware. For example, the implementation of the control module 610 is described below by taking the control module 610 as an example. Similarly, the implementation of the processing module 630 can refer to the implementation of the control module 610.

[0138] As an example of a software functional unit, the control module 610 may include code running on a computing instance. The computing instance may include at least one of a physical host (computing device), a virtual machine, and a container. Furthermore, the computing instance may be one or more.

[0139] As an example of a hardware functional unit, the control module 610 may include at least one computing device, such as a server, etc. Alternatively, the control module 610 may also be a device implemented using an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The PLD may be a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof.

[0140] The present application also provides a computing device 700. Figure 7 As shown, computing device 700 includes: bus 702, processor 704, memory 706 and communication interface 708. Processor 704, memory 706 and communication interface 708 communicate through bus 702. Computing device 700 can be a server or a terminal device. It should be understood that the present application does not limit the number of processors and memories in computing device 700.

[0141] The bus 702 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 7 The bus 702 may include a path for transmitting information between various components of the computing device 700 (eg, the memory 706, the processor 704, and the communication interface 708).

[0142] The processor 704 may include any one or more of a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP).

[0143] The memory 706 may include a volatile memory, such as a random access memory (RAM). The memory 706 may also include a non-volatile memory, such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD), or a solid state drive (SSD).

[0144] The memory 706 stores executable program codes, and the processor 704 executes the executable program codes to respectively implement the functions of the control module 610 and the processing module 630, thereby implementing the delay detection method. That is, the memory 706 stores instructions for executing the delay detection method.

[0145] The communication interface 708 uses a transceiver module such as, but not limited to, a network interface card or a transceiver to implement communication between the computing device 700 and other devices or a communication network. For example, the first NIC, the switch matrix of the switch, and the second NIC can be controlled according to the communication interface 708.

[0146] The embodiment of the present application also provides a computer program product including instructions. The computer program product may be software or a program product including instructions that can be run on a computing device or stored in any available medium. When the computer program product is run on at least one computing device, the at least one computing device executes the above-mentioned delay detection method.

[0147] The embodiment of the present application also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium that can be stored by the computing device or a data storage device such as a data center containing one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk). The computer-readable storage medium includes instructions that instruct the computing device to perform the above-mentioned delay detection method.

[0148] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A delay detection method, characterized in that: include: Controlling the first network interface card NIC to continuously send a first detection code and a first detection message to the second NIC through the switch matrix of the switch at a first moment, wherein the first detection code is sent before the first detection message; At a preset period from the first moment, the switch matrix is ​​turned on, wherein the switch matrix is ​​turned off after the second NIC receives the first detection message; In the case where the second NIC receives the incomplete first detection message, controlling the first network interface card NIC to continuously send a second detection code and a second detection message to the second NIC through the switch matrix of the switch at a second moment, wherein the number of bits of the second detection code is greater than the number of bits of the first detection code, and the length of the second detection message is equal to the length of the first detection message; Starting from the second moment and at a time interval of the preset period, the switch matrix is ​​turned on, wherein the switch matrix is ​​turned off after the second NIC receives the second detection message; When the second NIC receives the complete second detection message, the delay between the first NIC and the switch is determined according to the number of bits of the second detection code and the preset period.

2. The method according to claim 1, characterized in that The switch matrix comprises an optical switch matrix.

3. The method according to claim 1 or 2, characterized in that: The step of determining the delay between the first NIC and the switch according to the number of bits of the second detection code and the preset period includes: Determining, according to the number of bits of the second detection code, an additional delay caused by adding the second detection code; A delay between the first NIC and the switch is determined according to the additional delay and the preset period.

4. The method according to claim 3, characterized in that The step of determining the delay between the first NIC and the switch according to the additional delay and the preset period includes: determining the delay between the first NIC and the switch according to the following formula: T delay =ΔT switch -ΔT n ; Among them, T delay is the delay between the first NIC and the switch, ΔT switch is the preset period, ΔT n is the additional delay.

5. The method according to claim 3 or 4, characterized in that: The step of determining, according to the number of bits of the second detection code, an additional delay caused by adding the second detection code comprises: The additional delay is determined according to the number of bits of the second detection code and the rate at which the first NIC sends the second detection code.

6. The method according to any one of claims 1 to 5, characterized in that The difference between the number of bits of the second detection code and the number of bits of the first detection code is 1.

7. The method according to any one of claims 1 to 6, characterized in that Also includes: When the second NIC receives the incomplete second detection message, control the first NIC to send a third detection code and a third detection message to the second NIC through the switch matrix of the switch at a third time, wherein the number of bits of the third detection code is greater than the number of bits of the second detection code, and the length of the third detection message is equal to the length of the first detection message; Starting from the third moment and at a time interval of the preset period, the switch matrix is ​​turned on, wherein the switch matrix is ​​turned off after the second NIC receives the third detection message; When the second NIC receives the complete third detection message, the delay between the first NIC and the switch is determined according to the number of bits of the third detection code and the preset period.

8. The method according to any one of claims 1 to 7, characterized in that The number of 0s and 1s in the second detection code is close.

9. The method according to any one of claims 1 to 8, characterized in that The second detection message includes an indication field, where the indication field is used to indicate the number of bits of the second detection code, wherein the method further includes: The number of bits of the second detection code is determined according to the second detection message.

10. A delay detection device, characterized in that: include: A control module, used for controlling the first network interface card NIC to continuously send a first detection code and a first detection message to the second NIC through the switch matrix of the switch at a first moment, wherein the first detection code is sent before the first detection message; The control module is further configured to turn on the switch matrix at a preset period from the first moment, wherein the switch matrix is ​​turned off after the second NIC receives the first detection message; In the case where the second NIC receives the incomplete first detection message, the control module is further used to control the first network interface card NIC to continuously send a second detection code and a second detection message to the second NIC through the switch matrix of the switch at a second moment, wherein the number of bits of the second detection code is greater than the number of bits of the first detection code, and the length of the second detection message is equal to the length of the first detection message; The control module is further configured to turn on the switch matrix at intervals of the preset period from the second moment, wherein the switch matrix is ​​turned off after the second NIC receives the second detection message; The processing module is used to determine the delay between the first NIC and the switch according to the number of bits of the second detection code and the preset period when the second NIC receives the complete second detection message.

11. The device according to claim 10, characterized in that The switch matrix comprises an optical switch matrix.

12. The device according to claim 10 or 11, characterized in that The processing module is specifically used for: Determining, according to the number of bits of the second detection code, an additional delay caused by adding the second detection code; A delay between the first NIC and the switch is determined according to the additional delay and the preset period.

13. The device according to claim 12, characterized in that The processing module is specifically configured to determine the delay between the first NIC and the switch according to the following formula: T delay =ΔT switch -ΔT n ; Among them, T delay is the delay between the first NIC and the switch, ΔT switch is the preset period, ΔT n is the additional delay.

14. The device according to claim 12 or 13, characterized in that The processing module is specifically configured to determine the additional delay according to the number of bits of the second detection code and the rate at which the first NIC sends the second detection code.

15. The device according to any one of claims 10 to 14, characterized in that The difference between the number of bits of the second detection code and the number of bits of the first detection code is 1.

16. The device according to any one of claims 10 to 15, characterized in that In the case where the second NIC receives an incomplete second detection message, The control module is further used to control the first NIC to send a third detection code and a third detection message to the second NIC through the switch matrix of the switch at a third time, wherein the number of bits of the third detection code is greater than the number of bits of the second detection code, and the length of the third detection message is equal to the length of the first detection message; The control module is further configured to turn on the switch matrix at intervals of the preset period from the third moment, wherein the switch matrix is ​​turned off after the second NIC receives the third detection message; When the second NIC receives the complete third detection message, the processing module is further configured to determine a delay between the first NIC and the switch according to the number of bits of the third detection code and the preset period.

17. The device according to any one of claims 10 to 16, characterized in that The number of 0s and 1s in the second detection code is close.

18. The device according to any one of claims 10 to 17, characterized in that The second detection message includes an indication field, where the indication field is used to indicate the number of bits of the second detection code, wherein the processing module is further used to: The number of bits of the second detection code is determined according to the second detection message.

19. A computing device, characterized in that The method comprises a processor and a memory, wherein the processor is configured to execute instructions stored in the memory so that the computing device executes the method according to any one of claims 1 to 9.

20. A computer program product comprising instructions, characterized in that When the instructions are executed by a computing device, the computing device is caused to perform the method according to any one of claims 1 to 9.

21. A computer-readable storage medium, characterized in that: The method comprises computer program instructions, and when the computer program instructions are executed by a computing device, the computing device performs the method as claimed in any one of claims 1 to 9.

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