Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes: a substrate including a chip protection region; a stress relief pattern spaced apart from the substrate and disposed over the chip protection region; a dummy stack structure formed on the stress relief pattern; a conductive contact plug extending downward while penetrating the stress relief pattern; and a chip protection pattern in direct contact with the conductive contact plug while penetrating the dummy stack structure.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0079763 filed in the Korean Intellectual Property Office on June 21, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure generally relate to an electronic device, and more particularly, to a semiconductor device and a method for manufacturing the same. Background Art

[0004] A nonvolatile memory device is a memory device that retains stored data as is even when power is interrupted. As the increase in the integration density of a two-dimensional nonvolatile memory device in which memory cells are formed in a single layer on a substrate reaches a limit, a three-dimensional nonvolatile memory device in which memory cells are vertically stacked on a substrate has recently been proposed.

[0005] A three-dimensional nonvolatile memory device includes interlayer insulating layers and gate electrodes alternately stacked, and a channel layer penetrating the interlayer insulating layers and the gate electrodes, and memory cells are stacked along the channel layer. Various structures and various manufacturing methods have been developed to improve the operational reliability of such a nonvolatile memory device having a three-dimensional structure. Summary of the invention

[0006] According to an embodiment of the present disclosure, a semiconductor device is provided, which includes: a substrate including a chip protection area; a stress release pattern separated from the substrate and arranged above the chip protection area; a dummy stack structure formed on the stress release pattern; a conductive contact plug extending downward and penetrating the stress release pattern; and a chip protection pattern, which is in direct contact with the conductive contact plug and penetrates the dummy stack structure.

[0007] According to an embodiment of the present disclosure, a semiconductor device is provided, which includes: a substrate, which includes a main chip area and a chip protection area; a source layer, which is separated from the substrate and is arranged above the main chip area; a unit stack structure formed on the source layer; a stress release pattern, which is separated from the substrate and is arranged above the chip protection area; a dummy stack structure formed on the stress release pattern; and a conductive contact plug extending downward and penetrating the stress release pattern, wherein the stress release pattern includes a doped silicon layer or an undoped silicon layer.

[0008] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: forming a source layer on a substrate including a main chip area and a chip protection area; forming an insulating pattern that penetrates the source layer of the chip protection area, thereby defining the source layer between the insulating patterns as a stress release pattern; forming a conductive contact plug that penetrates the stress release pattern; forming a stacking structure in the main chip area and the chip protection area above the source layer, the stress release pattern and the conductive contact plug, in which a first material layer and a second material layer are alternately stacked; forming a groove for chip protection formation, which exposes the conductive contact plug and simultaneously penetrates the stacking structure of the chip protection area; and forming a chip protection pattern by filling the groove for chip protection formation with a conductive material. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Examples of embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein.

[0010] In the accompanying drawings, the dimensions may be exaggerated for clarity of illustration. It should be understood that when an element is referred to as being "between" two elements, it may be the only element between the two elements, or one or more intermediate elements may also be present. The same reference numerals refer to the same elements throughout.

[0011] Figure 1 is a block diagram schematically illustrating a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 2 is a plan view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 3 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Fig. 4I , Figure 4J and Figure 4K are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0015] Figure 5 is a block diagram illustrating a configuration of a memory system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] The specific structural or functional description disclosed herein is only for the purpose of describing the embodiments according to the concept of the present disclosure. The embodiments according to the concept of the present disclosure can be implemented in various forms and should not be interpreted as being limited to the embodiments set forth herein.

[0017] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical spirit of the present disclosure.

[0018] The embodiment provides a semiconductor device and a method for manufacturing the semiconductor device, wherein a stress release pattern is disposed on a bottom of a chip protection pattern, and the chip protection pattern is disposed in a chip protection region, thereby improving the reliability of the semiconductor device.

[0019] Figure 1 is a block diagram schematically illustrating a semiconductor device according to an embodiment of the present disclosure.

[0020] refer to Figure 1 , the semiconductor device may include a peripheral circuit structure PC and memory blocks BLK1 to BLKk (k is a natural number of 2 or more) disposed on a substrate SUB. The memory blocks BLK1 to BLKk may overlap with the peripheral circuit structure PC.

[0021] The substrate SUB may be a single crystal semiconductor layer. For example, the substrate SUB may be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial thin film formed by a selective epitaxial growth process.

[0022] The peripheral circuit structure PC may include a row decoder, a column decoder, a page buffer, a control circuit, etc., which constitute a circuit for controlling the operation of the memory blocks BLK1 to BLKk. For example, the peripheral circuit structure PC may include an NMOS transistor, a PMOS transistor, a resistor, a capacitor, etc. electrically connected to the memory blocks BLK1 to BLKk. The peripheral circuit structure PC may be disposed between the substrate SUB and the memory blocks BLK1 to BLKk. That is, the peripheral circuit structure PC and the memory blocks BLK1 to BLKk may be sequentially stacked on the substrate SUB along the vertical direction Z. However, an embodiment in which the peripheral circuit structure PC extends to another area of ​​the substrate SUB that does not overlap with the memory blocks BLK1 to BLKk is not excluded.

[0023] Each memory block in the memory blocks BLK1 to BLKk may include an impurity-doped region, a bit line, a cell string electrically connected to the impurity-doped region and the bit line, a word line electrically connected to the cell string, and a selection line electrically connected to the cell string. Each cell string may include a memory cell and a selection transistor connected in series by a channel structure. Each selection line may be used as a gate electrode of a selection transistor corresponding thereto, and each word line may be used as a gate electrode of a memory cell corresponding thereto. The memory blocks BLK1 to BLKk may be arranged sequentially along a first horizontal direction X. However, the present disclosure is not limited thereto, and the memory blocks BLK1 to BLKk may be arranged sequentially along a second horizontal direction Y or may be regularly arranged on an XY plane.

[0024] Figure 2 is a plan view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0025] refer to Figure 2 , the semiconductor device 10 may be defined as a main chip region Main Chip_R, a scribe line region SL_R, and a chip guard region CG_R between the main chip region Main Chip_R and the scribe line region SL_R.

[0026] A memory block including a plurality of memory cells ( Figure 1 BLK1 to BLKk) and a peripheral circuit structure for driving a plurality of memory cells ( Figure 1 The PC) shown in FIG. 1 may be formed in the main chip region Main Chip_R.

[0027] Overlapping cursor keys for aligning a plurality of masks used in a manufacturing process of a semiconductor device may be disposed on the scribe line region SL_R.

[0028] At least one chip guard pattern Chip Guard may be disposed in the chip guard region CG_R between the main chip region Main Chip_R and the scribe line region SL_R. When at least two chip guard patterns Chip Guard are disposed, the chip guard patterns Chip Guard may be disposed parallel to each other, and a buffer slit (not shown) may be formed in a space between the chip guard patterns Chip Guard.

[0029] At least one chip guard pattern Chip Guard may be provided in a line shape extending in the second horizontal direction Y. In an embodiment, at least one chip guard pattern Chip Guard may prevent cracks from extending toward the main chip region Main Chip_R in a sawing process of cutting the scribe line region SL_R, and prevent impurities from being introduced through an oxide layer exposed by a cutting surface. In addition, in an embodiment, a bottom of at least one chip guard pattern Chip Guard may be connected to a conductive contact plug, which will serve as a path for discharging abnormal charges accumulated in the semiconductor device.

[0030] Figure 3 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0031] refer to Figure 3 The semiconductor device may include a source layer SL arranged on a main chip region Main Chip_R of a substrate SUB, a unit stacking structure STc arranged on the source layer SL, a plurality of channel structures CH extending along a vertical direction Z in the unit stacking structure STc, a stress release pattern SR_P arranged on a chip protection region CG_R of the substrate SUB, a dummy stacking structure STd arranged on the stress release pattern SR_P, a chip protection pattern CG extending along the vertical direction Z in the dummy stacking structure STd, and a conductive contact plug DCC, the conductive contact plug DCC contacts a lower surface of the chip protection pattern CG and extends downward (i.e., opposite to the vertical direction Z) while penetrating the stress release pattern SR_P.

[0032] The substrate SUB can be made with the above reference Figure 1 The substrate SUB described above is formed of the same material. Conductive type dopants defining the well region may be implanted into the substrate SUB. Each conductive type dopant defining the well region may be an n-type or p-type impurity. The well region of the substrate SUB may be divided into active regions ACT1 and ACT2 divided by an isolation layer ISO. The isolation layer ISO may include an insulating material embedded in the substrate SUB. The active regions ACT1 and ACT2 may include a first active region ACT1 overlapping with a conductive contact plug DCC in the chip guard region CG_R and at least one second active region ACT2 overlapping with a cell stack structure STc in the main chip region Main Chip_R.

[0033] The peripheral circuit structure PC may include the above reference Figure 1At least one transistor TR described. The transistor TR may include a peripheral gate insulating layer PGI disposed on the second active region ACT2, a peripheral gate electrode PG disposed on the peripheral gate insulating layer PGI, and a first junction Jn1 and a second junction Jn2 disposed on both sides of the peripheral gate electrode PG in the second active region ACT2. The first junction Jn1 and the second junction Jn2 are regions defined by injecting n-type or p-type impurities into the second active region ACT2. One of the first junction Jn1 and the second junction Jn2 may be used as a source junction, and the other of the first junction Jn1 and the second junction Jn2 may be used as a drain junction.

[0034] The peripheral circuit structure PC may include a connection line PCL and a peripheral contact plug PCT connected to the transistor TR. In addition to the transistor TR and the connection line PCL and the peripheral contact plug PCT connected thereto, the peripheral circuit structure PC may also include a reference Figure 1 Described resistors, capacitors, etc.

[0035] Conductive type impurities may be implanted into the first active region ACT1. In an embodiment, a discharge impurity region DCI may be defined in the first active region ACT1. The discharge impurity region DCI may include conductive type impurities for forming a PN diode. The discharge impurity region DCI may be used as a path for discharging abnormal charges accumulated in the semiconductor device.

[0036] The above-mentioned peripheral circuit structure PC may be covered by a lower insulating structure LIL disposed between the source layer SL and the substrate SUB. The lower insulating structure LIL may extend to cover the discharge impurity region DCI. The lower insulating structure LIL may include insulating layers stacked in a multi-layer structure.

[0037] The source layer SL may be disposed to be spaced apart from the substrate SUB by the peripheral circuit structure PC and the lower insulating structure LIL.

[0038] The source layer SL may be disposed on the lower insulating structure LIL of the main chip region Main Chip_R. The source layer SL may include two or more semiconductor layers L1, L2, and L3.

[0039] For example, the source layer SL may include first to third semiconductor layers L1 to L3 sequentially stacked on the lower insulating structure LIL. Each of the first semiconductor layer L1 and the second semiconductor layer L2 may be a doped semiconductor layer including a source dopant. In an embodiment, each of the first semiconductor layer L1 and the second semiconductor layer L2 may include a doped silicon layer containing n-type impurities. The third semiconductor layer L3 may be omitted in some cases. The third semiconductor layer L3 may include any one of an n-type doped silicon layer and an undoped silicon layer.

[0040] The stress release pattern SR_P may be disposed on the lower insulating structure LIL of the chip guard region CG_R. The stress release pattern SR_P may be configured to include first to third buffer patterns B1 to B3 and include protective layers PT1 and PT2 stacked between the first to third buffer patterns B1 to B3. Each of the first to third buffer patterns B1 to B3 may include a doped silicon layer or an undoped silicon layer, and each of the protective layers PT1 and PT2 may include an oxide layer. The first buffer pattern B1 may be made of the same material as the first semiconductor layer L1, and the third buffer pattern B3 may be made of the same material as the third semiconductor layer L3. The first buffer pattern B1, the second buffer pattern B2, and the third buffer pattern B3 may be stacked sequentially in the vertical direction Z.

[0041] The source layer SL and the stress release pattern SR_P may be disposed at the same level.

[0042] The stress release pattern SR_P may be penetrated by the conductive contact plug DCC. The conductive contact plug DCC may penetrate the lower insulating structure LIL to contact the discharge impurity region DCI of the substrate SUB. The conductive contact plug DCC may be in direct contact with the discharge impurity region DCI and the stress release pattern SR_P. The sidewall of the conductive contact plug DCC may be in direct contact with the stress release pattern SR_P. The insulating pattern INS may be disposed on the outer wall of the stress release pattern SR_P. The insulating pattern INS may include an oxide layer. The insulating pattern INS may allow the source layer SL, which is disposed to extend from the main chip region Main Chip_R to the chip guard region CG_R, and the conductive contact plug DCC to be electrically spaced apart from each other.

[0043] The conductive contact plug DCC may include first to fifth patterns P1 to P5 stacked sequentially. The first pattern P1 and the third pattern P3 may be disposed inside the lower insulating structure LIL and respectively disposed at a level where the peripheral contact plug PCT is disposed. The second pattern P2 and the fourth pattern P4 may be disposed inside the lower insulating structure LIL and respectively disposed at a level where the connection line PCL is disposed. The fifth pattern P5 may penetrate the stress release pattern SR_P and extend to the inside of the lower insulating structure LIL to contact the fourth pattern P4.

[0044] The dummy stack structure STd may overlap the stress relief pattern SR_P and the insulating pattern INS. The dummy stack structure STd may include a dummy interlayer insulating layer ILDd and a sacrificial insulating layer SC.

[0045] The chip guard pattern CG may be in direct contact with the conductive contact plug DCC while penetrating the dummy stack structure STd along the vertical direction Z. The chip guard pattern CG may include a conductive material.

[0046] The cell stack structure STc may include cell interlayer insulating layers ILDc and conductive patterns CP1 to CPn (n is a natural number of 2 or more) alternately stacked on the source layer SL. The cell stack structure STc may be disposed at the same level as the dummy stack structure STd. The cell interlayer insulating layer ILDc may be disposed at the same level as the dummy interlayer insulating layer ILDd, and the conductive patterns CP1 to CPn may be disposed at the same level as the sacrificial insulating layer SC.

[0047] The unit interlayer insulating layer ILDc and the dummy interlayer insulating layer ILDd may be formed of the same material and formed by the same process. The sacrificial insulating layer SC may be formed of a material having an etching rate different from that of each of the unit interlayer insulating layer ILDc and the dummy interlayer insulating layer ILDd. For example, the unit interlayer insulating layer ILDc and the dummy interlayer insulating layer ILDd may include silicon oxide, and the sacrificial insulating layer SC may include silicon nitride.

[0048] Each of the conductive patterns CP1 to CPn may include various conductive materials such as a doped silicon layer, a metal layer, a metal silicide layer, and a barrier layer, and may include two or more conductive materials. For example, each of the conductive patterns CP1 to CPn may include tungsten and a titanium nitride layer (TiN) surrounding the surface of the tungsten. In an embodiment, tungsten is a low-resistance metal and can reduce the resistance of the conductive patterns CP1 to CPn. The titanium nitride layer TiN is a barrier layer and can prevent or mitigate direct contact between tungsten and the cell interlayer insulating layer ILDc.

[0049] Conductive patterns CP1 to CPn may be used as gate electrodes of cell strings. The gate electrodes of cell strings may include source selection lines, word lines, and drain selection lines. The source selection lines are used as gate electrodes of source selection transistors, the drain selection lines are used as gate electrodes of drain selection transistors, and the word lines are used as gate electrodes of memory cells.

[0050] The cell stack structure STc may surround each channel structure CH. That is, the channel structure CH may extend to a certain depth inside the source layer SL while penetrating the cell stack structure STc. The channel structure CH may include a channel semiconductor pattern SE. The channel semiconductor pattern SE may include a silicon layer. The central region of the channel semiconductor pattern SE may be filled with a core insulating layer CO. The core insulating layer CO may be formed to have a height lower than that of the channel semiconductor pattern SE. The upper central region of the channel semiconductor pattern SE extending upward from the core insulating layer CO may be filled with a doped semiconductor pattern DP disposed on the core insulating layer CO. The doped semiconductor pattern DP may include an n-type doped silicon layer. The channel semiconductor pattern SE of the channel structure CH may be used as a channel region of a cell string, and the doped semiconductor pattern DP of the channel structure may be used as a drain junction of the cell string. The sidewall of the channel structure CH may be surrounded by a memory layer ML.

[0051] The channel structure CH may penetrate the cell stack structure STc and extend to the inside of the source layer SL. Part of the sidewall of the channel structure CH may be in direct contact with the source layer SL. In an embodiment, the second semiconductor layer L2 of the source layer SL may be in direct contact with the sidewall of the channel semiconductor pattern SE. The memory layer ML may be divided into a first memory pattern ML1 and a second memory pattern ML2 by the second semiconductor layer L2. The first memory pattern ML1 may be disposed between the channel structure CH and the cell stack structure STc, and extend between the channel structure CH and the third semiconductor layer L3. The second memory pattern ML2 may be disposed between the channel structure CH and the first semiconductor layer L1.

[0052] The slit SI may be filled with a source contact structure SCT. The source contact structure SCT may be spaced apart from the cell stack structure STc by a sidewall insulating layer SWI formed on the sidewall of the slit SI. The sidewall insulating layer SWI may be penetrated by the source contact structure SCT. The source contact structure SCT may extend to contact the source layer SL. The source contact structure SCT may include a single conductive material or two or more conductive materials. The conductive material for the source contact structure SCT may include a doped silicon layer, a metal layer, a metal silicide layer, a barrier layer, and the like. For example, the source contact structure SCT may include a doped silicon layer in contact with the source layer and a metal layer disposed on the doped silicon layer.

[0053] The upper insulating structure UIL may include a single insulating layer or two or more insulating layers. For example, the upper insulating structure UIL may include an oxide layer. The upper insulating structure UIL may be penetrated by the bit line contact plug BCT. The bit line contact plug BCT may be connected to the doped semiconductor pattern DP of the channel structure CH.

[0054] Figures 4A to 4Kare plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0055] refer to Figure 4A The peripheral circuit structure PC and the first to fourth patterns P1 and P4 may be formed on the substrate SUB including the active areas ACT1 and ACT2 divided by the isolation layer ISO. The peripheral circuit structure PC and the first to fourth patterns P1 and P4 may be covered by the lower insulating structure LIL.

[0056] The active regions ACT1 and ACT2 may include a first active region ACT1 and at least one second active region ACT2. The first active region ACT1 may include a discharge impurity region DCI, and the second active region ACT may include junctions Jn1 and Jn2. A region overlapping the first active region ACT1 may be defined as a discharge contact region, and a region overlapping the second active region ACT2 may be defined as a cell region.

[0057] The isolation layer ISO, the active regions ACT1 and ACT2, the discharge impurity region DCI, the junctions Jn1 and Jn2, the peripheral circuit structure PC, and the lower insulating structure LIL have been described above. Figure 1 and Figure 3 The detailed descriptions are given below, and thus their repeated descriptions will be omitted.

[0058] The first to fourth patterns P1 to P4 may be formed of a conductive material and sequentially stacked on the discharge impurity region DCI. The first pattern P1 disposed in a lowermost layer among the first to fourth patterns P1 to P4 may directly contact the discharge impurity region DCI.

[0059] Subsequently, a lower stacked structure 100 may be formed on the lower insulating structure LIL. The lower stacked structure 100 may include a lower semiconductor layer 101, a sacrificial layer 105, and an upper semiconductor layer 109 that are sequentially stacked. Before depositing the sacrificial layer 105 on the lower semiconductor layer 101, a first protective layer 103 may be formed on the lower semiconductor layer 101. Before forming the upper semiconductor layer 109 on the lower semiconductor layer 101 or the first protective layer 103, a second protective layer 107 may be formed on the lower semiconductor layer 101 or the first protective layer 103.

[0060] The lower semiconductor layer 101 may include a doped semiconductor layer including conductive type impurities. For example, the lower semiconductor layer 101 may include an n-type doped silicon layer. The sacrificial layer 105 may include a material having an etching rate different from that of each of the first protective layer 103 and the second protective layer 107, and each of the first protective layer 103 and the second protective layer 107 may include a material having an etching rate different from that of each of the lower semiconductor layer 101 and the upper semiconductor layer 109. For example, the sacrificial layer 105 may include an undoped silicon layer, and each of the first protective layer 103 and the second protective layer 107 may include an oxide layer. The upper semiconductor layer 109 may include a semiconductor layer. For example, the upper semiconductor layer 100 may include a doped silicon layer or an undoped silicon layer.

[0061] refer to Figure 4B and Figure 4C , a first trench T1 and a second trench T2 may be formed, the first trench T1 and the second trench T2 exposing the lower insulating structure LIL while penetrating a portion of the lower stacked structure 100 overlapping the chip guard region CG_R. The first trench T1 and the second trench T2 may be formed to be spaced a certain distance from a conductive contact plug formed in a subsequent process. After that, an insulating pattern 111 may be formed by filling the inside of the first trench T1 and the second trench T2 with an insulating material.

[0062] The lower stack structure 100 formed on the main chip region Main Chip_R and the lower stack structure 100 between the insulating patterns 111 may be physically and electrically spaced apart from each other by the insulating patterns 111 .

[0063] When a conductive contact plug formed in a subsequent process is formed to extend in a line shape in the second horizontal direction Y, each insulating pattern 111 in the first trench T1 and the second trench T2 can be formed at the following position: wherein each insulating pattern 111 is spaced a certain distance from the conductive contact plug to extend in a line shape along the second horizontal direction Y.

[0064] The lower stacked structure 100 disposed between the first trench T1 and the second trench T2 may be defined as a stress release pattern. For example, the lower semiconductor layer 101, the sacrificial layer 105, and the upper semiconductor layer 109 disposed between the first trench T1 and the second trench T2 may be defined as a first buffer pattern, a second buffer pattern, and a third buffer pattern, respectively. Therefore, the stress release pattern may include first to third buffer patterns 101, 105, and 109, each of which includes a doped silicon layer or an undoped silicon layer.

[0065] In another embodiment, when the conductive contact plug is formed in a columnar shape, a trench ring spaced a certain distance from the conductive contact plug may be formed in an annular shape to surround the circumference of the conductive contact plug, and an insulating pattern may be formed by filling an insulating material in a trench. The insulating pattern may have an annular shape.

[0066] refer to Figure 4D and Figure 4E , a third trench T3 or a hole may be formed, which exposes the lower insulating structure LIL while penetrating a portion of the stress release pattern 100 between the insulating patterns 111. The third trench T3 or the hole may extend to a certain depth inside the lower insulating structure LIL. The third trench T3 or the hole may expose the fourth pattern P4 disposed in the uppermost layer among the first to fourth patterns P1 to P4.

[0067] After that, the conductive pattern 113 may be formed so that the third trench T3 or the hole is filled therewith. A diffusion barrier layer formed along the bottom surface and the sidewall of the third trench T3 or the hole may be formed before the conductive pattern 113 is formed.

[0068] The conductive pattern 113 may be directly connected to the fourth pattern P4. Therefore, the first to fourth patterns P1 to P4 and the conductive pattern 113 may constitute a conductive contact plug connected to the discharge impurity region DCI.

[0069] A sidewall of the conductive pattern 113 may contact the stress release pattern 100 (ie, the first to third buffer patterns 101 , 105 , and 109 ). A sidewall of the conductive pattern 113 may be surrounded by the first to third buffer patterns 101 , 105 , and 109 .

[0070] refer to Figure 4F The stack structure 120 may be formed on top of the lower stack structure 100 of the main chip region Main Chip_R and on top of the insulating pattern 111, the conductive pattern 113, and the third buffer pattern 109 of the chip guard region CG_R. That is, the stack structure 120 may be formed on top of the entire structure.

[0071] The stack structure 120 may include first material layers 121 and second material layers 123 that are alternately stacked.

[0072] The first material layer 121 may include a material different from that of the second material layer 123. In an embodiment, the first material layer 121 may include an insulating material, and the second material layer 123 may include a sacrificial material having an etching rate different from that of the first material layer 121. For example, each first material layer 121 may include silicon oxide, and each second material layer 123 may include silicon nitride.

[0073] After that, a channel hole H may be formed, which exposes the lower semiconductor layer 101 while penetrating the stack structure 120 of the main chip region Main Chip_R. The channel hole H may extend to a certain depth inside the lower semiconductor layer 101. That is, the channel hole H may be formed to extend to a certain depth inside the lower semiconductor layer 101 while penetrating the stack structure 120, the upper semiconductor layer 109, the second protective layer 107, the sacrificial layer 105, and the first protective layer 103.

[0074] refer to Figure 4G , the memory layer 125 may be provided at each channel hole ( Figure 4F The memory layer 125 may include a tunnel insulating layer, a data storage layer, and a blocking insulating layer.

[0075] The channel semiconductor pattern 127 may be formed in a central region of each channel hole opened by the memory layer 125. The channel semiconductor pattern 127 may be formed in a column shape filling the central region of each channel hole opened by the memory layer 125. Alternatively, the channel semiconductor pattern 127 may be conformally formed along the surface of the memory layer 125, and the central region of each channel hole may be opened by the channel semiconductor pattern 127. The central region of each channel hole opened by the channel semiconductor pattern 127 may be filled with the core insulating layer 129. The core insulating layer 129 may be formed to have a height lower than that of each of the channel semiconductor pattern 127 and the channel hole. The doped semiconductor pattern 131 may be formed on the core insulating layer 131. The doped semiconductor pattern 131 may be surrounded by the upper end of the channel semiconductor pattern 127 extending longer than the core insulating layer 129.

[0076] The channel semiconductor pattern 127 may include a silicon layer. The doped semiconductor pattern 131 may include an n-type doped silicon layer. The core insulating layer 129 may include an oxide.

[0077] refer to Figure 4H , a stacking structure penetrating the main chip region Main Chip_R can be formed ( Figure 4G The slit S1 of 120) shown in FIG. 1 is formed to expose the sidewall of the stacking structure of the main chip region Main Chip_R.

[0078] After that, the second material layer ( Figure 4G123 shown in ), and a conductive pattern 133 may be formed in the space where the second material layer is removed. Each conductive pattern 133 may include various conductive materials, such as a doped silicon layer, a metal layer, a metal silicide layer, and a barrier layer, and include two or more conductive materials. For example, each conductive pattern 133 may include tungsten and a titanium nitride layer (TiN) surrounding the surface of the tungsten. In an embodiment, tungsten is a low-resistance metal and can reduce the resistance of the conductive pattern 133. The titanium nitride layer TiN is a barrier layer and can prevent or mitigate direct contact between tungsten and the first material layer 121. The alternately stacked first material layers 121 and the conductive patterns 133 may constitute a unit stack structure 130.

[0079] The second material layer 123 formed in the chip guard region CG_R is not etched but may remain. The stack structure 120 including the first material layer 121 and the second material layer 123 formed in the chip guard region CG_R may be defined as a dummy stack structure.

[0080] refer to Fig. 4I , a sidewall insulating layer 135 is formed on the sidewall of the slit SI. The sidewall insulating layer 135 may be formed to expose the bottom surface of the slit SI. The upper semiconductor layer 109 may be exposed through the bottom surface of the slit SI exposed by the sidewall insulating layer 135.

[0081] After that, the upper semiconductor layer 109 and the second protective layer 107 exposed through the slit S1 may be etched, thereby exposing the sacrificial layer ( Figure 4H 105 shown in FIG.

[0082] After that, the horizontal space 137 may be formed by removing the exposed sacrificial layer 105. In the process of removing the sacrificial layer 105 of the main chip region Main Chip_R, the first protection layer ( Figure 4H 103 shown) and the second protective layer ( Figure 4H 107 ) shown can prevent or reduce the loss of the upper semiconductor layer 109 and the lower semiconductor layer 101 .

[0083] After that, a portion of the memory layer exposed by the horizontal space 137 may be etched, thereby exposing the channel semiconductor pattern 127. The memory layer may be divided into the first memory pattern 125a and the second memory pattern 125b through the etching process.

[0084] The first protective layer ( Figure 4H 103 shown in FIG. 103) and the second protective layer ( Figure 4H 107) shown in FIG. 1 can be removed together in the etching process of the memory layer.

[0085] refer to Figure 4J , can be achieved by allowing conductive material to enter the horizontal space through the slit SI ( Fig. 4I 137 shown in , the source semiconductor layer 141 is formed in the channel semiconductor pattern 127. The source semiconductor layer 141 may be in contact with each of the sidewalls of the channel semiconductor pattern 127, the lower semiconductor layer 101, and the upper semiconductor layer 109. The source semiconductor layer 141 may be formed using a chemical vapor deposition technique, or the source semiconductor layer 141 may be formed using a growth technique using each of the channel semiconductor pattern 127, the lower semiconductor layer 101, and the upper semiconductor layer 109 as a seed layer. The source semiconductor layer 141 may include a conductive type dopant. For example, the source semiconductor layer 161 may include an n-type doped silicon layer. The conductive type dopant in the source semiconductor layer 141 may be diffused into the upper semiconductor layer 109 and the channel semiconductor pattern 127 in contact with the source semiconductor layer 141 by heat.

[0086] After that, a source contact structure 143 that contacts the source semiconductor layer 14 and extends onto the sidewall insulating layer 135 may be formed by filling the inside of the slit SI with a conductive material.

[0087] refer to Figure 4K , a fourth trench T4 may be formed, the fourth trench T4 exposing the conductive pattern 113 while penetrating the dummy stack structure 120 of the chip guard region CG_R.

[0088] In the etching process for forming the fourth trench T4, in an embodiment, stress may be generated due to the etching process. However, in an embodiment, the stress concentrated on the edge side of the conductive pattern 113 can be dispersed by a stress release pattern (i.e., the first to third buffer patterns 101, 105, and 109) provided on the sidewall of the conductive pattern 113. In addition, in an embodiment, the stress release pattern (i.e., the first to third buffer patterns 101, 105, and 109) includes a silicon layer having a relatively high Young's modulus to absorb stress, thereby reducing the stress transmitted to its periphery. Therefore, in an embodiment, the occurrence of cracks in a semiconductor device due to stress can be reduced.

[0089] After that, a chip guarding pattern 151 may be formed by filling a conductive material into the fourth trench T4 .

[0090] A lower surface of the chip protection pattern 151 may be directly connected to the conductive pattern 113 .

[0091] Figure 5 is a block diagram illustrating a configuration of a memory system according to an embodiment of the present disclosure.

[0092] refer to Figure 5, a memory system 1000 according to an embodiment of the present disclosure may include a memory device 1200 and a controller 1100 .

[0093] The memory device 1200 may be used to store data information in various data forms such as text, graphics, and software codes. The memory device 1200 may be the memory device 1200 described above. Figures 1 to 3 The semiconductor device described above and according to the reference Figures 4A to 4K The structure and manufacturing method of the memory device 1200 are the same as those described above, and thus a detailed description thereof will be omitted.

[0094] The controller 1100 may be connected to the host and the memory device 1200 and configured to access the memory device 1200 in response to a request from the host. For example, the controller 1100 may be configured to control a read operation, a write operation, an erase operation, a background operation, etc. of the memory device 1200.

[0095] The controller 1100 may include a random access memory (RAM) 1110 , a central processing unit (CPU) 1120 , a host interface 1130 , an error correction code (ECC) circuit 1140 , a memory interface 1150 , and the like.

[0096] The RAM 1110 may be used as a working memory of the CPU 1120, a cache memory between the memory device 1200 and the host, a buffer memory between the memory device 1200 and the host, etc. The RAM 1110 may be replaced with a static random access memory (SRAM), a read only memory (ROM), etc.

[0097] The CPU 1120 may be configured to control the overall operation of the controller 1100. For example, the CPU 1120 may be configured to execute firmware such as a flash translation layer (FTL) stored in the RAM 1110.

[0098] The host interface 1130 may be configured to perform an interface connection with the host. For example, the controller 1100 may communicate with the host through at least one of various interface protocols such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, and a dedicated protocol.

[0099] The ECC circuit 1140 may be configured to detect errors included in data read from the memory device 1200 using ECC, and correct the detected errors.

[0100] The memory interface 1150 may be configured to perform an interface connection with the memory device 1200. For example, the memory interface 1150 may include a NAND interface or a NOR interface.

[0101] The controller 1100 may include a buffer memory (not shown) for temporarily storing data. The buffer memory may be used to temporarily store data transmitted to the outside through the host interface 1130 or to temporarily store data transmitted from the memory device 1200 through the memory interface 1150. Moreover, the controller 1100 may further include a ROM used to store code data for interfacing with the host.

[0102] As such, the memory system 1000 according to an embodiment of the present disclosure includes the memory device 1200 having improved integration and improved characteristics, and thus the integration and characteristics of the memory system 1000 may also be improved.

[0103] According to an embodiment of the present disclosure, a stress relief pattern is provided on a sidewall of a conductive contact plug contacting a bottom of a chip guard pattern, so that stress occurring in an etching process of forming the chip guard pattern can be reduced.

[0104] Although the present disclosure has been shown and described with reference to certain embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments, but should be determined not only by the appended claims but also by their equivalents.

[0105] In the above-described embodiments, all steps may be selectively performed, or some steps may be omitted. In each embodiment, the steps are not necessarily performed in the order described and may be rearranged. The embodiments disclosed in this specification and the accompanying drawings are only examples for facilitating understanding of the present disclosure, and the present disclosure is not limited thereto. That is, it is obvious to those skilled in the art that various modifications may be made on the basis of the technical scope of the present disclosure.

[0106] Meanwhile, embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used herein, these terms are only used to explain embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-described embodiments, and many modifications are possible within the spirit and scope of the present disclosure. It is obvious to those skilled in the art that, in addition to the embodiments disclosed herein, various modifications may also be made based on the technical scope of the present disclosure.

Claims

1. A semiconductor device, comprising: A substrate, including a chip protection area; a stress release pattern, spaced apart from the substrate and disposed above the chip protection region; a dummy stack structure formed on the stress release pattern; A conductive contact plug extending downwardly while penetrating the stress release pattern; as well as A chip protection pattern directly contacts the conductive contact plug and penetrates the dummy stack structure. 2 . The semiconductor device according to claim 1 , wherein the stress relief pattern surrounds a sidewall of the conductive contact plug. 3 . The semiconductor device of claim 1 , wherein the stress releasing pattern comprises a first buffer pattern, a second buffer pattern, and a third buffer pattern sequentially stacked in a vertical direction. 4 . The semiconductor device of claim 3 , wherein each of the first buffer pattern, the second buffer pattern, and the third buffer pattern comprises a doped silicon layer or an undoped silicon layer. 5 . The semiconductor device of claim 3 , wherein the stress release pattern comprises a first protection layer disposed between the first buffer pattern and the second buffer pattern and a second protection layer disposed between the second buffer pattern and the third buffer pattern.

6. The semiconductor device according to claim 1, wherein the substrate of the chip guard region includes a discharge impurity region, and The conductive contact plug is electrically connected to the discharge impurity region. 7 . The semiconductor device according to claim 1 , wherein the conductive contact plug has a substantially linear shape extending in a horizontal direction or has a substantially columnar shape.

8. The semiconductor device according to claim 3, wherein the substrate further comprises a main chip region, and The semiconductor device further comprises: a source layer, spaced apart from the substrate and disposed above the main chip region; as well as A cell stack structure is formed on the source layer. 9 . The semiconductor device according to claim 8 , wherein the source layer is disposed at substantially the same level as the stress relief pattern.

10. The semiconductor device according to claim 8, wherein the source layer comprises a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer which are sequentially stacked, and The first semiconductor layer is made of a material substantially the same as that of the first buffer pattern, and the third semiconductor layer is made of a material substantially the same as that of the third buffer pattern. 11 . The semiconductor device according to claim 1 , further comprising an insulating pattern contacting a sidewall of the stress relief pattern.

12. A semiconductor device comprising: A substrate, including a main chip area and a chip protection area; a source layer, spaced apart from the substrate and disposed above the main chip region; A unit stack structure is formed on the source layer; a stress release pattern, spaced apart from the substrate and disposed above the chip protection region; a dummy stack structure formed on the stress release pattern; as well as a conductive contact plug extending downwardly while penetrating the stress relief pattern, The stress release pattern includes a doped silicon layer or an undoped silicon layer. 13 . The semiconductor device according to claim 12 , further comprising a chip protection pattern that contacts the conductive contact plug while penetrating the dummy stack structure. 14 . The semiconductor device of claim 12 , wherein the stress releasing pattern comprises a first buffer pattern, a second buffer pattern, and a third buffer pattern, the first buffer pattern, the second buffer pattern, and the third buffer pattern surrounding a sidewall of the conductive contact plug and being sequentially stacked in a vertical direction.

15. The semiconductor device according to claim 14, wherein the source layer comprises a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer which are sequentially stacked, and The first buffer pattern is made of substantially the same material as the first semiconductor layer, and the third buffer pattern is made of substantially the same material as the third semiconductor layer.

16. The semiconductor device according to claim 12, wherein the substrate includes a discharge impurity region, and The conductive contact plug is electrically connected to the discharge impurity region. 17 . The semiconductor device according to claim 12 , further comprising an insulating pattern disposed on a sidewall of the stress relief pattern.

18. A method for manufacturing a semiconductor device, the method comprising: forming a source layer on the substrate including the main chip area and the chip protection area; forming an insulating pattern of the source layer penetrating the chip protection region, thereby defining the source layer between the insulating patterns as a stress release pattern; forming a conductive contact plug penetrating the stress release pattern; forming a stacking structure in the main chip region and the chip protection region above the source layer, the stress release pattern and the conductive contact plug, wherein first material layers and second material layers are alternately stacked in the stacking structure; forming a trench for chip protection, wherein the trench for chip protection exposes the conductive contact plug and penetrates the stacked structure of the chip protection area; as well as A chip protection pattern is formed by filling the trench for chip protection formation with a conductive material. 19 . The method of claim 18 , wherein each of the source layer and the stress relief pattern comprises a doped silicon layer or an undoped silicon layer.

20. The method of claim 18, wherein the forming of the conductive contact plug comprises: forming grooves or holes penetrating the stress release pattern between the insulation patterns; as well as forming the conductive contact plug by filling the trench or the hole penetrating the stress relief pattern with a conductive material, The stress relief pattern surrounds a sidewall of the conductive contact plug.

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