Semiconductor device

Abstract

A semiconductor device includes a lower chip structure and an upper chip structure on the lower chip structure. The lower chip structure comprises a storage structure; a lower interconnect structure, the lower interconnect structure being electrically connected to the memory structure; and a lower bond pad, the lower bond pad being electrically connected to the lower interconnect structure. The upper chip structure comprises an upper substrate; the peripheral transistor is positioned on the upper substrate; a first upper interconnect structure electrically connected to the peripheral transistor on the upper substrate; a via penetrating the upper substrate and electrically connected to the first upper interconnect structure; an upper bonding pad which is located below the upper substrate and is bonded to the lower bonding pad; and an intermediate connection structure electrically connecting the upper bond pad and the via between the upper substrate and the lower chip structure.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device. Background Art

[0002] Research is being conducted to reduce the size of elements constituting semiconductor devices and to improve their performance. For example, research is being conducted to reliably and stably form elements with reduced size in dynamic random access memories (DRAMs). Summary of the invention

[0003] Example embodiments provide a semiconductor device that may improve integration.

[0004] According to one aspect of an example embodiment, a semiconductor device includes: a lower chip structure; and an upper chip structure, the upper chip structure being located on the lower chip structure, wherein the lower chip structure includes: a storage structure; a lower interconnect structure, the lower interconnect structure being electrically connected to the storage structure; and a lower bonding pad, the lower bonding pad being electrically connected to the lower interconnect structure, and wherein the upper chip structure includes: an upper substrate; a peripheral transistor, the peripheral transistor being located on the upper substrate; a first upper interconnect structure, the first upper interconnect structure being located on the upper substrate and electrically connected to the peripheral transistor; a via, the via penetrating the upper substrate and being electrically connected to the first upper interconnect structure; an upper bonding pad, the upper bonding pad being located below the upper substrate and bonded to the lower bonding pad; and an intermediate connection structure, the intermediate connection structure being located between the upper substrate and the lower chip structure and electrically connecting the upper bonding pad and the via.

[0005] According to one aspect of an example embodiment, a semiconductor device includes: a lower chip structure, the lower chip structure including: a first storage area; a second storage area; and an extension area, the extension area is located between the first storage area and the second storage area; and an upper chip structure, the upper chip structure is located on the lower chip structure, wherein the lower chip structure also includes: a bit line, the bit line is located in the first storage area and extends into the extension area; and a complementary bit line, the complementary bit line is located in the second storage area and extends into the extension area, wherein the upper chip includes: an upper substrate; a read amplifier array area, the read amplifier array area is located on the upper substrate and includes a read amplifier array area. an amplifier region; and a path penetrating the upper substrate, wherein the sense amplifier array region vertically overlaps the first storage region, wherein a first sense amplifier region among the sense amplifier regions is electrically connected to a first bit line among the bit lines and a first complementary bit line among the complementary bit lines, wherein the first sense amplifier region includes: a first connection region; a second connection region; and a first sense amplifier, and wherein the path includes: a first routing path located below the first connection region and penetrating the upper substrate; and a second routing path located below the second connection region and penetrating the upper substrate.

[0006] According to one aspect of an example embodiment, a semiconductor device includes: a lower chip structure, the lower chip structure including: a first storage area; a second storage area; and an extension area, the extension area is located between the first storage area and the second storage area; and an upper chip structure, the upper chip structure is located on the lower chip structure, wherein the lower chip structure includes: a bit line, the bit line is located in the first storage area and extends into the extension area; a complementary bit line, the complementary bit line is located in the second storage area and extends into the extension area; a lower wiring bonding pad array area, the lower wiring bonding pad array area is located on the first storage area and includes a first lower wiring bonding pad and a second lower wiring bonding pad; a first lower wiring interconnect structure, the first lower wiring interconnect structure electrically connects the bit line and the first lower wiring bonding pad; and a second lower wiring interconnect structure, the second lower wiring interconnect structure electrically connects the complementary bit line and the second lower wiring bonding pad, wherein the upper chip structure includes: an upper substrate; a readout amplifier array area, the readout amplifier array area is located on the upper substrate and includes the readout amplifier area; an upper wiring bonding pad array area, The upper wiring bonding pad array region is located below the upper substrate and includes a first upper wiring bonding pad and a second upper wiring bonding pad; a wiring path, the wiring path penetrating the upper substrate and including a first wiring path and a second wiring path; a first intermediate wiring connection structure, the first intermediate wiring connection structure is located between the upper substrate and the upper wiring bonding pad array region and electrically connects the first wiring path and the first upper wiring bonding pad; and a second intermediate wiring connection structure, the second intermediate wiring connection structure is located between the upper substrate and the upper wiring bonding pad array region and electrically connects the second wiring path and the second upper wiring bonding pad, wherein the first lower wiring bonding pad and the second lower wiring bonding pad are bonded to the first upper wiring bonding pad and the second upper wiring bonding pad, wherein the read amplifier array region, the wiring path, the upper wiring bonding pad array region, and the lower wiring bonding pad array region vertically overlap with the first storage region, and wherein a first read amplifier region among the read amplifier regions is electrically connected to a first bit line among the bit lines and a first upper bit line among the complementary bit lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other aspects, features and advantages will be more readily understood from the following detailed description of example embodiments taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1A , Figure 1B , Figure 2 , Figure 3 , Figure 4 , Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 6 , Fig. 7A , Figure 7B , Figure 8 and Fig. 9 is a view showing a semiconductor device according to one or more example embodiments;

[0009] Fig.10 is a cross-sectional view illustrating a modified example of a semiconductor device according to one or more example embodiments;

[0010] Fig.11 is a top view showing a modified example of a semiconductor device according to one or more example embodiments;

[0011] Fig.12 is a top view showing a modified example of a semiconductor device according to one or more example embodiments;

[0012] Fig.13 is a top view showing a modified example of a semiconductor device according to one or more example embodiments;

[0013] Fig.14 is a top view showing a modified example of a semiconductor device according to one or more example embodiments;

[0014] Fig.15 is a top view showing a modified example of a semiconductor device according to one or more example embodiments;

[0015] Fig.16 is a cross-sectional view illustrating a modified example of a semiconductor device according to one or more example embodiments;

[0016] Fig.17 is a cross-sectional view illustrating a modified example of a semiconductor device according to one or more example embodiments;

[0017] Fig.18 is a cross-sectional view illustrating a modified example of a semiconductor device according to one or more example embodiments;

[0018] Fig.19 is a cross-sectional view illustrating a modified example of a semiconductor device according to one or more example embodiments;

[0019] Fig. 20A and Fig. 20B is a diagram illustrating a modified example of a semiconductor device according to one or more example embodiments;

[0020] Fig.21is a cross-sectional view illustrating a modified example of a semiconductor device according to one or more example embodiments;

[0021] Fig. 22 and Fig.23 is a diagram illustrating an example of a memory structure of a semiconductor device according to one or more example embodiments; and

[0022] Fig.24 , Fig.25A , Fig.25B , Fig.26A , Fig.26B , Fig.27A , Fig.27B , Fig.28A and Fig.28B is a diagram showing an illustrative example of a method of manufacturing a semiconductor device according to one or more example embodiments. DETAILED DESCRIPTION

[0023] Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used for the same components, and their repeated descriptions are omitted.

[0024] Hereinafter, terms such as "upper", "middle", "middle", "lower" and the like may be replaced with other terms such as "first", "second", "third" and the like to describe elements of one or more example embodiments. Terms such as "first", "second", and "third" may be used to describe individual elements of one or more example embodiments, but these elements are not limited by these terms, and the "first element" may be referred to as the "second element". Moreover, in example embodiments, terms such as "lower surface", "upper surface", "uppermost", and "lowermost" may be terms described based on the drawings.

[0025] Figure 1A is a schematic perspective view of a semiconductor device according to one or more example embodiments, and Figure 1B It is schematically shown Figure 1A A top view of a portion of memory body BA.

[0026] refer to Figure 1A and Figure 1B , the semiconductor device 1 according to one or more example embodiments may include a lower chip structure LC and an upper chip structure UC disposed on the lower chip structure LC. The lower chip structure LC and the upper chip structure UC may be sequentially stacked in a vertical direction Z.

[0027] The semiconductor device 1 may include a plurality of memory banks BA and a first peripheral circuit region PER1. Each of the plurality of memory banks BA may include a lower region BAa in the lower chip structure LC and an upper region BAb in the upper chip structure UC.

[0028] The first peripheral circuit region PER1 may include a first lower region PER1a in the lower chip structure LC and a first upper region PER1b in the upper chip structure UC. The first peripheral circuit region PER1 may be a peripheral circuit region in which a peripheral circuit for input / output of data or commands or input of power / ground is disposed.

[0029] Each memory body BA may include a memory region CR, extension regions EXTb and EXTw adjacent to the memory region CR, and a peripheral circuit region PC vertically overlapping the memory region CR. The memory region CR and the extension regions EXTb and EXTw may be disposed in a lower region BAa of a lower chip structure LC of the memory body BA, and the peripheral circuit region PC may be disposed in an upper region BAb of an upper chip structure UC of the memory body BA.

[0030] Each memory region CR includes a cell switching element including a gate electrode, a bit line electrically connected to the cell switching element, and a data storage structure electrically connected to the cell switching element. The gate electrode of the cell switching element may be a word line.

[0031] The extension region EXTb and EXTw may include an extension region EXTb adjacent to the storage region CR in the first direction X and an extension region EXTw adjacent to the storage region CR in the second direction Y. The extension region EXTb adjacent to the storage region CR in the first direction X may be a bit line extension region in which a bit line in the storage region CR extends, and the extension region EXTw adjacent to the storage region CR in the second direction Y may be a word line extension region in which a word line in the storage region CR extends.

[0032] In one or more example embodiments, the first direction X and the second direction Y may be perpendicular to each other. The first direction X and the second direction Y may be perpendicular to the vertical direction Z.

[0033] The storage region CR may include a first storage region CR1 and a second storage region CR2 adjacent to the first storage region CR1 and spaced apart from the first storage region CR1 by the extension region EXTb.

[0034] Each peripheral circuit region PC may include a sense amplifier array region SAR, a sub word line driver region SWDR, and a second peripheral circuit region PER2 located between the sense amplifier array region SAR and the sub word line driver region SWDR.

[0035] refer to Figure 2 , Figure 3 and Figure 4 as well as Figure 1A and Figure 1B, an electrical connection relationship between the first and second storage regions CR1 and CR2 included in the lower chip structure LC and the sense amplifier array region SAR included in the upper chip structure UC will be described. Figure 2 is a three-dimensional conceptual perspective view illustrating electrical connections of a semiconductor device according to one or more example embodiments. Figure 3 is a conceptual block diagram illustrating an electrical connection relationship between first and second storage regions CR1 and CR2 and a sense amplifier array region SAR included in an upper chip structure UC in a semiconductor device according to one or more example embodiments. Figure 4 According to one or more example embodiments, Figure 2 and Figure 3 The present invention is a diagram of a circuit of a sense amplifier SA, and is a diagram showing the electrical connection relationship between a first sense amplifier SA1 among the sense amplifier SA, a first bit line BL1 among multiple bit lines BL electrically connected to the first sense amplifier SA1, and a first complementary bit line BLB1 among multiple complementary bit lines BLB electrically connected to the first sense amplifier SA1.

[0036] refer to Figure 2 as well as Figure 1A and Figure 1B The first memory region CR1 may include a first memory structure including a bit line BL and a word line WL. The bit line BL may extend in a first direction X, and the word line WL1 may extend in a second direction Y perpendicular to the first direction X.

[0037] The second memory region CR2 may include a second memory structure including a bit line BLB and a word line WL2. The bit line BLB may extend in a first direction X, and the word line WL2 may extend in a second direction Y.

[0038] In the semiconductor device 1, when the first storage area CR1 is a normal storage area and the second storage area CR2 is a reference storage area, the bit line BL of the first storage area CR1 may be a bit line for sensing data stored in a data storage structure in the first storage area CR1, and the bit line BLB of the second storage area CR2 may be a complementary bit line.

[0039] Hereinafter, for the sake of description, the bit line BL of the first memory region CR is referred to as a “bit line”, and the bit line BLB of the second memory region CR2 will be referred to as a complementary bit line.

[0040] The sense amplifier array region SAR may include a plurality of unit sense amplifier regions SARu. Each unit sense amplifier region SARu may include a first connection region SAC1, a second connection region SAC2, and a sense amplifier SA located between the first connection region SAC1 and the second connection region SAC2.

[0041] The semiconductor device 1 may include a wiring structure CS electrically connecting a bit line BL of the first memory region CR1 , a complementary bit line BLB of the second memory region CR2 , and a unit sense amplifier region SARu.

[0042] The wiring structure CS may include a first wiring structure CS1 electrically connecting the bit lines BL of the first storage region CR1 and the first connection region SAC1, and a second wiring structure CS2 electrically connecting the complementary bit lines BLB of the second storage region CR2 and the second connection region SAC2.

[0043] The bit lines BL of the first storage region CR1 may be provided as a plurality of bit lines BL. The bit lines BL may be spaced apart from each other in the second direction Y. The complementary bit lines BLB of the second storage region CR2 may be provided as a plurality of complementary bit lines. The complementary bit lines BLB may be spaced apart from each other in the second direction Y.

[0044] The bit lines BL of the first memory region CR1 may extend into the extension region EXTb and may be electrically connected to the first wiring structure CS1. The complementary bit lines BLB of the second memory region CR2 may extend into the extension region EXTb and may be electrically connected to the second wiring structure CS2.

[0045] The first storage area CR1 and the second storage area CR2 may be electrically connected to the sense amplifier array area SAR. The bit lines BL of the first storage area CR1 may include n bit lines BL1, BL2, ..., BLn. The complementary bit lines BLB of the second storage area CR2 may include n complementary bit lines BLB1, BLB2, ..., BLBn. The sense amplifier SA of the sense amplifier array area SAR may include n sense amplifiers SA1, SA2, ..., SAn. One sense amplifier SA1 among the sense amplifiers SA1, SA2, ..., SAn may be electrically connected to a first bit line BL1 among the bit lines BL1, BL2, ..., BLn and a first complementary bit line BLB1 among the complementary bit lines BLB1, BLB2, ..., BLBn.

[0046] The bit line BL and the sense amplifier SA may be electrically connected through a first wiring structure CS1, and the complementary bit line BLB and the sense amplifier SA may be electrically connected through a second wiring structure CS2.

[0047] Each of the wiring structures CS may include a wiring via 145. For example, the first wiring structure CS1 may include a first wiring via 145a in the first connection area SAC1. The second wiring structure CS2 may include a second wiring via 145b in the second connection area SAC2.

[0048] The first sense amplifier SA1 may include a plurality of transistors P1_a, P1_b, N1_a, and N1_b.

[0049] Transistors P1_a, P1_b, N1_a, and N1_b may include transistors P1_a and P1_b as P-channel transistors, and transistors N1_a and N1_b as N-channel transistors. Transistors P1_a and P1_b may be referred to as a P-channel transistor pair, and transistors N1_a and N1_b may be referred to as an N-channel transistor pair.

[0050] In one or more example embodiments, the P-channel transistor may be a p-channel metal oxide semiconductor (PMOS) transistor, and the N-channel transistor may be an n-channel metal oxide semiconductor (NMOS) transistor.

[0051] The source of the transistor P1_a and the source of the transistor P1_b may be connected to the first control line LA through the first node ND1_a. The source of the transistor N1_a and the source of the transistor N1_b may be connected to the second control line LAB through the second node ND1_b.

[0052] The first node ND1_a and the second node ND1_b may be referred to as a first source node and a second source node, respectively.

[0053] The drain of the transistor P1_a and the drain of the transistor N1_a may be connected to the first bit line BL1 through the first drain node ND1_c. The first bit line BL1 may be connected to the first bit line BL1 through the first wiring structure ( Figure 2 CS1) is electrically connected to the first drain node ND1_c.

[0054] The drain of the transistor P1_b and the drain of the transistor N1_b may be connected to the first complementary bit line BLB1 through the second drain node ND1_d. The first complementary bit line BLB1 may be connected to the first complementary bit line BLB1 through the second wiring structure ( Figure 2 CS2) is electrically connected to the second drain node ND1_d.

[0055] The sense amplifier SA1 can sense and amplify the voltage change of the bit line BL1. When the sense amplifier SA1 performs sensing and amplification operations, the internal power supply voltage of the semiconductor device 1 can be applied to the first node ND1_a through the first control line LA, and the second node ND1_b can be connected to the ground terminal through the second control line LAB.

[0056] Figure 4 The sense amplifier SA1 includes a P-channel transistor pair and an N-channel transistor pair, and is implemented as a circuit configuration in which the transistors are cross-coupled, but this is an example embodiment, and the example embodiments are not limited thereto. For example, according to one or more example embodiments, Figure 4 The circuit of the sense amplifier SA1 can be implemented using various circuit configurations.

[0057] Next, we will refer to Figure 1, Figure 2 , Figure 3 and Figure 4 as well as Figure 5A , Figure 5B , Figure 5C and Figure 5D Elements of a semiconductor device according to one or more example embodiments are described. Figure 5A is a top view illustrating a memory cell array region MCA and bit lines BL in a first memory region CR1 according to one or more example embodiments, Figure 5B is a top view illustrating a unit sense amplifier region SARu provided in a sense amplifier array region SAR according to one or more example embodiments, Figure 5C is a block diagram illustrating a unit sense amplifier region SARu according to one or more example embodiments, and Figure 5D is a top plan view illustrating a pad array region PADR in which a unit bonding pad region PADu is disposed according to one or more example embodiments.

[0058] refer to Figure 5A , Figure 5B , Figure 5C and Figure 5D And Figure 1, Figure 2 , Figure 3 and Figure 4 The memory cell array area MCA may have a quadrilateral shape having a first length L1 in the second direction Y and a second length L2 in the first direction X. Each of the bit lines BL may have a line shape extending in the first direction X, and the bit lines BL may be spaced apart from each other in the second direction Y.

[0059] The bit lines BL may be arranged to have a first pitch a. According to one or more example embodiments, the first pitch a may be defined as a distance between a first side of one bit line and a first side of another bit line in a pair of adjacent bit lines among the bit lines BL. In this case, the "first side" may be a side in either direction.

[0060] The sense amplifier array region SAR may have a quadrilateral shape having a third length D1 in the second direction Y and a fourth length D2 in the first direction X. The memory cell array region MCA may vertically overlap the sense amplifier array region SAR.

[0061] The unit sense amplifier regions SARu may be two-dimensionally arranged in the first direction X and the second direction Y. Each of the unit sense amplifier regions SARu may have a quadrilateral shape having a fifth length d1 in the second direction Y and a sixth length d2 in the first direction X. Each of the unit sense amplifier regions SARu may include the first and second connection regions SAC1 and SAC2, and the sense amplifier SA between the first and second connection regions SAC1 and SAC2, as described above.

[0062] The pad array region PADR in which the unit bonding pad region PADu is disposed may have a quadrilateral shape having a seventh length α in the second direction Y and an eighth length β in the first direction X.

[0063] In the pad array region PADR, the unit landing pad regions PADu may be two-dimensionally arranged in the first direction X and the second direction Y. Each unit landing pad region PADu may have a quadrilateral shape having a ninth length b in the second direction Y and a tenth length c in the first direction X.

[0064] A wiring bonding pad may be disposed in each unit bonding pad region PADu. The wiring bonding pads PAD disposed in the pad array region PADR may be spaced apart from each other.

[0065] The lower chip structure LC may include a memory cell array area MCA in the memory region CR. For example, the first memory region CR may include the memory cell array area MCA.

[0066] The upper chip structure UC may include a sense amplifier array region SAR. The sense amplifier array region SAR of the upper chip structure UC may vertically overlap the memory cell array region MCA.

[0067] Each of the lower chip structure LC and the upper chip structure UC may include a pad array region PADR. The pad array region PADR of the lower chip structure LC and the pad array region PADR of the upper chip structure UC may face each other and may be joined to each other. The pad array region PADR of each of the lower chip structure LC and the upper chip structure UC may vertically overlap the memory cell array region MCA and the sense amplifier array region SAR.

[0068] In one or more example embodiments, the number N1 of wiring pads PAD disposed in the second direction Y in the pad array region PADR may be determined by Equation 1 below.

[0069]

[0070] In Formula 1, N1 is the number N1 of wiring pads PAD disposed in the second direction Y within the pad array region PADR, b is the ninth length b, and D1 is the third length D1, and n may be a positive integer.

[0071] In one or more example embodiments, the number N2 of wiring pads PAD disposed in the first direction X may be determined by Equation 2 below.

[0072]

[0073] In Formula 2, N2 is the number N2 of wiring pads PAD arranged in the first direction X within the pad array region PADR, c is the tenth length c, and D2 is the fourth length D2, and n may be a positive integer.

[0074] In one or more example embodiments, the wiring pad PAD and the bit line BL may be set to satisfy the condition of Equation 3 below.

[0075]

[0076] In Formula 3, a may be the first pitch a, and L1 may be the first length L1.

[0077] In one or more example embodiments, the number N3 of bit lines BL vertically overlapping the unit bonding pad region PADu may be determined by Equation 4 below.

[0078]

[0079] In Formula 4, N3 is the number N3 of bit lines BL vertically overlapping the unit pad region PADu, a is the first pitch a, and b is the ninth length b, and n may be a positive integer.

[0080] In one or more example embodiments, the unit bonding pad area PADu and the unit sense amplifier area SARu may be determined by Equation 5 and Equation 6 below.

[0081] b=n 1 ×d1,(n 1 =1,2,3,…)…Formula 5

[0082] In Formula 5, b is a ninth length b of the unit bonding pad region PADu in the second direction Y, and d1 may be a fifth length d1 of the unit sense amplifier region SARu in the second direction Y.

[0083] D2=n 2 ×d2,(n 2 =1,2,3,…)…Formula 6

[0084] In Formula 6, D2 may be a fourth length D2 of the sense amplifier array region SAR in the first direction X, and d2 may be a sixth length d2 of the unit sense amplifier region SARu in the first direction X.

[0085] In one or more example embodiments, the unit bonding pad region PADu and the unit sense amplifier region SARu may satisfy Expression 7 below.

[0086] n 1 ×n 2 ≥N2…Expression 7

[0087] In Expression 7, the number N2 of wiring pads PAD disposed in the first direction X determined by Expression 2 may be an odd number or an even number.

[0088] In one or more example embodiments, when the number of unit sense amplifier regions SARu disposed in the first direction X in the sense amplifier array region SAR is N4, the following number of interconnection lines may be required between the via 145 and the bit line BL. Therefore, the number N5 of interconnection lines disposed between the via 145 and the bit line BL may be determined by the following Formula 8.

[0089]

[0090] According to one or more example embodiments, the interconnection line may include interconnection lines arranged at different levels and may not include bonding pads. Each interconnection line may include a pad extending in a horizontal direction or an interconnection line including a pad, and in this case, the pad may include a pad of a contact plug instead of a bonding pad.

[0091] In one or more example embodiments, the number N5 of interconnection lines disposed between the via 145 and the bit line BL may be one or more additional interconnection lines required for alignment between the via 145 and the bonding pad PAD.

[0092] Next, we will refer to Figure 6 As well as Figure 1, Figure 2 , Figure 3 , Figure 4 , Figure 5A , Figure 5B , Figure 5C and Figure 5D Elements of a semiconductor device according to one or more example embodiments are described. Figure 6 1 is a diagram showing the above-mentioned electrical connection relationship between the unit sense amplifier region SARu, the bonding pad PAD of the unit bonding pad region PADu, and the wiring path 145. In detail, Figure 6 It is a conceptual diagram showing the electrical connection relationship between the first bit line BL1, the second bit line BL2, the third bit line BL3 and the fourth bit line BL4 among the bit lines BL, the first complementary bit line BLB1, the second complementary bit line BLB2, the third complementary bit line BLB3 and the fourth complementary bit line BLB4 among the complementary bit lines BLB, and the first unit sense amplifier region SARu1, the second unit sense amplifier region SARu2, the third unit sense amplifier region SARu3 and the fourth unit sense amplifier region SARu4 among the unit sense amplifier region SARu.

[0093] refer to Figure 6 And Figure 1, Figure 2 , Figure 3 , Figure 4 , Figure 5A , Figure 5B , Figure 5C and Figure 5D , each sense amplifier SA of the unit sense amplifier region SARu may be electrically connected to one bit line BL and one complementary bit line BLB through the wiring structure CS. For example, the sense amplifier SA1 of the first unit sense amplifier region SARu1 may be electrically connected to the first bit line BL1 and the first complementary bit line BLB1, the sense amplifier SA2 of the second unit sense amplifier region SARu2 may be electrically connected to the second bit line BL2 and the second complementary bit line BLB2, the sense amplifier SA3 of the third unit sense amplifier region SARu3 may be electrically connected to the third bit line BL3 and the third complementary bit line BLB3, and the sense amplifier SA4 of the fourth unit sense amplifier region SARu4 may be electrically connected to the fourth bit line BL4 and the fourth complementary bit line BLB4.

[0094] The bit line BL may be electrically connected to the sense amplifier SA through a first wiring via 145 a of the wiring structure CS, and the complementary bit line BLB may be electrically connected to the sense amplifier SA through a second wiring via 145 b of the wiring structure CS.

[0095] Next, we will refer to Fig. 7A , Figure 7B and Figure 8 To describe the reference Figure 1A , Figure 1B , Figure 2 , Figure 3 , Figure 4 , Figure 5A , Figure 5B , Figure 5C , Figure 5D and Figure 6 A cross-sectional structure of a semiconductor device 1 is described. Fig. 7A is a cross-sectional view illustrating a portion of a memory bank BA of a semiconductor device according to one or more example embodiments, Figure 7B is a cross-sectional view illustrating a portion of a first peripheral circuit region PER1 of a semiconductor device according to one or more example embodiments, and Figure 8 yes Fig. 7A A partial enlarged view of the area indicated by "B".

[0096] refer to Fig. 7A , Figure 7B and Figure 8 as well as Figure 1A , Figure 1B , Figure 2 , Figure 3 , Figure 4 , Figure 5A , Figure 5B , Figure 5C , Figure 5D and Figure 6 As described above, according to one or more example embodiments, the semiconductor device 1 may include a lower chip structure LC and an upper chip structure UC that are sequentially stacked.

[0097] As described above, the lower chip structure LC may include the first peripheral circuit region PER1 , the first storage region CR1 , the second storage region CR2 , and the extension region EXTb between the first storage region CR1 and the second storage region CR2 .

[0098] The lower chip structure LC may include a lower substrate 5, a storage structure MS and a power capacitor CAPp on the lower substrate 5, a lower interconnection structure 25 electrically connected to the storage structure MS and the power capacitor CAPp on the lower substrate 5, a lower insulating structure 20 covering the storage structure MS and the lower interconnection structure 25 on the lower substrate 5, and a lower bonding insulating layer 60 and a lower bonding pad 65 on the lower insulating structure 20.

[0099] Each memory structure MS may include a word line WL, bit lines BLa and BLb, and a data storage structure DS. Each data storage structure DS may include a first electrode SN, a second electrode PL covering the first electrode SN, and a dielectric layer DI between the first electrode SN and the second electrode PL.

[0100] The lower substrate 5 may include a lower semiconductor substrate and a cell isolation region cSTI located on the lower semiconductor substrate. The word lines WL may be buried in the lower substrate 5.

[0101] The data storage structure DS may be a memory cell capacitor capable of storing data in a memory such as a dynamic random access memory (DRAM).

[0102] The first peripheral circuit region PER1 may include a power capacitor CAPp. The power capacitor CAPp may include a lower electrode ELa, an upper electrode ELb, and a dielectric layer DIb located between the lower electrode ELa and the upper electrode ELb. The lower electrode ELa may include a first lower electrode ELa1, a second lower electrode ELa2 located on the first lower electrode ELa1, and a third lower electrode ELa3 located on the second lower electrode ELa2. The third lower electrode ELa3 may be disposed at substantially the same height as the first electrode SN.

[0103] The first storage region CR1 may include a first storage structure among the storage structures MS, and the second storage region CR2 may include a second storage structure among the storage structures MS.

[0104] The first memory structure MS of the first memory region CR1 may include a first bit line indicated by BLa among the bit lines BLa and BLb, and the first bit line BLa may be a bit line BL electrically connected to the above-mentioned sense amplifier SA.

[0105] Among the bit lines BLa and BLb, the second storage area ( Figure 1B and Figure 2 The second storage structure MS of CR2 in FIG. 5 may include a second bit line indicated by BLb. The second bit line BLb may be a complementary bit line BLB electrically connected to the above-mentioned sense amplifier SA.

[0106] Hereinafter, the first bit line BLa will be described by referring to the bit line BL electrically connected to the above-mentioned sense amplifier SA, and the second bit line BLb will be described by referring to the complementary bit line BLB electrically connected to the above-mentioned sense amplifier SA.

[0107] The lower interconnection structure 25 may include a first lower wiring interconnection structure 25 a electrically connected to the bit line BL, a second lower wiring interconnection structure 25 b electrically connected to the complementary bit line BLB, and a third lower wiring interconnection structure 25 c electrically connected to the upper electrode ELb.

[0108] Each of the lower interconnection structures 25 may include at least two horizontal portions 30L and 32L disposed at different heights, and may include vertical portions 30V, 32V, and 34V disposed at different heights.

[0109] In one or more example embodiments, the "vertical portion" may include a plug or a via extending vertically, and the "horizontal portion" may include a pad extending horizontally or an interconnect including the pad. Therefore, the "vertical portion" may be referred to as a plug or a via, and the "horizontal portion" may be referred to as an interconnect.

[0110] Therefore, each of the lower interconnection structures 25 may include at least two interconnection lines 30L and 32L disposed at different heights, and plugs 30V, 32V, and 34V electrically connected to the at least two interconnection lines 30L and 32L.

[0111] In the first lower wiring interconnect structure 25a electrically connected to the bit line BL and the second lower wiring interconnect structure 25b electrically connected to the complementary bit line BLB, at least one of the at least two interconnection lines 30L and 32L may extend from the extension region EXTb to the first storage region CR1. The at least two interconnection lines 30L and 32L may include a first lower interconnection line 30L and a second lower interconnection line 32L disposed at a height higher than the first lower interconnection line 30L.

[0112] In the first storage region CR1 , at least one of at least two interconnection lines 30L and 32L in the first and second lower wiring interconnection structures 25 a and 25 b may be disposed on the data storage structure DS of the memory structure MS.

[0113] The plugs 30V, 32V, and 34V of the first and second lower wiring interconnection structures 25a and 25b may include a first lower plug 30V located below the first lower interconnection line 30L, a second lower plug 32V located between the first and second lower interconnection lines 30L and 32L, and a third lower plug 34V located on the second lower interconnection line 32L.

[0114] The first lower wiring interconnection structure 25a may include: at least two lower interconnection lines 30L and 32L disposed at a higher height than the data storage structure DS and disposed at different heights; at least one middle plug 32V electrically connecting the at least two lower interconnection lines 30L and 32L; a lower plug 30V electrically connecting the lowermost lower interconnection line 30L of the at least two lower interconnection lines 30L and 32L and a bit line contact region of the bit line BL; and an upper plug 34V electrically connecting the uppermost lower interconnection line 32L of the at least two lower interconnection lines 30L and 32L and the lower bonding pad 65. In this case, the lower plug 30V does not vertically overlap the data storage structure DS, and at least one of the at least two lower interconnection lines 30L and 32L may include a region that does not vertically overlap the data storage structure DS, and may include a region that vertically overlaps the data storage structure DS.

[0115] The bit line BL may extend from the first storage region CR1 to the extension region EXTb. The bit line BL may have a contact region of the first lower plug 30V contacting the first lower wiring interconnect structure 25a in the extension region EXTb. The complementary bit line BLB may have a bit line contact region of the first lower plug 30V contacting the second lower wiring interconnect structure 25b in the extension region EXTb.

[0116] The lower bonding pads 65 may include lower wiring bonding pads 65 a and 65 b electrically connected to the first and second lower wiring interconnection structures 25 a and 25 b .

[0117] The lower wiring bonding pads 65a and 65b may be disposed in the first storage region CR1. The lower wiring bonding pads 65a and 65b may be disposed on the storage structure MS. The lower wiring bonding pads 65a and 65b may vertically overlap with the data storage structure DS of the storage structure MS. In the first storage region CR1, at least one of the at least two interconnection lines 30L and 32L of the first lower wiring interconnect structure 25a and the second lower wiring interconnect structure 25b may vertically overlap with the data storage structure DS on the data storage structure DS of the storage structure MS.

[0118] The third lower plug 34V of the first lower wiring interconnect structure 25a and the second lower wiring interconnect structure 25b may be electrically connected to the lower wiring bonding pads 65a and 65b. The lower wiring bonding pads 65a and 65b may include a first lower wiring bonding pad 65a connected to the first lower wiring interconnect structure 25a and a second lower wiring bonding pad 65b electrically connected to the second lower wiring interconnect structure 25b. The first lower wiring bonding pad 65a may contact and may be connected to the third lower contact plug 34V of the first lower wiring interconnect structure 25a, and the second lower wiring bonding pad 65b may contact and may be connected to the third lower contact plug 34V of the second lower wiring interconnect structure 25b.

[0119] An upper surface of the lower bonding pad 65 and an upper surface of the lower bonding insulation layer 60 may be coplanar.

[0120] The upper chip structure UC may include an upper bonding pad 165, an upper bonding insulation layer 160, an intermediate insulation structure 155, an intermediate connection structure 150, an upper substrate 105, a peripheral transistor PTR, a first upper interconnect structure 125, a first upper insulation structure 120, a second upper interconnect structure 175, a second upper insulation structure 170, a covering insulation layer 185, an input / output pad 190, a via 145, and an insulating spacer 147.

[0121] An upper bonding insulation layer 160 and an upper bonding pad 165 may be disposed under the upper substrate 105 .

[0122] The upper bonding insulation layer 160 may contact and may be bonded to the lower bonding insulation layer 60. The lower bonding insulation layer 60 may include the same material as the upper bonding insulation layer 160. Each of the lower bonding insulation layer 60 and the upper bonding insulation layer 160 may include at least one of silicon oxide, SiCN, and SiCON.

[0123] The upper bonding pad 165 may be bonded while contacting the lower bonding pad 65. The upper bonding pad 165 may include the same metal material as the lower bonding pad 65, for example, copper.

[0124] The upper bonding pad 165 may include upper wiring bonding pads 165a and 165b electrically connected to and bonded to the lower wiring bonding pads 65a and 65b. For example, the upper wiring bonding pads 165a and 165b may include a first upper wiring bonding pad 165a connected to the first lower wiring bonding pad 65a, and a second upper wiring bonding pad 165b connected to the second lower wiring bonding pad 65b.

[0125] The lower wiring bonding pads 65a and 65b and the upper wiring bonding pads 165a and 165b may include reference Figure 5D and Figure 6Therefore, the lower chip structure LC may include a wiring bonding pad array region ( Figure 5D The upper chip structure LC may include a wiring bonding pad array region (PADR) in which upper wiring bonding pads 165a and 165b are disposed. Figure 5D in PADR).

[0126] Wiring Bond Pad Array Area ( Figure 5D The PDAR in the first storage region CR1 may vertically overlap the data storage structure DS of the storage structure MS of the first storage region CR1.

[0127] The first lower wiring bonding pad 65a and the first upper wiring bonding pad 165a bonded to each other may include a wiring bonding pad PAD electrically connected to the bit line BL. The second lower wiring bonding pad 65b and the second upper wiring bonding pad 165b bonded to each other may be a wiring bonding pad PAD electrically connected to the complementary bit line BLB.

[0128] The intermediate connection structure 150 and the intermediate insulation structure 155 may be disposed on the upper bonding insulation layer 160 and the upper bonding pad 165, and may be disposed under the upper substrate 105. The intermediate connection structure 150 may be disposed within the intermediate insulation structure 155.

[0129] Each intermediate connection structure 150 may include at least one intermediate interconnection line 152L and intermediate plugs 152V1 and 152V2 connected to the at least one intermediate interconnection line 152L. For example, the intermediate plugs 152V1 and 152V2 may include a first intermediate plug 152V1 on the at least one intermediate interconnection line 152L and a second intermediate plug 152V2 under the at least one intermediate interconnection line 152L.

[0130] The intermediate connection structure 150 may include intermediate wiring connection structures 150a and 150b electrically connected to the upper wiring bonding pads 165a and 165b. The intermediate wiring connection structures 150a and 150b may include a first intermediate wiring connection structure 150a connected to the first upper wiring bonding pad 165a, and a second intermediate wiring connection structure 150b connected to the second upper wiring bonding pad 165b.

[0131] The upper substrate 105 may be disposed on the intermediate insulating structure 155 and the intermediate connecting structure 150. The upper substrate 105 may include an upper semiconductor substrate 110, a lower protective insulating layer 140 located below the upper semiconductor substrate 110, an upper active region pACT located on the upper semiconductor substrate 110, and an upper isolation region pSTI located on the upper semiconductor substrate 110 that may define the upper active region pACT.

[0132] The peripheral transistor PTR may include an upper gate PGox and PGE located on the upper active region pACT and an upper source / drain PSD located in the upper active region pACT on both sides of the upper gate PGox and PGE, respectively. The upper gate PGox and PGE may include an upper gate electrode PGE and an upper gate dielectric layer PGox between the upper gate electrode PGE and the upper active region pACT.

[0133] The peripheral transistor PTR may include a transistor vertically overlapping the storage structure MS of the first storage region CR1 and the second storage region CR2, and a transistor vertically overlapping the first peripheral circuit region PER1. For example, the peripheral transistor PTR may include a first transistor and a second transistor ( Figure 8 The first transistor and the second transistor can configure a plurality of transistors ( Figure 4 P1_a, P1_b, N1_a and N1_b) of the first storage region CR1 while vertically overlapping the storage structures MS of the first storage region CR1.

[0134] The first upper interconnection structures 125 may form a peripheral circuit by electrically connecting the peripheral transistors PTR on the upper substrate 105. Each of the first upper interconnection structures 125 may include vertical portions 130V and 132V disposed at different heights, and horizontal portions 130L and 132L disposed at different heights.

[0135] The first upper interconnect structure 125 may include a first transistor and a second transistor ( Figure 8 The first upper wiring interconnect structure 125a and the second upper wiring interconnect structure 125b of PTR1 and PTR2 in FIG. 125a and the second upper wiring interconnect structure 125b may constitute a plurality of transistors ( Figure 4 P1_a, P1_b, N1_a and N1_b in it).

[0136] The first upper insulating structure 120 may be disposed on the upper substrate 105 , and may cover the peripheral transistor PTR and the first upper interconnection structure 125 .

[0137] The via 145 may pass through the upper substrate 105. The via 145 may electrically connect the first upper interconnection structure 125 to the intermediate connection structure 150. The via 145 may be connected to the first horizontal portion 130L positioned in the lower portion among the horizontal portions 130L and 132L of the first upper interconnection structure 125.

[0138] The via 145 may include wiring vias 145a and 145b. The wiring vias 145a and 145b may include a first wiring via 145a electrically connecting the first upper wiring interconnect structure 125a and the first intermediate wiring connection structure 150a, and a second wiring via 145b electrically connecting the second upper wiring interconnect structure 125b and the second intermediate wiring connection structure 150b.

[0139] The first wiring via 145 a may pass through the upper substrate 105 under the first connection region SAC1 , and the second wiring via 145 b may pass through the upper substrate 105 under the second connection region SAC2 .

[0140] Each of the vias 145 may include a conductive pillar 142 a and a barrier layer 142 b covering side surfaces and a lower surface of the conductive pillar 142 a .

[0141] The passage 145 may have an inclined side surface whose width decreases in a direction from the bottom to the top.

[0142] The insulating spacer 147 may cover the side surface of the via 145 .

[0143] In one or more example embodiments, the bit line BL in the first storage region CR1 may be electrically connected to the peripheral transistor PTR constituting the sense amplifier SA through the first lower wiring interconnect structure 25a, the first lower wiring bonding pad 65a, the first wiring via 145a, and the first upper wiring interconnect structure 125a.

[0144] In one or more example embodiments, the second storage area ( Figure 2 and Figure 3 The complementary bit line BLB in CR2) can be electrically connected to the peripheral transistor PTR constituting the readout amplifier SA through the second lower wiring interconnect structure 25b, the second lower wiring bonding pad 65b, the second wiring path 145b and the second upper wiring interconnect structure 125b.

[0145] The second upper interconnection structure 175 may include vertical portions 172V, 174V, 176V, and 178V disposed at different heights, and horizontal portions 172L, 174L, and 176L disposed at different heights. At least one of the horizontal portions 172L, 174L, and 176L of the second upper interconnection structure 175 may have a thickness greater than that of the horizontal portions 130L and 132L of the first upper interconnection structure 125. The second upper insulating structure 170 may cover the second upper interconnection structure 175 on the first upper insulating structure 120. A cover insulating layer 185 may be disposed on the second upper insulating structure 170.

[0146] The input / output pad 190 may be electrically connected to the second upper interconnection structure 175, and a side surface thereof may be surrounded by the second upper insulating structure 170. An upper surface of the input / output pad 190 may be exposed.

[0147] Next, refer to Fig. 9 , will be described according to one or more example embodiments Fig. 7A , Figure 7B and Figure 8 145a and 145b in FIG. 146. An illustrative example of the planar arrangement of the intermediate wiring connection structures 150a and 150b, the upper wiring bonding pads 165a and 165b, and the wiring vias 145a and 145b in FIG. Fig. 9 1 is a top view showing intermediate wiring connection structures 150a and 150b, upper wiring bonding pads 165a and 165b, and wiring vias 145a and 145b.

[0148] refer to Fig. 9 As well as the above Fig. 7A , Figure 7B and Figure 8 , the upper wiring bonding pads 165a and 165b may be respectively disposed in the unit bonding pad region 165R. The unit bonding pad region 165R may correspond to the reference Figure 5D Describe the unit bonding pad area PADu.

[0149] The wiring paths 145 a and 145 b may vertically overlap the unit landing pad region 165R.

[0150] At least a portion of the first wiring via 145a may not vertically overlap the first upper wiring bonding pad 165a. At least a portion of the second wiring via 145b may not vertically overlap the second upper wiring bonding pad 165b.

[0151] In the first intermediate wiring connection structure 150a, the first intermediate plug 152V1 may be connected to the first wiring via 145a while vertically overlapping the first wiring via 145a; the second intermediate plug 152V2 may be connected to the first upper wiring bonding pad 165a while vertically overlapping the first upper wiring bonding pad 165a; and the intermediate interconnection line 152L may be connected to the first intermediate plug 152V1 and the second intermediate plug 152V2. In the first intermediate wiring connection structure 150a, a plurality of second intermediate plugs 152V2 may be provided, and the plurality of second intermediate plugs 152V2 may be connected to the intermediate interconnection line 152L and the first upper wiring bonding pad 165a.

[0152] In the second intermediate wiring connection structure 150b, the first intermediate plug 152V1 may be connected to the second wiring via 145b while vertically overlapping the second wiring via 145b, the second intermediate plug 152V2 may be connected to the second upper wiring bonding pad 165b while vertically overlapping the second upper wiring bonding pad 165b, and the intermediate interconnection line 152L may be connected to the first intermediate plug 152V1 and the second intermediate plug 152V2. In the second intermediate wiring connection structure 150b, a plurality of second intermediate plugs 152V2 may be provided, and the plurality of second intermediate plugs 152V2 may be connected to the intermediate interconnection line 152L and the second upper wiring bonding pad 165b.

[0153] Next, various modified examples of the elements of one or more of the above-described example embodiments will be described. Various modified examples of the elements of one or more of the above-described example embodiments described below will be described focusing on the modified or replaced elements. According to one or more example embodiments, the above-described elements may be directly referenced without a separate detailed description, or the description may be omitted. In addition, the elements described below that may be modified or replaced are described with reference to the following drawings, but the elements that may be modified or replaced may be combined with each other or with the above-described elements to configure a semiconductor device according to one or more example embodiments.

[0154] refer to Fig.10 , modified examples of the intermediate connection structure 150 , the upper bonding pads 165 , and the lower bonding pads 65 will be described according to one or more example embodiments. Fig.10 is a diagram showing a method according to one or more example embodiments Figure 8 A cross-sectional view of a modified example of the intermediate connection structure 150, the upper bonding pad 165, and the lower bonding pad 65 in the cross-sectional structure of FIG. Fig.11 is a diagram showing a method according to one or more example embodiments Fig. 9 FIG. 1 is a top view of a modified example of the intermediate connection structure 150 and the upper bonding pad 165 in a top view.

[0155] refer to Fig.10 and Fig.11 According to one or more exemplary embodiments, the intermediate connection structure ( Fig. 7A , Figure 7B and Figure 8 Each of the intermediate connection structures 150 in 150_1 may be replaced with an intermediate connection structure 150_1 that may be configured as a vertical portion without a horizontal portion. Therefore, the intermediate connection structure 150_1 may be referred to as an "intermediate plug" and described.

[0156] Upper Bond Pad( Fig. 7A , Figure 7B and Figure 8The lower bonding pad ( 165 ) may be replaced with an upper bonding pad 165_1 connected to an intermediate connection structure 150_1 that may be configured as a vertical portion without a horizontal portion. Fig. 7A , Figure 7B and Figure 8 65) in may be replaced with a lower bonding pad 65_1 bonded to an upper bonding pad 165_1.

[0157] The intermediate connection structure 150_1 may vertically overlap the upper bonding pad 165_1. At least a portion of each via 145 may vertically overlap the upper bonding pad 165_1. The intermediate connection structure 150_1 may be disposed between the via 145 and the upper bonding pad 165_1 while electrically connecting the via 145 and the upper bonding pad 165_1.

[0158] In a direction in which the upper bonding pads 165_1 are sequentially arranged, the vias 145 may be alternately arranged. Fig.11 The upper via 145 may be disposed adjacent to the right corner of the upper portion of the upper bonding pad 165_1 having a quadrilateral shape, and the lower via 145 may be disposed adjacent to the lower left corner of the upper bonding pad 165_1 having a quadrilateral shape when viewed from the top view shown.

[0159] In one or more example embodiments, referring to Fig.12 , will describe Fig.11 A modified example of the intermediate connection structure 150_1 and the via 145 in FIG. Fig.12 is a diagram showing a method according to one or more example embodiments Fig.11 FIG. 1 is a top view of a modified example of an intermediate connection structure 150_1 and a via 145 in a top view.

[0160] refer to Fig.12 ,path( Fig.11 145) can be replaced by a via 145_2 in one direction of the sequentially arranged bonding pad 165_1, and the intermediate connection structure ( Fig.11 150_1) in the embodiment can be replaced by an intermediate connection structure 150_2 arranged in a sequence in one direction of the bonding pad 165_1. Fig.12 The upper via 145_2 may be disposed adjacent to the center of the upper edge of the upper bonding pad 165_1 having a quadrilateral shape, and the lower via 145_2 may be disposed adjacent to the center of the lower edge of the upper bonding pad 165_1 having a quadrilateral shape when viewed from the top view shown.

[0161] Next, refer to Fig.13 and Fig.14, various plane shapes of the upper bonding pads 165 provided in the previously described unit bonding pad region 165R will be described according to one or more example embodiments. Fig.13 and Fig.14 1 is a top view illustrating various planar shapes of upper bonding pads 165 provided in the previously described unit bonding pad region 165R according to one or more example embodiments.

[0162] In one or more example embodiments, referring to Fig.13 , the above-mentioned upper bonding pad 165 having a quadrilateral shape may be modified to have an upper bonding pad 165_2 having a polygonal shape other than a quadrilateral shape. For example, according to one or more example embodiments, each upper bonding pad 165_2 may have a shape such as Fig.13 The upper bonding pad 165_2 is shown to have a pentagonal shape, but one or more example embodiments are not limited thereto, and the upper bonding pad 165_2 may have a polygonal shape other than the pentagonal shape.

[0163] In one or more example embodiments, referring to Fig.14 , the above-mentioned upper bonding pad 165 having a quadrilateral shape may be modified to an upper bonding pad 165_3 having a circular shape. For example, each upper bonding pad 165_3 may have a Fig.14 The upper bonding pad 165_3 is shown to have a circular shape, but one or more example embodiments are not limited thereto, and the upper bonding pad 165_3 may have an elliptical shape.

[0164] The above-mentioned upper bonding pads 165 may be sequentially arranged in the length direction of the bit line BL, but one or more example embodiments are not limited thereto. Fig.15 A modified example of the arrangement of the upper bonding pads 165 is described. Fig.15 is a top view illustrating a modified example of the arrangement of a bit line BL and an upper bonding pad 165 overlapping the bit line BL according to one or more example embodiments.

[0165] refer to Fig.15 , in the upper bonding pad 165 overlapping the bit line BL, the upper bonding pad 165 may be modified to be an upper bonding pad 165_4 sequentially arranged in a diagonal direction relative to the longitudinal direction of the bit line BL. Each of the upper bonding pads 165_4 may have a quadrilateral shape, but one or more example embodiments are not limited thereto. According to one or more example embodiments, each of the upper bonding pads 165_4 may also be modified to a polygonal shape, a circular shape, an elliptical shape, a diamond shape, etc., or any shape other than a quadrilateral.

[0166] In the above one or more example embodiments, the lower bonding pad 65 may have the same planar shape as the upper bonding pad 165 and may be vertically aligned with the upper bonding pad 165, but one or more example embodiments are not limited thereto. Fig.16 and Fig.17 Modifications of the lower bonding pad 65 and the upper bonding pad 165 are described. According to one or more example embodiments, among the lower bonding pad 65 and the upper bonding pad 165, one lower bonding pad 65 and one upper bonding pad 165 will be mainly described.

[0167] refer to Fig.16 , the lower bonding pad 65 and the upper bonding pad 165 vertically aligned as described above may be modified to be lower bonding pad 65c and upper bonding pad 165c not vertically aligned. For example, the vertical center axis of the lower bonding pad 65c may not be aligned with the vertical center axis of the upper bonding pad 165c.

[0168] refer to Fig.17 According to one or more example embodiments, the lower bonding pad 65 and the upper bonding pad 165 having the same width as described above may be modified to have a lower bonding pad 65d and an upper bonding pad 165d having different widths. For example, the width of the lower bonding pad 65d may be greater than the width of the upper bonding pad 165d. Alternatively, the width of the lower bonding pad 65d may be less than the width of the upper bonding pad 165d.

[0169] Next, we will refer to Fig.18 and Fig.19 Various modified examples of the via 145 and the first upper interconnection structure 125 according to one or more example embodiments are described. Fig.18 and Fig.19 is a partially enlarged cross-sectional view centered on one of the vias 145 to illustrate various modifications of the via 145 and the first upper interconnection structure 125. Hereinafter, one of the vias 145 will be mainly described.

[0170] In one or more modified example embodiments, reference is made to Fig.18 , the first upper interconnect structure 125 including the above-mentioned horizontal parts 130L and 132L can be modified into a first upper interconnect structure 225, which also includes: an additional horizontal part 228, which is arranged between the lower first horizontal part 130L among the horizontal parts 130L and 132L and the upper substrate 105; and an additional vertical part 229, which connects the additional horizontal part 228 and the first horizontal part 130L.

[0171] The additional horizontal portion 228 is disposed at the same level as the peripheral gate electrode ( Figure 8 The PGE) is at the same height as the peripheral gate electrode ( Figure 8 The buffer insulating layer 227 may be disposed between the additional horizontal portion 228 and the upper substrate 105.

[0172] path( Figure 8 145) may be modified as a via 245 that penetrates the upper substrate 105 and extends upward to contact and connect to the additional horizontal portion 228. The via 245 may include a conductive pillar 242b and a barrier layer 242a covering the side and upper surfaces of the conductive pillar 242b.

[0173] The previously described insulating spacer ( Figure 8 147) can be modified to be an insulating spacer 247 covering the side surface of the via 245.

[0174] In one or more modified example embodiments, reference is made to Fig.19 , the first upper interconnect structure 125 including the above-mentioned horizontal portions 130L and 132L can be modified into a first upper interconnect structure 325, which also includes an additional vertical portion 329, which is arranged between the first horizontal portion 130L arranged in the lower part among the horizontal portions 130L and 132L and the upper substrate 105.

[0175] path( Figure 8 145) may be modified as a via 345 that penetrates the upper substrate 105 and extends upward to contact and connect to the additional vertical portion 329. The via 345 may include a conductive pillar 342b and a barrier layer 342a covering the side and upper surfaces of the conductive pillar 342b.

[0176] The previously described insulating spacer ( Figure 8 147) can be modified to be an insulating spacer 347 covering the side surface of the via 345.

[0177] Next, we will refer to Fig. 20A and Fig. 20B One or more example embodiments of modifications to passage 145 are described. Fig. 20A and Fig. 20B 145 are views showing various modifications of the passage 145 . Fig. 20A It is shown Fig. 7A A modified cross-sectional view of the cross-sectional structure of the passage 145, and Fig. 20B yes Fig. 20A A partial magnified view of the area indicated by “C” in FIG.

[0178] In one or more modified example embodiments, reference is made to Fig. 20A and Fig. 20B , the above pathway ( Figure 8 145) may be modified to have a via 445 having an inclined side surface whose upper width is greater than the lower width. The via 445 may include a conductive pillar 442b and a barrier layer 442a covering the side surface and the lower surface of the conductive pillar 442b.

[0179] The above insulating spacer ( Figure 8 147) can be modified to be an insulating spacer 447 covering the side surface of the via 445.

[0180] Next, Fig.21 is corresponding to Fig. 20B A partial enlarged cross-sectional view of the Fig.21 , will show Fig. 20B One or more example embodiments of variations of the passage 445 and the intermediate connection structure 150 connected to the passage 445.

[0181] In one or more modified example embodiments, reference is made to Fig.21 , Fig. 20B The passage 445 in FIG. 1 may be modified into a passage 545 that extends downward while penetrating the upper surface of the upper substrate 105 and is located at a height higher than the lower surface of the upper substrate 105 .

[0182] The via 545 may include a conductive pillar 542 b and a barrier layer 542 a covering side surfaces and a lower surface of the conductive pillar 542 b .

[0183] The above insulating spacer ( Fig. 20B 447) can be modified to be an insulating spacer 547 covering the side surface of the via 545.

[0184] The vertical portion of the intermediate connection structure 150 connected to the via 545 may be modified into a vertical portion 252V1 of the intermediate connection structure that penetrates the upper substrate 105 and extends upward to be connected to the lower surface of the via 545 .

[0185] The vertical portion 252V1 of the intermediate connection structure may include a conductive pillar 251 b and a barrier layer 251 a covering side surfaces and an upper surface of the conductive pillar 251 b .

[0186] An insulating spacer 253 covering a side surface of the vertical portion 252V1 of the intermediate connection structure may be provided. The insulating spacer 253 may separate the vertical portion 252V1 of the intermediate connection structure from the upper semiconductor substrate 110.

[0187] Next, refer to Fig. 22 and Fig.23 , the above storage structure ( Fig. 7AOne or more example embodiments of the lower chip structure LC of MS). Fig. 22 The above storage structure ( Fig. 7A A top view of one or more example embodiments of MS), and Fig.23 is a schematic diagram showing the Fig. 22 A cross-sectional view of the area cut by lines II' and II-II'.

[0188] refer to Fig. 22 and Fig.23 , the lower base 5 of the lower chip structure LC may include a substrate 603, a cell active region 609a located on the substrate 603, and a cell isolation region 606 disposed on the substrate 603 and disposed on the side surface of the cell active region 609a. The cell active region 609a may have a shape protruding from the substrate 603 in a vertical direction. The cell isolation region 606 may be formed by shallow trench isolation. The cell isolation region 606 may be formed of an insulating material such as silicon oxide and / or silicon nitride. Fig. 7A The cell isolation region cSTI in the PCB may be formed simultaneously with the cell isolation region 606 .

[0189] The lower chip structure LC may include a cell gate structure GSa buried in the cell active region 609a and extending into the cell isolation region 606, and a cell gate capping layer 612 located on the cell gate structure GSa. The cell gate capping layer 612 may be formed of an insulating material.

[0190] The cell gate structure GSa and the cell gate capping layer 612 may be disposed in a cell gate trench extending into the cell isolation region 606 while crossing the cell active region 609 a .

[0191] Each cell gate structure GSa may include a cell gate dielectric layer 617 and a cell gate electrode WL located on the cell gate dielectric layer 617. The cell gate electrode WL may be a word line.

[0192] The lower chip structure LC may further include a first source / drain region 615a and a second source / drain region 615b disposed in the cell active region 609a. The cell gate structure GS and the first source / drain region 615a and the second source / drain region 615b may constitute a cell transistor TRc. The cell transistor TRc may include a cell switching element.

[0193] The lower chip structure LC may include: a buffer insulating layer 620, which is located on the cell active area 609a and the cell isolation area 606; a bit line BL, which is set on the buffer insulating layer 620 and includes a plug portion BLP penetrating the buffer insulating layer 620; a bit line covering layer 650, which is located on the bit line BL; a cell contact structure 660a, which is set on both sides of the bit line BL and includes a pad portion extending to the bit line covering layer 650; an insulating isolation structure 665, which is set between the pad portions of the cell contact structure 660a and extends downward; and an insulating spacer 655, which is located on the side of the bit line BL and the bit line covering layer 650.

[0194] The plug portion BLP of the bit line BL may be electrically connected to the first source / drain region 615a. The cell contact structure 660a may be electrically connected to the second source / drain region 615b.

[0195] refer to Fig. 7A The described data storage structure DS may be disposed on the cell contact structure 660a and the insulating isolation structure 665. In the data storage structure DS, the first electrode SN may be electrically connected to the cell contact structure 660a, the dielectric layer DI may cover the first electrode SN, and the second electrode PL may be disposed on the dielectric layer DI.

[0196] Next, refer to Fig.24 , Fig.25A , Fig.25B , Fig.26A , Fig.26B , Fig.27A , Fig.27B , Fig.28A and Fig.28B , an illustrative example of a method of forming a semiconductor device according to one or more example embodiments will be described. Fig.24 , Fig.25A , Fig.25B , Fig.26A , Fig.26B , Fig.27A , Fig.27B , Fig.28A and Fig.28B middle, Fig.24 is a process flow diagram showing an illustrative example of a method of forming a semiconductor device according to one or more example embodiments, Fig.25A and Fig.25B is a cross-sectional view illustrating one or more example embodiments of a method of forming a lower chip structure, Fig.26A and Fig.26B is a cross-sectional view illustrating one or more example embodiments of a method of forming a first preliminary upper chip structure, Fig.26A and Fig.26Bis a cross-sectional view illustrating one or more example embodiments of a method of forming a second preliminary upper chip structure, and Fig.28A and Fig.28B is a cross-sectional view showing bonding of a lower chip structure and a second preliminary upper chip structure. Fig.25A , Fig.26A , Fig.27A and Fig.28A is corresponding to Fig. 7A A cross-sectional view of the cross-sectional structure, and Fig.25B , Fig.26B , Fig.27B and Fig.28B is corresponding to Figure 7B Cross-sectional view of the cross-sectional structure.

[0197] refer to Fig.24 , Fig.25A and Fig.25B According to one or more example embodiments, a lower chip structure LC including a lower bonding pad 65 may be formed (S10). The lower chip structure LC may be a reference Fig. 7A and Figure 7B The lower chip structure LC is described. Therefore, Fig. 7A and Figure 7B As described, the lower chip structure LC may include a substrate 5, a memory structure MS, a power capacitor CAPp, a lower insulating structure 20, a lower interconnection structure 25, a lower bonding insulating layer 60, and a lower bonding pad 65. The lower bonding insulating layer 60 and the lower bonding pad 65 may have coplanar upper surfaces.

[0198] refer to Fig.26A and Fig.26B , a first preliminary upper semiconductor chip structure may be formed. Forming the first preliminary upper semiconductor chip structure may include forming a preliminary upper substrate 105a, forming a peripheral transistor PTR on the preliminary upper substrate 105a, forming a first upper interconnection structure 125 and a first upper insulating structure 120 covering the first upper interconnection structure 125 on the preliminary upper substrate 105a, and forming a protective insulating layer 134 on the first upper insulating structure 120.

[0199] Forming the preliminary upper base 105 a may include forming an upper isolation region pSTI defining an upper active region pACT on the upper semiconductor substrate 110 .

[0200] refer to Fig.24 , Fig.27A and Fig.27B, a preliminary upper chip structure UCa including an upper bonding pad 165 may be formed (S20). Forming the preliminary upper chip structure UCa may include forming a lower protective insulating layer 140, forming a via 145 and an insulating spacer 147, forming an intermediate insulating structure 155 and an intermediate connecting structure 150, and forming an upper bonding insulating layer 160 and an upper bonding pad 165.

[0201] The lower protective insulating layer 140 may be formed on the rear surface of the upper semiconductor substrate 110. Thus, a lower protective insulating layer 140 may be formed. Fig. 7A and Figure 7B The upper substrate 105 is shown.

[0202] Forming the via 145 and the insulating spacer 147 may include forming a through hole that passes through the upper substrate 105 and extends downward to expose a portion of the first upper interconnect structure 125, forming the insulating spacer 147 on a side surface of the through hole, and forming the via 145 in the through hole. The intermediate connection structure 150 may be formed to electrically connect the via 145 and the upper bonding pad 165. The upper bonding insulating layer 160 and the upper bonding pad 165 may be formed to have coplanar upper surfaces.

[0203] refer to Fig.24 , Fig.28A and Fig.28B According to one or more example embodiments, a bonding process may be performed to bond the lower bonding pad 65 and the upper bonding pad 165 (S30). During the bonding process, the lower bonding insulating layer 60 and the upper bonding insulating layer 160 may be bonded. Thus, the lower chip structure ( Fig.25A and Fig.25B LC) and preliminary chip structure ( Fig.27A and Fig.27B of UCa).

[0204] Reference again Fig. 7A , Figure 7B and Figure 8 , a second upper interconnection structure 175 may be formed (S40). The second upper interconnection structure 175 may be formed on the first upper insulating structure 120. Before forming the second upper interconnection structure 175, the protective insulating layer 134 may be removed. In one or more example embodiments, the process of removing the protective insulating layer 134 may be omitted. The second upper interconnection structure 175 may be buried in the second upper insulating structure 170 formed on the first upper insulating structure 120.

[0205] The input / output pad 190 may be formed (S50). The cover insulating layer 185 may be formed on the second upper insulating structure 170. The cover insulating layer 185 may have an opening exposing an upper surface of the input / output pad 190.

[0206] As explained above, according to one or more example embodiments, a semiconductor device including a lower semiconductor chip including a memory structure and an upper semiconductor chip including a peripheral circuit may be provided. Therefore, the integration degree of the semiconductor device may be improved.

[0207] Furthermore, since an optimal wiring structure for electrically connecting a lower semiconductor chip and an upper semiconductor chip can be provided, a semiconductor device having improved electrical characteristics can be provided.

[0208] While example embodiments have been particularly shown and described above, it will be apparent to those skilled in the art that modifications and changes in form and details may be made therein without departing from the scope of the appended claims.

Claims

1. A semiconductor device, comprising: Lower chip structure; as well as an upper chip structure, the upper chip structure being located on the lower chip structure, Wherein, the lower chip structure comprises: Storage structure; a lower interconnect structure electrically connected to the storage structure; and a lower bonding pad electrically connected to the lower interconnect structure, and wherein the upper chip structure comprises: upper base; A peripheral transistor, wherein the peripheral transistor is located on the upper substrate; a first upper interconnect structure, the first upper interconnect structure being located on the upper substrate and electrically connected to the peripheral transistor; a via penetrating the upper substrate and electrically connected to the first upper interconnect structure; an upper bonding pad located below the upper substrate and bonded to the lower bonding pad; and An intermediate connection structure is located between the upper substrate and the lower chip structure and electrically connects the upper bonding pad and the via.

2. The semiconductor device according to claim 1, wherein The lower interconnect structure comprises: at least two lower interconnect lines, the at least two lower interconnect lines being disposed at different heights between the storage structure and the lower bonding pad; at least two first lower plugs, the at least two first lower plugs being respectively located under the at least two lower interconnection lines; and A second lower plug is located between an uppermost lower interconnection line among the at least two lower interconnection lines and the lower bonding pad.

3. The semiconductor device according to claim 2, wherein: The intermediate connection structure comprises: at least one intermediate interconnect line; a first middle plug connecting the at least one middle interconnection line and the upper bonding pad; and A second middle plug is provided, the second middle plug connecting the at least one middle interconnection line and the via.

4. The semiconductor device according to claim 1, wherein: The storage structure vertically overlaps the lower bonding pad, the upper bonding pad, the intermediate connection structure, the via, and the peripheral transistor.

5. The semiconductor device according to claim 1, wherein The upper substrate comprises: an upper semiconductor substrate; a rear protective insulating layer, the rear protective insulating layer being located below the upper semiconductor substrate; an upper active region, the upper active region being located on the upper semiconductor substrate; and an upper isolation region, the upper isolation region being located on a side surface of the upper active region and in the upper semiconductor substrate, Wherein, the peripheral transistor comprises: a peripheral gate, the peripheral gate being located on the upper active region; and A peripheral source / drain is located on both sides of the peripheral gate in the upper active region.

6. The semiconductor device according to claim 1, wherein The storage structure includes: A unit transistor, the unit transistor comprising: a first source / drain; a second source / drain; and cell gate electrode, A bit line electrically connected to the first source / drain; and A data storage structure is electrically connected to the second source / drain.

7. The semiconductor device according to claim 6, wherein: The bit line extends outside the memory structure and includes a bit line contact region outside the memory structure, Wherein, the lower interconnection structure comprises: at least two lower interconnection lines, the at least two lower interconnection lines being at a height higher than that of the data storage structure and at different heights from each other; at least one first lower plug, the at least one first lower plug electrically connecting the at least two lower interconnection lines; a second lower plug electrically connecting a lowermost lower interconnection line among the at least two lower interconnection lines and the bit line contact region of the bit line; and a third lower plug electrically connecting an uppermost lower interconnection line among the at least two lower interconnection lines and the lower bonding pad, wherein the second lower plug does not vertically overlap the data storage structure, and Wherein, at least one of the at least two lower interconnect lines comprises: a first region that does not vertically overlap the data storage structure; and A second region vertically overlaps the data storage structure.

8. The semiconductor device according to claim 1, wherein The pathway includes: Conductive posts; and a barrier layer covering the side surface and the upper surface of the conductive pillar, and Wherein, the lower surface of the conductive column is connected to the intermediate connection structure.

9. The semiconductor device according to claim 1, wherein: The via includes a conductive pillar and a barrier layer covering a side surface and a lower surface of the conductive pillar, and Wherein, the upper surface of the conductive pillar is connected to the first upper interconnection structure.

10. The semiconductor device according to claim 1, wherein The upper chip structure further includes: a second upper interconnect structure at a height higher than that of the first upper interconnect structure, and an input / output pad at a height higher than that of the second upper interconnect structure, Wherein, the first upper interconnect structure includes at least one first upper interconnect line, and Wherein, the second upper interconnection structure includes at least one second upper interconnection line.

11. The semiconductor device according to claim 10, wherein: The thickness of the at least one second upper interconnection line is greater than the thickness of the at least one first upper interconnection line.

12. A semiconductor device, comprising: A lower chip structure, the lower chip structure comprising: a first storage area; a second storage area; and an extension area, the extension area being located between the first storage area and the second storage area; and an upper chip structure, the upper chip structure being located on the lower chip structure, Wherein, the lower chip structure further includes: a bit line located in the first storage region and extending into the extension region; and a complementary bit line, the complementary bit line being located in the second storage region and extending into the extension region, Wherein, the upper chip structure comprises: upper base; a sense amplifier array region located on the upper substrate and including a sense amplifier region; and a via, the via penetrating the upper substrate, wherein the sense amplifier array region vertically overlaps the first storage region, wherein a first sense amplifier region among the sense amplifier regions is electrically connected to a first bit line among the bit lines and a first complementary bit line among the complementary bit lines, Wherein, the first sense amplifier region comprises: a first connection region; a second connection region; and The first sense amplifier, and Wherein, the pathway includes: a first wiring via, the first wiring via being located below the first connection region and penetrating the upper substrate; and A second wiring via is located below the second connection region and penetrates the upper substrate.

13. The semiconductor device according to claim 12, wherein: The lower chip structure further includes: a lower wiring interconnect structure; and Lower wiring bonding pad, The upper chip structure further includes an upper wiring bonding pad located below the upper substrate and bonded to the lower wiring bonding pad. Wherein, the lower wiring interconnection structure comprises: a first lower wiring interconnect structure electrically connected to the first bit line; and a second lower wiring interconnect structure electrically connected to the first complementary bit line, Wherein, the lower wiring bonding pad comprises: a first lower wiring bonding pad electrically connected to the first lower wiring interconnect structure; and a second lower wiring bonding pad electrically connected to the second lower wiring interconnect structure, and Wherein, the upper wiring bonding pad comprises: a first upper wiring bonding pad bonded to the first lower wiring bonding pad; and A second upper wiring bonding pad is bonded to the second lower wiring bonding pad.

14. The semiconductor device according to claim 13, wherein: Each of the first lower wiring interconnect structure and the second lower wiring interconnect structure includes: at least two lower interconnect lines, the at least two lower interconnect lines being at different heights; at least two first lower plugs, the at least two first lower plugs being respectively located under the at least two lower interconnection lines; and a second lower plug located between an uppermost lower interconnection line among the at least two lower interconnection lines and the first lower wiring bonding pad, wherein the second lower plug of the first lower wiring interconnect structure is connected to the first lower wiring bonding pad, and Wherein, the second lower plug of the second lower wiring interconnect structure is connected to the second lower wiring bonding pad.

15. The semiconductor device according to claim 13, wherein: The chip-on-chip structure comprises: a first intermediate wiring connection structure located below the upper substrate and electrically connecting the first wiring via and the first upper wiring bonding pad; and A second intermediate wiring connection structure is located below the upper substrate and electrically connects the second wiring via and the second upper wiring bonding pad.

16. The semiconductor device according to claim 15, wherein: Each of the first intermediate wiring connection structure and the second intermediate wiring connection structure includes: at least one intermediate interconnect line; a first middle plug, the first middle plug being located below the at least one middle interconnection line; and A second middle plug is located on the at least one middle interconnection line.

17. The semiconductor device according to claim 15, wherein: The first sense amplifier comprises: a peripheral transistor, the peripheral transistor being located on the upper substrate; and an upper wiring interconnect structure, the upper wiring interconnect structure being located on the upper substrate and electrically connected to the peripheral transistor, wherein the first wiring path electrically connects the upper wiring interconnect structure and the first intermediate wiring connection structure in the first connection region, and Wherein, the second wiring via electrically connects the upper wiring interconnect structure and the second intermediate wiring connection structure in the second connection region.

18. The semiconductor device according to claim 16, wherein: A central vertical axis of the first wiring via and a central vertical axis of the first upper wiring bond pad are not vertically aligned.

19. A semiconductor device, comprising: A lower chip structure, the lower chip structure comprising: a first storage area; a second storage area; and an extension area, the extension area being located between the first storage area and the second storage area; and an upper chip structure, the upper chip structure being located on the lower chip structure, Wherein, the lower chip structure comprises: a bit line located in the first storage region and extending into the extension region; a complementary bit line located in the second storage region and extending into the extension region; a lower wiring bonding pad array region, the lower wiring bonding pad array region being located on the first storage region and comprising a first lower wiring bonding pad and a second lower wiring bonding pad; a first lower wiring interconnect structure electrically connecting the bit line and the first lower wiring bonding pad; and a second lower wiring interconnect structure electrically connecting the complementary bit line and the second lower wiring bonding pad, Wherein, the upper chip structure comprises: upper base; a sense amplifier array region, the sense amplifier array region being located on the upper substrate and including a sense amplifier region; an upper wiring bonding pad array region, the upper wiring bonding pad array region being located below the upper substrate and comprising a first upper wiring bonding pad and a second upper wiring bonding pad; a wiring path penetrating the upper substrate and comprising a first wiring path and a second wiring path; a first intermediate wiring connection structure located between the upper substrate and the upper wiring bonding pad array region and electrically connecting the first wiring via and the first upper wiring bonding pad; and a second intermediate wiring connection structure, the second intermediate wiring connection structure being located between the upper substrate and the upper wiring bonding pad array region and electrically connecting the second wiring via and the second upper wiring bonding pad, wherein the first lower wiring bonding pad and the second lower wiring bonding pad are bonded to the first upper wiring bonding pad and the second upper wiring bonding pad, wherein the sense amplifier array region, the wiring pathway, the upper wiring bonding pad array region, and the lower wiring bonding pad array region vertically overlap with the first storage region, and Wherein, a first sense amplifier region among the sense amplifier regions is electrically connected to a first bit line among the bit lines and a first upper bit line among the complementary bit lines.

20. The semiconductor device according to claim 19, wherein The first sense amplifier region comprises: a first connection region; a second connection region; and a first sense amplifier, the first sense amplifier being located between the first connection region and the second connection region, wherein the first wiring path penetrates the upper substrate and is located below the first connection area, and The second wiring path penetrates the upper substrate and is located below the second connection area.

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