Fast eight-bit floating point (FP8) simulation with learnable parameters

Abstract

A processor-implemented method for fast floating point simulation with learnable parameters includes receiving a single precision input. An integer quantization process is performed on the input. Each element of the input is scaled based on a scaling parameter to generate an m-bit floating point output, where m is an integer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. patent application No. 18 / 102,582, filed on January 27, 2023, entitled “FAST EIGHT-BIT FLOATING POINT (FP8) SIMULATION WITH LEARNABLE PARAMETERS,” which claims the benefit of U.S. Provisional Patent Application No. 63 / 343,968, filed on May 19, 2022, entitled “FAST EIGHT-BITFLOATING POINT (FP8) SIMULATION WITH LEARNABLE PARAMETERS,” the disclosures of which are expressly incorporated herein by reference in their entirety. Technical Field

[0003] Aspects of the present disclosure generally relate to floating point simulation utilizing learnable parameters. Background Art

[0004] An artificial neural network may include an interconnected group of artificial neurons (e.g., a neuron model). An artificial neural network may be a computing device or represented as a method to be performed by a computing device. A convolutional neural network (CNN) is a feedforward artificial neural network. A convolutional neural network may include a collection of neurons, each of which has a receptive field and together spells out an input space. Convolutional neural networks (CNNs) such as deep convolutional neural networks (DCNs) have numerous applications. Specifically, these neural network architectures are used in various technologies such as image recognition, speech recognition, acoustic scene classification, keyword detection, autonomous driving, and other classification tasks.

[0005] Deep neural networks are gaining popularity due to their ability to solve complex problems. Therefore, deep learning deployment on edge devices for real-time inference is an area of ​​interest. Unfortunately, model size and therefore memory consumption and complexity can be prohibitive with millions of parameters. Summary of the invention

[0006] The present disclosure is set out in the independent claims respectively. Some aspects of the present disclosure are described in the dependent claims.

[0007] In one aspect of the present disclosure, a computer-implemented method includes receiving an input. The processor-implemented method also includes performing an integer quantization process on the input. Each element of the input is scaled based on a scaling parameter to generate an m-bit floating point output, where m is an integer.

[0008] Another aspect of the present disclosure relates to an apparatus including a component for receiving an input. The apparatus also includes a component for performing an integer quantization process on the input. Each element of the input is scaled based on a scaling parameter to generate an m-bit floating point output, where m is an integer.

[0009] In another aspect of the present disclosure, a non-transitory computer-readable medium having non-transitory program code recorded thereon is disclosed. The program code is executed by a processor and includes program code for receiving an input. The program code also includes program code for performing an integer quantization process on the input. Each element of the input is scaled based on a scaling parameter to generate an m-bit floating point output, where m is an integer.

[0010] Another aspect of the present disclosure relates to an apparatus having a memory and one or more processors coupled to the memory. The processor is configured to receive an input. The processor is further configured to perform an integer quantization process on the input. Each element of the input is scaled based on a scaling parameter to generate an m-bit floating point output, where m is an integer.

[0011] Additional features and advantages of the present disclosure will be described below. It will be appreciated by those skilled in the art that the present disclosure can be easily used as a basis for modifying or designing other structures for implementing the same purpose as the present disclosure. It will also be appreciated by those skilled in the art that such equivalent constructions do not depart from the teachings of the present disclosure as set forth in the appended claims. The novel features considered to be characteristic of the present disclosure, both in terms of its organization and method of operation, together with further objects and advantages, will be better understood when the following description is considered in conjunction with the accompanying drawings. However, it is to be expressly understood that each of the drawings is provided for illustration and description purposes only and is not intended as a definition of limitations of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The features, nature and advantages of the present disclosure will become more apparent when the detailed description set forth below is read in conjunction with the accompanying drawings, in which like reference numerals are correspondingly identified throughout.

[0013] Figure 1 An example implementation of a neural network using a system on a chip (SOC) including a general purpose processor in accordance with certain aspects of the present disclosure is illustrated.

[0014] Figure 2A , Figure 2B and Figure 2C is a diagram illustrating a neural network according to aspects of the present disclosure.

[0015] Figure 2D is a diagram illustrating an exemplary deep convolutional network (DCN) according to aspects of the present disclosure.

[0016] Figure 3 is a block diagram illustrating an exemplary deep convolutional network (DCN) according to aspects of the present disclosure.

[0017] Figure 4 is a block diagram illustrating an exemplary software architecture that can modularize artificial intelligence (AI) functionality according to aspects of the present disclosure.

[0018] Figure 5 is a block diagram illustrating example pseudo code according to aspects of the present disclosure.

[0019] Figure 6 is a flow chart illustrating a processor-implemented method for utilizing eight-bit floating point simulation of learnable parameters in accordance with aspects of the present disclosure. DETAILED DESCRIPTION

[0020] The specific embodiments described below in conjunction with the accompanying drawings are intended as descriptions of various configurations and are not intended to represent the only configurations in which the described concepts can be practiced. In order to provide a comprehensive understanding of the various concepts, the specific embodiments include specific details. However, it is obvious to those skilled in the art that these concepts can be practiced without these specific details. In some instances, in order to avoid blurring such concepts, known structures and components are shown in block diagram form.

[0021] Based on the teachings, those skilled in the art will recognize that the scope of the present disclosure is intended to cover any aspect of the present disclosure, whether the aspect is implemented independently of any other aspect of the present disclosure or implemented in combination with any other aspect. For example, a device or a method can be implemented using any number of aspects described. In addition, the scope of the present disclosure is intended to cover such devices or methods that are practiced using other structures, functionality, or structures and functionality that are supplementary to or different from the various aspects of the present disclosure described. It should be understood that any aspect of the present disclosure disclosed can be embodied by one or more elements of the claims.

[0022] The word “exemplary” is used to mean “serving as an example, instance, or illustration.” Any aspect described as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0023] Although specific aspects are described, numerous variations and permutations of these aspects fall within the scope of the present disclosure. Although some benefits and advantages of preferred aspects are mentioned, the scope of the present disclosure is not intended to be limited to specific benefits, uses or purposes. On the contrary, various aspects of the present disclosure are intended to be broadly applicable to different technologies, system configurations, networks and protocols, some of which are illustrated as examples in the accompanying drawings and the following description of preferred aspects. The specific embodiments and drawings are merely illustrative of the present disclosure and are not limiting, and the scope of the present disclosure is defined by the appended claims and their equivalents.

[0024] As described, deep neural networks are growing in popularity due to their ability to solve complex problems. Therefore, deep learning deployment on edge devices for real-time inference is an area of ​​interest. Unfortunately, model size and therefore memory consumption and complexity can be prohibitive with millions of parameters.

[0025] Neural network quantization is an effective way to improve the efficiency of neural networks. In neural network quantization, weights and activations can be represented in a low-bit width format such as, for example, an eight-bit integer (INT8). When the network is executed on any device, neural network quantization (hereinafter referred to as "quantization") can result in a reduction in data movement and enable the use of low-bit width calculations, thus producing significantly faster inferences with reduced energy consumption.

[0026] Generally speaking, values ​​in neural networks can be represented in integer (INT) or floating point (FP) format. Conventional approaches to address this inefficiency have used 16-bit precision in an effort to reduce energy and memory consumption. However, despite such advances, conventional approaches have produced models whose memory consumption is still too large. In addition, training and simulation of models with parameters represented by less than 16 bits has been challenging. Conventional methods for eight-bit floating point (FP8) simulations are time-consuming or complex and difficult to adapt. In addition, such conventional methods do not allow for the definition of gradients relative to FP8 parameters, thus making range learning challenging.

[0027] Therefore, to address these and other challenges, aspects of the present disclosure relate to arbitrary bit width simulation using learnable parameters. In some aspects, for example, eight-bit floating point simulation using learnable parameters is described. According to aspects of the present invention, eight-bit floating point quantization can enable post-training quantization (PTQ) and quantization-aware training (QAT) experiments with many floating point formats. In addition, aspects of the present disclosure can enable learning of exponent bias values ​​and improved tradeoffs between the number of exponent bits and mantissa bits without manual intervention. Therefore, aspects of the present disclosure can beneficially provide floating point quantization that improves inference efficiency compared to integer quantization.

[0028] Figure 1An example implementation of a system on a chip (SOC) 100 is illustrated, which may include a central processing unit (CPU) 102 or a multi-core CPU configured for eight-bit floating point simulation using learnable parameters. Variables (e.g., neural signals and synaptic weights), system parameters associated with a computing device (e.g., a neural network with weights), delays, frequency bin information, and task information may be stored in a memory block associated with a neural processing unit (NPU) 108, a memory block associated with the CPU 102, a memory block associated with a graphics processing unit (GPU) 104, a memory block associated with a digital signal processor (DSP) 106, a memory block 118, or may be distributed across multiple blocks. Instructions executed at the CPU 102 may be loaded from a program memory associated with the CPU 102, or may be loaded from the memory block 118.

[0029] The SOC 100 may also include additional processing blocks tailored for specific functions, such as a GPU 104, a DSP 106, a connectivity block 110 (which may include fifth generation (5G) connectivity, fourth generation long term evolution (4G LTE) connectivity, Wi-Fi connectivity, USB connectivity, Bluetooth connectivity, etc.), and a multimedia processor 112 that may, for example, detect and recognize gestures. In one specific implementation, the NPU 108 is implemented in the CPU 102, the DSP 106, and / or the GPU 104. The SOC 100 may also include a sensor processor 114, an image signal processor (ISP) 116, and / or a navigation module 120, which may include a global positioning system.

[0030] SOC 100 may be based on the ARM instruction set. In one aspect of the present disclosure, the instructions loaded into the general purpose processor 102 may include code for receiving input. The general purpose processor 102 may also include code for performing an integer quantization process on the input. Each element of the input may be scaled based on a scaling parameter to generate an m-bit floating point input.

[0031] Deep learning architectures can perform object recognition tasks by learning to represent inputs at successively higher levels of abstraction in each layer, thereby building useful feature representations of the input data. In this way, deep learning solves the main bottleneck of traditional machine learning. Before the advent of deep learning, machine learning methods for object recognition problems may rely heavily on human-designed features, possibly in conjunction with shallow classifiers. A shallow classifier can be a two-class linear classifier, for example, in which the weighted sum of feature vector components can be compared to a threshold to predict which class the input belongs to. Human-designed features can be templates or kernels customized for a specific problem domain by engineers with domain expertise. In contrast, while deep learning architectures can learn to represent features similar to those that human engineers might design, they require training. In addition, deep networks can learn to represent and recognize new types of features that humans may not have considered.

[0032] Deep learning architectures can learn hierarchies of features. For example, if presented with visual data, the first layer can learn to recognize relatively simple features in the input stream, such as edges. In another example, if presented with auditory data, the first layer can learn to recognize spectral power in specific frequencies. The second layer, taking the output of the first layer as input, can learn to recognize combinations of features, such as simple shapes for visual data or combinations of sounds for auditory data. For example, higher layers can learn to represent complex shapes in visual data or words in auditory data. Even higher layers can learn to recognize common visual objects or spoken phrases.

[0033] Deep learning architectures can perform particularly well when applied to problems that have a natural hierarchical structure. For example, the classification of motorized vehicles can benefit from first learning to recognize wheels, windshields, and other features. These features can be combined in different ways at higher levels to recognize cars, trucks, and airplanes.

[0034] Neural networks can be designed to have a variety of connection patterns. In a feedforward network, information is passed from a lower layer to a higher layer, where each neuron in a given layer communicates with a neuron in a higher layer. As described above, hierarchical representations can be constructed in successive layers of a feedforward network. Neural networks can also have loops or feedback (also known as top-down) connections. In a loop connection, the output from a neuron in a given layer can be communicated to another neuron in the same layer. The loop architecture can help identify patterns that span more than one input data block in the input data blocks that are sequentially delivered to the neural network. The connection from a neuron in a given layer to a neuron in a lower layer is called a feedback (or top-down) connection. When the recognition of a high-level concept can assist in discerning specific low-level features of the input, a network with many feedback connections may be helpful.

[0035] The connections between neural network layers can be fully connected or partially connected. Figure 2A An example of a fully connected neural network 202 is illustrated. In a fully connected neural network 202, a neuron in a first layer may communicate its output to each neuron in a second layer, such that each neuron in the second layer will receive input from each neuron in the first layer. Figure 2B An example of a locally connected neural network 204 is illustrated. In the locally connected neural network 204, neurons in a first layer may be connected to a limited number of neurons in a second layer. More generally, the locally connected layers of the locally connected neural network 204 may be configured such that each neuron in the layer will have the same or similar connection pattern, but the connection strengths may have different values ​​(e.g., 210, 212, 214, and 216). The connection patterns of the local connections may produce spatially different receptive fields in higher layers because higher layer neurons in a given region may receive inputs that are tuned through training to the characteristics of a limited portion of the total input to the network.

[0036] An example of a locally connected neural network is a convolutional neural network. Figure 2C An example of a convolutional neural network 206 is illustrated. The convolutional neural network 206 may be configured such that the connection strengths associated with the inputs of each neuron in the second layer are shared (e.g., 208). Convolutional neural networks may be well suited for problems where the spatial location of the inputs is meaningful.

[0037] One type of convolutional neural network is a deep convolutional network (DCN). Figure 2D A detailed example of a DCN 200 designed to recognize visual features from an image 226 input from an image capture device 230, such as a vehicle-mounted camera, is illustrated. The DCN 200 of the current example can be trained to identify traffic signs and numbers provided on traffic signs. Of course, the DCN 200 can be trained for other tasks, such as identifying lane markings or identifying traffic lights.

[0038] The DCN 200 may be trained by supervised learning. During training, an image such as an image 226 of a speed limit sign may be presented to the DCN 200, and a forward pass may then be calculated to produce an output 222. The DCN 200 may include a feature extraction portion and a classification portion. Upon receiving the image 226, a convolutional layer 232 may apply a convolutional kernel (not shown) to the image 226 to generate a first set of feature maps 218. As an example, the convolutional kernel of the convolutional layer 232 may be a 5x5 kernel that generates a 28x28 feature map. In this example, because four different feature maps are generated in the first set of feature maps 218, four different convolutional kernels are applied to the image 226 at the convolutional layer 232. A convolutional kernel may also be referred to as a filter or a convolutional filter.

[0039] The first set of feature maps 218 may be subsampled by a maximum pooling layer (not shown) to generate a second set of feature maps 220. The maximum pooling layer reduces the size of the first set of feature maps 218. That is, the size of the second set of feature maps 220, such as 14x14, is smaller than the size of the first set of feature maps 218, such as 28x28. The reduced size provides similar information to subsequent layers while reducing memory consumption. The second set of feature maps 220 may be further convolved via one or more subsequent convolutional layers (not shown) to generate one or more sets of subsequent feature maps (not shown).

[0040] exist Figure 2D In the example of , the second set of feature maps 220 are convolved to generate a first feature vector 224. In addition, the first feature vector 224 is further convolved to generate a second feature vector 228. Each feature of the second feature vector 228 may include a number corresponding to a possible feature of the image 226, such as "sign", "60", and "100". A softmax function (not shown) may convert the numbers in the second feature vector 228 into probabilities. Therefore, the output 222 of the DCN 200 may be a probability that the image 226 includes one or more features.

[0041] In this example, the probability of "logo" and "60" in output 222 is higher than the probability of other numbers such as "30", "40", "50", "70", "80", "90", and "100" in output 222. Before training, the output 222 generated by DCN 200 may be incorrect. Therefore, the error between the output 222 and the target output can be calculated. The target output is the reference truth value of image 226 (e.g., "logo" and "60"). The weights of DCN 200 can then be adjusted so that the output 222 of DCN 200 is closer to the target output.

[0042] To adjust the weights, the learning algorithm may calculate a gradient vector for the weights. The gradient may indicate the amount by which the error will increase or decrease when the weights are adjusted. At the top layer, the gradient may correspond directly to the value of the weights connecting the activated neurons in the penultimate layer and the neurons in the output layer. In lower layers, the gradient may depend on the value of the weights and the calculated error gradients of the higher layers. The weights may then be adjusted to reduce the error. This manner of adjusting weights may be referred to as "backward propagation" because it involves a "backward pass" through the neural network.

[0043] In practice, the error gradient of the weights may be calculated over a small number of examples so that the calculated gradient is close to the true error gradient. This approximation method may be referred to as "stochastic gradient descent". Stochastic gradient descent may be repeated until the achievable error rate of the entire system stops decreasing or until the error rate reaches a target level. After learning, the DCN 200 may be presented with new images, and a forward pass through the DCN 200 may produce an output 222 that may be considered an inference or prediction of the DCN 200.

[0044] A Deep Belief Network (DBN) is a probabilistic model that includes multiple layers of hidden nodes. A DBN can be used to extract a hierarchical representation of a training data set. A DBN can be obtained by stacking layers of Restricted Boltzmann Machines (RBMs). RBMs are a type of artificial neural network that can learn a probability distribution over a set of inputs. Because RBMs can learn probability distributions without information about the category to which each input should be classified, RBMs are often used for unsupervised learning. Using a hybrid unsupervised and supervised paradigm, the bottom RBM of a DBN can be trained in an unsupervised manner and can be used as a feature extractor, while the top RBM can be trained in a supervised manner (on the joint distribution of the input and target class from the previous layer) and can be used as a classifier.

[0045] A DCN is a network of convolutional networks, configured with additional pooling and normalization layers. DCN has achieved state-of-the-art performance on many tasks. DCN can be trained using supervised learning, where both the input and output targets are known for many examples and are used to modify the weights of the network using a gradient descent method.

[0046] The DCN may be a feed-forward network. In addition, as described above, the connections from a neuron in the first layer of the DCN to a set of neurons in the next higher layer are shared across the neurons in the first layer. The feed-forward and shared connections of the DCN can be used for fast processing. For example, the computational burden of the DCN may be much smaller than that of a similarly sized neural network that includes loops or feedback connections.

[0047] The processing of each layer of the convolutional network can be thought of as a spatially invariant template or basis projection. If the input is first decomposed into multiple channels, such as the red, green, and blue channels of a color image, then the convolutional network trained on the input can be thought of as three-dimensional, where two spatial dimensions are along the axes of the image and the third dimension captures color information. The output of the convolutional connection can be thought of as forming a feature map in a subsequent layer, each element in which receives input from a range of neurons in the previous layer (e.g., feature map 218) and from each of the multiple channels. The values ​​in the feature map can be further processed with nonlinearities (such as correction, max(0,x)). The values ​​from neighboring neurons can be further pooled, which corresponds to downsampling and can provide additional local invariance and dimensionality reduction. Normalization corresponding to whitening can also be applied by lateral inhibition between neurons in the feature map.

[0048] The performance of deep learning architectures can increase as more labeled data points become available or as computing power increases. Modern deep neural networks are often trained with computing resources that are thousands of times greater than what was available to a typical researcher just fifteen years ago. New architectures and training paradigms can further improve the performance of deep learning. Rectified linear units can reduce the training problem known as vanishing gradients. New training techniques can reduce overfitting, allowing larger models to achieve better generalization. Encapsulation techniques can extract data within a given receptive field and further improve overall performance.

[0049] Figure 3 is a block diagram illustrating a deep convolutional network (DCN) 350. The DCN 350 may include multiple different types of layers based on connections and weight sharing. Figure 3 As shown, DCN 350 includes convolution blocks 354A, 354B. Each of the convolution blocks 354A, 354B may be configured with a convolution layer (CONV) 356, a normalization layer (LNorm) 358, and a maximum pooling layer (MAX POOL) 360. Although only two of the convolution blocks 354A, 354B are shown, the present disclosure is not limited thereto, and any number of convolution blocks 354A, 354B may be included in DCN 350 according to design preferences.

[0050] The convolution layer 356 may include one or more convolution filters that may be applied to the input data to generate a feature map. The normalization layer 358 may normalize the output of the convolution filter. For example, the normalization layer 358 may provide whitening or lateral suppression. The maximum pooling layer 360 may provide spatial downsampling aggregation to achieve local invariance and dimensionality reduction.

[0051] For example, a parallel filter bank of the DCN may be loaded on the SOC 100 (eg, Figure 1 ) on the CPU 102 or GPU 104 of the SOC 100 to achieve high performance and low power consumption. In an alternative embodiment, the parallel filter bank can be loaded on the DSP 106 or ISP 116 of the SOC 100. In addition, the DCN 350 can access other processing blocks that may exist on the SOC 100, such as the sensor processor 114 and the navigation module 120 dedicated to sensors and navigation, respectively.

[0052] The DCN 350 may also include one or more fully connected layers 362 (FC1 and FC2). The DCN 350 may also include a logistic regression (LR) layer 364. Between each layer 356, 358, 360, 362, 364 of the DCN 350 are weights (not shown) to be updated. The output of each layer in the layers (e.g., 356, 358, 360, 362, 364) may be used as an input to a subsequent layer in the layers (e.g., 356, 358, 360, 362, 364) in the DCN 350 to learn a hierarchical feature representation from the input data 352 (e.g., images, audio, video, sensor data, and / or other input data) supplied at the first convolutional block in the convolutional block 354A. The output of the DCN 350 is a classification score 366 for the input data 352. The classification score 366 may be a set of probabilities, where each probability is a probability that the input data includes a feature from a set of features.

[0053] Figure 4 400 is a block diagram illustrating an exemplary software architecture 400 that can modularize artificial intelligence (AI) functions. According to aspects of the present disclosure, using the architecture 400, a SOC 420 (which can be similar to Figure 1 Various processing blocks (e.g., CPU 422, DSP 424, GPU 426, and / or NPU 428) of SoC 100 support floating-point simulation for AI application 402. Architecture 400 may be included in a computing device such as a smart phone, for example.

[0054] The AI ​​application 402 may be configured to call functions defined in the user space 404 that may, for example, provide detection and recognition of scenes indicating the location where the computing device (including the architecture 400) is currently operating. For example, the AI ​​application 402 may configure microphones and cameras differently depending on whether the identified scene is an office, a lecture hall, a restaurant, or an outdoor environment such as a lake. The AI ​​application 402 may make a request for compiled program code associated with a library defined in the AI ​​function application programming interface (API) 406. The request may ultimately rely on the output of a deep neural network configured to provide an inferred response based on, for example, video and positioning data.

[0055] The runtime engine 408, which may be compiled code of the runtime framework, may further be accessible to the AI ​​application 402. The AI ​​application 402 may cause the runtime engine 408 to request inference, for example, at specific time intervals or triggered by an event detected by a user interface of the AI ​​application 402. When causing the runtime engine 408 to provide an inference response, the runtime engine may in turn transmit a signal to an operating system (such as a kernel 412) in an operating system (OS) space 410 running on the SOC 420. In some examples, the kernel 412 may be a LINUX kernel. The operating system may then cause continuous quantization relaxation to be performed on a CPU 422, a DSP 424, a GPU 426, an NPU 428, or some combination thereof. The CPU 422 may be directly accessible by the operating system, while other processing blocks may be accessed through drivers, such as drivers 414, 416, or 418 for the DSP 424, the GPU 426, or the NPU 428, respectively. In an illustrative example, the deep neural network may be configured to run on a combination of processing blocks such as CPU 422 , DSP 424 , and GPU 426 , or may run on NPU 428 .

[0056] The AI ​​application 402 may be configured to call functions defined in the user space 404 that may, for example, provide detection and identification of a scene indicating the location at which the computing device (including the architecture 400) is currently operating. For example, the AI ​​application 402 may configure microphones and cameras differently depending on whether the identified scene is an office, a lecture hall, a restaurant, or an outdoor environment such as a lake. The application 402 may make a request to a compiled program code associated with a library defined in a scene detection application programming interface (API) 406 to provide an estimate of the current scene. The request may ultimately rely on the output of a differential neural network configured to provide scene estimates based on, for example, video and positioning data.

[0057] The runtime engine 408, which may be compiled code of the runtime framework, may further be accessible by the AI ​​application 402. The AI ​​application 402 may cause the runtime engine 408 to request scene estimation, for example, at specific time intervals or triggered by an event detected by a user interface of the AI ​​application 402. When causing the runtime engine to estimate the scene, the runtime engine may in turn transmit a signal to an operating system 410, such as a kernel 412, running on the SOC 420. The operating system 410 may then cause the calculation to be performed on the CPU 422, the DSP 424, the GPU 426, the NPU 428, or some combination thereof. The CPU 422 may be directly accessible by the operating system, and other processing blocks may be accessed through drivers, such as drivers 414-418 for the DSP 424, for the GPU 426, or for the NPU 428. In an illustrative example, the differential neural network may be configured to run on a combination of processing blocks, such as the CPU 422 and the GPU 426, or may run on the NPU 428.

[0058] As described, aspects of the present disclosure relate to arbitrary bit width simulation (e.g., eight-bit floating point (FP8) simulation) utilizing learnable parameters. According to aspects of the present disclosure, a floating point input x may be received. For example, the input may include a single precision (e.g., 32-bit) floating point value. The input x may be received by, for example, an artificial neural network. The input value is typically provided in a binary representation. The binary representation may include a sign bit, a mantissa, and an exponent. The mantissa refers to a binary number of the floating point value, and the exponent refers to a binary number indicating the number of positions to move the decimal point. An integer quantization operation utilizing per-element scaling may be performed on the input value. This operation is opposite to the conventional method of applying one scale to each channel or tensor. In some aspects, the scale s may be determined based on the number of mantissa bits, the nearest integer power of two below the input, and a bias value.

[0059] Quantization is often applied to implement efficient integer matrix multiplication rather than 32-bit floating point (FP32) multiplication. This is because performing such computations involves large memory consumption and latency. mxn can be quantized into an integer matrix with associated scale s as follows in indicates round-to-nearest operation, and clip(·,·,·) indicates element-by-element clipping operation, which ensures that X (int) The dequantization operation can then be generated as the input matrix X:X (q) =sX (int) ≈The quantized approximation matrix X of X (q) . The quantized approximation of the input matrix enables the use of efficient integer matrix multiplication. For a matrix Y∈R nxk ,

[0060] XY≈X(q) Y (q) =s x s y X (int) Y (int) (1)

[0061] Floating point number set is a set whose elements are defined as follows:

[0062]

[0063] Where s∈{0,1} is the flag bit, d i ∈{0,1} is the m-bit mantissa, 0≤p<2 e is the e-bit exponent, and b is defined as 2 e-1 The integer exponent bias of .

[0064] Floating point numbers can be viewed as two consecutive (integer) powers of two. a ,2 a+1 A uniform m-bit grid between . The range [2 a ,2 a+1 The distance between the grid points in ] is 2 a-m Increasing the number of mantissa bits thus increases the range of each [2 a ,2 a+1 ]. In the definition provided, the range of the floating point number system representable is [2 a ,2 a+1 ] is determined by the number of exponent bits, e. Increasing the number of exponent bits increases the dynamic range of representable values ​​(e.g., the ratio of the largest non-zero value to the smallest non-zero value). Fixed-bitwidth floating-point systems trade off the dynamic range of representable values ​​(e) against precision (m). For example, IEEE-754 32-bit "full precision" floating-point numbers (FP32) use one sign bit, 23 mantissa bits, and eight exponent bits. The resulting effect is that the floating-point format has greater precision near zero than the integer format because the range [2 a ,2 a+1 ] is smaller for lower values ​​of a; and has less precision away from zero. Intuitively, the floating point format is a better match for peaked distributions such as the Gaussian distribution, which has greater density near zero, and for distributions with large tails and outliers such as the Student's t distribution.

[0065] Note that this definition does not allow for the representation of zero. To enable the representation of zero, the exponent value p=0 may be reserved to indicate a subnormal number. In this case, the exponent value may be implicitly set to one, and In addition to enabling exact representation of zero, subnormal numbers also enable more graceful representation of values ​​close to zero. That is, without subnormal ranges, the range between -2 -b with 2 -b There will be gaps in representable values, including the value zero, between .Thus, aspects of the present disclosure may advantageously enable a more complete representation of values ​​that reduces and in some aspects may eliminate gaps in the subnormal range and may increase model accuracy.

[0066] Additionally, according to aspects of the present disclosure, a (per tensor or per channel) quantization scale γ may be provided. Because there may not be a standard allocation of mantissa and exponent bits for floating point formats, various allocations of mantissa and exponent bits may be considered, as the choice of a tradeoff between precision and dynamic range may have a greater impact on lower floating point bit widths.

[0067] Aspects of the present disclosure may utilize floating point quantization as consecutive integer powers of two [2 a ,2 a+1 ] is the union of the m-bit uniformly quantized grids between ]. Therefore, we can associate the scale s in the input vector x i With each element x i To simulate floating point quantization (e.g., FP8) of x:

[0068]

[0069] in Represents x quantized to floating point i . Scales i It depends on the number of mantissa digits m and x i The range that falls within [2 a ,2 a+1 ]. Therefore, the scale s i It can be given by the following formula:

[0070]

[0071] In some respects, value and i Can be clipped to ensure It can be expressed by given m, e and b. For example, a value greater than the maximum value c or less than -c The value of can be clipped at c and -c respectively, where is the maximum representable value in a given floating point format. 1-b-m is the smallest representable value, so p is less than 1-bm i The value of can be clipped to 1-bm.

[0072] In some aspects, a quantization scaling factor may be applied (eg, a quantization scaling factor γ≠1). In this case, pi can be adapted. For example, to adapt the quantization scaling factor γ, it can be folded into the re-parameterized bias value Therefore, p i The calculation can be given as follows:

[0073]

[0074] Additionally, aspects of the present invention may be applied to implement quantization aware training (QAT). In QAT, rather than calculating scaling factors after the neural network is trained, the quantization error may be used to train the neural network and in doing so scale the neural network parameters. A straight-through estimator (STE) of the gradient for non-differentiable rounding operations may be used to enable the gradient to flow through each step of the quantizer. Furthermore, a maximum clipping value c may be learned instead of To improve training stability. Then It can be determined based on the maximum limit value c, expressed as:

[0075]

[0076] value can be considered as a constant that receives no gradients. This prevents the operation from being relative to x. i The (sometimes very large) gradients are back-propagated. Thus, x receives the “straight-through” gradients for the full quantization procedure, e.g. where F(·,·,·) represents a floating point quantizer.

[0077] Therefore, aspects of the present disclosure provide floating point quantization with an adaptable bit width that can beneficially produce better tensor reconstruction than integer (e.g., INT8) quantization through the selection of the division between the exponent bits and the mantissa bits and the value of the exponent bias. In addition, aspects of the present disclosure can be implemented in a common deep learning framework and can beneficially expose the parameters of a floating point (e.g., FP8) quantizer (e.g., the number of mantissa bits, the exponent, and the exponent bias), so that these parameters can be learned via back propagation.

[0078] Figure 5 is a block diagram illustrating an example pseudo code 500 according to aspects of the present disclosure. Figure 5 , the example pseudocode 500 provides that an input x for a neural network may be received. The input may, for example, include a floating point value, such as a 32-bit floating point number. The input x may be represented in a binary format such that the floating point value is represented via a number of mantissa bits M. Additionally, a maximum input clipping value c may be determined (or indicated).

[0079] The learnable clipping value c can be determined. Using the maximum clipping value c, the range of values ​​for the input x can be determined. In line 2, the number of exponent bits E can be redefined as a function of the number of mantissa bits M, where M is learnable. In line 3, the reparameterized bias value can be determined based on the learned maximum limit value c. In line 4, the learned mantissa M and the re-parameterized bias value to determine the number of exponent bits used for FP8. At line 5, the scale s can be calculated. The scale s corresponds to the grid defined by the learnable mantissa bits M and the clipping value c. Finally, at line 6, the input x can be quantized using the scale s (e.g., x i (q) ).

[0080] Figure 6 6 is a flowchart illustrating a processor-implemented method 600 for floating-point simulation with learnable parameters according to aspects of the present disclosure. The processor-implemented method 600 may be executed by a processor such as, for example, the CPU 102, the NPU 108, or other processing device. Figure 6 As shown, at block 602, the processor receives an input. As described, an input x may be received. The input may include a floating point value. For example, the input may include a single precision (e.g., 32-bit) floating point value. The input x may be received via, for example, an artificial neural network.

[0081] At block 604, the processor performs an integer quantization process on the input. Each element of the input may be scaled based on a scaling parameter to generate an m-bit floating point output. For example, FP8 quantization of the input vector x may be performed by associating a scale s i With every element x in x i To simulate. Scales i It depends on the number of mantissa digits m and x i The range that falls within [2 a ,2 a+1 ]. Therefore, FP8 quantization can use consecutive integer powers of two [2 a ,2 a+1 ] is the union of the m-bit uniformly quantized grids between ]. In addition, in some aspects, a straight-through estimator (STE) for gradients of non-differentiable rounding operations can be used to enable the gradient to flow through each step of the quantizer.

[0082] At block 606, the processor may optionally process the m-bit floating point (eg, FP8) output via an artificial neural network to generate an inference. For example, the inference may provide an indication of a classification of the input.

[0083] Although the example output described is in eight-bit floating point format, the present disclosure is not limited thereto. Instead, any floating point format may be simulated according to aspects of the present disclosure.

[0084] Example aspects

[0085] Aspect 1: A processor-implemented method, comprising: receiving an input; and performing an integer quantization process on the input, each element of the input being scaled based on a scaling parameter to generate an m-bit floating point output, where m is an integer.

[0086] Aspect 2: The processor-implemented method according to aspect 1, further comprising processing the m-bit floating point output via an artificial neural network to generate inferences.

[0087] Aspect 3: The processor-implemented method of aspect 1 or 2, wherein the scaling parameter is determined based on a first number of mantissa bits, a nearest integer power of two below the input, and an exponent bias.

[0088] Aspect 4: The processor-implemented method according to any one of aspects 1 to 3, wherein the exponent bias is a floating point value.

[0089] Aspect 5: The processor-implemented method according to any one of aspects 1 to 4, further comprising: determining a range of m-bit floating-point values ​​represented in the quantization grid based on the first number of mantissa bits, the second number of exponent bits, and the bias value.

[0090] Aspect 6: A processor-implemented method according to any one of Aspects 1 to 5, wherein the range of m-bit floating-point values ​​and the first number of mantissa bits are learnable parameters, the second number of exponent bits is determined from the first number of mantissa bits, and the bias value is determined from the range of m-bit floating-point values, the first number of mantissa bits, and the second number of exponent bits.

[0091] Aspect 7: The processor-implemented method according to any one of aspects 1 to 6, wherein the m-bit floating point output comprises an eight-bit floating point output.

[0092] Aspect 8: The processor-implemented method of any one of aspects 1 to 7, wherein the input is a single precision 32-bit value.

[0093] Aspect 9: An apparatus comprising: a memory; and at least one processor coupled to the memory, the at least one processor being configured to: receive an input; and perform an integer quantization process on the input, each element of the input being scaled based on a scaling parameter to generate an m-bit floating-point output, where m is an integer.

[0094] Aspect 10: The apparatus of aspect 9, wherein the at least one processor is further configured to: process the m-bit floating point output via an artificial neural network to generate inferences.

[0095] Aspect 11: The apparatus according to aspect 9 or 10, wherein the at least one processor is further configured to: determine the scaling parameter based on a first number of mantissa bits, a nearest integer power of two below the input, and an exponent bias.

[0096] Aspect 12: The apparatus according to any one of aspects 9 to 11, wherein the exponent bias is a floating point value.

[0097] Aspect 131: An apparatus according to any one of Aspects 9 to 12, wherein the at least one processor is further configured to: determine a range of m-bit floating-point values ​​represented in a quantization grid based on a first number of mantissa bits, a second number of exponent bits, and a bias value.

[0098] Aspect 14: An apparatus according to any one of Aspects 9 to 13, wherein the range of m-bit floating-point values ​​and the first number of mantissa bits are learnable parameters, the second number of exponent bits is determined from the first number of mantissa bits, and the bias value is determined from the range of m-bit floating-point values, the first number of mantissa bits and the second number of exponent bits.

[0099] Aspect 15: The apparatus of any one of Aspects 9 to 14, wherein the m-bit floating point output comprises an eight-bit floating point output.

[0100] Aspect 16: The apparatus of any one of aspects 9 to 15, wherein the input is a single precision 32-bit value and the m-bit floating point output comprises an eight-bit floating point output.

[0101] Aspect 17: A non-transitory computer-readable medium having program code recorded thereon, the program code being executed by a processor and comprising: program code for receiving an input; and program code for performing an integer quantization process on the input, each element of the input being scaled based on a scaling parameter to generate an m-bit floating-point output, where m is an integer.

[0102] Aspect 18: The non-transitory computer readable medium of aspect 17, further comprising: program code for processing the m-bit floating point output via an artificial neural network to generate an inference.

[0103] Aspect 19: The non-transitory computer readable medium of aspect 17 or 18, further comprising: program code for determining the scaling parameter based on a first number of mantissa bits, a nearest integer power of two below the input, and an exponent bias.

[0104] Aspect 20: The non-transitory computer-readable medium of any one of aspects 17 to 19, wherein the exponent bias is a floating point value.

[0105] Aspect 21: The non-transitory computer-readable medium according to any one of Aspects 17 to 20, further comprising: program code for determining a range of m-bit floating-point values ​​represented in a quantization grid based on a first number of mantissa bits, a second number of exponent bits, and a bias value.

[0106] Aspect 22: A non-transitory computer-readable medium according to any one of Aspects 17 to 21, wherein the range of m-bit floating-point values ​​and the first number of mantissa bits are learnable parameters, the second number of exponent bits is determined based on the first number of mantissa bits, and the bias value is determined based on the range of m-bit floating-point values, the first number of mantissa bits, and the second number of exponent bits.

[0107] Aspect 23: The non-transitory computer-readable medium of any one of Aspects 17 to 22, wherein the m-bit floating point output comprises an eight-bit floating point output.

[0108] Aspect 24: The non-transitory computer-readable medium of any one of Aspects 17 to 23, wherein the input is a single-precision 32-bit value and the m-bit floating point output comprises an eight-bit floating point output.

[0109] Aspect 25: An apparatus for a processor-implemented method, comprising: a component for receiving an input; and a component for performing an integer quantization process on the input, each element of the input being scaled based on a scaling parameter to generate an m-bit floating-point output, where m is an integer.

[0110] Aspect 26: The apparatus according to Aspect 25, further comprising means for processing the m-bit floating point output via an artificial neural network to generate an inference.

[0111] Aspect 27: The apparatus according to aspect 25 or 26, further comprising: a component for determining the scaling parameter based on a first number of mantissa bits, a nearest integer power of two below the input, and an exponent bias.

[0112] Aspect 28: The apparatus according to any one of aspects 25 to 27 further comprises means for determining a range of m-bit floating point values ​​represented in the quantization grid based on the first number of mantissa bits, the second number of exponent bits, and the bias value.

[0113] Aspect 29: An apparatus according to any one of Aspects 25 to 28, wherein the range of m-bit floating-point values ​​and the first number of mantissa bits are learnable parameters, the second number of exponent bits is determined from the first number of mantissa bits, and the bias value is determined from the range of m-bit floating-point values, the first number of mantissa bits and the second number of exponent bits.

[0114] Aspect 30: The apparatus of any one of Aspects 25 to 28, wherein the m-bit floating point output comprises an eight-bit floating point output.

[0115] In one aspect, the receiving means, executing means, defining means and / or applying means may be the GPU 104, a program memory associated with the GPU 104, the fully connected layer 362, the NPU 428 and / or the routing connection processing unit 216 configured to perform the recited functions. In another configuration, the aforementioned means may be any module or any device configured to perform the functions recited by the aforementioned means.

[0116] The various operations of the above methods may be performed by any suitable components capable of performing the corresponding functions. These components may include various hardware and / or software components and / or modules, including but not limited to circuits, application specific integrated circuits (ASICs), or processors. In general, where operations are illustrated in the accompanying drawings, these operations may have corresponding paired components plus function components with similar numbers.

[0117] As used, the term "determining" encompasses a wide variety of actions. For example, "determining" may include calculating, computing, processing, deriving, investigating, searching (e.g., searching in a table, database, or another data structure), ascertaining, etc. Additionally, "determining" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), etc. Furthermore, "determining" may include resolving, selecting, choosing, establishing, etc.

[0118] As used, a phrase referring to "at least one of" a list of items refers to any combination of those items, including single members. As an example, "at least one of a, b, or c" is intended to cover: a, b, c, ab, ac, bc, and abc.

[0119] The various illustrative logical blocks, modules, and circuits described in conjunction with the present disclosure may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array signal (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described. A general purpose processor may be a microprocessor, but in an alternative, the processor may be any commercially available processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0120] The steps or algorithms of the methods described in conjunction with the present disclosure may be directly embodied in hardware, software modules executed by a processor, or a combination of the two. The software module may be located in any form of storage medium known in the art. Some examples of usable storage media include random access memory (RAM), read-only memory (ROM), flash memory, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, removable disks, CD-ROMs, and the like. The software module may include a single instruction, perhaps multiple instructions, and may be distributed over several different code segments, distributed between different programs, and distributed across multiple storage media. The storage medium may be coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. In an alternative solution, the storage medium may be integral with the processor.

[0121] The disclosed methods include one or more steps or actions for implementing the described methods. The steps and / or actions of the methods may be interchanged with each other without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of specific steps and / or actions may be modified without departing from the scope of the claims.

[0122] The functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in hardware, an example hardware configuration may include a processing system in a device. The processing system may be implemented using a bus architecture. Depending on the specific application and overall design constraints of the processing system, the bus may include any number of interconnecting buses and bridges. The bus may link various circuits together, including a processor, a machine-readable medium, and a bus interface. The bus interface may be used to connect a network adapter, etc., to the processing system via the bus. The network adapter may be used to implement signal processing functions. For some aspects, a user interface (e.g., a keypad, a display, a mouse, a joystick, etc.) may also be connected to the bus. The bus may also link various other circuits, such as timing sources, peripherals, voltage regulators, power management circuits, etc., which are well known in the art and will not be described further.

[0123] The processor may be responsible for managing the bus and general processing, including executing software stored on the machine-readable medium. The processor may be implemented using one or more general-purpose processors and / or special-purpose processors. Examples include microprocessors, microcontrollers, DSP processors, and other circuits that can execute software. Software should be broadly interpreted as meaning instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or other. By way of example, a machine-readable medium may include a random access memory (RAM), a flash memory, a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a register, a disk, an optical disk, a hard disk drive, or any other suitable storage medium, or any combination thereof. The machine-readable medium may be embodied in a computer program product. The computer program product may include packaging material.

[0124] In hardware implementation, machine-readable media can be a part of a processing system separated from a processor. However, as will be readily appreciated by those skilled in the art, machine-readable media or any part thereof can be outside a processing system. By way of example, machine-readable media can include transmission lines, carrier waves modulated by data, and / or computer products separated from devices, all of which can be accessed by a processor through a bus interface. Alternatively or in addition thereto, machine-readable media or any part thereof can be integrated into a processor, such as with a cache and / or a general register stack. Although the various components discussed can be described as having specific locations, such as local components, they can also be configured in various ways, such as certain components being configured as a part of a distributed computing system.

[0125] The processing system can be configured as a general processing system having one or more microprocessors providing processor functionality and an external memory providing at least a portion of a machine-readable medium, all of which are linked together with other supporting circuit systems through an external bus architecture. Alternatively, the processing system may include one or more neuromorphic processors for implementing the described neuron model and neural system model. As another alternative, the processing system may be implemented with an application specific integrated circuit (ASIC) having at least a portion of a processor, a bus interface, a user interface, a support circuit, and a machine-readable medium integrated in a single chip, or with one or more field programmable gate arrays (FPGAs), programmable logic devices (PLDs), controllers, state machines, gated logic, discrete hardware components, or any other suitable circuits, or circuits capable of performing the various functionalities described throughout this disclosure. Those skilled in the art will recognize how to best implement the functionality of the processing system depending on the specific application and the overall design constraints imposed on the entire system.

[0126] The machine-readable medium may include multiple software modules. These software modules include instructions that cause the processing system to perform various functions when executed by the processor. The software modules may include a sending module and a receiving module. Each software module may reside in a single storage device or be distributed across multiple storage devices. By way of example, when a triggering event occurs, the software module may be loaded from a hard drive into a RAM. During the execution of the software module, the processor may load some of the instructions into a cache to increase access speed. Then one or more cache lines may be loaded into a general register stack for execution by the processor. When the functionality of a software module is mentioned below, it will be understood that such functionality is implemented by the processor when executing instructions from the software module. In addition, it should be understood that various aspects of the present disclosure produce improvements in the functionality of a processor, a computer, a machine, or other systems that implement such aspects.

[0127] If implemented in software, each function can be stored on a computer-readable medium or transmitted as one or more instructions or codes.Computer-readable media includes both computer storage media and communication media, including any medium that facilitates a computer program to be transmitted from one place to another.Storage media can be any available medium that can be accessed by a computer.By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage devices, disk storage devices or other magnetic storage devices, or may be used to carry or store desired program code in the form of an instruction or data structure and any other medium that can be accessed by a computer.Additionally, any connection is also appropriately referred to as a computer-readable medium.For example, if software is transmitted from a website, a server or other remote sources using a coaxial cable, an optical cable, a twisted pair, a digital subscriber line (DSL), or a wireless technology such as infrared (IR), radio, and microwaves, then the coaxial cable, optical cable, twisted pair, DSL, or a wireless technology such as infrared, radio, and microwaves are included in the definition of medium. As used herein, disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray Optical disks, where magnetic disks typically reproduce data magnetically, and optical disks reproduce data optically with lasers. Thus, in some aspects, computer-readable media may include non-transitory computer-readable media (e.g., tangible media). Additionally, for other aspects, computer-readable media may include transient computer-readable media (e.g., signals). Combinations of the above should also be included within the scope of computer-readable media.

[0128] Thus, some aspects may include a computer program product for performing the operations presented. For example, such a computer program product may include a computer-readable medium having stored (and / or encoded) thereon instructions that can be executed by one or more processors to perform the described operations. For some aspects, the computer program product may include packaging materials.

[0129] In addition, it should be understood that the modules and / or other appropriate components for performing the described methods and techniques can be downloaded and / or otherwise obtained by the user terminal and / or base station when applicable. For example, such a device can be coupled to a server to facilitate the transfer of components for performing the described methods. Alternatively, the various methods described can be provided via a storage component (e.g., RAM, ROM, a physical storage medium such as a compact disc (CD) or a floppy disk, etc.) so that once the storage device is coupled to or provided to the user terminal and / or base station, the device can obtain the various methods. In addition, any other suitable technology suitable for providing the described methods and techniques to the device can be used.

[0130] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. A processor-implemented method, comprising: Receive input; as well as An integer quantization process is performed on the input, and each element of the input is scaled based on a scaling parameter to generate an m-bit floating point output, where m is an integer.

2. The processor-implemented method of claim 1 , further comprising: The m-bit floating point output is processed via an artificial neural network to generate inferences. 3 . The processor-implemented method of claim 1 , wherein the scaling parameter is determined based on a first number of mantissa bits, a nearest integer power of two below the input, and an exponent bias. The processor-implemented method of claim 3 , wherein the exponent bias is a floating point value.

5. The processor-implemented method of claim 1 , further comprising: A range of m-bit floating point values ​​represented in a quantization grid is determined based on the first number of mantissa bits, the second number of exponent bits, and the bias value.

6. The processor-implemented method of claim 5, wherein the range of m-bit floating-point values ​​and the first number of mantissa bits are learnable parameters, the second number of exponent bits is determined from the first number of mantissa bits, and the bias value is determined from the range of m-bit floating-point values, the first number of mantissa bits, and the second number of exponent bits.

7. The processor-implemented method of claim 1, wherein the m-bit floating point output comprises an eight-bit floating point output.

8. The processor-implemented method of claim 1, wherein the input is a single-precision 32-bit value.

9. An apparatus comprising: Memory; and at least one processor coupled to the memory, the at least one processor configured to: Receive input; as well as An integer quantization process is performed on the input, and each element of the input is scaled based on a scaling parameter to generate an m-bit floating point output, where m is an integer.

10. The apparatus of claim 9, wherein the at least one processor is further configured to process the m-bit floating point output via an artificial neural network to generate inferences.

11. The apparatus of claim 9, wherein the at least one processor is further configured to determine the scaling parameter based on a first number of mantissa bits, a nearest integer power of two below the input, and an exponent bias. The apparatus of claim 11 , wherein the exponent bias is a floating point value.

13. The apparatus of claim 9, wherein the at least one processor is further configured to determine a range of m-bit floating point values ​​represented in a quantization grid based on a first number of mantissa bits, a second number of exponent bits, and a bias value.

14. The apparatus of claim 13, wherein the range of m-bit floating point values ​​and the first number of mantissa bits are learnable parameters, the second number of exponent bits is determined from the first number of mantissa bits, and the bias value is determined from the range of m-bit floating point values, the first number of mantissa bits, and the second number of exponent bits.

15. The apparatus of claim 9, wherein the m-bit floating point output comprises an eight-bit floating point output.

16. The apparatus of claim 9, wherein the input is a single precision 32-bit value and the m-bit floating point output comprises an eight-bit floating point output.

17. A non-transitory computer readable medium having program code recorded thereon, the program code being executed by a processor and comprising: Program code for receiving input; and Program code for performing an integer quantization process on the input, each element of the input being scaled based on a scaling parameter to generate an m-bit floating point output, where m is an integer.

18. The non-transitory computer readable medium of claim 17, further comprising: Program code is provided for processing the m-bit floating point output via an artificial neural network to generate inferences.

19. The non-transitory computer readable medium of claim 17, further comprising: Program code for determining the scaling parameter based on a first number of mantissa bits, a nearest integer power of two below the input, and an exponent bias.

20. The non-transitory computer readable medium of claim 19, wherein the exponent bias is a floating point value.

21. The non-transitory computer readable medium of claim 17, further comprising: Program code for determining a range of m-bit floating point values ​​represented in a quantization grid based on a first number of mantissa bits, a second number of exponent bits, and a bias value.

22. The non-transitory computer-readable medium of claim 21 , wherein the range of m-bit floating point values ​​and the first number of mantissa bits are learnable parameters, the second number of exponent bits is determined based on the first number of mantissa bits, and the bias value is determined based on the range of m-bit floating point values, the first number of mantissa bits, and the second number of exponent bits.

23. The non-transitory computer readable medium of claim 17, wherein the m-bit floating point output comprises an eight-bit floating point output.

24. The non-transitory computer readable medium of claim 17, wherein the input is a single precision 32-bit value and the m-bit floating point output comprises an eight-bit floating point output.

25. An apparatus for a processor-implemented method, comprising: A component for receiving input; and Means for performing an integer quantization process on the input, each element of the input being scaled based on a scaling parameter to generate an m-bit floating point output, where m is an integer.

26. The apparatus according to claim 25, further comprising: Means for processing the m-bit floating point output via an artificial neural network to generate an inference.

27. The apparatus of claim 25, further comprising: Program code for determining the scaling parameter based on a first number of mantissa bits, a nearest integer power of two below the input, and an exponent bias.

28. The apparatus of claim 25, further comprising: Means for determining a range of m-bit floating point values ​​represented in a quantization grid based on a first number of mantissa bits, a second number of exponent bits, and a bias value.

29. The apparatus of claim 28, wherein the range of m-bit floating point values ​​and the first number of mantissa bits are learnable parameters, the second number of exponent bits is determined from the first number of mantissa bits, and the bias value is determined from the range of m-bit floating point values, the first number of mantissa bits, and the second number of exponent bits.

30. The apparatus of claim 25, wherein the m-bit floating point output comprises an eight-bit floating point output.

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