Memory device, operating method thereof, and memory system

Abstract

The embodiment of the invention provides a memory device, an operation method thereof and a memory system. The memory device includes: a memory cell array including a plurality of memory blocks; and a peripheral circuit coupled to the memory cell array and configured to apply a plurality of different erase verification voltages to a selected memory block after applying a first effective erase voltage to the selected memory block in the plurality of memory blocks; according to the multiple erasing verification results corresponding to the multiple different erasing verification voltages, a second effective erasing voltage applied to the selected storage block is determined, and the second effective erasing voltage is larger than the first effective erasing voltage.

Description

Memory device and operation method thereof, and memory system Technical Field

[0001] The present application relates to the field of semiconductor technology, and relates to, but is not limited to, a memory device and an operating method thereof, and a memory system. Background Art

[0002] Memory devices are used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) memory has become a mainstream product in the memory market due to its high storage density, manageable production costs, suitable programming and erasing speeds, and retention characteristics.

[0003] However, as people's requirements for storage devices continue to increase, there is still much room for improvement in memory devices and systems.

[0004] Application Contents

[0005] Based on this, the embodiments of the present disclosure provide a memory device and an operating method thereof, and a memory system. On the one hand, the embodiments of the present disclosure provide a memory device comprising: a memory cell array, wherein the memory cell array comprises a plurality of memory blocks; and

[0006] a peripheral circuit coupled to the memory cell array and configured to: apply a first valid erase voltage to a selected memory block among the plurality of memory blocks, and then apply a plurality of different erase verification voltages to the selected memory block;

[0007] A second effective erase voltage applied to the selected memory block is determined according to results of multiple erase verifications corresponding to the multiple different erase verification voltages, where the second effective erase voltage is greater than the first effective erase voltage.

[0008] In one embodiment, the multiple different erase verification voltages include three different erase verification voltages, and the results of the multiple erase verifications include three erase verification results.

[0009] In one embodiment, the three different erase verification voltages include: a first erase verification voltage, a second erase verification voltage, and a third erase verification voltage, whose voltage values ​​increase in sequence; the first erase verification voltage, the second erase verification voltage, and the third erase verification voltage correspond to the results of the first erase verification, the second erase verification, and the third erase verification, respectively;

[0010] The peripheral circuit is further configured to: when a result of the first erase verification fails and a result of the second erase verification succeeds, determine that a voltage value of the second effective erase voltage is increased by a first voltage increment compared to a voltage value of the first effective erase voltage;

[0011] When a result of the second erase verification fails and a result of the third erase verification succeeds, determining that a voltage value of the second effective erase voltage is increased by a second voltage increment compared to a voltage value of the first effective erase voltage;

[0012] When a result of the third erasure verification fails, determining that a voltage value of the second effective erasure voltage is increased by a third voltage increment compared to a voltage value of the first effective erasure voltage;

[0013] The third voltage increment is greater than the second voltage increment, and the second voltage increment is greater than the first voltage increment.

[0014] In one embodiment, the memory block includes a drain terminal and a source terminal, and the source terminal is provided with a source line and a source selection gate;

[0015] The peripheral circuit is further configured to: apply a pulse corresponding to a first erase voltage to the source line of the selected memory block; in the process of the voltage of the source line rising to the first erase voltage, apply a first voltage to the source select gate of the selected memory block and float the source select gate after a preset time; in the process of the voltage of the source line being stable at the first erase voltage, the voltage of the source select gate is stable at a second voltage, the second voltage is less than the first erase voltage, and the difference between the first erase voltage and the second voltage constitutes a second effective erase voltage;

[0016] The longer the preset time is, the greater the voltage value of the second effective erase voltage is.

[0017] In one embodiment, the peripheral circuit is further configured to: when a result of the first erasure verification fails and a result of the second erasure verification succeeds, determine that the preset time length is a first time length;

[0018] When a result of the second erasure verification fails and a result of the third erasure verification succeeds, determining the preset duration to be a second duration;

[0019] When the result of the third erasure verification fails, determining the preset time length as a third time length;

[0020] The first duration is shorter than the second duration, and the second duration is shorter than the third duration.

[0021] In one embodiment, the selected memory block includes a plurality of memory blocks;

[0022] The peripheral circuit is configured to simultaneously apply a pulse corresponding to a first erase voltage to the source line of each of the selected memory blocks.

[0023] In one embodiment, the memory cell array includes a plurality of memory planes; the selected plurality of memory blocks are respectively stored in different of the memory planes;

[0024] The peripheral circuit is further configured to apply different second effective erasing voltages to the selected memory blocks in different memory planes by changing the preset time lengths when performing an erasing operation on the selected memory blocks in the plurality of memory planes.

[0025] In one embodiment, the memory block includes a drain terminal and a source terminal, the source terminal is provided with a source line; the memory block includes a plurality of word lines located between the drain terminal and the source terminal;

[0026] The peripheral circuit is further configured to: apply a second erase voltage to the source line of the selected memory block, and apply a first voltage to all word lines of the selected memory block, wherein the difference between the second erase voltage and the first voltage constitutes the second effective erase voltage;

[0027] The greater the voltage value of the second erase voltage is, the greater the voltage value of the second effective erase voltage is.

[0028] In one embodiment, the first voltage is a ground voltage.

[0029] In one embodiment, the peripheral circuit is further configured to: perform an erase operation on the selected memory block by applying a gradually increasing effective erase voltage multiple times;

[0030] After applying the effective erase voltage each time for a preset number of times, directly applying the third erase verification voltage to the selected memory block, and determining the effective erase voltage to be applied to the selected memory block next time according to the result of the erase verification corresponding to the third erase verification voltage;

[0031] After each application of the effective erase voltage exceeds the preset number of times, the multiple different erase verification voltages are applied to the selected storage block, and the next effective erase voltage to be applied to the selected storage block is determined based on the results of the multiple erase verifications corresponding to the multiple different erase verification voltages.

[0032] In one embodiment, the peripheral circuit is further configured to: apply the second erase verification voltage to the selected memory block when the result of the first erase verification fails;

[0033] When the result of the second erase verification fails, the third erase verification voltage is applied to the selected memory block.

[0034] In one embodiment, the first voltage is increased in increments of a step voltage.

[0035] In another aspect, an embodiment of the present disclosure provides a memory system, including:

[0036] One or more memory devices as described in the above embodiments of the present disclosure; and

[0037] A memory controller is coupled to the memory device and controls the memory device.

[0038] In another aspect, an embodiment of the present disclosure provides a method for operating a memory device, the method comprising:

[0039] After applying a first effective erase voltage to a selected memory block of the memory device, applying a plurality of different erase verification voltages to the selected memory block;

[0040] A second effective erase voltage applied to the selected memory block is determined according to results of multiple erase verifications corresponding to the multiple different erase verification voltages, where the second effective erase voltage is greater than the first effective erase voltage.

[0041] In one embodiment, the multiple different erase verification voltages include three different erase verification voltages, and the results of the multiple erase verifications include three erase verification results.

[0042] In one embodiment, the three different erase verification voltages include: a first erase verification voltage, a second erase verification voltage, and a third erase verification voltage, whose voltage values ​​increase sequentially; the first erase verification voltage, the second erase verification voltage, and the third erase verification voltage correspond to the results of the first erase verification, the second erase verification, and the third erase verification, respectively; the method further includes:

[0043] When a result of the first erase verification fails and a result of the second erase verification succeeds, determining that a voltage value of the second effective erase voltage is increased by a first voltage increment compared to a voltage value of the first effective erase voltage;

[0044] When a result of the second erase verification fails and a result of the third erase verification succeeds, determining that a voltage value of the second effective erase voltage is increased by a second voltage increment compared to a voltage value of the first effective erase voltage;

[0045] When a result of the third erasure verification fails, determining that a voltage value of the second effective erasure voltage is increased by a third voltage increment compared to a voltage value of the first effective erasure voltage;

[0046] The third voltage increment is greater than the second voltage increment, and the second voltage increment is greater than the first voltage increment.

[0047] In one embodiment, the memory block includes a drain terminal and a source terminal, and the source terminal is provided with a source line and a source select gate; the method further includes:

[0048] A pulse corresponding to a first erase voltage is applied to the source line of the selected memory block. When the voltage of the source line increases to the first erase voltage, a first voltage is applied to the source select gate of the selected memory block and the source select gate is floated after a preset time. When the voltage of the source line is stabilized at the first erase voltage, the voltage of the source select gate is stabilized at a second voltage, the second voltage is lower than the first erase voltage, and a difference between the first erase voltage and the second voltage constitutes a second effective erase voltage.

[0049] The longer the preset time is, the greater the voltage value of the second effective erase voltage is.

[0050] In one embodiment, the method further includes: when a result of the first erasure verification fails and a result of the second erasure verification succeeds, determining the preset duration to be a first duration;

[0051] When a result of the second erasure verification fails and a result of the third erasure verification succeeds, determining the preset duration to be a second duration;

[0052] When the result of the third erasure verification fails, determining the preset time length as a third time length;

[0053] The first duration is shorter than the second duration, and the second duration is shorter than the third duration.

[0054] In one embodiment, the memory block includes a drain terminal and a source terminal, the source terminal is provided with a source line; the memory block includes a plurality of word lines located between the drain terminal and the source terminal; the method further includes:

[0055] Applying a second erase voltage to the source line of the selected memory block and applying a first voltage to all word lines of the selected memory block, wherein the difference between the second erase voltage and the first voltage constitutes the second effective erase voltage;

[0056] The greater the voltage value of the second erase voltage is, the greater the voltage value of the second effective erase voltage is.

[0057] In one embodiment, the method further comprises: performing an erase operation on the selected memory block by applying a gradually increasing effective erase voltage multiple times;

[0058] After applying the effective erase voltage each time for a preset number of times, directly applying the third erase verification voltage to the selected memory block, and determining the effective erase voltage to be applied to the selected memory block next time according to the result of the erase verification corresponding to the third erase verification voltage;

[0059] After each application of the effective erase voltage exceeds the preset number of times, the multiple different erase verification voltages are applied to the selected storage block, and the next effective erase voltage to be applied to the selected storage block is determined based on the results of the multiple erase verifications corresponding to the multiple different erase verification voltages.

[0060] In the embodiments of the present disclosure, a memory device and an operating method thereof, and a memory system are proposed; wherein the memory device includes: a memory cell array and a peripheral circuit; wherein the memory cell array includes multiple memory blocks; the peripheral circuit is configured to: after applying a first effective erase voltage to a selected memory block from the multiple memory blocks, apply multiple different erase verification voltages to the selected memory block; and determine a second effective erase voltage applied to the selected memory block based on the results of multiple erase verifications corresponding to the multiple different erase verification voltages, wherein the second effective erase voltage is greater than the first effective erase voltage. In the embodiment of the present disclosure, after applying a first effective erase voltage to each selected storage block among a plurality of storage blocks, the erase degree of each storage block is determined by applying multiple different erase verification voltages to the plurality of storage blocks, and different second effective erase voltages are applied to the plurality of storage blocks according to their different erase degrees, so that the erase degrees of the plurality of storage blocks after applying the different second effective erase voltages tend to be consistent, and the erase speeds also tend to be consistent, thereby making the threshold voltage distribution of the erased state between different storage blocks tend to be uniform and consistent, thereby improving the read window margin of the storage block, and thus improving the read performance and erase performance of the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] FIG1 is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0062] FIG2 a is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0063] FIG2 b is a schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present disclosure;

[0064] FIG3 a is a schematic diagram showing the distribution of storage cells of a three-dimensional NAND memory according to an embodiment of the present disclosure;

[0065] FIG3 b is a schematic diagram of an exemplary memory including peripheral circuits according to an embodiment of the present disclosure;

[0066] FIG4 is a cross-sectional schematic diagram of a memory cell array including a NAND memory string according to an embodiment of the present disclosure;

[0067] FIG5 is a schematic diagram of an exemplary memory device including a memory cell array and peripheral circuits according to an embodiment of the present disclosure;

[0068] FIG6 is a schematic diagram illustrating an example of a threshold voltage distribution of a three-bit memory cell according to an embodiment of the present disclosure;

[0069] FIG7 is a schematic diagram illustrating an example of applying three different erase verification voltages to a memory block according to an embodiment of the present disclosure;

[0070] FIG8a is a schematic diagram illustrating an example of applying different second voltages to multiple memory blocks according to an embodiment of the present disclosure;

[0071] FIG8b is another exemplary schematic diagram of applying different second voltages to multiple memory blocks provided by an embodiment of the present disclosure;

[0072] FIG9 is a schematic diagram illustrating an example of a method for adjusting the voltage difference between a source line and all bit lines of a plurality of memory blocks provided by an embodiment of the present disclosure;

[0073] [Corrected 23.04.2023 according to Rule 91] FIG10 is a schematic diagram of threshold voltage distribution of a memory block in an erased state obtained by reading using different erase methods in a storage state according to an embodiment of the present disclosure;

[0074] [Corrected 23.04.2023 according to Rule 91] FIG11 is a schematic diagram of threshold voltage distribution of an erased state obtained by adopting different erasing methods for a storage block in another storage state provided by another embodiment of the present disclosure.

[0075] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation. DETAILED DESCRIPTION

[0076] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0077] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0078] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0079] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0080] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0081] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0082] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference only and are not intended to limit the embodiments of the present disclosure.

[0083] The memory device in the embodiments of the present disclosure includes but is not limited to a three-dimensional NAND memory. For ease of understanding, the three-dimensional NAND memory is used as an example for description.

[0084] FIG1 shows a block diagram of an exemplary system 100 with a memory device according to some aspects of the present disclosure. System 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As shown in FIG1 , system 100 can include a host 108 and a memory system 102, and memory system 102 has one or more memory devices 104 and a memory controller 106. Host 108 can be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. Host 108 can be configured to send data to or receive data from memory device 104.

[0085] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment, such as a solid state drive (SSD) or an embedded multimedia card (eMMC), which is used as data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.

[0086] The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions related to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction code (ECC) on data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with an external device (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Mini Interface (SCSI) protocol, Enhanced MiniDisk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.

[0087] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end-use electronic products. In one example, as shown in FIG2a, the memory controller 106 and a single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS card, etc. The memory card 202 can also include a memory card connector 204 that couples the memory card 202 to a host (e.g., the host 108 in FIG1 ). In another example, as shown in FIG2b, the memory controller 106 and multiple memory devices 104 can be integrated into an SSD 206. SSD 206 may also include an SSD connector 208 that couples SSD 206 to a host (eg, host 108 in FIG. 1 ). In some implementations, SSD 206 has a greater storage capacity and / or operating speed than memory card 202.

[0088] Figure 3a illustrates a schematic structural diagram of a memory cell array of a three-dimensional NAND memory. As shown in Figure 3a, the memory cell array of the three-dimensional NAND memory comprises several parallel, staggered rows of memory cell rows parallel to gate isolation structures. Every two rows of memory cell rows are separated by a gate isolation structure and an upper select gate isolation structure, and each memory cell row includes multiple memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory cell array into multiple memory blocks. The multiple second gate isolation structures may divide the memory blocks into multiple finger storage areas. An upper select gate isolation structure disposed between each finger storage area may divide the finger storage area into two parts, thereby dividing the finger storage area into two memory slices. The memory block shown in Figure 3a includes six memory slices. In practical applications, the number of memory slices in a memory block is not limited to this.

[0089] In some embodiments, each memory block may be coupled to multiple word lines, and multiple memory cells coupled to each independently controlled word line constitute a page. For example, all memory cells in each memory slice in FIG3 a are coupled to constitute a page.

[0090] It should be noted that the number of memory cell rows between the gate isolation structure and the upper select gate isolation structure shown in FIG3a is merely illustrative and does not limit the number of memory cell rows contained in a finger storage area of ​​the 3D NAND memory disclosed herein. In actual applications, the number of memory cell rows contained in a finger storage area can be adjusted based on actual conditions, such as 2, 4, 8, or 16.

[0091] FIG3 b shows a schematic circuit diagram of an exemplary memory device 300 including peripheral circuitry according to aspects of the present disclosure. Memory device 300 may be an example of memory device 104 in FIG1 . Memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to memory cell array 301. For illustration, memory cell array 301 is described as a three-dimensional NAND-type memory cell array, wherein memory cells 306 are NAND-type memory cells provided in an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and vertically stacked. Each memory cell 306 may hold a continuous analog value, such as a voltage or charge, that depends on the number of electrons trapped within the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0092] In some embodiments, each memory cell 306 is a single-level cell (SLC) that has two possible storage states and can therefore store one bit of data. For example, the first storage state "0" can correspond to a first voltage range, and the second storage state "1" can correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) that can store more than one bit of data in more than four storage states. For example, an MLC can store two bits per cell (also known as a two-bit memory cell, Double-Level Cell), three bits per cell (also known as a three-bit memory cell (TLC), four bits per cell (also known as a four-bit memory cell (QLC), five bits per cell (also known as a five-bit memory cell (PLC), or more than five bits per cell. Each MLC can be programmed to take on a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to assume one of three possible programming levels from the erased state by writing one of three possible nominal storage values ​​to the cell, a fourth nominal storage value can be used for the erased state.

[0093] As shown in FIG3b , each memory string 308 may include a lower select transistor 310 (also known as a source-side select transistor, which includes a source select gate BSG) at its source terminal and an upper select transistor 312 (also known as a drain-side select transistor, which includes a drain select gate TSG) at its drain terminal. The source select transistor BSG310 and the drain select transistor TSG312 may be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of the memory strings 308 in the same memory block 304 are coupled via the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, and data can be read from or written to the bit line 316 via an output bus (not shown). In some embodiments, each memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of a transistor having TSG 312) or a deselect voltage (e.g., 0V) to a corresponding TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of a transistor having BSG 310) or a deselect voltage (e.g., 0V) to a corresponding BSG 310 via one or more BSG lines 315.

[0094] As shown in FIG3 b , a memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for erase operations, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase the memory cells 306 in a selected memory block 304, the source lines 314 coupled to the selected memory block 304 and to unselected memory blocks 304 in the same plane as the selected memory block 304 can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, referring to FIG. 3 a , multiple memory cells are isolated from each other by an upper select gate isolation structure and a gate isolation structure. The memory cells between the upper select gate isolation structure and the gate isolation structure are arranged into multiple memory cell rows, with each memory cell row being parallel to the gate isolation structure and the upper select gate isolation structure. The memory cells in a memory slice sharing the same word line form a physical page 320. Each physical page 320 can be mapped to at least one logical page based on the storage mode of the corresponding memory cell 306 (e.g., SLC or MLC as described above). The logical page can constitute the basic data unit for programming and reading operations.

[0095] 3a and 3b, each memory cell 306 in the plurality of memory cells is coupled to a corresponding word line 318, and each memory string 308 is coupled to a corresponding bit line 316 via a corresponding selection transistor (eg, top selection transistor (TSG) 312).

[0096] FIG4 illustrates a cross-sectional schematic diagram of an exemplary memory cell array 301 including a NAND memory string 308, according to some aspects of the present disclosure. As shown in FIG4 , the NAND memory cell array 301 may include a stacked structure 410 comprising a plurality of gate layers 411 and a plurality of insulating layers 412 alternately stacked in sequence, and a channel structure vertically extending through the gate layers 411 and the insulating layers 412. The channel structure is coupled to each gate layer to form a memory cell, and the channel structure is coupled to the plurality of gate layers in the stacked structure 410 to form the memory string 308. The gate layers 411 and the insulating layers 412 may be alternately stacked, with two adjacent gate layers 411 separated by an insulating layer 412.

[0097] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower selection gate line, and the gate layer 411 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer.

[0098] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0099] In some embodiments, memory string 308 includes a channel structure extending vertically through stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with one or more semiconductor materials (e.g., serving as a semiconductor channel) and one or more dielectric materials (e.g., serving as a memory film). In some embodiments, the semiconductor channel includes silicon, such as polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). In some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially in this order from the center of the pillar toward the outer surface of the pillar. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0100] 3 b , peripheral circuitry 302 may be coupled to memory cell array 301 via bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. Peripheral circuitry 302 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory cell array 301 by applying and sensing voltage and / or current signals to and from each target memory cell 306 via bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. Peripheral circuitry 302 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, FIG5 shows some exemplary peripheral circuits, where the peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuits not shown in FIG5 may also be included.

[0101] The page buffer / sense amplifier 504 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to a control signal from the control logic 512. In one example, the page buffer / sense amplifier 504 can store program data (write data) to be programmed into the memory cell array 301. In another example, the page buffer / sense amplifier 504 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 316 representing the data bit stored in the memory cell 306 and amplify the small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512 and select one or more memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0102] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of the memory blocks 304. The row decoder / word line driver 508 can also be configured to drive the word lines 318 using word line voltages generated from a voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive the BSG lines 315 and the TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cells 306 coupled to the selected word line(s) 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., a read voltage, a program voltage, a pass voltage, a channel boosting voltage, a verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0103] The control logic 512 can be coupled to each of the other parts in the peripheral circuit described above and is configured to control the operation of each of the other parts in the peripheral circuit. The register 514 can be coupled to the control logic 512 and includes a status register, a command register, and an address register for storing status information, command operation code (OP code), and command address for controlling the operation of each peripheral circuit. The interface 516 can be coupled to the control logic 512 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 512, as well as buffer status information received from the control logic 512 and relay it to the host. The interface 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518 and act as a data I / O interface and data buffer to buffer data and relay it to the memory cell array 301 or relay or buffer data from the memory cell array 301.

[0104] Returning to Figures 3a and 3b, in a NAND memory, there are two ways to erase the memory cell array. One way is P-well erasing, that is, biasing the P-well substrate (such as a P-type doped well region (P-Well)) to a high voltage, and applying a lower bias voltage to the control gate of the memory cell to perform an erase operation. The other way is GIDL erasing, applying a high voltage to the source line or bit line, gradually floating the BSG line 315 or the TSG line 313 from a lower voltage, generating a gate-induced drain leakage (GIDL) current, and applying a lower bias voltage to the control gate of the memory cell to perform an erase operation. Among them, both P-well erasing and GIDL erasing can be used to reduce the threshold voltage (Vt) of the memory cell. It should be understood that the memory cell array may include multiple memory blocks, and the basic unit of the above-mentioned erase operation is a memory block.

[0105] However, as the number of erase and programming times increases, the tunneling efficiency of the tunneling layer in the storage unit will gradually weaken (that is, the tunneling layer will wear out), so that the number of pulses required for the erase operation will increase by one or even several times, which is equivalent to the number of erase times required for a complete erase operation increasing by one or even several times, thereby causing the erase speed of a single storage block to become slower and slower. Moreover, due to the different degrees of wear of the tunneling layer in different storage blocks, the erase speeds of the storage blocks will also be inconsistent, and the erase time will fluctuate greatly, affecting the erase performance of NAND memory.

[0106] In addition, during the execution of the above-mentioned erase operation, the increase in the number of erase operations will also lead to a shallow erase effect (Shallow Erase), which causes the threshold voltage distributions of multiple memory cells in the memory block to be different, and then causes the erased state read window margins (read window margin / budget) between multiple sub-memory blocks in the memory block and between memory blocks to differ greatly, affecting the read performance of the memory block and the memory device; here, multiple memory cells connected on the same word line in the memory block constitute a sub-memory block. Exemplarily, referring to Figure 6, the memory device includes multiple memory blocks, each memory block includes multiple sub-memory blocks, and Figure 6 shows only one of the multiple sub-memory blocks. The multiple memory cells in the exemplary sub-memory block are all three-bit memory cells, and each three-bit memory cell has eight states (L0-L7), which can be specifically divided into an erase state L0 and seven storage states (L1-L7), wherein the eight states correspond to seven read windows (such as RD1, RD2, RD3, RD4, RD5, RD6, and RD7). Due to the influence of the shallow erase effect, the difference in the read window margin E0 of the multiple erase states L0 corresponding to the multiple memory blocks in the memory device is about 400mV, thereby affecting the read performance of the memory block and the memory device.

[0107] In order to improve the problem of large differences in the read window margins E0 of the erased states L0 of multiple storage blocks caused by erasure, incremental step pulse erase (ISPE) can be used for erasure; wherein, an erase process may include multiple erase cycles, each of the multiple erase cycles may include an erase operation and an erase verification operation; the erase voltage of the erase operation gradually increases according to a step amount, and an erase verification operation is performed after each erase operation.

[0108] However, referring to FIG6 , after the memory block is erased using the incremental step pulse erasing method described above, there are still large differences in the read window margin E0 of the erased state L0 among the multiple memory blocks. This results in the subsequent testing process causing the threshold voltage distribution range of the erased state of the memory block to be judged as being too wide between +3σ and -3σ according to the 3σ (sigma) criterion of the normal distribution, thereby affecting the performance of the memory device.

[0109] It should be noted that the 3σ criterion, also known as the Laida criterion, assumes that a set of test data contains only random errors. The standard deviation is then calculated and an interval is determined based on a certain probability. Any error exceeding this interval is considered not random but gross error, and the data containing this error should be eliminated. The 3σ criterion is based on the assumption that repeated measurements of equal precision are normally distributed, but the interference or noise caused by singular data makes it difficult to conform to a normal distribution. If the absolute value of the residual error νi of a measurement value in a set of measurement data exceeds 3σ, the measurement value is considered bad and should be eliminated. An error equal to ±3σ is usually considered the limiting error. For a normally distributed random error, the probability of falling outside ±3σ is only 0.27%, which is very unlikely to occur in a finite number of measurements, hence the 3σ criterion. The 3σ criterion is the most commonly used and simplest criterion for identifying gross errors. It is generally applied when the number of measurements is sufficiently large (n ≥ 30) or when n > 10 for rough identification.

[0110] Therefore, based on one or more of the above problems, the embodiments of the present disclosure propose a memory device, an operating method thereof, and a memory system; wherein, the memory device includes a memory cell array, and the memory cell array may include multiple memory blocks; a peripheral circuit is coupled to the memory cell array and configured to: after applying a first effective erase voltage to a selected memory block among the multiple memory blocks, apply multiple different erase verification voltages to the selected memory block; and determine a second effective erase voltage applied to the selected memory block based on the results of multiple erase verifications corresponding to the multiple different erase verification voltages, wherein the second effective erase voltage is greater than the first effective erase voltage.

[0111] The memory cell array and the peripheral circuit are coupled to each other; wherein, the memory cell array may include multiple memory planes, each memory plane may include multiple memory blocks, each memory block may include multiple memory pages, the memory page is the minimum unit of read and write (i.e., programming) operations, and the memory block is the minimum unit of erase operation.

[0112] The peripheral circuits may include any suitable digital, analog, and / or mixed-signal circuits configured to facilitate various operations such as reading, writing, and erasing of the memory device. For example, the peripheral circuits may include control logic (e.g., a control circuit or controller), a data buffer, a decoder (a decoder may also be referred to as a decoder), a driver, and a read / write circuit. When the control logic receives a read / write operation command and address data, the decoder, under the control of the control logic, may apply a corresponding voltage from the driver to the corresponding bit line or word line based on the decoded address to implement data reading and writing, and exchange data with the outside through the data buffer.

[0113] 3 b , a memory string 308 includes a plurality of memory cells 306, a drain-side select transistor 312 at one end of the memory string, the drain-side select transistor 312 connecting the memory string 308 to a bit line 316, and a source-side select transistor 310 at one end of the memory string, the source-side select transistor 310 connecting the memory string 308 to a source line 314. The drain-side select transistor 312 has a corresponding drain select gate (TSG), and the source-side select transistor 310 has a corresponding source select gate (BSG).

[0114] It should be understood that the voltage difference between the drain select gate TSG and the bit line 316 negatively biases the gate of the drain-side select transistor, thereby forming a PN junction at the drain of the drain-side select transistor 312 and generating a hole current flowing downward from the drain to the source. The voltage difference between the drain select gate TSG and the bit line 316 applies a high electric field to the PN junction, causing the hole current to flow downward from the drain to the source, establishing a high potential within the semiconductor channel. Furthermore, the negative bias of the word line relative to the channel can inject holes into the storage layer, generating a gate-induced drain leakage current between the bit line and the drain select gate due to the band-to-band tunneling mechanism, which facilitates data erase operations.

[0115] Similarly, referring to FIG4 , the voltage difference between the source select gate (BSG) and the N-type doped well region in source-side select transistor 310 negatively biases the gate of the source-side select transistor, thereby forming a PN junction at the drain of the source-side select transistor. Furthermore, the voltage difference between the source select gate (BSG) and the N-type doped well region applies a high electric field to the PN junction. This high electric field generates gate-induced drain leakage current between the N-type doped well region and the source select gate (BSG) due to band-to-band tunneling, enabling data erase operations.

[0116] In an embodiment of the present disclosure, during an erase process using an incremental step pulse erase (ISPE) method, a peripheral circuit is configured to apply a first effective erase voltage to a selected memory block from a plurality of memory blocks. Here, the first effective erase voltage can be the voltage difference between the source line SL and the source select gate BSG of the selected memory block in the first erase cycle of an erase process, or the voltage difference between the source line SL and all word lines WL of the selected memory block. After applying the first effective erase voltage, multiple different erase verify voltages are applied to the selected memory block, and corresponding erase verify results are obtained based on the multiple different erase verify voltages. Based on the different erase verify results, it can be determined that the second effective erase voltage applied to the selected memory block is different. Here, the second effective erase voltage is the voltage difference between the source line SL and the source select gate BSG in the second erase cycle of an erase process, or the voltage difference between the source line SL and all word lines WL of the selected memory block, wherein the second effective erase voltage is greater than the first effective erase voltage.

[0117] In some embodiments, the multiple different erase verification voltages may include three different erase verification voltages, and accordingly, the results of the multiple erase verifications may include the results of three erase verifications; in other embodiments, the multiple different erase verification voltages may also include two, four, five... different erase verification voltages, and here only three different erase verification voltages are taken as an example.

[0118] It should be noted that, when multiple different erase verification voltages are applied to the selected storage block, there is a certain correlation between the multiple different erase verification voltages; specifically, after applying the first erase verification voltage, it is determined whether it is necessary to apply a second erase verification voltage to the selected storage block based on the result of the first erase verification; exemplarily: when the result of the first erase verification is successful, it indicates that all storage cells in the selected storage block under the first erase verification voltage have completed the corresponding degree of erase operation, that is, there is no need to apply the second erase verification voltage to the selected storage block; when the result of the first erase verification fails, it indicates that there are storage cells in the selected storage block under the first erase verification voltage that have not been erased to the corresponding degree, and then it is necessary to apply the second erase verification voltage to the selected storage block. Similarly, after applying the second erase verification voltage, it is determined whether it is necessary to apply a third erase verification voltage to the selected storage block based on the result of the second erase verification; wherein, when the result of the second erase verification is successful, it indicates that all storage cells in the selected storage block under the second erase verification voltage have completed the corresponding degree of erase operation, that is, there is no need to apply the third erase verification voltage to the selected storage block; when the result of the second erase verification fails, it indicates that there are storage cells in the selected storage block under the second erase verification voltage that have not been erased to the corresponding degree, and then it is necessary to apply the third erase verification voltage to the selected storage block.

[0119] In some embodiments, the three different erase verification voltages include: a first erase verification voltage, a second erase verification voltage, and a third erase verification voltage whose voltage values ​​increase successively; the first erase verification voltage, the second erase verification voltage, and the third erase verification voltage correspond to the result of the first erase verification, the result of the second erase verification, and the result of the third erase verification, respectively.

[0120] For example, referring to FIG7 , three different erase verification voltages are a first erase verification voltage Vev, a second erase verification voltage Vev_coarse1, and a third erase verification voltage Vev_coarse2, wherein the third erase verification voltage Vev_coarse2 is greater than the second erase verification voltage Vev_coarse1, and the second erase verification voltage Vev_coarse1 is greater than the first erase verification voltage Vev. In some specific embodiments, the voltage difference between the first erase verification voltage Vev and the second erase verification voltage Vev_coarse1 is within 0.5V, and the voltage difference between the second erase verification voltage Vev_coarse1 and the third erase verification voltage Vev_coarse2 is within 0.5V.

[0121] It should be noted that in some embodiments, a state dual strobe sense verification method can also be used to simultaneously obtain three verification results corresponding to three erase verification voltages, that is, after applying the first erase verification voltage Vev, the verification results after applying the second erase verification voltage Vev_coarse1 and the third erase verification voltage Vev_coarse2 can be obtained simultaneously.

[0122] Correspondingly, based on the different erase verification voltages of the three times, the results of the three erase verifications are also different. Referring to FIG7 , the first erase verification voltage Vev corresponds to the first erase verification result D1, the second erase verification voltage Vev_coarse1 corresponds to the second erase verification result D2, and the third erase verification voltage Vev_coarse2 corresponds to the third erase verification result D3. The first erase verification result D1, the second erase verification result D2, and the third erase verification result D3 can all be used to indicate whether the selected memory block has been successfully erased or the extent of the erase at the corresponding erase verification voltage.

[0123] Based on the above multiple erase verification voltages, the corresponding verification results can be divided into: the first erase verification result is successful, the first erase verification result fails and the second erase verification result is successful, the second erase verification result fails and the third erase verification result is successful, and the third erase verification result fails. According to the above different erase verification results, the voltage value of the second effective erase voltage is different. Specifically: the peripheral circuit is further configured to:

[0124] When the result of the first erase verification fails and the result of the second erase verification succeeds, determining that the voltage value of the second effective erase voltage is increased by a first voltage increment compared to the voltage value of the first effective erase voltage;

[0125] When the result of the second erase verification fails and the result of the third erase verification succeeds, determining that the voltage value of the second effective erase voltage is increased by a second voltage increment compared to the voltage value of the first effective erase voltage;

[0126] When the result of the third erasure verification fails, determining that the voltage value of the second effective erasure voltage is increased by a third voltage increment compared to the voltage value of the first effective erasure voltage;

[0127] The third voltage increment is greater than the second voltage increment, and the second voltage increment is greater than the first voltage increment.

[0128] Referring to FIG7 , when the result D1 of the first erase verification fails, the second erase verification voltage Vev_coarse1 is applied to the selected memory block, and the result D2 of the second erase verification is obtained; when the result D2 of the second erase verification is successful, that is, the result D1 of the first erase verification fails and the result D2 of the second erase verification is successful, the voltage value of the second effective erase voltage applied to the selected memory block is: the voltage value of the first effective erase voltage is increased by the first voltage increment; illustratively, the voltage value of the first effective erase voltage is Vera-init, and the first voltage increment is V ISPE , then the second effective erase voltage is Vera_init+V ISPE In some other embodiments, the first voltage is increased by V ISPE It can be a step voltage when performing an incremental step pulse erase (ISPE) operation.

[0129] When the result D2 of the second erase verification fails, the third erase verification voltage Vev_coarse2 is applied to the selected memory block, and the result D3 of the third erase verification is obtained; when the result D3 of the third erase verification is successful, that is, the result D2 of the second erase verification fails and the result D3 of the third erase verification is successful, the voltage value of the second effective erase voltage applied to the selected memory block is: adding the second voltage increment on the basis of the voltage value of the first effective erase voltage, where the second voltage increment is greater than the first voltage increment; illustratively, the voltage value of the first effective erase voltage is Vera-init, and the second voltage increment is V ISPE +ΔV1, the second effective erase voltage is Vera_init+V ISPE +ΔV1.

[0130] When the result D3 of the third erase verification fails, the voltage value of the second effective erase voltage applied to the selected memory block is: based on the voltage value of the first effective erase voltage plus a third voltage increment, where the third voltage increment is greater than the second voltage increment; illustratively, the voltage value of the first effective erase voltage is Vera-init, and the third voltage increment is V ISPE +ΔV2, where ΔV2 is greater than ΔV1, then the second effective erase voltage is: Vera_init+V ISPE +ΔV2. In this way, different erasure degrees of multiple memory blocks can be determined based on different erase verification results. Different second effective erase voltages can be applied to the memory blocks with different erase degrees, so that the erase degrees of the multiple memory blocks after applying the different second effective erase voltages tend to be consistent, and the erase speeds tend to be consistent. In turn, the threshold voltage distribution of the erased state between different memory blocks tends to be uniform and consistent, thereby improving the read performance and erase performance of the memory device.

[0131] It should be noted that when the result D1 of the first erasure verification is success, it indicates that the erasure operation has been completed, and there is no need to perform subsequent erasure verification operations.

[0132] In order to further understand the present solution, the specific operation of how to apply different second effective erase voltages to the storage block is described in detail below in conjunction with Figures 8a, 8b, and 9. It should be understood that applying different second effective erase voltages can be applied to the same storage block at different times, or to different storage blocks in the same storage plane, or to multiple storage blocks stored in different storage planes. However, whether applying different second effective erase voltages to the same storage block at different times, or applying different second effective erase voltages to multiple storage blocks, the voltage value of the second effective erase voltage can be adjusted / changed by changing the preset duration. Specifically:

[0133] In some embodiments, a pulse corresponding to a first erase voltage is applied to the source line of the selected storage block, and in the process of the voltage of the source line rising to the first erase voltage, a first voltage is applied to the source select gate of the selected storage block and the source select gate is floated after a preset time, and in the process of the voltage of the source line stabilizing at the first erase voltage, the voltage of the source select gate is stabilized at a second voltage, the second voltage is less than the first erase voltage, and the difference between the first erase voltage and the second voltage constitutes the second effective erase voltage; wherein, the longer the preset time, the greater the voltage value of the second effective erase voltage.

[0134] Here, the initial voltages on the source line SL of the selected storage block and the corresponding source selection gate BSG are both the first voltage (such as the ground voltage Vss). At the first moment, the first erase voltage Vers is applied to the source line SL of the selected storage block. After a period of time, the voltage of the source line SL reaches the first erase voltage Vers and stabilizes at the first erase voltage Vers.

[0135] During the process of the voltage of the source line SL of the selected memory block rising from the ground voltage Vss to the first erase voltage Vers, the source select gate BSG of the selected memory block is changed from being applied with the first voltage (e.g., the ground voltage Vss) to being in a floating state after a preset duration. Here, the preset duration can be set according to actual needs. When the voltage of the source line SL of the selected memory block reaches the first erase voltage Vers, the voltage of the source select gate BSG in the corresponding memory block stabilizes at a second voltage (Vers-V) due to coupling. This second voltage is also called the Hold and Release (H&R) voltage. It should be noted that the selected memory block may have multiple source select gates BSG, such as the first source select gate BSG0_0 and the second source select gate BSG0_1. When there are multiple source select gates BSG in the memory block, corresponding voltages are applied to each of the multiple source select gates BSG after the preset duration.

[0136] It should be understood that the voltage difference between the source line SL and the corresponding source select gate BSG of a selected memory block is the second effective erase voltage. When the first erase voltage on the source line SL of the selected memory block remains unchanged, the longer the preset duration is, the longer the voltage on the source select gate BSG in the memory block is forced to remain at the first voltage. Consequently, the shorter the duration of the coupling effect on the source line SL, the lower the final stable second voltage on the corresponding source select gate BSG, and the larger the voltage value of the second effective erase voltage. Therefore, based on different erase verification results, the preset duration can be changed to adjust / variate the voltage value of the second effective erase voltage, so that the erase levels of multiple memory blocks tend to be consistent.

[0137] Exemplarily, when the result of the first erasure verification fails and the result of the second erasure verification succeeds, the preset duration is determined to be the first duration;

[0138] When a result of the second erasure verification fails and a result of the third erasure verification succeeds, determining the preset duration to be a second duration;

[0139] When the result of the third erasure verification fails, determining the preset time length as a third time length;

[0140] The first duration is shorter than the second duration, and the second duration is shorter than the third duration.

[0141] In the embodiment of the present disclosure, when the result of the first erase verification fails and the result of the second erase verification succeeds, it indicates that the current erase degree of the selected memory block is relatively deep, that is, there are a small number of memory cells in the selected memory block that have not been erased (the first corresponding degree). At this time, the voltage value of the second effective erase voltage can be increased by the first voltage increment V compared to the voltage value of the first effective erase voltage by controlling the preset time length (such as setting the preset time length to the first time length). ISPE .

[0142] When the result of the second erase verification fails and the result of the third erase verification succeeds, it indicates that the current erase degree of the selected memory block is shallower than the first corresponding degree, that is, there are a certain number of memory cells in the selected memory block that have not been erased (the second corresponding degree). At this time, the voltage value of the second effective erase voltage can be increased by the second voltage increment V compared to the voltage value of the first effective erase voltage by controlling the preset time length (for example, setting the preset time length to the second time length). ISPE +ΔV1.

[0143] When the result of the third erasure verification fails, it indicates that the current erasure degree of the selected memory block is shallower than the second relative degree, that is, there are a large number of memory cells in the selected memory block that have not been erased (third relative degree). At this time, the voltage value of the second effective erasure voltage can be increased by a third voltage increment V compared to the voltage value of the first effective erasure voltage by controlling the preset time length (such as setting the preset time length to the third time length). ISPE +ΔV2.

[0144] In other words, the erasure degrees of the storage blocks represented by the first corresponding degree, the second corresponding degree, and the third corresponding degree gradually become shallower, and the corresponding control preset time lengths, such as the first time length, the second time length, and the third time length, gradually increase.

[0145] In other embodiments, referring to Figure 8a, the selected storage block includes multiple storage blocks; and the selected multiple storage blocks are respectively stored in different storage planes; here, applying different second effective erase voltages to the selected multiple storage blocks means applying different second effective erase voltages to the selected multiple storage planes; the peripheral circuit is configured to: simultaneously apply a pulse corresponding to the first erase voltage to the source line of each storage block in the selected multiple storage blocks.

[0146] It should be noted that after applying multiple different erase verification voltages, the erase degrees of multiple storage blocks in multiple storage planes may be the same or different. When the erase degrees of the selected storage blocks in the multiple storage planes are the same, refer to Figure 9, the preset durations set are the same, all t', and the second effective erase voltage applied is the same (all v0). When the erase degrees of the selected storage blocks in the multiple storage planes are different, refer to Figures 8a and 8b, the preset durations set are different (such as t1, t2, t3 or t4, t5, t6), and the second effective erase voltage applied is also different. In order to more clearly understand the present disclosure, the following embodiments are described by taking the different erase degrees of multiple storage blocks as an example.

[0147] Referring to Figure 8a, the initial voltage on the source line SL and the corresponding source selection gate BSG of each storage block in the selected multiple storage blocks is the first voltage (such as the ground voltage Vss). At the first moment (such as t0), the first erase voltage Vers is applied to the source line SL of each storage block in the selected multiple storage blocks at the same time. After a period of time, the voltages of the multiple source lines SL reach the first erase voltage Vers and stabilize at the first erase voltage Vers.

[0148] During the process of the voltage of the source line SL of each of the selected multiple memory blocks rising from the ground voltage Vss to the first erase voltage Vers, after a preset duration, the source select gate BSG of each of the selected multiple memory blocks changes from being applied with the first voltage to being in a floating state. Here, the preset duration can be set according to actual needs. When the voltage of the source line SL of each of the selected multiple memory blocks reaches the first erase voltage Vers, the voltage of the source select gate BSG in the corresponding memory block stabilizes at a second voltage (Vers-v*) due to coupling. v* corresponds to different memory blocks.

[0149] Continuing to refer to FIG8a, the selected multiple memory blocks are respectively stored in the first memory plane (pl0), the second memory plane (pl1), and the third memory plane (pl2), and the erase degrees of the selected multiple memory blocks gradually become shallower. When the first voltage on the source select gate BSG is kept for different lengths of time and then floated at different times, the second voltages on the source select gates (bsg-pl0, bsg-pl1, bsg-pl2) corresponding to the multiple memory blocks are Vers-v0, Vers-v1, and Vers-v2, respectively. Here, The second voltages on the source select gates BSG of the memory blocks corresponding to the first to third memory planes gradually decrease, such as Vers-v0>Vers-v1>Vers-v2 (this situation is shown in FIG8 a ). In other embodiments, when the erase levels of the selected multiple memory blocks gradually deepen, the second voltages on the source select gates BSG corresponding to different memory planes can be gradually increased, such as Vers-v0<Vers-v1<Vers-v2, by adjusting the floating timing of the source select gates BSG. Other configurations can also be selected based on actual needs and are not described in detail here. When the voltage of the source line SL of each of the selected multiple storage blocks is stabilized at the first erase voltage, the second effective erase voltages applied to the selected multiple storage blocks are v0, v1, and v2, respectively; wherein, the magnitude relationship between v0, v1, and v2 is related to the second voltage (H&R) on the corresponding source select gate BSG. Here, the smaller (the shallower) the erase degree of the storage block, the larger the second voltage (Vers-v*), and the smaller the corresponding second effective erase voltage (v*).

[0150] Based on this, when performing an erase operation on multiple storage blocks selected from multiple storage planes, the second voltage of the source selection gate (maintaining the release voltage) can be changed by changing the preset time length to apply different second effective erase voltages to the storage blocks selected from different storage planes.

[0151] Referring to Figure 8a, when the result of the first erase verification fails and the result of the second erase verification succeeds, it indicates that the degree of erasure of the currently selected memory block is relatively deep, and the second effective erase voltage v0 can be determined by setting the preset time length to t1 to obtain the second voltage Vers-v0. When the result of the second erase verification fails and the result of the third erase verification succeeds, it indicates that the degree of erasure of the currently selected memory block is relatively shallow, and the second effective erase voltage v1 can be determined by setting the preset time length to t2 to obtain the second voltage Vers-v1.

[0152] When the result of the third erasure verification fails, it indicates that the erasure degree of the currently selected memory block is very shallow, and the second effective erasure voltage v2 can be determined by setting the preset time length to t3 to obtain the second voltage Vers-v2. Here, t1<t2<t3.

[0153] That is to say, in the embodiment of the present disclosure, each storage plane can be controlled separately, and different second voltages (H&R voltages) can be applied separately to the storage blocks in each storage plane to achieve different second effective erase voltages applied to different storage blocks in different storage planes. In this way, the second effective erase voltage can be flexibly adjusted / changed according to the degree of erase, thereby reducing the difference in threshold voltage distribution of the erased state L0 between storage blocks and improving the reading performance and erase performance of the memory device.

[0154] In other embodiments, referring to FIG8b , the selected multiple memory blocks are different memory blocks (e.g., block-a, block-b, and block-c) in the same memory plane. When the first voltage on the source select gate BSG is maintained for different durations and then floated at different times, the second voltages on the source select gates BSG corresponding to the multiple memory blocks are respectively Vers-va, Vers-vb, and Vers-vc. As the erase levels of block-a, block-b, and block-c gradually decrease, the different preset durations corresponding to the different times gradually increase, e.g., t4 < t5 < t6, and the corresponding second voltages gradually decrease, e.g., Vers-va > Vers-vb > Vers-vc. The corresponding second effective erase voltages gradually increase, e.g., va > vb > vc. In this way, the second effective erase voltage applied to the memory blocks can be adjusted / changed by controlling the preset durations.

[0155] In addition, it should be noted that after the selected memory block completes an erase cycle, all source lines SL and source selection gates BSG are restored to the first voltage (ground voltage, Vss).

[0156] In an embodiment of the present disclosure, an example is also provided of applying different second effective erase voltages to different storage blocks when adopting another erasing method, that is, changing the second effective erase voltage of the corresponding storage block by changing the voltage difference between the source line SL of the selected storage block and all word lines WL.

[0157] In some embodiments, the memory block includes a drain terminal and a source terminal, the source terminal is provided with a source line; the memory block includes a plurality of word lines located between the drain terminal and the source terminal;

[0158] The peripheral circuit is also configured to: apply a second erase voltage to the source line of the selected storage block, and apply a first voltage to all word lines of the selected storage block, and the difference between the second erase voltage and the first voltage constitutes the second effective erase voltage; wherein, when the first voltage is fixed, the larger the voltage value of the second erase voltage, the larger the voltage value of the second effective erase voltage.

[0159] Exemplarily, the voltage applied to the source line SL of each of the selected multiple memory blocks is the second erase voltage, the voltage applied to all word lines WL of the selected memory block is the first voltage, and the difference between the second erase voltage and the first voltage constitutes the second effective erase voltage. When the first voltage remains unchanged, the second erase voltage is directly proportional to the voltage value of the second effective erase voltage; for example, the greater the voltage value of the second erase voltage, the greater the voltage value of the second effective erase voltage. In this way, by changing the second erase voltage, different second effective erase voltages can be applied to different memory blocks.

[0160] In some embodiments, the peripheral circuit is further configured to: perform an erase operation on the selected memory block by applying gradually increasing effective erase voltages multiple times;

[0161] After applying the effective erase voltage each time for a preset number of times, directly applying the third erase verification voltage to the selected memory block, and determining the effective erase voltage to be applied to the selected memory block next time according to the result of the erase verification corresponding to the third erase verification voltage;

[0162] After each application of the effective erase voltage exceeds the preset number of times, the multiple different erase verification voltages are applied to the selected storage block, and the next effective erase voltage to be applied to the selected storage block is determined based on the results of the multiple erase verifications corresponding to the multiple different erase verification voltages.

[0163] Here, in the process of performing erasure using the incremental step pulse erase (ISPE) method, an erase process may include multiple erase cycles. In the first few erase cycles (i.e., the preset number of erase cycles), it is possible that the first erase verification result is successful after applying the first erase verification voltage. Therefore, in the first few erase cycles, the third erase verification voltage is directly applied to the selected memory block, and the result of the third erase verification is determined. The preset number of times can be inferred based on historical experience. Here, the preset number of times is the critical number of times the result of the third erase verification changes from failure to success.

[0164] If the third erase verification result is successful in the first few erase cycles, in each of the subsequent erase cycles (i.e., beyond the preset number of times), after applying the first effective erase voltage to the selected memory block each time, multiple different erase verification voltages are applied, and the second effective erase voltage to be applied to the selected memory block next time is determined based on the results of the multiple erase verifications corresponding to the multiple different erase verification voltages. In this way, the time of the erase verification operation can be saved and the efficiency of the erase verification operation can be improved.

[0165] As mentioned above, an erase process in an embodiment of the present disclosure may include multiple erase cycles, and each erase cycle in the multiple erase cycles includes an erase operation and three erase verification operations. The specific method is as follows: when the result D1 of the first erase verification fails, a second erase verification voltage Vev_coarse1 is applied to the selected memory block, and a second erase verification result D2 is obtained; when the result D2 of the second erase verification fails, a third erase verification voltage Vev_coarse2 is applied to the selected memory block, and a third erase verification result D3 is obtained. In another embodiment of the present disclosure, in the first few erase cycles of the multiple erase cycles, a third erase verification can be directly performed on the memory cell, that is, after applying the first valid erase voltage to the selected memory block, a third erase verification voltage Vev_coarse2 is directly applied to the selected memory block, and the result of the third erase verification is judged.

[0166] In the verification result, if there is no storage cell with a threshold voltage lower than the third erase verification voltage Vev_coarse2, it indicates that the threshold voltage of all storage cells will not reach below the second erase verification voltage Vev_coarse1. At this time, it directly enters the next erase cycle; if there is a storage cell with a threshold voltage lower than the third erase verification voltage Vev_coarse2, it is verified with the second erase verification voltage Vev_coarse1. If there is no storage cell with a threshold voltage lower than the second erase verification voltage Vev_coarse1, it enters the next erase cycle; if there is a storage cell with a threshold voltage lower than the second erase verification voltage Vev_coarse1, it is verified with the first erase verification voltage Vev, and then enters the next erase cycle according to the verification result. After that, the verification can be started from the first erase verification voltage Vev each time. In this way, the early verification time can be reduced, thereby reducing the erase time.

[0167] Based on this, in the embodiment of the present disclosure, after applying a first effective erase voltage to each selected storage block among a plurality of storage blocks, the erase degree of each storage block is determined by applying multiple different erase verification voltages to the plurality of storage blocks, and different second effective erase voltages are applied to the plurality of storage blocks according to their different erase degrees, so that the erase degrees of the plurality of storage blocks after applying different second effective erase voltages tend to be consistent, and the erase speeds also tend to be consistent, thereby making the threshold voltage distribution of the erased state between different storage blocks tend to be uniform and consistent, thereby improving the reading performance and erase performance of the memory device.

[0168] In addition, the embodiments of the present disclosure also provide comparative examples of threshold voltage distributions in the erased state of a memory block using two different erase methods in different storage states. The first erase method is the method described in the above embodiments of the present disclosure, in which each erase cycle includes one erase operation and three erase-verify operations; the second erase method is the method described in the related art, in which each erase cycle includes one erase operation and one erase-verify operation.

[0169] Referring to Figures 10 and 11, Figure 10 shows a schematic diagram of the threshold voltage distribution in the erased state of the storage block when no data is stored in some of its storage cells, after the first erasure method (P1) and the second erasure method (P2) are respectively adopted. Figure 11 shows a schematic diagram of the threshold voltage distribution in the erased state of the storage block when data is stored in all of its storage cells, after the first erasure method (P3) and the second erasure method (P4) are respectively adopted.

[0170] As can be seen from FIG6 and FIG10, when there are memory cells in the memory block that do not store data, after applying the second effective erase voltage to the selected memory block using the first erase method, the threshold voltage range of the erased state L0 of the memory block between +3σ and -3σ decreases, that is, the read window margin E0 of the erased state L0 increases. As can be seen from FIG6 and FIG11, when all memory cells in the memory block store data, after applying the second effective erase voltage to the selected memory block using the first erase method, the threshold voltage range of the erased state L0 of the memory block between +3σ and -3σ decreases, that is, the read window margin E0 of the erased state L0 increases. In other words, regardless of whether there are memory cells in the memory block that do not store data, applying the second effective erase voltage to the selected memory block using the first erase method can increase the read window margin of the erased state of the memory block, thereby improving the read performance of the memory block and the memory device.

[0171] On the other hand, an embodiment of the present disclosure further provides an operating method for a memory device, the operating method comprising: applying a first effective erase voltage to a selected memory block of the memory device, and then applying a plurality of different erase verification voltages to the selected memory block;

[0172] A second effective erase voltage applied to the selected memory block is determined according to results of multiple erase verifications corresponding to the multiple different erase verification voltages, where the second effective erase voltage is greater than the first effective erase voltage.

[0173] In some embodiments, the multiple different erase verification voltages include three different erase verification voltages, and the results of the multiple erase verifications include three erase verification results.

[0174] In some embodiments, the three different erase verification voltages include: a first erase verification voltage, a second erase verification voltage, and a third erase verification voltage, whose voltage values ​​increase in sequence; the first erase verification voltage, the second erase verification voltage, and the third erase verification voltage correspond to the results of the first erase verification, the second erase verification, and the third erase verification, respectively; and the method further includes:

[0175] When a result of the first erase verification fails and a result of the second erase verification succeeds, determining that a voltage value of the second effective erase voltage is increased by a first voltage increment compared to a voltage value of the first effective erase voltage;

[0176] When a result of the second erase verification fails and a result of the third erase verification succeeds, determining that a voltage value of the second effective erase voltage is increased by a second voltage increment compared to a voltage value of the first effective erase voltage;

[0177] When a result of the third erasure verification fails, determining that a voltage value of the second effective erasure voltage is increased by a third voltage increment compared to a voltage value of the first effective erasure voltage;

[0178] The third voltage increment is greater than the second voltage increment, and the second voltage increment is greater than the first voltage increment.

[0179] In some embodiments, the memory block includes a drain terminal and a source terminal, the source terminal is provided with a source line and a source select gate; the method further includes:

[0180] A pulse corresponding to a first erase voltage is applied to the source line of the selected memory block. When the voltage of the source line increases to the first erase voltage, a first voltage is applied to the source select gate of the selected memory block and the source select gate is floated after a preset time. When the voltage of the source line is stabilized at the first erase voltage, the voltage of the source select gate is stabilized at a second voltage, the second voltage is lower than the first erase voltage, and a difference between the first erase voltage and the second voltage constitutes a second effective erase voltage.

[0181] The longer the preset time is, the greater the voltage value of the second effective erase voltage is.

[0182] In some embodiments, the method further comprises:

[0183] When a result of the first erasure verification fails and a result of the second erasure verification succeeds, determining the preset duration to be a first duration;

[0184] When a result of the second erasure verification fails and a result of the third erasure verification succeeds, determining the preset duration to be a second duration;

[0185] When the result of the third erasure verification fails, determining the preset time length as a third time length;

[0186] The first duration is shorter than the second duration, and the second duration is shorter than the third duration.

[0187] In some embodiments, the memory block includes a drain terminal and a source terminal, the source terminal is provided with a source line; the memory block includes a plurality of word lines located between the drain terminal and the source terminal; the method further includes:

[0188] Applying a second erase voltage to the source line of the selected memory block and applying a first voltage to all word lines of the selected memory block, wherein the difference between the second erase voltage and the first voltage constitutes the second effective erase voltage;

[0189] The greater the voltage value of the second erase voltage is, the greater the voltage value of the second effective erase voltage is.

[0190] In some embodiments, the method further comprises: performing an erase operation on the selected memory block by applying a gradually increasing effective erase voltage multiple times;

[0191] After applying the effective erase voltage each time for a preset number of times, directly applying the third erase verification voltage to the selected memory block, and determining the effective erase voltage to be applied to the selected memory block next time according to the result of the erase verification corresponding to the third erase verification voltage;

[0192] After each application of the effective erase voltage exceeds the preset number of times, the multiple different erase verification voltages are applied to the selected storage block, and the next effective erase voltage to be applied to the selected storage block is determined based on the results of the multiple erase verifications corresponding to the multiple different erase verification voltages.

[0193] In another aspect, embodiments of the present disclosure further disclose a memory system, wherein the memory system includes a memory controller and the memory device described in the above embodiments of the present disclosure. The memory controller is configured to control the memory device to perform read, write, and erase operations. The memory controller and the memory device may be coupled in any suitable manner. In embodiments of the present disclosure, the memory device may be a semiconductor memory for storing non-volatile data, such as a NAND memory. The memory system is connected to a host, which may be an electronic device such as a personal computer or a mobile terminal.

[0194] In some embodiments, the memory system includes a universal flash storage (UFS) device or a solid-state drive (SSD).

[0195] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0196] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0197] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A memory device, comprising: A memory cell array, the memory cell array comprising a plurality of memory blocks; as well as A peripheral circuit is coupled to the memory cell array and is configured to: After applying a first effective erase voltage to a selected memory block among the plurality of memory blocks, applying a plurality of different erase verification voltages to the selected memory block; According to the results of multiple erasure verifications corresponding to the multiple different erasure verification voltages, a second effective erasure voltage applied to the selected memory block is determined, and the second effective erasure voltage is greater than the first effective erasure voltage.

2. The memory device according to claim 1, wherein: The multiple different erase verification voltages include three different erase verification voltages, and the multiple erase verification results include three erase verification results.

3. The memory device according to claim 2, wherein: The three different erase verification voltages include: a first erase verification voltage, a second erase verification voltage, and a third erase verification voltage whose voltage values ​​increase in sequence; the first erase verification voltage, the second erase verification voltage, and the third erase verification voltage correspond to the result of the first erase verification, the result of the second erase verification, and the result of the third erase verification, respectively; The peripheral circuit is further configured as: When the result of the first erasure verification fails and the result of the second erasure verification succeeds, determining that the voltage value of the second effective erasure voltage is increased by a first voltage increment compared to the voltage value of the first effective erasure voltage; When the result of the second erasure verification fails and the result of the third erasure verification succeeds, determining that the voltage value of the second effective erasure voltage is increased by a second voltage increment compared with the voltage value of the first effective erasure voltage; When the result of the third erasure verification fails, determining that the voltage value of the second effective erasure voltage is increased by a third voltage increment compared with the voltage value of the first effective erasure voltage; The third voltage increment is greater than the second voltage increment, and the second voltage increment is greater than the first voltage increment.

4. The memory device according to claim 3, wherein: The storage block includes a drain terminal and a source terminal, and the source terminal is provided with a source line and a source selection gate; The peripheral circuit is further configured as: A pulse corresponding to a first erasing voltage is applied to the source line of the selected memory block, and in the process of the voltage of the source line rising to the first erasing voltage, a first voltage is applied to the source selection gate of the selected memory block and the source selection gate is floated after a preset time, and in the process of the voltage of the source line being stabilized at the first erasing voltage, the voltage of the source selection gate is stabilized at a second voltage, the second voltage is less than the first erasing voltage, and the difference between the first erasing voltage and the second voltage constitutes the second effective erasing voltage; The longer the preset time is, the greater the voltage value of the second effective erasing voltage is.

5. The memory device according to claim 4, wherein: The peripheral circuit is further configured as: When a result of the first erasure verification fails and a result of the second erasure verification succeeds, determining the preset time length to be a first time length; When a result of the second erasure verification fails and a result of the third erasure verification succeeds, determining the preset time length to be a second time length; When the result of the third erasure verification fails, determining the preset time length as a third time length; The first duration is shorter than the second duration, and the second duration is shorter than the third duration.

6. The memory device according to claim 4, wherein: The selected storage block includes a plurality of storage blocks; The peripheral circuit is configured as: A pulse corresponding to a first erasing voltage is simultaneously applied to the source line of each of the selected plurality of memory blocks.

7. The memory device according to claim 6, wherein: The storage cell array comprises a plurality of storage planes; the selected plurality of storage blocks are respectively stored in different storage planes; The peripheral circuit is further configured as: When performing an erase operation on a plurality of storage blocks selected from a plurality of storage planes, different second effective erase voltages are applied to a plurality of storage blocks selected from different storage planes by changing the preset time lengths.

8. The memory device according to claim 3, wherein: The storage block includes a drain terminal and a source terminal, and the source terminal is provided with a source line; the storage block includes a plurality of word lines located between the drain terminal and the source terminal; The peripheral circuit is further configured as: Applying a second erasing voltage to the source line of the selected memory block, and applying a first voltage to all word lines of the selected memory block, wherein the difference between the second erasing voltage and the first voltage constitutes the second effective erasing voltage; The greater the voltage value of the second erase voltage is, the greater the voltage value of the second effective erase voltage is.

9. The memory device according to claim 4 or 8, wherein: The first voltage is a ground voltage.

10. The memory device according to claim 3, wherein: The peripheral circuit is further configured as: performing an erase operation on the selected memory block by applying a gradually increasing effective erase voltage multiple times; After applying the effective erase voltage each time in a preset number of times, directly applying the third erase verification voltage to the selected memory block, and determining the effective erase voltage to be applied to the selected memory block next time according to the result of the erase verification corresponding to the third erase verification voltage; After each application of the effective erase voltage exceeds the preset number of times, the multiple different erase verification voltages are applied to the selected storage block, and the next effective erase voltage to be applied to the selected storage block is determined based on the results of the multiple erase verifications corresponding to the multiple different erase verification voltages.

11. The memory device according to claim 3, wherein: The peripheral circuit is further configured as: When the result of the first erasure verification fails, applying the second erasure verification voltage to the selected memory block; When the result of the second erasure verification fails, the third erasure verification voltage is applied to the selected memory block.

12. The memory device according to claim 3, wherein: The first voltage is increased to a step voltage.

13. A memory system comprising: One or more memory devices as claimed in any one of claims 1 to 12; as well as A memory controller is coupled to the memory device and controls the memory device.

14. A method for operating a memory device, the method comprising: After applying a first effective erase voltage to a selected memory block of the memory device, applying a plurality of different erase verification voltages to the selected memory block; According to the results of multiple erasure verifications corresponding to the multiple different erasure verification voltages, a second effective erasure voltage applied to the selected memory block is determined, and the second effective erasure voltage is greater than the first effective erasure voltage.

15. The operating method according to claim 14, wherein: The multiple different erase verification voltages include three different erase verification voltages, and the multiple erase verification results include three erase verification results.

16. The operating method according to claim 15, wherein: The three different erase verification voltages include: a first erase verification voltage, a second erase verification voltage, and a third erase verification voltage whose voltage values ​​increase in sequence; the first erase verification voltage, the second erase verification voltage, and the third erase verification voltage correspond to the result of the first erase verification, the result of the second erase verification, and the result of the third erase verification, respectively; the method further includes: When the result of the first erasure verification fails and the result of the second erasure verification succeeds, determining that the voltage value of the second effective erasure voltage is increased by a first voltage increment compared to the voltage value of the first effective erasure voltage; When the result of the second erasure verification fails and the result of the third erasure verification succeeds, determining that the voltage value of the second effective erasure voltage is increased by a second voltage increment compared with the voltage value of the first effective erasure voltage; When the result of the third erasure verification fails, determining that the voltage value of the second effective erasure voltage is increased by a third voltage increment compared with the voltage value of the first effective erasure voltage; The third voltage increment is greater than the second voltage increment, and the second voltage increment is greater than the first voltage increment.

17. The operating method according to claim 16, wherein: The storage block includes a drain terminal and a source terminal, and the source terminal is provided with a source line and a source selection gate; The method further comprises: A pulse corresponding to a first erasing voltage is applied to the source line of the selected memory block, and in the process of the voltage of the source line rising to the first erasing voltage, a first voltage is applied to the source selection gate of the selected memory block and the source selection gate is floated after a preset time, and in the process of the voltage of the source line being stabilized at the first erasing voltage, the voltage of the source selection gate is stabilized at a second voltage, the second voltage is less than the first erasing voltage, and the difference between the first erasing voltage and the second voltage constitutes the second effective erasing voltage; The longer the preset time is, the greater the voltage value of the second effective erasing voltage is.

18. The operating method according to claim 17, wherein: The method further comprises: When a result of the first erasure verification fails and a result of the second erasure verification succeeds, determining the preset time length to be a first time length; When a result of the second erasure verification fails and a result of the third erasure verification succeeds, determining the preset time length to be a second time length; When the result of the third erasure verification fails, determining the preset time length as a third time length; The first duration is shorter than the second duration, and the second duration is shorter than the third duration.

19. The operating method according to claim 16, wherein: The storage block includes a drain terminal and a source terminal, and the source terminal is provided with a source line; the storage block includes a plurality of word lines located between the drain terminal and the source terminal; The method further comprises: Applying a second erasing voltage to the source line of the selected memory block, and applying a first voltage to all word lines of the selected memory block, wherein the difference between the second erasing voltage and the first voltage constitutes the second effective erasing voltage; The greater the voltage value of the second erase voltage is, the greater the voltage value of the second effective erase voltage is.

20. The operating method according to claim 16, wherein: The method further comprises: performing an erase operation on the selected memory block by applying a gradually increasing effective erase voltage multiple times; After applying the effective erase voltage each time in a preset number of times, directly applying the third erase verification voltage to the selected memory block, and determining the effective erase voltage to be applied to the selected memory block next time according to the result of the erase verification corresponding to the third erase verification voltage; After each application of the effective erase voltage exceeds the preset number of times, the multiple different erase verification voltages are applied to the selected storage block, and the next effective erase voltage to be applied to the selected storage block is determined based on the results of the multiple erase verifications corresponding to the multiple different erase verification voltages.

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