Vertical power device with mesas and etched trenches therebetween

Abstract

The invention discloses a vertical semiconductor and a manufacturing method thereof. In one embodiment, fabrication entails providing a precursor comprising a substrate and a drift region over the substrate. The plurality of trenches are etched into the drift region from a top surface of the drift region such that the plurality of mesas remain in an upper portion of the drift region. The plurality of trenches are then filled with a first material. The vertical semiconductor device includes a plurality of mesas extending from an upper portion of a drift region, wherein there is no regrowth interface between the drift region and the plurality of mesas. A first material fills the trenches between each of the plurality of mesas. And at least one first contact portion over at least one of the plurality of mesas. And at least one second contact over the bottom surface of the substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. application serial number 17 / 744,604, filed on May 13, 2022, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to vertical field effect devices with improved performance and efficient manufacturing techniques for making the devices. Background Art

[0003] There are several categories of vertical semiconductor devices, each of which can be used for different applications. One notable use of vertical semiconductor devices is for high power applications. In particular, devices such as PiN diodes, Schottky diodes, metal oxide semiconductor field effect transistors (MOSFETs), junction field effect transistors (JFETs), etc. can be rated for high blocking voltages and on-state currents, and are therefore often used in these power applications. In view of the increasing pressure to provide higher performance devices at lower costs, there is a continuing need for new device structures and manufacturing techniques that result in higher performance, lower cost, or both. Summary of the invention

[0004] A vertical semiconductor and a method for manufacturing the same are disclosed. In one embodiment, the manufacturing first requires providing a precursor, which includes a substrate and a drift region above the substrate, wherein the substrate and the drift region are doped with a first type of dopant and are formed by a first material system. A plurality of grooves are etched into the drift region from the top surface of the drift region so that a plurality of mesas remain in the upper portion of the drift region. The plurality of grooves are then filled with a first material doped with a second type of dopant opposite in polarity to the first type. At least one first contact is provided above at least one of the plurality of mesas, and at least one second contact is provided above the bottom surface of the substrate.

[0005] In another embodiment, a vertical semiconductor device includes a substrate and a drift region above the substrate. The substrate and the drift region are doped with a first type of dopant and are formed of a first material system. A plurality of mesas extend from an upper portion of the drift region, wherein no regrown interface exists between the drift region and the plurality of mesas. A first material doped with a second type of dopant fills a trench between each of the plurality of mesas, and the second type is opposite in polarity to the first type. At least one first contact is formed above at least one of the plurality of mesas. At least one second contact is formed above a bottom surface of the substrate.

[0006] The first material system may be silicon carbide, and the first material may be silicon carbide, silicon, or a metal. During fabrication, the step of filling the plurality of trenches may include providing a first layer of the first material over a top surface of the drift region such that the plurality of trenches are filled and the plurality of mesas are covered; and planarizing the first layer to expose the plurality of mesas.

[0007] The vertical semiconductor device may be a transistor or a diode. For a transistor, the remaining portion of the first layer filling the plurality of trenches forms a plurality of gate regions, at least one first contact is a source contact, and at least one second contact is a drain contact. After planarizing the first layer, at least one gate contact is provided over at least a portion of the gate layer.

[0008] In some embodiments, the at least one gate contact is not provided over the at least one gate region, wherein in other embodiments the at least one gate contact comprises a plurality of gate contacts, each gate contact being provided over a corresponding gate region of the plurality of gate regions.

[0009] In certain embodiments, after planarizing the first layer, a second layer is formed from the first material system over a remaining portion of the first layer and the plurality of mesas, wherein at least one first contact is provided over a portion of the first layer.

[0010] The drift region and the plurality of mesas may be continuously grown such that no regrown interface exists between the drift region and the plurality of mesas. In addition, in some embodiments, the first type of dopant may be an N-type dopant and the second type of dopant may be a P-type dopant, while in other embodiments the opposite is true.

[0011] In one embodiment, each of the plurality of mesas is an elongated strip such that one of the plurality of grooves is provided between adjacent pairs of the plurality of mesas. Alternatively, each of the plurality of mesas may be a pillar having a horizontal cross-section of nearly any shape, such as circular, square, rectangular, polygonal, etc.

[0012] The drift region may have a plurality of regions with different doping concentrations. Each of the plurality of mesas may have a plurality of regions with different doping concentrations. One or more of the plurality of mesas or drift regions may have at least one region with a graded doping profile. The drift region may have at least one charge propagation layer below the plurality of mesas, and at least one drift layer.

[0013] In one embodiment, the doping concentration of the second type of the first material is at least twice the doping concentration of the first type in the plurality of mesas.

[0014] In one embodiment, the width of each of the plurality of mesas at its narrowest portion is between one and two times the height of each of the plurality of mesas.

[0015] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are incorporated into and constitute a part of this specification, illustrate several aspects of the present disclosure and, together with the present description, are used to explain the principles of the present disclosure. For simplicity and readability, these figures identify exemplary doping polarities or types (N-type and P-type) of various layers, regions and / or portions of vertical semiconductor devices. In alternative embodiments, these polarities or types may be reversed.

[0017] 1A and 1B are a cross-sectional view and a top view of a junction field effect transistor (JFET) according to a first related art.

[0018] Figure 2 is a cross-sectional view of a transistor according to a second related art.

[0019] Figures 3A-3F A portion of a first exemplary manufacturing process according to one embodiment of the present disclosure is illustrated.

[0020] Figures 4A-4C A portion of a second exemplary manufacturing process according to one embodiment of the present disclosure is illustrated.

[0021] Figure 5 is a cross-section of a JFET according to one embodiment of the present disclosure.

[0022] Figure 6 is a JFET according to one embodiment of the present disclosure.

[0023] Figures 7A-7K A portion of a first exemplary manufacturing process according to one embodiment of the present disclosure is illustrated.

[0024] Figures 8A-8C A portion of a first exemplary manufacturing process according to one embodiment of the present disclosure is illustrated.

[0025] Figures 9A-9K A portion of a first exemplary manufacturing process according to one embodiment of the present disclosure is illustrated.

[0026] Fig.10 is a cross-section of a JFET according to one embodiment of the present disclosure.

[0027] Fig.11 is a cross-section of a JFET according to one embodiment of the present disclosure.

[0028] Fig.12 is a cross-section of a vertical diode according to one embodiment of the present disclosure.

[0029] Fig.13 is a cross-section of a vertical diode according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] The embodiments set forth below represent the information necessary to enable those skilled in the art to practice the embodiments and illustrate the best way to practice the embodiments. When reading the following description in consideration of the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and will recognize the applications of these concepts not specifically discussed herein. These concepts and applications fall within the scope of the present disclosure and the appended claims.

[0031] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present disclosure. As used herein, the term "and / or" includes all combinations of one or more of the listed related items.

[0032] It will be understood that when an element (such as a layer, area or substrate) is referred to as being "on" or "extending to" another element "on", it can be directly on or directly extended to another element, or there can also be an intermediate element. Conversely, when an element is referred to as being "directly on" or "directly extending to" another element "on", there are no intermediate elements. Similarly, it will be understood that when an element (such as a layer, area or substrate) is referred to as being "above" or "extending to" another element "above", it can be directly above or directly extended to another element, or there can also be an intermediate element. Conversely, when an element is referred to as being "directly on" or "extending to" another element "above", there are no intermediate elements. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to another element, or there can be an intermediate element. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intermediate elements.

[0033] Relative terms such as "below," "above," "upper," "lower," "horizontal," or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region, as illustrated in the figures. It will be understood that these terms, as well as the terms discussed above, are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0034] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a, an" and "the" are intended to also include plural forms. It will be further understood that the terms "include", "include", "include" and / or "include" specify the presence of the features, wholes, steps, operations, elements or components when used herein, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components or groups thereof.

[0035] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the related art, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein. The following nomenclature is used to refer to doping concentrations: aEb cm-3, which means a×10 b cm-3, and cm is centimeters. For example, 5E16 cm -3 Equal to 5x10 16 cm -3 , where a is 5 and b is 16. For simplicity and readability, these figures identify exemplary doping polarities or types (N-type and P-type) of various layers, regions and / or portions of vertical semiconductor devices. In alternative embodiments, these polarities or types may be reversed.

[0036] The present disclosure relates to vertical semiconductor devices, such as transistors, diodes, etc., and manufacturing techniques for constructing these devices. In one embodiment, manufacturing requires initially providing a precursor, which includes a substrate and a drift region above the substrate, wherein the substrate and the drift region are doped with a first type of dopant and are formed by a first material system. A plurality of grooves are etched into the drift region from the top surface of the drift region so that a plurality of mesas remain in the upper portion of the drift region. The plurality of grooves are then filled with a first material doped with a second type of dopant opposite in polarity to the first type. At least one first contact is provided above at least one of the plurality of mesas, and at least one second contact is provided above the bottom surface of the substrate.

[0037] In another embodiment, a vertical semiconductor device includes a substrate and a drift region above the substrate. The substrate and the drift region are doped with a first type of dopant and are formed by a first material system. A plurality of mesas extend from an upper portion of the drift region, wherein no regrown interface exists between the drift region and the plurality of mesas. A first material doped with a second type of dopant fills a trench between each of the plurality of mesas, and the second type is opposite in polarity to the first type. At least one first contact is formed above at least one of the plurality of mesas. At least one second contact is formed above the bottom surface of the substrate. The first material system may be silicon carbide, and the first material may be silicon carbide, silicon, or a metal.

[0038] Details for these manufacturing techniques and device structures are provided below. A specific example of a junction field effect transistor (JFET) is described; however, as will be appreciated by those skilled in the art, the concepts provided are applicable to other implant regions of other types of transistors (such as MOSFETs and IGBTs), as well as to junction barrier Schottky (JBS), merged PiN Schottky (MPS), and similar diodes by modifying the contact structure and placement. The relevant figures for the following relate to strip-shaped device structures extending into the plane of the drawing, but the layout is not limited to such structures. The surface layout can be strips, rectangles, circles, polygons, etc.

[0039] Fig. 1A illustrates a cross-sectional view of a junction field effect transistor (JFET) 10A of the related art. JFET 10A is a vertical JFET because, based on the voltage applied at the gate (G), current flows vertically through the device between the source (S) and the drain (D). In the illustrated embodiment, JFET 10A includes a substrate 12, a drift region 14 above the substrate 12, and a channel region 16 above the drift region 14. The upper portion of the body of JFET 10A is etched to form a mesa 18. A gate region 20 is formed on the opposite side of the mesa 18 and extends downward and outward along the upper portion of the JFET 10A body. Therefore, the channel region 16 resides between the gate regions 20 in the mesa 18 and between the bottom of the corresponding gate region 20 and the top of the drift region 14.

[0040] An ohmic region 22 is formed in the top of the mesa 18, with a source contact 24 provided on top of the ohmic region 22. Gate contacts 26 are formed on the recessed portions residing on either side of the mesa 18. The gate contacts 26 reside over the horizontal portions of the respective gate regions 20. A drain contact 28 resides along the bottom of the substrate 12.

[0041] As illustrated, the body of the JFET 10A is silicon carbide (SiC); however, other semiconductor material systems, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (Ga2O3), and diamond are also suitable. The substrate 12, drift region 14, channel region 16, and gate region 20 can be SiC, each of which is formed by implanting N-type or P-type dopants at varying locations and concentrations within the body of the JFET 10A. In the illustrated example, the substrate 12 is moderately doped with N-type dopants, the drift region 14 is moderately doped with N-type dopants, the channel region 16 is moderately doped with N-type dopants, the gate region 20 is heavily doped with P-type dopants, and the ohmic region 22 is heavily doped with N-type dopants. As will be appreciated by those skilled in the art, the actual and relative doping levels of each region of the JFET 10A will depend on the desired characteristics of the JFET 10A and may vary from application to application. The polarity of doping of each region may be opposite to that illustrated in the following embodiments.The source, gate and drain contacts 24, 26, 28 may be formed of a suitable metal or other highly conductive material.

[0042] The vertical portion of the mesa 18 residing between the gate regions 20 provides the JFET conductive gap CG. The illustrated portion is a cross section of a complete repeating unit in a larger device including many units, which are strip-shaped in the Z direction (into the figure). The mesa 18 is formed by an etching process, and the gate region 20 is formed using angled implants with different orientations. In the illustrated example, the implantation is provided at four different angles. Thus, the manufacture of this embodiment is a complex process, and the more complex the process, the more expensive the device is to manufacture. For more complex situations, the amount of P-type dopant along the side of the mesa 18 necessary to form the gate region 20 is a function of the sidewall angle of the mesa 18. Angled implants with four incident directions are performed to achieve a P+ type gate region 20, which generally surrounds each strip of the N-type channel region 16 within the mesa 18. Thus, etching control for forming the mesa 18 is a critical, complex and relatively expensive process.

[0043] Figure 1Bis a cross-sectional SEM image of the device showing the gate contact 26 and source fingers S extending in the z-direction. Further information may be found in Kiran Chatty, David C Sheridan, Volodymyr Bondarenko, Robin Schrader, and Jeffrey B Casady, “900V, 1.46mOhm-cm2 4H-SiC Depletion Mode Vertical JFET,” Materials Science Forum, Vol. 740-742, pp. 915-920 (2013), which is incorporated herein by reference in its entirety.

[0044] Figure 2 Another JFET structure 10B of the related art is illustrated, which includes a P+ type gate stripe 30 buried in an N-type drift region 32. The drift region 32 resides above an N+ type SiC substrate 34, which includes a drain contact 36 on its bottom. The gate stripe 30 is created by forming a P-type layer (not shown) and etching the layer to leave the illustrated gate stripe 30. Subsequently, the trenches between the gate stripes 30 are filled with N-type material to provide an N-type material layer above the gate stripes 30, thereby forming the remaining portion (i.e., the upper portion) of the drift region 32, so that the gate stripe 30 is buried in the drift region 32. The upper portion of the drift region 32 between the gate stripes 30 is a channel region. A disadvantage of this type of process is that the channel region and the drift region 32 that carry current for the JFET 10B are not grown continuously. Whenever current has to flow across an interface where the growth process has stopped and then started again, inefficiencies arise due to the disruption of the lattice structure at the interface between the two regions.

[0045] An ohmic contact 38 is formed in the upper portion of the layer where the source contact 40 resides. A gate contact 42 is connected to the gate region 30A formed by the gate strips 30 so that each gate region 30A or gate strip 30 is connected. Long gate strips can lead to high resistance and slow switching speeds, and a portion of the drift region 32 is formed by epitaxial regrowth after etching. Unfortunately, the drift region 32 is a critical semiconductor portion that carries all device current and should be as defect-free as possible to optimize performance. Further information can be found in the following document: Yasunori Tanaka, Koji Yano, Mitsuo Okamoto, Akio Takatsuka, Kazuo Arai and Tsutomu Yatsuo, "1270V, 1.21mΩ·cm2SiC Buried Gate Static Induction Transistors (SiC-BGSITs)", Materials Science Forum, Vol. 600-603, pp. 1071-1074 (2009), which is incorporated herein by reference in its entirety. As provided in the following embodiments, improvements to the related art are provided by forming a channel region in the original epitaxial layer to avoid the defects inherent in the regrowth process.

[0046] Figures 3A to 3F A first exemplary process for manufacturing a vertical semiconductor device according to an embodiment of the present disclosure is illustrated. Initially, as Figure 3A As shown, a precursor 50 is provided. The precursor 50 may be a continuously grown SiC or the like having a substrate 52 moderately doped (N+) with an N-type dopant, a drift region 54 moderately doped (N) with an N-type dopant over the substrate, and an ohmic layer 56 heavily doped (N+) with an N-type dopant over the drift region 54. The ohmic layer 56 may be grown continuously with the precursor 50 as described above, or may be grown as a separate epitaxial layer.

[0047] Next, trenches 58 are etched into the top surface of precursor 50, wherein trenches 58 are located in a region where gate regions 64 ( Figure 3D and 3E ) position, such as Figure 3B The unetched portion of the precursor 50 between the trenches 58 is referred to as a mesa 60. Each mesa 60 provides a channel region 62 and an ohmic region 64 above the channel region 62. The ohmic region 64 of each mesa 60 is formed by the unetched portion of the ohmic layer 56, and each channel region 62 is formed by the unetched portion of the drift region 54.

[0048] like Figure 3CAs shown, once the trench 58 is formed, a gate layer 66 is formed in the trench 58 and above the top of the ohmic region 64 of the mesa 60. The gate layer 66 is doped with a P-type dopant. In the illustrated embodiment, the gate layer 66 is P-type silicon carbide; however, P-type silicon or a suitable P-type conductor, such as nickel oxide, may also be used. For P-type silicon, it is not necessary to use an epitaxial film. The trench 58 can be simply filled with P-type silicon by chemical vapor deposition or other similar film deposition methods. Other materials for the gate layer and / or gate region 68 include any other P-type material that is chemically compatible with SiC. At this point, if necessary, the gate layer 66 is then planarized using an etching process or the like to remove the upper portion of the gate layer 66 extending above the top surface of the mesa 60 so that the ohmic region 64 is exposed, such as Figure 3D The remaining portion of gate layer 66 filling trench 58 provides a gate region 68 .

[0049] After planarization, a gate contact 70 is formed on top of each gate region 68, and a source contact 72 is formed on the ohmic region 64 above the channel region 62 of each mesa 60, as shown in FIG. Figure 3E If drain contact 74 is not already provided on precursor 50, drain contact 74 is now formed on the bottom of substrate 52. In one embodiment, mesa 60, channel region 62, gate region 68, source contact 72 and gate contact 70 are extended to Figure 3E These features can take on a variety of shapes, as will be described further below.

[0050] exist Figure 3F An alternative process for forming source contact 72 is provided in FIG. Figure 3D The process is still the same as the above process. Thus, a gate contact 70 is formed on top of each gate region 68, but the source contact 72 is not formed as a strip at this time. Instead, a dielectric 83, such as a suitable gate oxide 83, is formed over the gate contact 70 so that the ohmic region 64 over the channel region 62 remains exposed. Then, a metal or other conductive material is formed on top of the precursor 50 to form a unified source contact 72', which covers the dielectric 83 and the ohmic region 64, so that the unified source contact 72' is in electrical contact with the ohmic region 64 and is electrically isolated from the gate contact 70.

[0051] For these embodiments, it is not necessary to Figure 1B The angled implant required for the JFET 10A and the use of trench etching in the N-type SiC of the precursor 50, rather than as for Figure 2The current is therefore carried through the continuously grown N-type epitaxial channel region 62 and drift region 54, rather than through the P-type layer as is done for the JFET of FIG. Figure 2 The JFET 10B requires a regrown epitaxial structure.

[0052] In selected embodiments, the substrate 52 is heavily doped with an N-type dopant at an exemplary concentration in the range of 1E18 to 1E19 cm-3; 1E19 to 1E20 cm-3; or 1E18 to 1E19 cm-3; and the drift region 54 is moderately doped with an N-type dopant at an exemplary concentration in the range of 1E15 to E16 cm-3; 1E16 to 2E17 cm-3; or 1E15 to 2E17 cm-3; and the channel region 62 is moderately doped with an N-type dopant at an exemplary concentration in the range of 1E15 to E16 cm-3; 1E16 to 2E17 cm-3; or 1E15 to 2E17 cm-3. The gate region 68 is heavily doped with P-type dopants at an exemplary concentration in the range of 5E16 to 1E18cm-3; 1E18 to 1E20cm-3; or 5E16 to 1E20cm-3; and the ohmic region 64 is heavily doped with N-type dopants at an exemplary concentration in the range of 1E18 to 1E19cm-3; 1E19 to 1E21cm-3; or 1E18 to 1E21.

[0053] In some embodiments, the doping concentration level of the gate region 68 is at least 1.5 times, 2 times, or 2.5 times the doping concentration level of the channel region 62, which is provided by the mesa 60 extending vertically upward from the top of the drift region 54. Generally, the doping of the gate region 68 should be high enough to allow the channel region 62 to be depleted under reverse bias conditions. The height of the mesa 60 (channel region 62) can be one to two times (1X-2X) the width of the mesa 60 (channel region 62). The width of the trench 58 can range from 0.5 microns to 5 microns, 0.75 microns to 4 microns, 1 micron to 3.5 microns, 1 micron to 4 microns, and 1.5 to 3.5 microns.

[0054] The concepts provided are particularly beneficial in power applications, which are defined as applications having a blocking voltage of more than 400V when reverse biased, being able to pass a current of more than 1A when forward biased, and / or having a power rating of at least 2 Watts.

[0055] These are merely exemplary doping levels and dimensions, wherein embodiments incorporating the inventive concepts described herein and within the scope of the following claims may fall anywhere within or outside the ranges listed above, depending on the desired performance parameters of the device. Unless otherwise stated, these exemplary doping concentrations apply to the following embodiments. Where gradient doping levels are discussed, the gradient doping profile may range from the lower end to the higher end of the range, and increase or decrease in concentration from the bottom to the top of a particular region.

[0056] Figures 4A to 4C Another embodiment is shown. Figures 3A to 3D The process is the same as in the example above, where the ohmic region 64 at the top of the mesa 60 is optional. Once the gate layer 66 is planarized to form the various gate regions 68, an isolation layer 79 is applied over a portion of the top surface of the precursor 50 using a deposition and etching process, etc. and an ohmic layer 80 is applied over the top surface of the isolation layer 79, such as Figure 4A As shown. The isolation layer 79 and the ohmic layer 80 cover the gate region 68 and a portion of the channel region 62 where one or more source contacts 82 will be applied. Then, one or more source contacts 82 are formed over the ohmic layer 80, as shown. Figure 4B In this step or in a separate step, the gate contact 84 may be formed directly over the exposed gate region 68G, as shown in FIG. Figure 4C As shown. The gate contact 84 makes ohmic contact with the P-type gate region 68G as an extension of the gate region 68, but does not make ohmic contact with the source contact 82. In other words, the metals of the corresponding source contact 82 and gate contact 84 are isolated from each other. The isolation layer 79 and the ohmic layer 80 can be formed as an integral layer with different N-type doping levels, or formed in separate steps.

[0057] In this embodiment, if Figure 4C As shown, the gate connector region 68G is formed vertically and intersects with various gate regions 68, which are elongated strips in this embodiment. A gate contact 84 resides above the gate connector region 68G, wherein there is no N-type material, such as an ohmic layer 80, between the gate contact 84 and the gate connector region 68G. The upper portion of the gate connector region 68G, or an additional layer above it, can be heavily doped (P-type) to provide an ohmic region, thereby facilitating electrical connection between the gate contact 84 and the gate connector region 68G. The gate region 68 can also be epitaxially grown with the rest of the precursor 50, or formed by deposited silicon or other P-type materials. This is possible because the P-type gate material does not carry the main device current.

[0058] For any of the embodiments described herein, any of the various regions and layers may have the same or different doping levels using uniform and / or gradient type doping profiles. Figure 5 Some of these concepts are illustrated, which may be provided individually or in combination. The drift region 54 may be divided into a plurality of layers 88, 90, wherein a charge propagation layer 86 may be provided near the upper portion of the drift region 54 and just below the mesa 60, such that the mesa 60 effectively extends from the charge propagation layer 86. One or more drift layers 88, 90 may be provided below the charge propagation layer 86. Each of these layers may have a uniform or gradient doping profile. In addition, in any of the doping combinations for the drift region 54, the channel region 62 may have a uniform or gradient doping profile 62P. These doping options provide designers with the ability to customize device electrical properties (such as on-state and off-state properties).

[0059] Figure 6 and Figures 7A-7J An embodiment is illustrated in which the N-type mesas 60 and channel regions 62 are in the form of columns, in contrast to the elongated strips of the previous embodiment. The columnar channel region 62 can be a horizontal cross-section of almost any shape (such as square, rectangular, circular, octagonal, hexagonal, triangular, etc.). This grid-like layout can reduce gate resistance by reducing the contact connection distance. As illustrated relative to the previous embodiment, this embodiment can provide a larger source contact 82 while reducing the layout challenges associated with having to work around numerous elongated gate contacts 84. The N-type isolation layer 79 and the ohmic layer 80 effectively isolate the source contact 82 from the gate region 68.

[0060] Figures 7A to 7K Picture shows Figure 6 The salient steps of an exemplary manufacturing process of an embodiment. Fig. 7A and 7B are top and side views of the precursor 50 after the etching step. In this embodiment, the mesas 60 have a square cross-section and are aligned in a grid pattern. Figure 7C and 7D 6 is a top view and a side view of the precursor 50 after the gate layer 66 (not shown) is planarized to form the gate region (s) 68. In this embodiment, there is a gate region 68G on the precursor that does not have a mesa 60 and is reserved for a gate contact 84 (not shown). It is worth noting that the portion of the gate region (s) 68 in the gate region 68G is integrally formed with and connected to those portions surrounding the mesa 60. The mesa 60 provides a channel region 62, wherein the upper portion of the mesa 60 is heavily doped to provide an ohmic contact 64.

[0061] Fig. 7E and 7F are top and side views of the precursor 50 after an isolation layer 79 is formed over the active area of ​​the device. Figure 7G and 7H 8 is a top view and a side view of the precursor 50 after an N-type ohmic layer 80 is provided over the isolation layer 79 so that the N-type isolation layer 79 and the ohmic layer 80 do not cover the gate region 68G. After the N-type ohmic layer 80 is provided, a source contact 82 is provided over the ohmic layer 80, and a gate contact 84 is provided over the gate region 68G, as shown in FIG. Figures 7I-7K As shown, the source contact 82 and the gate contact 84 are separated from each other. Fig. 8A , 8B and 8C illustrate a hexagonal cross section corresponding to Fig. 7A , 7C and a countertop of 7E.

[0062] For similar Figure 3F Source contact configuration for source contact configuration, refer to Figures 9A to 9K . Fig.9A and 9B are top and side views of the precursor 50 after the etching step. In this embodiment, the mesas 60 have a square cross-section and are aligned in a grid pattern. Fig. 9C and 9D 6 is a top view and a side view of the precursor 50 after the gate layer 66 (not shown) is planarized to form the gate region (s) 68. In this embodiment, there is a gate region 68G on the precursor that does not have a mesa 60 and is reserved for a gate contact 84 (not shown). It is worth noting that the portion of the gate region (s) 68 in the gate region 68G is integrally formed with and connected to those portions surrounding the mesa 60. The mesa 60 provides a channel region 62, wherein the upper portion of the mesa 60 is heavily doped to provide an ohmic contact 64.

[0063] Fig.9E and 9F are top and side views of the precursor 50 after a dielectric layer 83' is formed over the active area of ​​the device. Figure 9G and 9H 8 is a top view and a side view of the precursor 50 after forming an opening 85 in the dielectric layer 83 to expose the ohmic region 64 of the channel region 62. The dielectric layer 83 is formed or etched so as not to cover the gate region 68G. Figures 9I-9K As illustrated, source contact 82 is provided over dielectric layer 83 and into opening 85 to cover the exposed surface of ohmic layer 64. Gate contact 84 is provided over gate region 68G.

[0064] Embodiments such as those described above may have various doping profiles and additional layers, such as Figure 5 discussed. Fig.10 Such an embodiment is illustrated in . Note that there is a charge propagation layer 86 and drift layers 88, 90 in the drift region 54. Each of these layers as well as the mesa 60 or source region 62 may also have a gradient type doping profile. Fig.11 A variation is shown in which the mesa 60 / source region 62 is elongated, has a rectangular cross section, and the different regions are as shown above. Figure 5 , 6 and 10 are doped as described in connection with the above.

[0065] As described above, the concepts provided herein can be applied to various types of vertical semiconductor devices. Fig.12 and 13 Exemplary vertical diode structures are illustrated for vertical diodes 90A and 90B, respectively. The fundamental difference between the transistor device described above and vertical diodes 90A and 90B is the absence of a gate contact and the expansion of the source contact 92 and underlying active area. The details and structure of the precursor 50 are substantially the same.

[0066] Fig.12 The diode 90A provides a grid of mesas 60 for the source region 62, wherein the mesas 60 are formed using an etching process and the resulting trenches are filled with P-type material using a deposition or growth process to generate P regions 96 (i.e., gate regions). The trenches and resulting P regions 96 provide a cross-hatched pattern around most of the mesas 60.

[0067] Fig.13 The diode 90B of FIG. 9B further differs in that the mesas 60 are interconnected and form a cross-hatched pattern. The P regions 96 are formed in holes etched into the drift region 54 and filled with P-type material. These holes, and therefore the P regions 96, can take on almost any geometric shape, such as having a horizontal cross-section that is square, rectangular, circular, hexagonal, octagonal, triangular, etc. In this embodiment, the mesas 60 form a cross-hatched pattern that surrounds the individual P regions, as well as the majority of the unconnected P regions 96. The doping and additional layers provided in FIGS. 9 and 10 can be applied to Fig.12 and 13 Embodiment of the invention.

[0068] Those skilled in the art will recognize additional improvements and modifications to the disclosed embodiments of the present disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the following claims.

Claims

1. A method for manufacturing a vertical semiconductor device, comprising: providing a precursor, the precursor comprising a substrate and a drift region above the substrate, wherein the substrate and the drift region are doped with a first type of dopant; etching a plurality of trenches into the drift region from a top surface of the drift region such that a plurality of mesas remain in an upper portion of the drift region; filling the plurality of trenches with a first material doped with a second type of dopant opposite in polarity to the first type; providing at least one first contact over at least one of the plurality of mesas; as well as At least one second contact is provided over the bottom surface of the substrate. The method of claim 1 , wherein the drift region is silicon carbide. The method of claim 2 , wherein the first material is silicon carbide. The method of claim 3 , wherein the first material is silicon. The method of claim 4 , wherein the first material is a metal.

6. The method of claim 1 , wherein the step of filling the plurality of trenches comprises: providing a first layer of a first material over a top surface of the drift region such that the plurality of trenches are filled and the plurality of mesas are covered; as well as The first layer is planarized to expose the plurality of mesas.

7. A method according to claim 6, wherein the vertical semiconductor device is a transistor, the remaining portion of the first layer filling the plurality of trenches forms a plurality of gate regions, the at least one first contact is a source contact, and the at least one second contact is a drain contact; and the method further includes providing at least one gate contact above at least a portion of the first layer after planarizing the first layer. The method of claim 7 , wherein the at least one gate contact is not provided over the plurality of gate regions. 9 . The method of claim 7 , wherein the at least one gate contact comprises a plurality of gate contacts, each gate contact being provided over a corresponding gate region of the plurality of gate regions.

10. The method according to claim 6, further comprising: After planarizing the first layer, a second layer is provided over a remaining portion of the first layer and the plurality of mesas, wherein the at least one first contact is provided over a portion of the first layer. 11 . The method of claim 1 , wherein the drift region and the plurality of mesas are grown continuously such that no regrown interface exists between the drift region and the plurality of mesas. 12 . The method of claim 1 , wherein the first type of dopant is an N-type dopant and the second type of dopant is a P-type dopant.

13. The method of claim 1, wherein each of the plurality of mesas is an elongated strip such that one of the plurality of grooves is provided between adjacent pairs of the plurality of mesas. The method of claim 1 , wherein each of the plurality of mesas is a pillar.

15. The method of claim 14, wherein each of the pillars has a circular horizontal cross-section.

16. The method of claim 15, wherein each of the pillars has a square horizontal cross-section.

17. The method of claim 16, wherein each of the pillars has a polygonal horizontal cross-section. The method of claim 1 , wherein the drift region comprises a plurality of regions having different doping concentrations.

19. The method of claim 1, wherein each of the plurality of mesas has a plurality of regions having different doping concentrations.

20. The method of claim 1, wherein at least one of the plurality of mesas or the drift region has at least one region having a gradient type doping profile.

21. The method of claim 1, wherein the drift region comprises at least one charge propagation layer below the plurality of mesas, and at least one drift layer.

22. The method of claim 1, wherein the vertical semiconductor device is a diode.

23. The method of claim 1, wherein a doping concentration of the second type of the first material is at least twice a doping concentration of the first type in the plurality of mesas.

24. The method of claim 1, wherein a width at a narrowest portion of each of the plurality of mesas is between one and two times a height of each of the plurality of mesas.

25. The method of claim 1, wherein the substrate and the drift region comprise a first material system.

26. A vertical semiconductor device comprising: substrate; a drift region above the substrate, wherein the substrate and the drift region are doped with a first type of dopant; a plurality of mesas extending from an upper portion of the drift region, wherein no regrown interface exists between the drift region and the plurality of mesas; a first material doped with a second type of dopant and filling the trench between each of the plurality of mesas, the second type being opposite in polarity to the first type; at least one first contact over at least one of the plurality of mesas; as well as At least one second contact is over the bottom surface of the substrate.

27. The vertical semiconductor device of claim 26, wherein the drift region is silicon carbide.

28. The vertical semiconductor device of claim 27, wherein the first material is silicon carbide.

29. The vertical semiconductor device of claim 28, wherein the first material is silicon.

30. The vertical semiconductor device of claim 29, wherein the first material is a metal.

31. The vertical semiconductor device according to claim 26 further comprises a first layer of a first material filling a plurality of trenches, wherein the vertical semiconductor device is a transistor, the first material filling the plurality of trenches forms a plurality of gate regions, the at least one first contact is a source contact, and the at least one second contact is a drain contact; and the vertical semiconductor device further comprises at least one gate contact above at least a portion of the first layer. 32 . The vertical semiconductor device of claim 31 , wherein the at least one gate contact is not provided over the plurality of gate regions. 33 . The vertical semiconductor device of claim 31 , wherein the at least one gate contact comprises a plurality of gate contacts, each gate contact being provided over a corresponding gate region of the plurality of gate regions. 34 . The vertical semiconductor device of claim 26 , wherein the drift region and the plurality of mesas are continuously grown such that no regrown interface exists between the drift region and the plurality of mesas.

35. The vertical semiconductor device of claim 26, wherein the first type of dopant is an N-type dopant and the second type of dopant is a P-type dopant.

36. The vertical semiconductor device of claim 26, wherein each of the plurality of mesas is an elongated strip such that one of the plurality of trenches is provided between adjacent pairs of the plurality of mesas.

37. The vertical semiconductor device of claim 26, wherein each of the plurality of mesas is a pillar.

38. The vertical semiconductor device of claim 37, wherein each of the pillars has a circular horizontal cross-section.

39. The vertical semiconductor device of claim 38, wherein each of the pillars has a square horizontal cross-section.

40. The vertical semiconductor device of claim 39, wherein each of the pillars has a polygonal horizontal cross-section.

41. The vertical semiconductor device of claim 26, wherein the drift region comprises a plurality of regions having different doping concentrations.

42. The vertical semiconductor device of claim 26, wherein each of the plurality of mesas has a plurality of regions having different doping concentrations.

43. The vertical semiconductor device of claim 26, wherein at least one of the plurality of mesas or the drift region has at least one region having a gradient type doping profile.

44. The vertical semiconductor device of claim 26, wherein the drift region comprises at least one charge propagation layer below the plurality of mesas, and at least one drift layer.

45. The vertical semiconductor device of claim 26, wherein the vertical semiconductor device is a diode.

46. ​​The vertical semiconductor device of claim 26, wherein a doping concentration of the second type of the first material is at least twice a doping concentration of the first type in the plurality of mesas.

47. The vertical semiconductor device of claim 26, wherein a width at a narrowest portion of each of the plurality of mesas is between one and two times a height of each of the plurality of mesas.

48. The vertical semiconductor device of claim 26, wherein the substrate and the drift region comprise a first material system.

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