Semiconductor device and power conversion device

Abstract

Provided is a semiconductor device capable of suppressing a snapback phenomenon when an IGBT is turned on and hole injection from an IGBT region to a diode region when a diode is turned on by a simple structure in an RC-IGBT. In a semiconductor device having an IGBT region (21) and a diode region (22) in the same chip, the gate resistance (R) of the IGBT near the boundary portion between the IGBT region (21) and the diode region (22) is greater than the gate resistance of the IGBT near the center portion of the IGBT region (21).

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a power conversion device. Background Art

[0002] RC-IGBT (RC: Reverse-Conducting, reverse-conducting IGBT) with IGBT (Insulated Gate Bipolar Transistor) and diode built in the same chip can share the terminal area of ​​IGBT and diode, so it has the advantage of reducing chip size. In addition, since the timing of IGBT and diode operation is different, the heat caused by the loss in one of the IGBT area and the diode area is dispersed to the other, and since the heat can be dissipated by the entire chip, it also has the advantage of reducing thermal resistance.

[0003] On the other hand, the RC-IGBT has the following problem: when the IGBT is turned on, especially the electrons injected from the surface side of the IGBT near the boundary with the diode do not pass through the collector layer, i.e., the p-layer, on the back side of the IGBT, but pass through the cathode layer, i.e., the n+ layer, of the diode. If a voltage higher than the built-in voltage of the pn junction on the back side is not applied, hole injection from the p-layer on the back side will not occur, causing a snapback phenomenon when the IGBT is turned on.

[0004] In addition, the RC-IGBT has the following problem: when the IGBT is turned off and the potential of the surface electrode becomes higher than the potential of the back electrode and the diode is turned on, holes are also injected into the diode region, especially from the main layer, that is, the p-layer, on the surface side of the IGBT near the boundary with the diode. The concentration of holes in the drift layer near the boundary between the diode region and the IGBT region becomes high. Thereafter, when the potential of the surface electrode becomes lower than the potential of the back electrode and the diode performs a recovery action, the holes in the drift layer flow toward the surface electrode, thereby causing the recovery current to flow. However, since the concentration of holes becomes high near the boundary between the diode region and the IGBT region, the recovery current flows at a higher density near the boundary, placing a higher load on the semiconductor substrate, and holes are injected from the IGBT region into the diode region when the diode is turned on.

[0005] Here, Patent Document 1 describes the following semiconductor device: a semiconductor substrate includes an IGBT region overlapping with a collector region, a diode region overlapping with a cathode region, a drift region distributed from the IGBT region across the diode region, a body region, a body contact region, and an emitter region arranged in the IGBT region, an anode region and an anode contact region arranged in the diode region, the body region includes a first body region and a second body region having a lower p-type impurity concentration than the first body region and the anode region, the second body region is adjacent to the anode region, and the first body region is adjacent to the second body region on the side opposite to the anode region (Abstract, Figure 2 ).

[0006] According to the semiconductor device of Patent Document 1, the following technology is described, for example: since the p-type impurity concentration in the second body region adjacent to the anode region is low, when the diode is turned on, the number of holes flowing from the second body region toward the cathode region decreases, and the concentration of holes in the drift region near the boundary between the diode region and the IGBT region does not become so high. During the recovery action, the higher recovery current flowing near the boundary between the diode region and the IGBT region is suppressed, and the load applied to the semiconductor substrate can be reduced (paragraph 0007).

[0007] Thus, Patent Document 1 describes a structure for solving the problem of hole injection from the IGBT region to the diode region when the diode is turned on. In addition, although Patent Document 1 does not mention the problem of snapback when the IGBT is turned on, it is believed that the structure of Patent Document 1 can solve it.

[0008] Prior art literature

[0009] Patent Literature

[0010] Patent Document 1: Japanese Patent Application Publication No. 2019-106430 Summary of the invention

[0011] Problems to be solved by the invention

[0012] However, in Patent Document 1, in order to make the p-type impurity concentration of the main region of the IGBT near the boundary portion (the second main region of the IGBT adjacent to the anode region) lower than that of the main region of the IGBT near the central portion (the first main region of the IGBT), new photolithography processes and ion implantation processes are required, resulting in issues such as increased manufacturing costs.

[0013] Therefore, an object of the present invention is to provide a semiconductor device and a power conversion device that can suppress the snapback phenomenon when the IGBT is turned on and the injection of holes from the IGBT region to the diode region when the diode is turned on in an RC-IGBT with a simple structure.

[0014] Solutions to Solve Problems

[0015] In order to solve this problem, the semiconductor device of the present invention has an IGBT region and a diode region in the same chip, and the semiconductor device is characterized in that the gate resistance of the IGBT near the boundary between the IGBT region and the diode region is larger than the gate resistance of the IGBT near the center of the IGBT region.

[0016] Furthermore, a power conversion device according to the present invention is characterized by including, for example, the above-mentioned semiconductor device as a switching element.

[0017] Effects of the Invention

[0018] According to the present invention, by adopting a simple structure in which the gate resistance of the IGBT near the boundary portion is larger than that near the center portion, when the IGBT is turned on, the IGBT near the center portion, which is far from the boundary portion, is turned on earlier than the IGBT near the boundary portion. Therefore, the path from the electrons from the IGBT near the center portion flowing through the vicinity of the surface of the pn junction portion on the back side until reaching the cathode layer of the diode becomes longer. Therefore, during the period when the electrons flow through this length portion, a voltage drop occurs to become a forward bias. If the built-in voltage is exceeded, hole injection from the collector layer on the back side begins. Therefore, the snapback phenomenon when the IGBT is turned on can be suppressed.

[0019] In addition, by adopting a simple structure in which the gate resistance of the IGBT near the boundary portion is larger than that near the center portion, when the IGBT is turned off, the IGBT near the center portion, which is far away from the boundary portion, is turned off earlier than the IGBT near the boundary portion. The IGBT near the center portion that is turned off first has a smaller amount of hole injection from it due to its greater distance, and the IGBT near the boundary portion that is turned off slowly has a shorter time for hole injection, so the amount of hole injection from it can be reduced. Therefore, compared with the case where both are turned off at the same time, the hole injection from the IGBT region to the diode region when the diode is turned on can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a cross-sectional view illustrating a schematic structure of the semiconductor device according to the first embodiment.

[0021] Figure 2 It is a plan view for explaining the shape of the gate wiring of the semiconductor device of Example 1.

[0022] Figure 3 It is a plan view for explaining the shape of the gate wiring of the semiconductor device of the second embodiment.

[0023] Figure 4 This is the current-voltage characteristic that explains the snapback phenomenon in the RC-IGBT. DETAILED DESCRIPTION

[0024] Hereinafter, embodiments of the present invention will be described using the accompanying drawings. In each of the drawings and embodiments, the same or similar components are denoted by the same reference numerals, and repeated descriptions are omitted.

[0025] Example 1

[0026] Figure 1 This is a cross-sectional view illustrating a schematic structure of the semiconductor device according to the first embodiment.

[0027] The semiconductor device 100 of the first embodiment is an RC-IGBT, and includes an IGBT region 21 and a diode region 22 in the same chip (on the same semiconductor substrate).

[0028] An IGBT is formed in the IGBT region 21. The IGBT has, for example, a first conductivity type ( Figure 1 The drift layer 1 is an n-type layer in the embodiment of the present invention, a trench 3, a gate electrode 5 provided in the trench 3, and a second conductive type layer (n-type in the embodiment of the present invention) provided adjacent to the trench 3 on the surface side of the drift layer 1. Figure 1 The main body layer 2 is a p-type main body layer 2, an emitter layer 7 of a first conductivity type provided on the surface side of the main body layer 2, and a collector layer 11 of a second conductivity type provided on the back side of the drift layer 1.

[0029] In addition, Figure 1 In the example in which the first conductivity type is n-type and the second conductivity type is p-type, the present invention is not limited thereto, and the first conductivity type may be p-type and the second conductivity type may be n-type. In this case, the electrons and holes are opposite.

[0030] A diode is formed in the diode region 22 . The diode includes, for example, a drift layer 1 , a body layer 2 provided on the surface side of the drift layer 1 and functioning as a second conductivity type anode layer, and a first conductivity type cathode layer 12 provided on the back side of the drift layer 1 .

[0031] In addition, the semiconductor device 100 has a first conductive buffer layer 10 formed between the collector layer 11 or the cathode layer 12 and the drift layer 1, a surface electrode 13, an interlayer insulating film 9 arranged between the emitter layer 7 or the main layer 2 and the surface electrode 13, and a back electrode 14 in common in the IGBT region 21 and the diode region 22.

[0032] The surface electrode 13 is connected to the body layer 2 via the contact hole and the second conductivity type body contact layer 8 in the IGBT region 21 and the diode region 22. Therefore, the surface electrode 13 is at the emitter potential E and the anode potential A.

[0033] The gate electrode 5 is adjacent to the body layer 2 and the emitter layer 7 via the insulating film 4 formed in the trench 3. The gate electrode 5 is supplied with a gate potential G from a gate driving circuit (not shown) or the like.

[0034] The diode region 22 also has a trench 3, and an insulating film 4 and a dummy electrode 6 are provided in the trench 3 of the diode region 22. The dummy electrode 6 is supplied with, for example, an emitter potential E, but the present invention is not limited thereto and may be supplied with other potentials such as a gate potential.

[0035] Regarding the impurity concentration of each layer, for example, the impurity concentration of the drift layer 1 is a low concentration of n−, the impurity concentration of the emitter layer 7 is a high concentration of n+, and the impurity concentration of the cathode layer 12 is a high concentration of n+.

[0036] Here, the semiconductor device 100 of the first embodiment is characterized in that the gate resistance R of the IGBT near the boundary between the IGBT region 21 and the diode region 22 is larger than the gate resistance R of the IGBT near the center of the IGBT region 21 .

[0037] Through this simple structure, the timing at which the IGBT near the boundary portion is turned on is later than the timing at which the IGBT near the center portion is turned on. Therefore, as described later, the snapback phenomenon when the IGBT is turned on can be suppressed, and the timing at which the IGBT near the boundary portion is turned off is later than the timing at which the IGBT near the center portion is turned off. Therefore, as described later, the hole injection from the IGBT region to the diode region when the diode is turned on can be suppressed.

[0038] Figure 4 This is the current-voltage characteristic that explains the snapback phenomenon in the RC-IGBT.

[0039] exist Figure 4 In the figure, the horizontal axis is voltage V and the vertical axis is current I. Figure 4 In FIG. 1 , a characteristic 31 without snapback is indicated by a dotted line, and a characteristic 32 with snapback is indicated by a solid line.

[0040] IGBT usually has the characteristic 31 without snapback. If the pn junction on the back side (at Figure 1 When the p-type collector layer 11 and the n-type buffer layer 10 in the middle become above the built-in voltage, hole injection starts, the IGBT operation starts, and the current I rises in a curve with respect to the voltage V.

[0041] However, in the RC-IGBT, when the IGBT is turned on, initially, the pn junction on the back side is lower than the built-in voltage. Therefore, near the boundary between the IGBT region 21 and the diode region 22, the electrons 15 injected from the main body layer 2 on the surface side of the IGBT do not pass through the collector layer 11 on the back side of the IGBT, i.e., the p layer, but pass through the cathode layer 12 of the diode, i.e., the n+ layer. As shown in the characteristic 32 with snapback, the MOS operation in which the current I increases linearly with respect to the voltage V is initially performed. The reason for this is that the structure in which the p layer on the back side of the IGBT is set as the n+ layer is the same as the structure of the MOSFET (Metal Oxide Semiconductor Field Effect Transistor). After that, if the voltage applied to the pn junction on the back side rises and exceeds the built-in voltage, the IGBT operation starts. At this time, since the characteristic 31 without snapback is returned to be the same, the voltage V temporarily decreases as shown in the characteristic 32 with snapback. This phenomenon is called snapback phenomenon. When the snapback phenomenon occurs, there is a problem that the voltage during MOS operation becomes higher than the waveform during normal IGBT operation, and the loss becomes larger accordingly.

[0042] In contrast, in the semiconductor device 100 of the first embodiment, by making the gate resistance R of the IGBT near the boundary portion larger than that near the center portion, when the IGBT is turned on, the IGBT near the center portion, which is far from the boundary portion, is turned on earlier than the IGBT near the boundary portion. Figure 1 As shown, the path of the electrons 15 from the IGBT near the central portion flowing through the surface of the pn junction on the back side until reaching the cathode layer 12 of the diode becomes longer. Therefore, during the period when the electrons 15 flow through this length portion, a voltage drop occurs and becomes a positive bias. If the built-in voltage is exceeded, hole injection from the collector layer 11 on the back side begins, thereby being able to suppress the snapback phenomenon when the IGBT is turned on.

[0043] In addition, in the semiconductor device 100 of Example 1, by adopting a simple structure in which the gate resistance R of the IGBT near the boundary portion is larger than that near the center portion, when the IGBT is turned off, the IGBT near the center portion, which is far away from the boundary portion, is turned off earlier than the IGBT near the boundary portion. Since the IGBT near the center portion that is turned off first is farther away, the amount of hole injection from there is reduced. Since the time for hole injection to occur is shorter for the IGBT near the boundary portion that is turned off slowly, the amount of hole injection from there is reduced. Compared with the case where both IGBTs are turned off at the same time, the hole injection from the IGBT region 21 to the diode region 22 when the diode is turned on can be suppressed.

[0044] Next, a method for realizing the first embodiment of making the gate resistance R of the IGBT larger near the boundary portion than near the center portion will be described.

[0045] Figure 2 It is a plan view for explaining the shape of the gate wiring of the semiconductor device of Example 1.

[0046] like Figure 2 As shown, the gate wiring of the semiconductor device 100 of the first embodiment includes a gate common wiring 16 also called a gate finger, and a gate lead wiring 17 connecting the gate common wiring 16 and each gate electrode 5, and a gate potential G is supplied to the gate electrode 5 via the gate wiring. In addition, each virtual electrode 6 of the diode region 22 is connected by a virtual wiring 18, and an emitter potential E is supplied.

[0047] Furthermore, the gate lead line 17 of the IGBT near the boundary is thinner than the gate lead line 17 of the IGBT near the center. Thus, the gate resistance R of the IGBT near the boundary can be made larger than that near the center.

[0048] Here, it is desirable that the gate lead line 17 gradually becomes thicker as it moves from the vicinity of the boundary portion toward the vicinity of the center portion. Figure 2 , an example is shown in which the width of the gate lead line 17 increases as Wc<Wb<Wa from the vicinity of the boundary portion toward the vicinity of the center portion.

[0049] Thereby, the effect of Example 1 can be obtained more effectively.

[0050] Furthermore, since this can be achieved simply by changing the shape of the gate wiring, during manufacturing, only the shape of the mask used to pattern the gate wiring needs to be changed, and no new photolithography process or ion implantation process is required, thereby not increasing the manufacturing cost.

[0051] Example 2

[0052] Figure 3 It is a plan view for explaining the shape of the gate wiring of the semiconductor device of the second embodiment.

[0053] Example 2 is a modified example of Example 1, and is different from Example 1 in that the gate lead wiring 17 is connected to each other near the center by the gate lead wiring 17 for adjacent gate electrodes 5 to form an integral whole. In this case, the width of the gate lead wiring 17 corresponding to each gate electrode 5 is considered to be divided by the virtual gate lead wiring 17 up to the middle point between the adjacent gate electrodes 5, so it is considered that Figure 3 Thus, the gate resistance of the IGBT near the center can be made smaller than that of the first embodiment. Other aspects are the same as those of the first embodiment, and therefore, duplicate descriptions are omitted.

[0054] Example 3

[0055] Embodiment 3 is an embodiment of a power conversion device using the semiconductor device of Embodiment 1 or Embodiment 2 as a switching element. Since the structure of the power conversion device is the same as a general structure, detailed description is omitted.

[0056] Although the embodiments of the present invention have been described above, the present invention is not limited to the structures described in the embodiments, and various changes can be made within the scope of the technical concept of the present invention. In addition, part or all of the structures described in the embodiments can also be combined and applied.

[0057] Explanation of symbols

[0058] 1—drift layer, 2—body layer, 3—trench, 4—insulating film, 5—gate electrode, 6—dummy electrode, 7—emitter layer, 8—body contact layer, 9—interlayer insulating film, 10—buffer layer, 11—collector layer, 12—cathode layer, 13—surface electrode, 14—back electrode, 15—electrons, 16—gate common wiring, 17—gate lead wiring, 18—dummy wiring, 21—IGBT region, 22—diode region, 31—characteristics without snapback, 32—characteristics with snapback, 100—semiconductor device, G—gate potential, E—emitter potential, A—anode potential, R—resistance, I—current, V—voltage.

Claims

1. A semiconductor device having an IGBT region and a diode region in the same chip, wherein: The gate resistance of the IGBT near the boundary portion between the IGBT region and the diode region is larger than the gate resistance of the IGBT near the center portion of the IGBT region.

2. The semiconductor device according to claim 1, wherein: The timing at which the IGBT near the boundary portion is turned on is delayed compared to the timing at which the IGBT near the center portion is turned on.

3. The semiconductor device according to claim 1, wherein: The timing at which the IGBT near the boundary portion is turned off is delayed compared to the timing at which the IGBT near the center portion is turned off.

4. The semiconductor device according to claim 1, wherein: The gate lead-out wiring of the IGBT near the boundary portion is thinner than the gate lead-out wiring of the IGBT near the center portion.

5. The semiconductor device according to claim 4, wherein: The gate lead line gradually becomes thicker from the vicinity of the boundary portion toward the vicinity of the center portion.

6. The semiconductor device according to claim 1, wherein: The IGBT comprises a drift layer of a first conductivity type, a trench, a gate electrode provided in the trench, a body layer of a second conductivity type provided adjacent to the trench and on a surface side of the drift layer, an emitter layer of the first conductivity type provided on a surface side of the body layer, and a collector layer of the second conductivity type provided on a back side of the drift layer. The diode in the diode region includes the drift layer, the body layer provided on the surface side of the drift layer and functioning as an anode layer of the second conductivity type, and a cathode layer of the first conductivity type provided on the back side of the drift layer.

7. A power conversion device, characterized in that: A semiconductor device according to any one of claims 1 to 6 is provided as a switching element.

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