Phase shift modulated full bridge power inverter and method of operation thereof

Abstract

A phase shift modulation full-bridge power inverter includes: a leading bridge arm including: a first power switch having a first power switch parasitic capacitance; and a second power switch having a second power switch parasitic capacitance. The lagging bridge arm comprises a third power switch with a third power switch parasitic capacitor; and the fourth power switch is provided with a fourth power switch parasitic capacitor. Each of the power switches is turned on and off during a switching period. An enhanced passive circuit includes an inductor that combines with a third power switch parasitic capacitance and a fourth power switch capacitance to form a resonator when a first of the third and fourth power switches is off and a second of the third and fourth power switches is in an off state. Before the second one of the third power switch and the fourth power switch is turned on, the energy stored in the parasitic capacitance of the second one of the third power switch and the fourth power switch is released.

Description

Technical Field

[0001] The present invention relates generally to the field of power electronics and, more specifically, to wirelessly transmitting power. Aspects of the present invention relate to a phase-shift modulated full-bridge power inverter configured for a wireless power transmission system. Another aspect of the present invention relates to a method of operating a phase-shift modulated full-bridge power inverter in a wireless power transmission system. Another aspect of the present invention relates to a method of assembling an enhanced passive circuit to a phase-shift modulated full-bridge power inverter configured for a wireless power transmission system. Another aspect of the present invention relates to a set of enhanced passive circuit components for assembling to a phase-shift modulated full-bridge power inverter configured for a wireless power transmission system.

[0002] In this regard, it is worth noting that the term "enhanced passive circuit" is used in the sense that no active switches are required in the enhanced passive circuit.

[0003] One aspect of the present invention is particularly (but not exclusively) applicable to reducing power losses in power inverters. For example, the use of the techniques disclosed herein may allow a power inverter to enable all power switches in a wireless power transmission power inverter to be soft switched in all operating regions. The use of the techniques disclosed herein may allow zero voltage switching (ZVS) to be achieved in all power switches of a power inverter under all load conditions without coordinated control and communication with a receiver circuit. Background Art

[0004] Power electronic devices such as power metal oxide semiconductor field effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs) have been widely used for power conversion as switching speeds and power capabilities have increased. Recent advances in wide bandgap (WBG) semiconductor technology have further improved the switching frequency range and power rating of these power devices. Power converters based on power electronics can switch at frequencies of hundreds of kilohertz in commercial switched mode power supplies (SMPSs), and are being considered for switching at frequencies up to tens of megahertz in some emerging applications such as wireless power transfer (WPT).

[0005] The main limitation on switching frequency is the switching power loss in the power switch of the power converter. During the turn-on and turn-off process, the instantaneous voltage across the power switch and the current in the power switch vary with time. The instantaneous product of the instantaneous voltage and current leads to the switching power loss of this power switch. The switching power loss causes thermal losses and thermal stresses in the structure of the power switch. The large voltage change rate (dv / dt) and current change rate (di / dt) also lead to electromagnetic interference (EMI). Traditional switching methods that do not reduce switching power losses are called "hard switching" techniques. In the past two decades, "soft switching" methods have been developed and used in many power converters and power inverters. Soft switching methods generate zero voltage and / or zero current for the power switch during the turn-on and turn-off transients, which can ideally eliminate switching losses. Soft switching techniques can be classified as zero voltage switching (ZVS) and zero current switching (ZCS).

[0006] In the 1980s and 1990s, soft switching techniques for half-bridge and full-bridge power inverters under 50% duty cycle pulse width modulation (PWM) control were reported in several seminal papers [1]-[3]. Switching the inverter at an operating frequency that falls within the inductive region of the load impedance ensures ZVS under conditions where the load current is continuous. Under light load conditions, the load current becomes discontinuous and the ZVS condition is lost. This problem can be addressed by adding enhanced inductor-capacitor (LC) circuit branches across the load to maintain a minimum continuous current, thereby ensuring ZVS [4].

[0007] For a full-bridge power inverter under phase-shift modulation (PSM) control, discontinuous current occurs when the phase shift angle is large (e.g., greater than 150°). Adding an additional LC circuit branch cannot achieve ZVS. This well-known problem has been a major technical challenge, and despite several proposals in the past, no good solution has yet been found. A recent review paper [5] comprehensively introduces various forms of symmetrical PWM phase-shift converters [6] and asymmetrical PWM phase-shift converters with high-frequency isolation transformers [7] for dc / dc power conversion. That is, the phase-shift converters in [6] and [7] are proposed as dc-dc power supplies for telecommunication applications, which is different from the WPT considerations in this article because the coupling coefficient in WPT applications is not always constant like that of high-frequency isolation transformers. The uncertain but large leakage inductance in the loosely coupled transmitter and receiver coils in the WPT system may affect the soft switching condition in the phase-shift converter.

[0008] A partial solution to achieve soft switching in a phase-shift modulated power inverter is to use a quasi-resonant circuit as reported in [8]. Another proposal to achieve soft switching in a phase-shift modulated inverter is to use a modified inverter as reported in [9]. This is a rather complex circuit compared to a standard full-bridge inverter (having four switches with anti-parallel diodes). The additional components include 8 diodes and 8 inductors. The authors of this reference claim that their circuit can achieve ZCS over a wider operating region (i.e., not the full operating region). Understandably, the reference shows that the quasi-resonant circuit cannot achieve soft switching over the full phase shift angle range and hard switching occurs when the phase shift angle exceeds 120 degrees. An industrial control integrated circuit

[10] for full ZVS of a phase-shift inverter is available, but it requires coordinated control of the transmitter circuit and the receiver circuit.

[0009] Phase shift control is commonly used in WPT systems as reflected in recent publications

[11] -

[18] . In

[11] , the effect of dead time on harmonics is studied. In

[12] , phase shift control is used for power and signal transmission, and in

[13] , phase shift control is used to balance the current in a three-phase WPT system. Phase shift control is also used for active rectifiers on the receiver side of WPT systems

[14] . Phase shift control has been reported for soft switching over a wide operating range

[15] and to improve efficiency at light loads

[16] . Other WPT control schemes for parameter estimation and maximum efficiency tracking based on phase shift inverters can be found in

[17] and

[18] . However, it is difficult to achieve soft switching of phase shift inverters over the full operating range of phase shift angles from 0° to 180° without communication and coordinated control between the transmitter (Tx) and receiver (Rx) circuits.

[0010] Hard switching of known WPT systems with phase shift control

[0011] A. Known SS Compensated WPT Systems

[0012] Figure 1 A schematic diagram of a known SS compensated WPT system is depicted in FIG. The full-bridge inverter converts the dc voltage V dc Converted to high frequency ac voltage v p . Power is sent via the SS compensation resonator. L p and L s are the self-inductance of the transmitting coil and the receiving coil respectively. M is the mutual inductance between the two coils. R p and R s is the equivalent series resistance (ESR) of the resonator. Compensation capacitor C p and C s is designed to resonate with the self-inductance of the coil so that the switching frequency and the resonant frequency of the resonator are equal

[0013] (1)

[0014] Where ω is the switching angular frequency of the inverter. For the resonator, according to Kirchhoff's circuit law,

[0015] (2.1)

[0016] (2.2)

[0017] Among them, i p1 and i s1 is the fundamental component of the transmitter and receiver current, and v s1 is the fundamental component of the output voltage of the receiving resonator. By substituting (1) into (2.1) and (2.2), we can eliminate L p , C p , L s and C s ,

[0018] (3.1)

[0019] (3.2)

[0020] According to (3.1), the receiver current i s1 The fundamental component of the input voltage of the transmitting resonator (i.e., v p1 ) to regulate. The diode bridge rectifier converts the receiver current into i rec , whose harmonics are generated by the parallel capacitor C f Filtering makes the dc current I b The battery load can be charged. The charging current is related to v p1 The magnitude (i.e., V p1 ) has a linear relationship. The larger V p1 Leading to a larger I b According to (3.2), v s1 The transmitter current i p1 The diode bridge rectifier converts v s1 Converted to charging voltage V b , which is related to i p1 The magnitude (i.e., I p1 ) has a linear relationship. The larger I p Leading to a larger V b Therefore, the battery charging current and charging voltage can be regulated by the output of the primary side inverter

[19] . Here, both the battery charging current and the output voltage are fed back to the phase shift controller to regulate the primary side inverter. Figure 2As shown in FIG. 1 , schematic waveforms of the switching signals (i.e., S1, S2, S3, and S4) are plotted. The switching signals of each bridge arm are complementary and have a duty cycle of 0.5. The phase shift angle (i.e., α) between the diagonal switching signals is controlled by the primary side controller. Figure 2 In the example, S1 and S2 are leading signals relative to S4 and S3. Therefore, Φ1 and Φ2 can be considered as leading bridge arms, while Φ3 and Φ4 can be considered as lagging bridge arms. Based on the rough waveform (not considering the dead time, so that the switching signals are complementary to one bridge arm), it can be analyzed by using Fourier analysis based on V dc and I dc To calculate V p1 and I p1 , as shown below:

[0021] (4.1)

[0022] (4.2)

[0023] The phase shift angle can be controlled to make V p and I p Regulation is performed so that the charge current and voltage can track reference values ​​during constant-current (CC) and constant-voltage (CV) charging modes.

[0024] like Figure 3 As shown in the figure, the control block diagram of primary side CC and CV charging control based on phase shift control is depicted. b With the threshold voltage V val The comparison is performed to determine whether the WPT system is operating in CC mode or CV mode. Typically, the threshold voltage can be set to a reference voltage V bref If V b Less than V val , then the output is 0, so that the phase shift angle is derived by the current controller (ie, controller 2). Controlling the charging current I b , to track the current reference value I bref . The WPT system operates in CC charging mode. On the contrary, when V b Greater than V val When , the output is 1, so that the phase shift angle is derived by the voltage controller (ie, controller 1). Controlling the charging voltage V b , to track the voltage reference value V bref According to (3) and (4), both Controller 1 and Controller 2 can be linear controllers (eg, proportional-integral (PI) controllers).

[0025] B. Operation Principle of Known Full-Bridge Inverter with Phase-Shift Control

[0026] Without loss of generality, when the harmonics of the resonator current are small, the equivalent impedance Z of the resonator and the nonlinear load is in can be modeled as a pure resistor

[20] . Therefore, the transmitter current i p The input voltage v of the transmitting resonator p In phase. For WPT systems under light load conditions, the phase shift angle of the controller is usually large. Figure 2 As shown, i under large phase shift angle is plotted p and v p Typical waveform. p From t1 to t 13 In each complete operation cycle, v p The waveform includes eight steady states (SS) (i.e., SS1: SS2: SS3: SS4: SS5: SS6: SS7: and SS8: ) and four transient states (TS) (i.e., TS1: TS2: TS3: and TS4: ). Figure 4 The equivalent circuit of a full-bridge inverter with phase-shift control in 12 states is shown in . Here, the parasitic capacitances (i.e., C1, C2, C3, and C4) and diodes (i.e., D1, D2, D3, and D4) of the four power switches (i.e., Φ1, Φ2, Φ3, and Φ4) are assumed to be the same, although it will be understood that in practice, there may be some minor parameter differences due to manufacturing tolerances.

[0027] Now turn to Figure 4 , the operating principle of the power inverter in the equivalent circuit of the known WPT system during one cycle will now be described. In the following discussion, paragraph references - such as (a), (b), etc. - refer to the corresponding circuit diagrams in the respective circuit diagrams.

[0028] (a) At t1, switch Φ3 turns off, while switch Φ1 remains on and switches Φ2 and Φ4 remain off. The voltage across parasitic capacitors C2 and C4 is V dc , while the voltage across the parasitic capacitors C1 and C3 is 0. Since the voltage across the capacitor C4 is V dc , so diode D3 is turned on. ) period, the transmitter current continues to be positive (i.e., i p >0).

[0029] (b) At t2, switch Φ4 is turned on, while switch Φ1 remains on and switches Φ2 and Φ3 remain off. ), the parasitic capacitor C3 is charged and the parasitic capacitor C4 is discharged. Since there is a voltage across the capacitor C4 (i.e., V ds4 >0), so switch Φ4 is turned on in a hard-on manner. During this period, the inverter current is still positive (i.e., i p >0).

[0030] (c) At t3, parasitic capacitor C4 is fully discharged and parasitic capacitor C3 is fully charged. Switches Φ1 and Φ4 are in the on state, while switches Φ2 and Φ3 are in the off state. ), the voltage across capacitors C1 and C4 is 0, while the voltage across capacitors C2 and C3 is V dc The transmitter current remains positive (i.e., i p >0).

[0031] (d) At t4, switch Φ1 turns off, while switch Φ4 remains on and switches Φ2 and Φ3 remain off. The voltage across parasitic capacitors C3 and C4 remains unchanged, while parasitic capacitor C1 is charged and parasitic capacitor C2 is discharged. ) period, capacitor C1 charges from 0 to V dc , while capacitor C2 is from V dc discharges to 0. The transmitter current remains positive (i.e., i p >0).

[0032] (e) At t5, parasitic capacitor C2 is fully discharged, and parasitic capacitor C1 is fully charged. Therefore, diode D2 is turned on. ), switch Φ4 remains on, while switches Φ1, Φ2, and Φ3 are off. The transmitter current is positive (i.e., i p >0).

[0033] (f) At t6, switch Φ2 is turned on. The voltage across the parasitic capacitors C1 and C3 is V dc , while the voltage across the parasitic capacitors C2 and C4 is 0. Therefore, switch Φ2 is turned on in a ZVS manner. ), switches Φ2 and Φ4 are in the on state, while switches Φ1 and Φ3 are in the off state. The transmitter current is positive during the first half of the period (i.e., i p >0), and is negative during the second half of the period (i.e., i p <0).

[0034] (g) At t7, switch Φ4 turns off. Switch Φ2 remains on, while switches Φ1 and Φ3 remain off. The voltage across the parasitic capacitor C4 is 0, and the transmitter current is negative (i.e., i p <0). Therefore, in SS5 ( ) period, diode D4 is turned on.

[0035] (h) At t8, switch Φ3 turns on. Switch Φ2 remains on, while switches Φ1 and Φ3 remain off. The voltage across the parasitic capacitors C1 and C3 is V dc , while the voltage across the parasitic capacitors C2 and C4 is 0. At TS3 ( ), capacitor C3 is discharged, while capacitor C4 is charged. Since there is a voltage across capacitor C3 (i.e., V ds3 >0), so Φ3 is turned on in a hard switching manner. The transmitter current is still negative (i.e., i p <0).

[0036] (i) At t9, capacitor C3 is fully discharged, while capacitor C4 is fully charged. Therefore, the voltage across the parasitic capacitors C1 and C4 is V dc , and the voltage across the parasitic capacitors C2 and C3 is 0 at this moment. ), switches Φ2 and Φ3 are in the on state, while switches Φ1 and Φ4 are in the off state. The transmitter current remains negative (i.e., i p <0).

[0037] (j) at t 10 At TS4 ( ) period, capacitor C1 is dc discharges to 0, while capacitor C2 charges from 0 to V dc . The transmitter current is still negative (i.e., i p <0).

[0038] (k) at t 11 At SS7 ( ), switch Φ3 is still on, while switches Φ1, Φ2, and Φ4 are off. The transmitter current is still negative (i.e., i p <0).

[0039] (l) at t 12At , switch Φ1 is turned on. The voltage across the parasitic capacitors C2 and C4 is V dc , while the voltage across the parasitic capacitors C1 and C3 is 0. Therefore, Φ1 is turned on in a ZVS manner. ), switches Φ1 and Φ3 are in the on state, while switches Φ2 and Φ4 are in the off state. The transmitter current is negative during the first half of the period (i.e., i p <0, and is positive during the second half of the period (i.e., i p >0).

[0040] According to the analysis, ZVS can be naturally achieved by controlling the leading arm of the inverter with a known phase shift, while the switching of the lagging arm is controlled during the transient period TS1 ( ) and TS3 ( ). Therefore, the EMI emission of the full-bridge inverter (especially the conducted EMI from 150kHz to 30MHz) can be high, which may violate the EMC standard EN55022. Summary of the invention

[0041] Aspects of the invention are set out in the independent claims. Some optional features are defined in the dependent claims.

[0042] Implementing the techniques disclosed herein can provide significant technical advantages. For example, as will be demonstrated below, zero voltage switching (ZVS) can be achieved to enable a phase shift modulator power inverter to soft-switch all power switches in all operating regions (including the lagging bridge arm). As a result, the power inverter can operate with reduced switching power losses and reduced electromagnetic interference. As a result, the converter can operate at a higher frequency while EMI is still within the required range.

[0043] In one arrangement, an "enhanced passive circuit" includes two diodes, two capacitors, and an inductor for a full-bridge inverter with known phase shift control in a wireless power transfer (WPT) system. This operation can achieve soft switching and reduce EMI radiation over a wide phase shift angle range (up to the full range of phase shift angles from 0° to 180°). This full-range ZVS operation can be achieved without any communication and / or coordinated control with the receiver circuit. Both simulation and experimental results show that the enhanced circuit of the WPT system can achieve ZVS in both constant current (CC) control mode and constant voltage (CV) control mode. Actual EMI testing shows that the enhanced circuit can reduce the conducted EMI of the full-bridge inverter to meet the standard EN55022 over the full range of phase shift angles from 0° to 180°. Therefore, the proposed enhanced circuit adds a soft switching feature to the phase shift inverter, regardless of the type of resonant circuit in the WPT system, thereby enabling the inverter to flexibly drive different types of WPT systems in existing wireless charging standards.

[0044] The existing methods require more circuit components and cannot achieve soft switching within the entire operating range of the phase shift modulation inverter. The technology disclosed in this article has at least the following advantages:

[0045] • Fewer circuit components than existing methods, reducing costs.

[0046] •There are no active power switches, so no additional gate drive circuitry for the power switches is required.

[0047] • Enhanced passive circuits can be added to existing phase-shift modulated power inverters.

[0048] • Enhanced passive circuits enable soft switching (via zero voltage switching) of the phase-shift modulated power inverter over the entire operating range.

[0049] An enhanced passive circuit (having Figure 5 The connection shown) includes two diodes, two capacitors and an inductor, which are used to achieve soft switching of all power switches in the power inverter under phase-shift modulation control.

[0050] Enhanced passive circuits may be added to the power inverter to achieve soft switching in either fixed frequency operation or variable frequency operation of the power inverter.

[0051] Enhanced passive circuits can reduce switching power stress and power loss to increase the service life and conversion efficiency of the power inverter.

[0052] The enhanced passive circuits can be used to modify existing designs of wireless power transfer systems that comply with Wireless Power Consortium and Society of Automotive Engineers standards without changing the control algorithms.

[0053] This article also discloses a design method for enhancing passive circuits based on equations (25) to (27) set forth below.

[0054] Power inverters are widely used in a wide range of modern commercial applications such as switch-mode power supplies, battery chargers and wireless charging systems, with a market value of tens of billions of dollars. The technology can be applied to a wide variety of applications, but is particularly useful in wireless charging, including mobile phones and mobile robots (e.g., lawn mowers and vacuum cleaners). BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The present invention will now be described by way of example only and with reference to the accompanying drawings, in which:

[0056] Figure 1 is a schematic diagram of a typical SS compensated WPT system;

[0057] Figure 2 are voltage-time diagrams and current-time diagrams showing schematic waveforms of switching signals of a known power inverter for a WPT system;

[0058] Figure 3 is a control block diagram for implementing known phase shift control for CC and CV charging for WPT systems described in

[19] ;

[0059] Figure 4 is a series of equivalent circuit diagrams showing the operation cycle of a power inverter of a known WPT system;

[0060] Figure 5 is a circuit diagram of a power inverter implementing an exemplary passive enhancement circuit according to the techniques described herein;

[0061] Figure 6 1 is a voltage-time diagram and a current-time diagram showing schematic waveforms of switching signals of a power inverter implementing an exemplary passive enhancement circuit for a WPT system according to the techniques described herein;

[0062] Figure 7 is a series of equivalent circuit diagrams illustrating the operating cycle of a power inverter implementing an enhanced passive circuit according to the techniques described herein;

[0063] Figure 8 I of (a) WPT system without enhancement circuit and (b) WPT system with enhancement circuit under simulation case 1 are shown. b ,I bref 、i p 、v p and waveforms of switching signals;

[0064] FIG9 shows waveforms of drain current and drain-source voltage of four switches of (a) a WPT system without an enhancement circuit and (b) a WPT system with an enhancement circuit under simulation case 1;

[0065] Fig.10 The V of four switches of the WPT system without enhancement circuit and the WPT system with enhancement circuit in case 1 are shown. ds -I d curve;

[0066] Fig.11 V of (a) a WPT system without a boosting circuit and (b) a WPT system with a boosting circuit under Case 2 are shown. b 、V bref 、i p 、v p and waveforms of switching signals;

[0067] Fig.12 The waveforms of drain current and drain-source voltage of four switches in case 2 are shown for (a) a WPT system without an enhancement circuit and (b) a WPT system with an enhancement circuit;

[0068] Fig.13 The V of four switches of the WPT system without enhancement circuit and the WPT system with enhancement circuit in case 2 are shown. ds -I d curve;

[0069] Fig.14 shows the v of a WPT system with (a) no enhancement circuit for current control and (b) an enhancement circuit for current control ds3 、i d3 、i p and v p The waveform of

[0070] Fig.15 shows the conducted EMI from a full-bridge inverter (a) without an enhancement circuit for current control and (b) with an enhancement circuit for current control;

[0071] Fig.16 shows the v of a WPT system with (a) no enhancement circuit for voltage control and (b) an enhancement circuit for voltage control ds3 and i d3 The enlarged waveform of

[0072] Fig.17 shows conducted EMI from a full-bridge inverter (a) without an enhancement circuit for voltage control and (b) with an enhancement circuit for voltage control;

[0073] Fig.18 Conducted EMI from a full-bridge inverter without an enhancement circuit and a full-bridge inverter with an enhancement circuit when the phase shift angle is controlled at 120°, 90°, 60°, 30°, and 0° is shown.

[0074] Fig.19 shows the background EMI of the test chamber; and

[0075] Fig. 20 The v of WPT system with and without enhancement circuit at different phase shift angles is shown. ds3 、i d3 、i p and v p waveform. DETAILED DESCRIPTION

[0076] A circuit diagram of a power inverter implementing an exemplary enhanced passive circuit according to the technology disclosed herein is shown in FIG. Figure 5 In this circuit diagram, the proposed enhanced passive circuit includes an inductor L A , two diodes D A1 and D A2 , and two capacitors C connected in parallel A1 and C A2 The circuit is called an "enhanced passive circuit" because it is "passive" and does not require any active switching components. The circuit "enhances" the known phase-shift modulated full-bridge power inverter. Figure 5 In the example of FIG. 5 , the power inverter 500 is manufactured together with the enhanced passive circuit, however, the enhanced passive circuit can also be assembled (eg, retrofitted) to an existing power inverter of known design.

[0077] like Figure 5 As shown, the phase-shift modulation full-bridge power inverter 500 includes an advanced bridge arm 502, which includes: a first power switch Φ1, which has a first power switch parasitic capacitance C1; and a second power switch Φ2, which has a second power switch parasitic capacitance C2. The first power switch Φ1 and the second power switch Φ2 are connected in series with each other at the advanced bridge arm connection point A of the advanced bridge arm 502. The power inverter 500 also includes a lagging bridge arm 504, which includes: a third power switch Φ3, which has a third power switch parasitic capacitance C3; and a fourth power switch Φ4, which has a fourth power switch parasitic capacitance C4. The third power switch Φ3 and the fourth power switch Φ4 are connected in series with each other at the lagging bridge arm connection point B of the lagging bridge arm 504.

[0078] As mentioned above, typical types of power switches include MOSFETs and IGBTs.

[0079] exist Figure 5 In the example of FIG. 5 , the power inverter 500 includes a capacitor circuit branch 506 including a first enhancement circuit capacitor C connected in series with each other at a capacitor branch connection point X1. A1 and the second enhancement circuit capacitor C A2 The capacitor circuit branch 506 is connected in parallel with the leading bridge arm 502 and the lagging bridge arm 504. Continuing with the example, the power inverter 500 includes a diode circuit branch 508 including a first enhancement circuit diode D connected in series with each other at the diode branch connection point X2. A1 and the second enhancement circuit diode D A2 The diode circuit branch 508 is connected in parallel with the leading bridge arm 502 and the lagging bridge arm 504. In this example, the capacitor circuit branch connection point X1 and the diode circuit branch connection point X2 are electrically connected to each other.

[0080] The leading bridge arm connection point A is connected to the first output terminal 510 of the power inverter to connect to the load Z, in this case the wireless power transfer charging load. The lagging bridge arm connection point B is connected to the second output terminal 512 of the power inverter to connect to the load Z. In operation, a load voltage V is generated across the load Z. p , and the load current i p Flows through the load Z.

[0081] The power inverter 500 further includes an enhancement circuit inductor L A , whose first side (at the first inductor terminal) is connected to the capacitor branch connection point X1 and the diode branch connection point X2. A A second side (at the second inductor terminal) of is connected to one of the first output terminal 510 and the second output terminal 512 .

[0082] Enhancement circuit inductor L A , capacitor circuit branch 506 and diode circuit branch 508 together form an enhanced passive circuit that operates to reduce or even eliminate the discontinuous current that occurs, especially when the phase shift angle is large. This in turn achieves soft switching and reduces (or even eliminates) power losses and electromagnetic interference (EMI) caused by switching of the power switch.

[0083] like Figure 6 As shown, the switching signal i of the WPT system with enhanced circuit is plotted p and v p Schematic waveform of. In each cycle (i.e., from t1 to t 13 ) period, v p The waveform includes eight steady states (SS) (i.e., SS1: SS2: SS3: SS4: SS5: SS6: SS7: and SS8: ) and four transient states (TS) (i.e., TS1: TS2: TS3: TS4: ).like Figure 7 , depicts an equivalent circuit during one operating cycle. In the following discussion, paragraph references—eg, (a), (b), etc.—refer to corresponding circuit diagrams in the various circuit diagrams.

[0084] (a) At t1, switch Φ3 turns off, while switch Φ1 remains on and switches Φ2 and Φ4 remain off. The transmitter current is positive (i.e., i p >0). The voltage across the parasitic capacitors C2 and C4 is V dc , while the voltage across the parasitic capacitors C1 and C3 is 0. ), capacitor C3 is charged and capacitor C4 is discharged. A And the parasitic capacitors C3 and C4 can form an LC resonator, so that the energy stored in the parasitic capacitor C4 can be discharged before the switch Φ4 is turned on.

[0085] Therefore, it will be understood that Figure 5 and Figure 6 and the associated text shows and describes a phase-shift modulated full-bridge power inverter 500 configured for a wireless power transmission system, the power inverter 500 comprising: an advanced bridge arm 502, comprising: a first power switch Φ1, the first power switch Φ1 having a first power switch parasitic capacitance C1; and a second power switch Φ2, the second power switch Φ2 having a second power switch parasitic capacitance C2; ​​a lagging bridge arm 504, comprising: a third power switch Φ3, the third power switch Φ3 having a third power switch parasitic capacitance C3; and a fourth power switch Φ4, the fourth power switch Φ4 having a fourth power switch parasitic capacitance C4; wherein the power inverter 500 is configured to turn each power switch on and off during a switching cycle; and wherein the power inverter further comprises: an enhanced passive circuit, the enhanced passive circuit comprising an inductor L A, wherein the power inverter 500 is configured to: when the first of the third power switch Φ3 and the fourth power switch Φ4 (in this step (a), this is the third power switch Φ3) is turned off and the second of the third power switch Φ3 and the fourth power switch Φ4 (in this step (a), this is the fourth power switch Φ4) is in the off state, the inductor L A Combined with the third power switch parasitic capacitance Φ3 and the fourth power switch capacitance Φ4 to form a resonator, and before the second one of the third power switch and the fourth power switch (in this step (a), this is Φ4) is turned on, the energy stored in the parasitic capacitance of the second one of the third power switch and the fourth power switch (in this step (a), this is C4 of Φ4) is released.

[0086] Corresponding methods are also described.

[0087] The importance of releasing the energy stored in the parasitic capacitor C4 will become apparent from step (c) below. The discharge / release of the energy of the parasitic capacitor C4 may be a full discharge or a partial discharge.

[0088] According to the resonant circuit, the current flowing through the boost inductor and the voltage across capacitors C3 and C4 can be expressed as

[0089] (5)

[0090] (6)

[0091] (7)

[0092] Here, the transmitter current is mainly determined by the resonator of the WPT system, which will not affect the amplitude and frequency of the boost inductor current and the voltage across the capacitor. In addition, due to the continuity of the system circuit, the amplitude of the boost inductor current is determined by the previous state of the system circuit. The TS1 period can be calculated based on (6) or (7) as follows:

[0093] (8)

[0094] (b) At t2, parasitic capacitor C3 is fully charged and parasitic capacitor C4 is fully discharged. Switch Φ1 is in the on state, while switches Φ2, Φ3, and Φ4 are in the off state. The boost inductor current can be calculated by substituting (8) into (5) as follows:

[0095] (9)

[0096] In SS1 ( ) during which both the transmitter current and the boost inductor current are positive (i.e., ip and i LA >0).

[0097] (c) At t3, switch Φ4 turns on. Switch Φ1 remains on, and switches Φ2 and Φ3 remain off. The transmitter current is still positive (i.e., i p >0). In SS2 ( ), when a DC source is connected, the boost inductor current decreases as shown below:

[0098] (10)

[0099] Since the voltage across capacitor C4 is zero, Φ4 is turned on in a ZVS manner. Therefore, incorporating enhanced passive circuits into power inverter 500 is important in reducing or even eliminating the undesirable power losses and EMI caused by power switches present in the prior art.

[0100] (d) At t4, switch Φ1 turns off. Switch Φ4 remains on, and switches Φ2 and Φ3 remain off. The voltage across the parasitic capacitors C1 and C4 is 0, while the voltage across the parasitic capacitors C2 and C3 is V dc The transmitter current is still positive (i.e., i p >0). In TS2 ( ), the boost inductor current is further reduced based on (10). By assuming the transmitter current is , the voltage across the parasitic capacitors C1 and C2 can be expressed as:

[0101] (11)

[0102] (12)

[0103] Then, the TS2 period can be calculated by the following formula:

[0104] (13)

[0105] (e) At t5, since C2 is fully discharged, diode D2 is turned on. ) period, the transmitter current remains positive (i.e., i p >0), and the boost inductor current is further reduced based on (10).

[0106] (f) At t6, switch Φ2 is turned on, while switch Φ4 remains on and switches Φ1 and Φ3 remain off. Since the voltage across capacitor C2 is zero, Φ2 is turned on in a ZVS manner. ), the transmitter current is positive during the first half period, and it is negative during the second half period. Based on (10), the boost inductor current is further reduced. When the inductor current decreases to 0, the diode D A1 The inductor current becomes negative, which is the sum of the boost capacitor current (i.e., ),like Figure 7 (f2). When the enhancement capacitor C A1 is fully charged and enhances the capacitor C A2 When fully discharged, the diode D A2 is turned on and the boost inductor remains at its minimum value, as shown in the following equation:

[0107] (14)

[0108] Therefore, to summarize here, the enhanced passive circuit further includes a diode circuit branch 508, which includes first diodes D connected in series with each other. A1 and the second diode D A2 , the diode circuit branch 508 is connected in parallel to the leading bridge arm 502 and the lagging bridge arm 504, and the power inverter 500 is configured to: when the first of the first power switch and the second power switch (in this step (f), this is Φ2) is turned on and the second of the first power switch and the second power switch (in this step (f), this is Φ1) is in the off state, the first of the third power switch and the fourth power switch (in this step (f), this is Φ3) is in the off state and the second of the third power switch and the fourth power switch (in this step (f), this is Φ4) is in the on state, the first of the first diode and the second diode (in this step (f), this is D A1 ) is in the conducting state and the second of the first diode and the second diode (in this step (f), this is D A2 ) is in a non-conductive state; and wherein the power inverter 500 is configured to make the inductor L A The current in the first diode becomes zero and the first of the first diode and the second diode (in this step (f), this is D A1 ) is switched to a non-conducting state.

[0109] To summarize further, the enhanced passive circuit further includes a capacitor circuit branch 506, which includes a first capacitor CA1 and a second capacitor C connected in series with each other. A2 , the capacitor circuit branch 506 is connected in parallel to the leading bridge arm 502 and the lagging bridge arm 504, and the power inverter 500 is configured to: make the inductor L AThe increase in the current amplitude in (in this step (f), the inductor current becomes negative after having been zero), causes the first of the first capacitor and the second capacitor (in this step (f), this is C A1 ) is fully charged, so that the first capacitor and the second capacitor (in this step (f), this is C A2 ) is fully discharged and the first diode and the second diode (in step (f), this is D A2 ) is switched to a conducting state.

[0110] (g) At t7, switch Φ4 turns off, while switch Φ2 remains on and switches Φ1 and Φ3 remain off. The transmitter current is negative (i.e., i p <0). The voltage across the parasitic capacitors C1 and C3 is V dc , while the voltage across the parasitic capacitors C2 and C4 is 0. At TS3 ( ), capacitor C3 is discharged and capacitor C4 is charged. A And the parasitic capacitors C3 and C4 can form an LC resonator, so that the energy stored in the parasitic capacitor C3 can be discharged before the switch Φ3 is turned on. The current flowing through the enhanced inductor and the voltage across the capacitors C3 and C4 can be expressed as:

[0111] (15)

[0112] (16)

[0113] (17)

[0114] The TS3 period can be calculated based on (16) or (17) as follows:

[0115] (18)

[0116] Therefore, in this step, the enhanced passive circuit operates again, wherein the power inverter 500 is configured such that when the first of the third power switch Φ3 and the fourth power switch Φ4 (in this step (g), this is now the fourth power switch Φ4) is turned off and the second of the third power switch and the fourth power switch Φ3, Φ4 (at this time, in this step (g), the third power switch Φ3) is in the off state, the inductor L AThe third power switch parasitic capacitance C3 and the fourth power switch capacitance C4 are combined to form a resonator, but the switch arrangement is opposite to the switch arrangement described above in step (a), and before the second one of the third power switch and the fourth power switch (in this step (g), this is Φ3) is turned on, the energy stored in the parasitic capacitance of the second one of the third power switch and the fourth power switch (in this step (g), this is C3 of Φ3) is released.

[0117] (h) At t8, parasitic capacitor C4 is fully charged and parasitic capacitor C3 is fully discharged. Switch Φ2 is in the on state, while switches Φ1, Φ3, and Φ4 are in the off state. The boost inductor current can be calculated by substituting (18) into (15) as follows:

[0118] (19)

[0119] In SS5 ( ), both the transmitter current and the boost inductor current are negative (i.e., i p <0 and i LA <0).

[0120] (i) At t9, switch Φ3 is turned on, switch Φ2 remains on, and switches Φ1 and Φ4 remain off. The transmitter current is still negative (i.e., i p <0). In SS6 ( ), when a DC source is connected, the boost inductor current increases as shown below:

[0121] (20)

[0122] Since the voltage across capacitor C3 is zero, Φ3 is turned on in a ZVS manner.

[0123] (j) at t 10 At , switch Φ2 is turned off. Switch Φ3 remains on, and switches Φ1 and Φ4 remain off. The voltage across the parasitic capacitors C2 and C3 is 0, while the voltage across the parasitic capacitors C1 and C4 is V dc . The transmitter current is still negative (i.e., i p <0). In TS4 ( ), the boost inductor current further increases based on (20). By assuming that the transmitter current is , then the voltage across capacitors C1 and C2 can be expressed as:

[0124] (twenty one)

[0125] (twenty two)

[0126] Then, the TS4 period can be calculated as:

[0127] (twenty three)

[0128] (k) at t 11 At SS7 ( ), the transmitter current remains negative and the boost inductor current increases further based on (20).

[0129] (l) at t 12 At SS8 ( ), the transmitter current is negative during the first half period, and it is positive during the second half period. The boost inductor current is further increased based on (20). When the inductor current increases to 0, the diode D A2 The inductor current becomes positive, which is the sum of the reinforcing capacitor current (i.e., ),like Figure 7 (l2). When the enhancement capacitor C A1 is fully discharged and enhances the capacitor C A2 When fully charged, diode D A1 The inductor is turned on and the boost inductor remains at its maximum value, as shown in the following equation:

[0130] (twenty four)

[0131] Therefore, in summary again here, it will be seen again that the power inverter 500 is configured to: turn on the first of the first power switch and the second power switch (in this step (l), this is Φ1) and the second of the first power switch and the second power switch (in this step (l), this is Φ2) in the off state, turn off the first of the third power switch and the fourth power switch (in this step (l), this is Φ4) in the off state and the second of the third power switch and the fourth power switch (in this step (l), this is Φ3) in the on state, turn on the first diode and the second diode (in this step (l), this is D A2 ) is in the conducting state and the second of the first diode and the second diode (in this step (l), this is D A1 ) is in a non-conductive state; and wherein the power inverter 500 is configured to make the inductor L A The current in the diode becomes zero and the first of the first diode and the second diode (in this step (l), this is DA2 ) is switched to a non-conducting state.

[0132] To summarize further, it will be seen again that the power inverter 500 is configured to make the inductor L A The increase in the current amplitude in (in this step (l) the inductor current becomes positive after having been zero) causes the first of the first capacitor and the second capacitor (in this step (l), this is C A2 ) is fully charged, so that the second of the first capacitor and the second capacitor (in this step (l), this is C A1 ) is fully discharged, and the first diode and the second diode (in step (l), this is D A1 ) is switched to a conducting state.

[0133] Obviously, the WPT system with known phase shift control can achieve ZVS of both bridge arms by enhancing the integration of the circuit. Therefore, EMI radiation, especially conducted EMI, can be reduced.

[0134] Assume that increasing the inductor current requires approximately The switching cycle increases from 0 to the maximum value (i.e., I max ),For example

[0135] (25)

[0136] Then, the parameters of the enhanced inductor and capacitor can be calculated based on (24) and (25) as follows:

[0137] (26)

[0138] (27)

[0139] Therefore, a passive enhancement circuit is disclosed which can transform a phase-shifted power inverter into a fully soft-switching power inverter over the entire operating range (i.e., from 0° to 180° of phase shift angle). The proposed passive circuit has the following advantageous features:

[0140] • Compensation topology independent of transmitter (Tx) and receiver (Rx) circuits. For wireless power transfer systems, the leakage inductance of the transmitter coil and the receiver coil requires capacitor compensation. The compensation network can be of various types, i.e. series-series (both the Tx coil and the Rx coil are connected in series with a capacitor), series-shunt (capacitor is connected in series with the Tx coil, and capacitor is connected in parallel with the Rx coil), LCC-LCC, etc.;

[0141] • No need to adjust the firing angle or switching frequency of the power switch based on in-band or out-of-band communication between the Tx circuit and the Rx circuit;

[0142] • It can be implemented for full load operation, including light load and no load conditions;

[0143] • It can be implemented for constant frequency operation of inverter output voltage.

[0144] The proposed circuit has been tested for the full range of phase shift angles from 0° to 180°. Actual measurements of circuit waveforms and electromagnetic emissions are included to confirm the feasibility of achieving soft switching over the entire operating range.

[0145] As described above, the enhanced passive circuit can be assembled (e.g., retrofitted) to a phase shift modulation full-bridge power inverter configured for a wireless power transmission system. Therefore, a method of assembly (retrofitting) includes: connecting a capacitor circuit branch 506 in parallel to the leading bridge arm 502 and the lagging bridge arm 504, the capacitor circuit branch including a first capacitor C connected in series with each other at a capacitor branch connection point X1. A1 and the second capacitor C A2 The diode circuit branch 508 is connected in parallel to the leading bridge arm 502 and the lagging bridge arm 504, the diode circuit branch 508 includes a first diode D connected in series with each other at the diode branch connection point X2 A1 and the second diode D A1 ; and the inductor L A The capacitor branch connection point X1 and the diode branch connection point X2 are connected, and the inductor L is connected at the second inductor terminal. A Connected to one of the first output terminal 510 and the second output terminal 512 .

[0146] The components for enhancing the passive circuit can be provided in the form of a set of components for assembly to a phase shift modulation full-bridge power inverter configured for any wireless power transmission system. Therefore, a set of enhanced passive circuit components for assembly to a phase shift modulation full-bridge power inverter 500 configured for a wireless power transmission system includes: a first capacitor C A1 and the second capacitor C A2 , are connected in series with each other at a capacitor branch connection point X1 in a capacitor circuit branch 506, which is connected in parallel to the leading bridge arm 502 and the lagging bridge arm 504 of the power inverter; a first diode D A1 and the second diode D A2 , are connected in series with each other at a diode branch connection point X2 in a diode circuit branch 508, which is connected in parallel to the leading bridge arm 502 and the lagging bridge arm 504; and an inductor L A, connected to the capacitor branch connection point X1 and the diode branch connection point X2 at a first inductor terminal, and connected to one of the power inverter first output terminal 510 and the power inverter second output terminal 512 at a second inductor terminal.

[0147] Simulation Results

[0148] By using Psim10.0, the WPT system (schematic diagram as shown in Figure 1 The battery load is modeled as a pure resistive load R L The switching frequency is 100kHz. The dead time of the switching signal is 0.1μs. Both current and voltage control use PI controllers. The parameters of the current controller are K PI =1 and K iI =100000, and the voltage controller parameter is K PV = 0.1 and K iV =10000. The output current and voltage reference values ​​are I bref =1.675A and V bref =4.2V. Two cases are studied in the simulation. In case 1, the output current is controlled to track the current reference with a phase shift angle greater than 120°. In case 2, the output voltage is controlled to track the voltage reference with a phase shift angle greater than 165°, which means that the transmitter input voltage (i.e., v p ) has a conduction pulse width less than 15°.

[0149] parameter value parameter value <![CDATA[V dc ]]> 24V <![CDATA[L p ]]> 48.4μH <![CDATA[L s ]]> 48.4μH M 7.1μH <![CDATA[C p ]]> 52.3nF <![CDATA[C s ]]> 52.3nF <![CDATA[R p ]]> 0.1Ω <![CDATA[R s ]]> 0.1Ω <![CDATA[C f ]]> 20μF <![CDATA[R L ]]> 10Ω <![CDATA[C1]]> 1nF <![CDATA[C2]]> 1nF <![CDATA[C3]]> 1nF <![CDATA[C4]]> 1nF <![CDATA[C A1 ]]> 100nF <![CDATA[C A2 ]]> 100nF <![CDATA[L A ]]> 1μH

[0150] Table 1. Main parameters of the WPT system in the simulation

[0151] For case 1, Figure 8 The output current (i.e., I b ), output current reference value (i.e., I bref ), the transmitter current (i.e., i p ), the input voltage of the transmitting resonator (i.e., v p ), and the waveforms of the four switching signals (i.e., S1, S2, S3, and S4). The two output currents are well regulated to track the current reference value (i.e., I bref =1.675A), and the transmitter current is in phase with the input voltage of the transmitting resonator. The phase shift angle between the diagonal switching signals is controlled at 131.8° and 129.2° for the WPT system without the enhancement circuit and the WPT system with the enhancement circuit, respectively.

[0152] The corresponding drain currents of the four switches (i.e., I d1 ,I d2 ,I d3 and I d4 ) and the drain-source voltage (i.e., V ds1 、V ds2 、V ds3 and V ds4 ) is shown in Figure 9. For the WPT system without the enhancement circuit, the four transient periods are marked as TS A1 TS A2 TS A3 and TS A4 , while for the WPT system with enhanced circuits, the four transient periods are marked as TS B1 TS B2 TS B3 and TS B4 Obviously, in TS A1 and TS A3 During this period, hard switching occurred on the lagging bridge arms (i.e., Φ3 and Φ4) of the WPT system without the enhancement circuit, respectively. However, with the enhancement circuit, ZVS can be achieved for all four switches of the WPT system.

[0153] like Fig.10 As shown, the corresponding V of the switch of the WPT system without the enhancement circuit and the WPT system with the enhancement circuit are plotted. ds -I d Curve. It can be clearly observed that the enclosed area of ​​Φ3 and Φ4 of the WPT system with the enhancement circuit is significantly reduced. By incorporating the enhancement circuit, the hard switching problem of Φ3 and Φ4 of the known WPT system with phase shift control is solved.

[0154] For case 2, Fig.11 The output voltages of a WPT system without an enhancement circuit (known WPT system) and a WPT system with an enhancement circuit (ie, V b ), output current reference value (ie, V bref ), the transmitter current (i.e., i p ), the input voltage of the transmitting resonator (i.e., v p ), and the waveforms of the four switching signals (i.e., S1, S2, S3, and S4). The output voltage is adjusted to track the reference value (i.e., V bref =4.2V). For the WPT system without enhancement circuit and the WPT system with enhancement circuit, the phase shift angle between the diagonal switching signals is controlled at 165.4° and 169.2°, respectively.

[0155] like Fig.12As shown, the corresponding V of the switch of the WPT system without the enhancement circuit and the WPT system with the enhancement circuit are plotted. ds -I d Similar to the results of Case 1, hard switching occurs on the lagging bridge arm of the WPT system without the enhancement circuit, while all switches of the WPT system with the enhancement circuit achieve ZVS.

[0156] like Fig.13 As shown, the V of the switch of the WPT system with the enhanced circuit is plotted. ds -I d Similar to the results of Case 1, the enclosed areas of Φ3 and Φ4 of the WPT system with enhanced circuits are significantly reduced.

[0157] Experimental verification

[0158] The experiments were conducted on a WPT system with the same parameters as shown in Table 1. The frequency and dead time of the switching signal of the full-bridge inverter are also the same as those used in the simulation. The MOSFET of the full-bridge inverter adopts Infineon's IRFP250M. A Rogowski coil is used to measure the drain current of the four DIP MOSFETs. The conducted EMI of the full-bridge inverter is measured by Advantest's spectrum analyzer R3261C. The background EMI of the EMC room is shown in the "Other Data, Part A" below. RIGOL's DP832 is used as the DC power supply for the WPT system. The controller is implemented using the digital signal processor (DSP) TMS320F28335 from Texas Instruments (TI). The parameters of the current controller are K PI = 0.00001 and K iI = 0.1, and the voltage controller parameter is K PV = 0.00001 and K iV =10000. The output current and voltage reference values ​​are also I bref =1.675A and V bref = 4.2 V. In the experiments, both CC control and CV control were studied.

[0159] First, the output current of the WPT system (i.e., I b ) to track the reference value of 1.675A (i.e., I bref ). Fig.16 The drain-source voltage and drain current (i.e., v ds3 and i d3 ), the transmitter current (i.e., i p), and the input voltage of the transmitting resonator (i.e., v p For the WPT system without the enhancement circuit, the phase shift angle is controlled at 148.6°, while for the WPT system with the enhancement circuit, the phase shift angle is controlled at 148.2°. Fig.14 (a2) and Fig.14 The waveforms in (b2) are respectively Fig.14 (a1) and Fig.14 The waveform in (b1) is magnified. Fig.14 (a3) and Fig.14 The waveforms in (b3) are respectively Fig.14 (a2) and Fig.14 The waveform in (b2) is magnified. ds3 and i d3 The waveforms of indicate that hard switching occurs in the known WPT system without the enhancement circuit. However, when the enhancement circuit is integrated into the full-bridge inverter, ZVS can be achieved, as shown in Fig.14 (b3) shown. Fig.15 1 shows a comparison of conducted EMI between a full-bridge inverter without an enhancement circuit and a full-bridge inverter with an enhancement circuit in the range from 150kHz to 30MHz. Obviously, the conducted EMI of the full-bridge inverter without an enhancement circuit exceeds the upper limit of standard EN55022. By incorporating an enhancement circuit, the conducted EMI of the full-bridge inverter is significantly reduced to below the upper limit.

[0160] Then, the output voltage of the WPT system (i.e., V b ) to track the 4.2V reference value (i.e., V bref ). The phase shift angles of the WPT system without enhancement circuit and the WPT system with enhancement circuit are controlled at 166.2° and 169.8° respectively. Fig.16 The figure shows the difference between the full-bridge inverter with enhancement circuit and the full-bridge inverter without enhancement circuit within 0.5μs transient. ds3 and i d3 The enlarged waveform shows that the known WPT system without the enhancement circuit undergoes hard switching, while the integrated enhancement circuit can achieve ZVS even when the phase shift angle has reached about 170° (i.e., v p The on-pulse width is only about 10°). Fig.17 The comparison of conducted EMI between a full-bridge inverter without an enhancement circuit and a full-bridge inverter with an enhancement circuit in the range from 150kHz to 30MHz is shown in FIG. Obviously, the conducted EMI of the full-bridge inverter without an enhancement circuit also exceeds the upper limit of the standard EN55022 for voltage control. However, by integrating an enhancement circuit, EMI can be significantly reduced.

[0161] Similar experiments were conducted for WPT systems with phase shift angles of 120°, 90°, 60°, 30°, and 0°. The following “Other Data, Part B” shows the v of the WPT system with the enhancement circuit and the WPT system without the enhancement circuit. ds3 、i d3 、i p and v p The corresponding waveform of . The results show that the enhanced circuit can also achieve ZVS under heavy load conditions. Fig.18 The corresponding conducted EMI of a full-bridge inverter without and with an enhancement circuit are presented in Figure 2. Obviously, the enhancement circuit can mitigate the conducted EMI under heavy load conditions. However, it is worth noting that the EMI reduction is more significant for WPT systems with larger phase shift angles.

[0162] Other data

[0163] A. Background EMI in the EMC room

[0164] Since the full-bridge inverter and controller circuit are placed inside the test chamber, Fig.19 As shown, four background EMIs (including (i) conducted EMI of a power supply without an auxiliary circuit and a controller circuit of a full-bridge inverter, (ii) conducted EMI of a power supply with an auxiliary circuit of a full-bridge inverter but without a controller circuit, (iii) conducted EMI of a power supply without an auxiliary circuit of a full-bridge inverter but with a controller circuit, and (iv) conducted EMI of a power supply with an auxiliary circuit of a full-bridge inverter) are measured as reference values.

[0165] B. v of WPT systems with different phase shift angles ds3 、i d3 、i p and v p Waveform

[0166] Fig. 20 The full-bridge inverter with an enhancement circuit and the full-bridge inverter without an enhancement circuit are shown in FIG. 1 when the phase shift angle is 120°, 90°, 60°, 30°, and 0°. ds3 、i d3 、i p and v p The experimental waveform.

[0167] It will be understood that the present invention has been described by way of example only. Various modifications may be made to the techniques described herein without departing from the spirit and scope of the appended claims. The disclosed techniques include techniques that can be provided in an independent manner or in combination with each other. Therefore, features described for one technique may also be presented in combination with another technique.

[0168] This application also describes the following concepts.

[0169] 1 An enhanced passive circuit (having Figure 5 The connection shown in FIG. 1 includes two diodes, two capacitors and one inductor for realizing soft switching of all power switches in the power inverter under phase-shift modulation control.

[0170] 2 The enhanced passive circuit can be added to the power inverter to achieve soft switching under fixed frequency or variable frequency operation of the power inverter.

[0171] 3 The enhanced passive circuit can reduce switching power stress and power loss to improve the service life and conversion efficiency of the power inverter.

[0172] 4 The enhanced passive circuit can be used to modify existing wireless power transfer system designs to comply with Wireless Power Consortium and Society of Automotive Engineers standards without changing the control algorithm.

[0173] 5 The enhanced passive circuit can be converted into an enhanced active circuit by replacing the inductor with an active controlled current source or an equivalent current source, while still maintaining the functions described in points 2 to 4 above.

[0174] 6 A design method for enhanced passive circuits based on equations (25) to (27).

[0175] References

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Claims

1. A phase shift modulation full bridge power inverter configured for use in a wireless power transmission system, the power inverter comprising: Leading bridge arm, including: a first power switch having a first power switch parasitic capacitance; and a second power switch, the second power switch having a second power switch parasitic capacitance; The lagging bridge arm includes: a third power switch having a third power switch parasitic capacitance; and A fourth power switch, wherein the fourth power switch has a fourth power switch parasitic capacitance; wherein, The power inverter is configured to turn each of the power switches on and off during a switching cycle; and wherein the power inverter further comprises: An enhanced passive circuit includes an inductor, wherein the power inverter is configured to: when the first of the third power switch and the fourth power switch is turned off and the second of the third power switch and the fourth power switch is in an off state, the inductor is combined with the third power switch parasitic capacitance and the fourth power switch capacitance to form a resonator, and before the second of the third power switch and the fourth power switch is turned on, the energy stored in the parasitic capacitance of the second of the third power switch and the fourth power switch is released.

2. The power inverter according to claim 1, wherein the enhanced passive circuit further comprises a diode circuit branch, wherein the diode circuit branch comprises a first diode and a second diode connected in series with each other, wherein the diode circuit branch is connected in parallel to the leading bridge arm and the lagging bridge arm, and wherein the power inverter is configured as follows: A first one of the first power switch and the second power switch is turned on and a second one of the first power switch and the second power switch is in an off state; The first of the third power switch and the fourth power switch is in an off state and the second of the third power switch and the fourth power switch is in an on state; as well as placing a first one of the first diode and the second diode in a conducting state and placing a second one of the first diode and the second diode in a non-conducting state; and wherein, The power inverter is configured to cause the current in the inductor to become zero and to cause the first one of the first diode and the second diode to be switched to a non-conducting state.

3. The power inverter according to claim 2, the enhanced passive circuit also includes a capacitor circuit branch, the capacitor circuit branch includes a first capacitor and a second capacitor connected in series with each other, the capacitor circuit branch is connected in parallel to the leading bridge arm and the lagging bridge arm, and the power inverter is configured to: increase the amplitude of the current in the inductor, fully charge the first of the first capacitor and the second capacitor, fully discharge the second of the first capacitor and the second capacitor, and switch the second of the first diode and the second diode to a conducting state.

4. A phase shift modulated full-bridge power inverter configured for use in a wireless power transmission system, the power inverter comprising: Advanced bridge arm; Lagging bridge arm; A first output terminal connected from a leading bridge arm connection point in the leading bridge arm; A second output terminal connected from a lagging bridge arm connection point in the lagging bridge arm; as well as Enhanced passive circuits, including: a capacitor circuit branch including a first capacitor and a second capacitor connected in series to each other at a capacitor branch connection point, the capacitor circuit branch being connected in parallel to the leading bridge arm and the lagging bridge arm; a diode circuit branch including a first diode and a second diode connected in series with each other at a diode branch connection point, the diode circuit branch being connected in parallel to the leading bridge arm and the lagging bridge arm; and An inductor is connected to the capacitance branch connection point and the diode branch connection point at a first inductor terminal and is connected to one of the first output terminal and the second output terminal at a second inductor terminal.

5. A method of operating a phase shift modulated full bridge power inverter in a wireless power transmission system, the power inverter comprising: Leading bridge arm, including: a first power switch having a first power switch parasitic capacitance; and a second power switch, the second power switch having a second power switch parasitic capacitance; The lagging bridge arm includes: a third power switch, wherein the third power switch has a third power switch parasitic capacitance; a fourth power switch having a fourth power switch parasitic capacitance; and Enhance passive circuits, including inductors; The method comprises: operating the power inverter so that each of the power switches is turned on and off during a switching cycle; and When the second one of the third power switch and the fourth power switch is in an off state, the first one of the third power switch and the fourth power switch is turned off so that the inductor is combined with the parasitic capacitance of the third power switch and the capacitance of the fourth power switch to form a resonator, and the energy stored in the parasitic capacitance of the second one of the third power switch and the fourth power switch is released before the second one of the third power switch and the fourth power switch is turned on.

6. The method according to claim 5, wherein: The enhanced passive circuit further includes a diode circuit branch, the diode circuit branch includes a first diode and a second diode connected in series with each other, the diode circuit branch is connected in parallel to the leading bridge arm and the lagging bridge arm, and the method further includes: When the second of the first power switch and the second power switch is in the off state, and when the first of the third power switch and the fourth power switch is in the off state and the second of the third power switch and the fourth power switch is in the on state, the first of the first power switch and the second power switch is turned on; wherein the first of the first diode and the second diode is in the on state and the second of the first diode and the second diode is in the non-conducting state; wherein the power inverter current in the inductor becomes zero, and the method also includes switching the first of the first diode and the second diode to the non-conducting state.

7. The method according to claim 6, wherein: The enhanced passive circuit also includes a capacitor circuit branch, which includes a first capacitor and a second capacitor connected in series with each other, and the capacitor circuit branch is connected in parallel to the leading bridge arm and the lagging bridge arm. The method also includes: increasing the amplitude of the current in the inductor, and fully charging the first of the first capacitor and the second capacitor and fully discharging the second of the first capacitor and the second capacitor; and switching the second of the first diode and the second diode to a conductive state.

8. A method of assembling an enhanced passive circuit to a phase-shift modulated full-bridge power inverter, the phase-shift modulated full-bridge power inverter being configured for use in a wireless power transmission system, the power inverter comprising: Advanced bridge arm; Lagging bridge arm; A first output terminal connected from a leading bridge arm connection point in the leading bridge arm; as well as A second output terminal connected from a lagging bridge arm connection point in the lagging bridge arm; The method comprises: connecting a capacitor circuit branch in parallel to the leading bridge arm and the lagging bridge arm, the capacitor circuit branch comprising a first capacitor and a second capacitor connected in series to each other at a capacitor branch connection point; connecting the diode circuit branch in parallel to the leading bridge arm and the lagging bridge arm, the diode circuit branch comprising a first diode and a second diode connected in series with each other at a diode branch connection point; and An inductor is connected to the capacitor branch connection point and the diode branch connection point at a first inductor terminal, and is connected to one of the first output terminal and the second output terminal at a second inductor terminal.

9. An enhanced passive circuit component kit for assembly to a phase-shift modulated full-bridge power inverter, the phase-shift modulated full-bridge power inverter being configured for use in a wireless power transmission system, the enhanced passive circuit component kit comprising: a first capacitor and a second capacitor connected in series with each other at a capacitor branch connection point in a capacitor circuit branch connected in parallel to a leading bridge arm and a lagging bridge arm of the power inverter; a first diode and a second diode connected in series with each other at a diode branch connection point in a diode circuit branch connected in parallel to the leading bridge arm and the lagging bridge arm; as well as An inductor is connected to the capacitor branch connection point and the diode branch connection point at a first inductor terminal and is connected to one of a power inverter first output terminal and a power inverter second output terminal at a second inductor terminal.

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