Epitaxial wafer and preparation method thereof

Abstract

The invention discloses an epitaxial wafer and a preparation method thereof, and belongs to the technical field of semiconductor manufacturing. The preparation method of the epitaxial wafer is used for forming an epitaxial layer on a substrate, the epitaxial layer comprises a plurality of epitaxial sub-layers, and the preparation method comprises the following steps: determining the number n of the epitaxial sub-layers according to the preset thickness D0 [mu] m of the epitaxial layer; forming an epitaxial layer on the substrate, wherein the epitaxial layer comprises n layers of epitaxial sub-layers which are stacked; wherein the average thickness of the epitaxial sub-layer is H0 [mu] m, D0 / H0 is greater than or equal to 2 and less than or equal to 5, D0 is equal to nH0, and n is a positive integer greater than or equal to 2. According to the preset thickness D0 [mu] m of the epitaxial layer, the layer number n of the epitaxial sub-layers is determined, the epitaxial layer is formed on the substrate, the epitaxial layer comprises the n layers of epitaxial sub-layers which are arranged in a stacked mode, that is, the epitaxial layer is divided into the multiple epitaxial sub-layers to be formed for multiple times, foreign particles on the surface of the epitaxial layer can be effectively reduced, and therefore the quality of the epitaxial wafer is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to an epitaxial wafer and a method for preparing the same. Background Art

[0002] Silicon carbide (SiC) is a semiconductor material with excellent performance. It has outstanding advantages such as large bandgap, high thermal conductivity, high breakdown field strength, high electron saturation drift rate, high temperature resistance, and radiation resistance. In recent years, it has been widely used in important fields such as new energy vehicles, photovoltaic power generation, 5G communications, smart grids, and national defense. At present, chemical vapor deposition is generally used to prepare silicon carbide epitaxial layers, but the growth rate is low and cannot meet the needs of thick films. At the same time, compared with the growth of thin epitaxial layers, the growth of thick epitaxial layers is inevitably accompanied by a longer growth time. As the epitaxial growth time increases, the particles in the chamber will fall onto the surface of the epitaxial wafer, resulting in an increase in triangular defects (the sum of Triangle and Pit Triangle), thereby reducing the quality of the epitaxial wafer and the device yield. Summary of the invention

[0003] The purpose of the present application is to provide a method for preparing an epitaxial wafer, which can reduce the defect density and thus improve the quality of the epitaxial wafer.

[0004] The embodiment of the present application provides a method for preparing an epitaxial wafer, which is used to form an epitaxial layer on a substrate, wherein the epitaxial layer includes a plurality of stacked epitaxial sub-layers, and the preparation method includes:

[0005] Determining the number n of the epitaxial sublayers according to the preset thickness D0 μm of the epitaxial layer;

[0006] forming the epitaxial layer on the substrate, wherein the epitaxial layer comprises n epitaxial sublayers stacked in layers;

[0007] The average thickness of the epitaxial sublayer is H0 μm, which satisfies: 2≤D0 / H0≤5, and D0=nH0, where n is a positive integer greater than or equal to 2.

[0008] In some embodiments, the preset thickness D0 μm satisfies: 30 μm≤D0≤100 μm.

[0009] In some embodiments, the average thickness H0 μm satisfies: 10 μm≤H0≤35 μm.

[0010] In some embodiments, during the process of forming the epitaxial layer on the substrate, a purge step is performed between adjacent epitaxial sub-layers.

[0011] In some embodiments, the preset thickness D0 μm satisfies: 30 μm≤D0≤50 μm, and the number of layers n of the epitaxial sublayer satisfies n=2; or,

[0012] The preset thickness D0 μm satisfies: 50 μm≤D0≤70 μm, and the number of layers n of the epitaxial sublayer satisfies n=3; or,

[0013] The preset thickness D0 μm satisfies: 70 μm≤D0≤100 μm, and the number of layers n of the epitaxial sublayer satisfies n=4.

[0014] In some embodiments, before forming the epitaxial layer on the substrate, the method further includes:

[0015] placing the substrate in a reaction chamber;

[0016] A buffer layer is formed on the substrate.

[0017] In some embodiments, after placing the substrate in the reaction chamber, the method further includes:

[0018] The temperature of the reaction chamber is raised to a first preset temperature T1° C. to perform etching on the substrate.

[0019] In some implementations, after etching the substrate, the method further includes:

[0020] The temperature of the reaction chamber is lowered from the first preset temperature T1°C to the second preset temperature T2°C;

[0021] Wherein, the first preset temperature T1°C and the second preset temperature T2°C satisfy: 1.0125T2≤T1≤1.05T2.

[0022] In some embodiments, the first preset temperature T1°C satisfies: 1600°C≤T1≤1680°C.

[0023] In some embodiments, the second preset temperature T2°C satisfies: 1580°C≤T2≤1600°C.

[0024] In some embodiments, a first carbon source and a first silicon source are introduced into the reaction chamber to form a buffer layer on the substrate;

[0025] A second carbon source and a second silicon source are introduced into the reaction chamber to form the epitaxial layer on a side of the buffer layer away from the substrate.

[0026] In some embodiments, the first carbon source includes a first carbon element, the second carbon source includes a second carbon element, and the ratio of the number of atoms of the first carbon element to the second carbon element is 0.1 to 0.3.

[0027] In some embodiments, the first silicon source includes a first silicon element, the second silicon source includes a second silicon element, and the ratio of the number of atoms of the first silicon element to the second silicon element is 0.25.

[0028] In some embodiments, the first carbon source includes a first carbon element, the first silicon source includes a first silicon element, the ratio of the number of atoms of the first carbon element to the first silicon element is a first carbon-silicon ratio w1, the second carbon source includes a second carbon element, the second silicon source includes a second silicon element, the ratio of the number of atoms of the first carbon element to the first silicon element is a second carbon-silicon ratio w2, and the first carbon-silicon ratio w1 and the second carbon-silicon ratio w2 satisfy: 1.4w1≤w2≤1.6w1.

[0029] In some embodiments, the first carbon-to-silicon ratio w1 satisfies: 0.4≤w1≤0.6.

[0030] In some embodiments, the second carbon-to-silicon ratio w2 satisfies: 0.64≤w2≤0.96.

[0031] In some embodiments, the flow rate of the first carbon source is 15 to 22.5 sccm.

[0032] In some embodiments, the flow rate of the first silicon source is 75 sccm.

[0033] In some embodiments, the flow rate of the second carbon source is 96-144 sccm.

[0034] In some embodiments, the flow rate of the second silicon source is 300 sccm.

[0035] In some embodiments, a first doping source is introduced during the process of forming a buffer layer on the substrate; a second doping source is introduced during the process of forming the epitaxial layer on the side of the buffer layer away from the substrate; wherein the flow rate of the first doping source is 50 to 300 sccm; and / or the flow rate of the second doping source is 150 to 450 sccm.

[0036] The embodiment of the present application further provides an epitaxial wafer, which is prepared by the method for preparing the epitaxial wafer as described above, and the epitaxial wafer comprises:

[0037] substrate;

[0038] a buffer layer, the buffer layer being located on one side of the substrate;

[0039] The epitaxial layer is located on a side of the buffer layer away from the substrate, and the epitaxial layer includes a plurality of epitaxial sub-layers stacked together.

[0040] In some embodiments, the buffer layer has a first carbon-to-silicon ratio w1, and the epitaxial layer has a second carbon-to-silicon ratio w2, satisfying: 1.4w1≤w2≤1.6w1.

[0041] In some embodiments, the first carbon-to-silicon ratio w1 satisfies: 0.4≤w1≤0.6.

[0042] In some embodiments, the second carbon-to-silicon ratio w2 satisfies: 0.64≤w2≤0.96.

[0043] In some embodiments, the thickness of the substrate is 340-360 μm.

[0044] In some embodiments, the buffer layer has a thickness of 0.8-1 μm.

[0045] In some embodiments, the epitaxial layer has a thickness of 30 to 100 μm.

[0046] The beneficial effects of this application are:

[0047] The present application provides a method for preparing an epitaxial wafer, which is used to form an epitaxial layer on a substrate, wherein the epitaxial layer includes multiple epitaxial sublayers, and the preparation method includes: determining the number of epitaxial sublayers n according to the preset thickness D0μm of the epitaxial layer; forming an epitaxial layer on the substrate, wherein the epitaxial layer includes n stacked epitaxial sublayers; wherein the average thickness of the epitaxial sublayer is H0μm, and satisfies: 2≤D0 / H0≤5, and D0=nH0, and n is a positive integer greater than or equal to 2. The present application determines the number of epitaxial sublayers n according to the preset thickness D0μm of the epitaxial layer, and forms an epitaxial layer on the substrate, wherein the epitaxial layer includes n stacked epitaxial sublayers, that is, the epitaxial layer is divided into multiple epitaxial sublayers and formed multiple times, which can effectively reduce the particle foreign matter on the surface of the epitaxial layer, thereby improving the quality of the epitaxial wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 A schematic diagram of the structure of the epitaxial wafer provided in this application;

[0049] Figure 2 A flow chart of a method for preparing an epitaxial wafer provided in an embodiment of the present application;

[0050] Figure 3 A surface defect map of the epitaxial wafer provided in Example 1 of the present application;

[0051] Figure 4 A surface defect map of the epitaxial wafer provided in Example 2 of the present application;

[0052] Figure 5 A surface defect map of the epitaxial wafer provided in Example 3 of the present application;

[0053] Figure 6 Surface defect map of the epitaxial wafer provided for comparative example 1 of the present application;

[0054] Figure 7 A surface defect map of an epitaxial wafer provided for comparative example 2 of the present application;

[0055] In the accompanying drawings, the components represented by the reference numerals are as follows:

[0056] 10. Substrate; 20. Epitaxial layer; 21. Epitaxial sublayer; 30. Buffer layer. DETAILED DESCRIPTION

[0057] The technical solution of the present application will be described clearly and completely below in conjunction with the embodiments and drawings of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. The various embodiments of the present application may exist in the form of a range; it should be understood that the description in the form of a range is only for convenience and simplicity, and should not be understood as a rigid limitation on the scope of the present application; therefore, it should be considered that the range description has specifically disclosed all possible sub-ranges and single values ​​within the range. For example, it should be considered that the range description from 1 to 6 has specifically disclosed sub-ranges, such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., as well as single numbers within the range, such as 1, 2, 3, 4, 5 and 6, which are applicable regardless of the range. In addition, whenever a numerical range is indicated in this article, it is meant to include any quoted numbers (fractions or integers) within the indicated range.

[0058] like Figure 1-Figure 2 As shown, the embodiment of the present application provides a method for preparing an epitaxial wafer, which is used to form an epitaxial layer 20 on a substrate 10, wherein the epitaxial layer 20 includes a plurality of epitaxial sublayers 21, and the preparation method includes:

[0059] Step S1: Determine the number n of epitaxial sublayers 21 according to a preset thickness D0 μm of the epitaxial layer 20; wherein the average thickness of the epitaxial sublayer 21 is H0 μm, satisfying: 2≤D0 / H0≤5, and D0=nH0, where n is a positive integer greater than or equal to 2;

[0060] Step S2: forming an epitaxial layer 20 on the substrate 10, wherein the epitaxial layer 20 comprises n stacked epitaxial sublayers 21. Specifically, the value of D0 / H0 can be any ratio of 2, 3, 4, 5 or a range consisting of any two ratios.

[0061] It can be understood that the average thickness of the epitaxial sublayer 21 is the quotient of the total thickness of multiple epitaxial sublayers 21 and the number of epitaxial sublayers 21. The present application determines the number n of epitaxial sublayers based on the preset thickness D0μm of the epitaxial layer 20, and forms the epitaxial layer 20 on the substrate 10. The epitaxial layer 20 includes n stacked epitaxial sublayers 21, which can effectively reduce the granular foreign matter on the surface of the epitaxial layer 20, thereby improving the quality of the epitaxial wafer.

[0062] In some embodiments, the preset thickness D0 μm satisfies: 30 μm ≤ D0 ≤ 100 μm. Specifically, the preset thickness D0 μm may be any one of 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, and 100 μm, or a range consisting of any two values.

[0063] It can be understood that the epitaxial wafer formed in the present application is a thick epitaxial wafer, and the 4H-SiC power device prepared from the epitaxial wafer has the characteristics of high voltage, high current, high power, etc.

[0064] In some embodiments, the average thickness H0 μm satisfies: 10 μm ≤ D0 ≤ 35 μm. The average thickness H0 μm may be any one of 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, and 35 μm, or a range consisting of any two values.

[0065] In some embodiments, during the process of forming the epitaxial layer 20 on the substrate 10 , a purge step is performed between adjacent epitaxial sub-layers 21 .

[0066] It is understandable that in the process of forming the epitaxial layer 20, the particles in the reaction chamber will fall onto the surface of the epitaxial wafer, resulting in an increase in epitaxial wafer defects, thereby reducing the quality of the epitaxial wafer and the device yield. The present application determines the number n of epitaxial sublayers 21 according to the preset thickness D0μm of the epitaxial layer 20, and forms the epitaxial layer 20 on the substrate 10. The epitaxial layer 20 includes n stacked epitaxial sublayers 21, and a purging step is performed between adjacent epitaxial sublayers 21. This can effectively reduce the particle foreign matter on the surface of the epitaxial layer 20, thereby improving the quality of the epitaxial wafer.

[0067] In some embodiments, performing the purging step includes:

[0068] Hydrogen gas is introduced into the reaction chamber to purge the reaction chamber.

[0069] It is understandable that in the process of forming the epitaxial layer 20, the particles in the reaction chamber will fall onto the surface of the epitaxial wafer, resulting in an increase in epitaxial wafer defects, thereby reducing the quality of the epitaxial wafer and the device yield. The present application forms multiple epitaxial sublayers 21 and performs a purging step between adjacent epitaxial sublayers 21, which can effectively reduce the particle foreign matter on the surface of the epitaxial layer 20, thereby improving the quality of the epitaxial wafer.

[0070] In some embodiments, the purging time is 30 to 50 seconds. Specifically, the purging time can be any one of 30 seconds, 35 seconds, 40 seconds, 45 seconds, and 50 seconds, or a range consisting of any two of the values.

[0071] In some embodiments, the preset thickness D0 μm satisfies: 30 μm≤D0≤50 μm, and the number of layers n of the epitaxial sublayer 21 satisfies n=2.

[0072] It is understandable that during the process of forming the epitaxial layer 20, the particles in the reaction chamber will fall onto the surface of the epitaxial wafer, resulting in an increase in epitaxial wafer defects, thereby reducing the quality of the epitaxial wafer and the device yield. For the epitaxial layer 20 with a preset thickness D0μm that satisfies: 30μm≤D0≤50μm, the present application can effectively reduce the particle foreign matter on the surface of the epitaxial layer 20 by forming two epitaxial sub-layers, thereby improving the quality of the epitaxial wafer.

[0073] In some embodiments, the preset thickness D0 μm satisfies: 50 μm≤D0≤70 μm, and the number of layers n of the epitaxial sublayer 21 satisfies n=3.

[0074] It is understandable that during the process of forming the epitaxial layer 20, the particles in the reaction chamber will fall onto the surface of the epitaxial wafer, resulting in an increase in epitaxial wafer defects, thereby reducing the quality of the epitaxial wafer and the device yield. For the epitaxial layer 20 with a preset thickness D0μm that satisfies: 50μm≤D0≤70μm, the present application can effectively reduce the particle foreign matter on the surface of the epitaxial layer 20 by forming three epitaxial sublayers 21, thereby improving the quality of the epitaxial wafer.

[0075] In some embodiments, the preset thickness D0 μm satisfies: 70 μm≤D0≤100 μm, and the number of layers n of the epitaxial sublayer 21 satisfies n=4.

[0076] It is understandable that in the process of forming the epitaxial layer 20, the particles in the reaction chamber will fall onto the surface of the epitaxial wafer, resulting in an increase in epitaxial wafer defects, thereby reducing the quality of the epitaxial wafer and the device yield. For the epitaxial layer 20 with a preset thickness D0μm that satisfies: 70μm≤D0≤100μm, the present application forms 4 epitaxial sublayers 21, which can effectively reduce the particle foreign matter on the surface of the epitaxial layer 20, thereby improving the quality of the epitaxial wafer.

[0077] In some embodiments, before forming a plurality of stacked epitaxial sub-layers on the substrate 10, the method further includes:

[0078] Placing the substrate 10 in the reaction chamber;

[0079] A buffer layer 30 is formed on the substrate 10 .

[0080] In some embodiments, after placing the substrate 10 in the reaction chamber, the method further includes:

[0081] The temperature of the reaction chamber is raised to a first preset temperature T1° C. to perform an etching process on the substrate 10 .

[0082] It can be understood that by etching the substrate 10 , the contact surface between the substrate 10 and the buffer layer 30 can be cleaned and improved, thereby reducing the defect density and further improving the crystal quality.

[0083] In some embodiments, an etching gas is introduced into the reaction chamber to perform an etching process on the substrate 10 .

[0084] In some embodiments, the etching gas is selected from hydrogen.

[0085] In some embodiments, the etching time is 7 to 10 minutes. Specifically, the etching time can be any one of 7 minutes, 7.5 minutes, 8 minutes, 8.5 minutes, 9 minutes, 9.5 minutes, and 10 minutes, or a range consisting of any two of the values.

[0086] It can be understood that, in the present application, by etching the substrate 10 for 7 to 10 minutes, the contact surface between the substrate 10 and the buffer layer 30 can be cleaned and improved, thereby reducing the defect density and further improving the crystal quality.

[0087] In some embodiments, the temperature of the reaction chamber is increased from the standby temperature T0°C to the first preset temperature T1°C.

[0088] In some embodiments, the standby temperature T0°C satisfies: 800°C≤T0≤900°C. Specifically, the standby temperature T0°C may be any one of 800°C, 820°C, 840°C, 850°C, 860°C, 880°C, and 900°C, or a range consisting of any two of the values.

[0089] In some embodiments, the time for raising the temperature of the reaction chamber from the standby temperature T0°C to the first preset temperature T1°C is the first heating time, and the first heating time is 10 to 13 minutes. Specifically, the first heating time can be any one of 10 minutes, 10.5 minutes, 11 minutes, 11.5 minutes, 12 minutes, 12.5 minutes, and 13 minutes, or a range consisting of any two values.

[0090] In some embodiments, after the temperature of the reaction chamber is raised to the first preset temperature T1°C, the method further includes: performing a first heat preservation step to stabilize the temperature of the reaction chamber at the first preset temperature T1°C.

[0091] In some embodiments, the time for performing the first insulation step is the first insulation time, and the first insulation time is 1 to 2 minutes. Specifically, the first insulation time can be any one of 1 minute, 1.5 minutes, and 2 minutes, or a range consisting of any two values.

[0092] In some embodiments, after etching the substrate 10, the method further includes:

[0093] The temperature of the reaction chamber is lowered from a first preset temperature T1°C to a second preset temperature T2°C;

[0094] The first preset temperature T1°C and the second preset temperature T2°C satisfy: 1.0125T2≤T1≤1.05T2. Specifically, the ratio of T1 to T2 can be any one of 1.0125, 1.02, 1.03, 1.04, 1.05, or a range consisting of any two values.

[0095] It is understandable that a reasonable heat treatment is performed on the surface of the substrate 10 so that the surface of the substrate 10 is etched more uniformly, thereby controlling the thickness uniformity of the epitaxial layer 20 .

[0096] In some embodiments, the time for cooling the temperature of the reaction chamber from the first preset temperature T1°C to the second preset temperature T2°C is the first cooling time, and the first cooling time is 10 to 13 minutes. Specifically, the first cooling time can be any one of 10 minutes, 10.5 minutes, 11 minutes, 11.5 minutes, 12 minutes, 12.5 minutes, and 13 minutes, or a range consisting of any two values.

[0097] In some embodiments, after the temperature of the reaction chamber is cooled from the first preset temperature T1° C. to the second preset temperature T2° C., a second heat preservation step is further performed to stabilize the temperature of the reaction chamber at the second preset temperature T2.

[0098] In some embodiments, the time for performing the second insulation step is the second insulation time, and the second insulation time is 1 to 2 minutes. Specifically, the second insulation time can be any one of 1 minute, 1.5 minutes, and 2 minutes, or a range consisting of any two values.

[0099] In some embodiments, the first preset temperature T1°C satisfies: 1600°C≤T1≤1680°C. Specifically, the first preset temperature T1°C may be any one of 1600°C, 1620°C, 1640°C, 1660°C, 1680°C, or a range consisting of any two values.

[0100] In some embodiments, the second preset temperature T2°C satisfies: 1580°C≤T2≤1600°C. Specifically, the second preset temperature T2°C may be any one of 1580°C, 1585°C, 1590°C, 1595°C, and 1600°C, or a range consisting of any two of the values.

[0101] In some embodiments, a first carbon source and a first silicon source are introduced into the reaction chamber to form a buffer layer 30 on the substrate 10;

[0102] A second carbon source and a second silicon source are introduced into the reaction chamber to form an epitaxial layer 20 on a side of the buffer layer 30 facing away from the substrate 10 .

[0103] It can be understood that by passing the first carbon source and the first silicon source into the reaction chamber and controlling their flow rates, a buffer layer 30 is formed on the substrate 10, and by passing the second carbon source and the second silicon source into the reaction chamber and controlling their flow rates, an epitaxial layer 20 is formed on the side of the buffer layer 30 facing away from the substrate 10.

[0104] In some embodiments, the first carbon source includes a first carbon element, the second carbon source includes a second carbon element, and the ratio of the number of atoms of the first carbon element to the second carbon element is 0.1 to 0.3. Specifically, the ratio of the number of atoms of the first carbon element to the second carbon element can be any one of 0.1, 0.15, 0.2, 0.25, 0.3, or a range consisting of any two values.

[0105] It can be understood that the number of atoms of the first carbon element in the first carbon source is related to the flow rate and molecular formula of the first carbon source, and the number of atoms of the second carbon element in the second carbon source is related to the flow rate and molecular formula of the second carbon source. When the molecular formulas of the first carbon source and the second carbon source are the same, the ratio of the number of atoms of the first carbon element to the second carbon element is also the flow ratio of the first carbon source to the second carbon source.

[0106] In some embodiments, the first silicon source includes a first silicon element, the second silicon source includes a second silicon element, and the ratio of the number of atoms of the first silicon element to the second silicon element is 0.25.

[0107] It can be understood that the number of atoms of the first silicon element in the first silicon source is related to the flow rate and molecular formula of the first silicon source, and the number of atoms of the second silicon element in the second silicon source is related to the flow rate and molecular formula of the second silicon source. When the molecular formulas of the first silicon source and the second silicon source are the same, the ratio of the number of atoms of the first silicon element to the second silicon element is also the ratio of the flow rates of the first silicon source to the second silicon source.

[0108] In some embodiments, the first carbon source includes a first carbon element, the first silicon source includes a first silicon element, the ratio of the number of atoms of the first carbon element to the first silicon element is a first carbon-silicon ratio w1, the second carbon source includes a second carbon element, the second silicon source includes a second silicon element, the ratio of the number of atoms of the first carbon element to the first silicon element is a second carbon-silicon ratio w2, and the first carbon-silicon ratio w1 and the second carbon-silicon ratio w2 satisfy: 1.4w1≤w2≤1.6w1. Specifically, the value of w2 / w1 can be any one of 1.4, 1.45, 1.5, 1.55, 1.6, or a range consisting of any two values.

[0109] It can be understood that the buffer layer 30 has a first carbon-to-silicon ratio w1, and the epitaxial layer 20 has a second carbon-to-silicon ratio w2. By controlling the growth process of the buffer layer 30 and the epitaxial layer 20, the first carbon-to-silicon ratio w1 and the second carbon-to-silicon ratio w2 satisfy: 1.4w1≤w2≤1.6w1. The growth rate of the epitaxial layer 20 can be adjusted to control the thickness of the epitaxial layer 20, thereby improving the crystal quality.

[0110] In some embodiments, the first carbon-to-silicon ratio w1 satisfies: 0.4≤w1≤0.6. Specifically, the first carbon-to-silicon ratio w1 may be any one of 0.4, 0.45, 0.5, 0.55, and 0.6, or a range consisting of any two of the values.

[0111] It can be understood that the buffer layer 30 provides a flat surface during the epitaxial growth process, reduces the stress and defects of the substrate 10, and the buffer layer 30 has a lower carbon-silicon ratio, which means that the silicon content in the buffer layer 30 is relatively high, while the carbon content is relatively low, which can improve the uniformity of the doping concentration of the buffer layer 30 and thus improve the crystal quality.

[0112] In some embodiments, the second carbon-to-silicon ratio w2 satisfies: 0.64≤w2≤0.96. Specifically, the second carbon-to-silicon ratio w2 may be any one of 0.64, 0.7, 0.75, 0.8, 0.85, 0.9, and 0.96, or a range consisting of any two of the values.

[0113] It is understandable that the epitaxial layer 20 has a higher carbon-silicon ratio, which means that the carbon content in the epitaxial layer 20 is relatively high, while the silicon content is relatively low, which can improve the uniformity of the doping concentration of the epitaxial layer 20 and thus improve the crystal quality.

[0114] In some embodiments, the flow rate of the first carbon source is 15 to 22.5 sccm. Specifically, the flow rate of the first carbon source can be any one of 15 sccm, 16 sccm, 17 sccm, 18 sccm, 19 sccm, 20 sccm, 21 sccm, 22 sccm, and 22.5 sccm, or a range consisting of any two of the values.

[0115] In some embodiments, the flow rate of the first silicon source is 75 sccm.

[0116] In some embodiments, the first carbon source is selected from at least one of ethylene, acetylene, methane, and propane.

[0117] In some embodiments, the first silicon source is selected from at least one of silane or silane derivatives.

[0118] In some embodiments, the silane derivative is selected from at least one of dichlorosilane, trichlorosilane, and tetrachlorosilane.

[0119] In some embodiments, the flow rate of the second carbon source is 96 to 144 sccm. Specifically, the flow rate of the second carbon source can be any one of 96 sccm, 100 sccm, 105 sccm, 110 sccm, 115 sccm, 120 sccm, 125 sccm, 130 sccm, 135 sccm, 140 sccm, and 144 sccm, or a range consisting of any two of the values.

[0120] In some embodiments, the flow rate of the second silicon source is 300 sccm.

[0121] In some embodiments, the second carbon source is selected from at least one of ethylene, acetylene, methane, and propane.

[0122] In some embodiments, the second silicon source is selected from at least one of silane or silane derivatives.

[0123] In some embodiments, the silane derivative is selected from at least one of dichlorosilane, trichlorosilane, and tetrachlorosilane.

[0124] In some embodiments, during the process of forming the buffer layer 30 on the substrate 10, a first doping source is also introduced; the flow rate of the first doping source is 50 to 300 sccm. Specifically, the flow rate of the first doping source can be any one of 50 sccm, 100 sccm, 150 sccm, 200 sccm, 250 sccm, and 300 sccm, or a range consisting of any two values.

[0125] In some embodiments, during the process of forming the epitaxial layer 20 on the side of the buffer layer 30 facing away from the substrate 10, a second doping source is also introduced; the flow rate of the second doping source is 150 to 450 sccm. Specifically, the flow rate of the second doping source can be any one of 150 sccm, 200 sccm, 250 sccm, 300 sccm, 350 sccm, 400 sccm, and 450 sccm, or a range consisting of any two values.

[0126] In some embodiments, the first doping source is selected from an n-type doping source or a p-type doping source.

[0127] In some embodiments, the n-type doping source is selected from nitrogen (N2) or ammonia (NH3).

[0128] In some embodiments, the p-type dopant source is selected from trimethylaluminum (TMA).

[0129] In some embodiments, the second doping source is selected from an n-type doping source or a p-type doping source.

[0130] In some embodiments, the n-type doping source is selected from nitrogen (N2) or ammonia (NH3).

[0131] In some embodiments, the p-type dopant source is selected from trimethylaluminum (TMA).

[0132] In some embodiments, the first carbon source and the second carbon source can be the same or different.

[0133] In some embodiments, the first silicon source and the second silicon source can be the same or different.

[0134] In some embodiments, the first doping source and the second doping source may be the same or different.

[0135] In some embodiments, after forming the epitaxial layer 20 on the substrate 10, the method further includes:

[0136] The temperature of the reaction chamber is cooled from the second preset temperature T2°C to the standby temperature T0°C.

[0137] In some embodiments, the time for cooling the temperature of the reaction chamber from the second preset temperature T2°C to the standby temperature T0°C is the cooling time, and the cooling time is 10 to 13 minutes. Specifically, the cooling time can be any one of 10 minutes, 10.5 minutes, 11 minutes, 11.5 minutes, 12 minutes, 12.5 minutes, and 13 minutes, or a range consisting of any two values.

[0138] In some embodiments, the gas flow rate is directly controlled by a mass flow meter; the liquid flow rate is controlled by controlling the carrier gas flow rate to control the flow rate of the corresponding liquid.

[0139] The embodiment of the present application further provides an epitaxial wafer, which is prepared by the above-mentioned method for preparing an epitaxial wafer, and the epitaxial wafer comprises:

[0140] Substrate 10;

[0141] A buffer layer 30, wherein the buffer layer 30 is located on one side of the substrate 10;

[0142] The epitaxial layer 20 is located on a side of the buffer layer 30 facing away from the substrate 10 . The epitaxial layer 20 includes a plurality of epitaxial sub-layers 21 stacked together.

[0143] In some embodiments, the buffer layer 30 has a first carbon-to-silicon ratio w1, and the epitaxial layer 20 has a second carbon-to-silicon ratio w2, satisfying: 1.4w1≤w2≤1.6w1.

[0144] It can be understood that the buffer layer 30 has a first carbon-to-silicon ratio w1, and the epitaxial layer 20 has a second carbon-to-silicon ratio w2. By controlling the growth process of the buffer layer 30 and the epitaxial layer 20 so that the first carbon-to-silicon ratio w1 and the second carbon-to-silicon ratio w2 satisfy: 1.4w1≤w2≤1.6w1, the uniformity of the doping concentration of the epitaxial layer 20 can be improved, thereby improving the crystal quality.

[0145] In some embodiments, the first carbon-to-silicon ratio w1 satisfies: 0.4≤w1≤0.6. Specifically, the first carbon-to-silicon ratio w1 may be any one of 0.4, 0.45, 0.5, 0.55, and 0.6, or a range consisting of any two of the values.

[0146] It can be understood that the buffer layer 30 provides a flat surface during the epitaxial growth process, reduces the stress and defects of the substrate 10, and the buffer layer 30 has a lower carbon-silicon ratio, which means that the silicon content in the buffer layer 30 is relatively high, while the carbon content is relatively low, which can improve the uniformity of the doping concentration of the buffer layer 30 and thus improve the crystal quality.

[0147] In some embodiments, the second carbon-to-silicon ratio w2 satisfies: 0.64≤w2≤0.96. Specifically, the second carbon-to-silicon ratio w2 may be any one of 0.64, 0.7, 0.75, 0.8, 0.85, 0.9, and 0.96, or a range consisting of any two of the values.

[0148] It is understandable that the epitaxial layer 20 has a higher carbon-silicon ratio, which means that the carbon content in the epitaxial layer 20 is relatively high, while the silicon content is relatively low, which can improve the uniformity of the doping concentration of the epitaxial layer 20 and thus improve the crystal quality.

[0149] In some embodiments, the thickness of the substrate 10 is 340-360 μm. Specifically, the thickness of the substrate 10 can be any one of 340 μm, 345 μm, 350 μm, 355 μm, and 360 μm, or a range consisting of any two of the values.

[0150] It can be understood that the substrate 10 is the basis for the formation of the buffer layer 30 and the epitaxial layer 20; the thickness of the substrate 10 is usually determined according to specific application requirements and preparation processes.

[0151] In one embodiment, the substrate 10 is made of silicon carbide.

[0152] In some embodiments, the thickness of the buffer layer 30 is 0.8-1 μm. Specifically, the thickness of the buffer layer 30 can be any one of 0.8 μm, 0.85 μm, 0.9 μm, 0.95 μm, and 1 μm, or a range consisting of any two of the values.

[0153] It can be understood that the buffer layer 30 is used to reduce the defects on the substrate 10 from extending to the epitaxial layer 20. If the thickness of the buffer layer 30 is too thin, it may not be able to reduce the defects on the substrate 10. If the thickness of the buffer layer 30 is too thick, new defects may be introduced. Therefore, controlling the thickness of the buffer layer 30 to 0.8 to 1 μm can reduce the impact of the defects on the substrate 10 on the epitaxial layer 20, thereby improving the crystal quality.

[0154] In some embodiments, the thickness of the epitaxial layer 20 is 30-100 μm. Specifically, the thickness of the epitaxial layer 20 can be any one of 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, and 100 μm, or a range consisting of any two of the values.

[0155] It is understandable that the thickness of the epitaxial layer 20 has an important influence on the performance and characteristics of the semiconductor device. A thinner epitaxial layer 20 can provide better electron transport performance and higher carrier mobility, thereby improving the speed and efficiency of the device. On the other hand, a thicker epitaxial layer 20 can increase the capacity and current carrying capacity of the device; the thickness of the epitaxial layer 20 is usually determined according to the specific application requirements and the preparation process.

[0156] The present application will be described below with reference to specific embodiments.

[0157] Example 1

[0158] Step S11: placing a silicon carbide substrate in a reaction chamber of an epitaxial furnace, wherein the thickness of the silicon carbide substrate is 350 μm;

[0159] Step S12: raising the temperature of the reaction chamber from 850°C (standby temperature T0°C) to 1620°C (first preset temperature T1°C) within 10 minutes, and keeping the temperature for 2 minutes;

[0160] Step S13: introducing hydrogen (etching gas) into the reaction chamber to etch the silicon carbide substrate for 8 minutes;

[0161] Step S14: lowering the temperature of the reaction chamber from 1620° C. (the first preset temperature T1° C.) to 1580° C. (the second preset temperature T2° C.) within 2 minutes, and keeping the temperature for 2 minutes;

[0162] Step S15: introducing ethylene (first carbon source) with a flow rate of 19 sccm, trichlorosilane (first silicon source) with a flow rate of 75 sccm, and nitrogen (first doping source) with a flow rate of 100 sccm into the reaction chamber to grow a silicon carbide buffer layer on the silicon carbide substrate. The growth time of the silicon carbide buffer layer is 7 min, the thickness of the silicon carbide buffer layer is 1 um, and the carbon-silicon ratio of the silicon carbide buffer layer (first carbon-silicon ratio w1) is 0.5;

[0163] Step S16: Ethylene (the second carbon source) with a flow rate of 120 sccm, trichlorosilane (the second silicon source) with a flow rate of 300 sccm, and nitrogen (the second doping source) with a flow rate of 200 sccm are introduced into the reaction chamber to form four silicon carbide epitaxial sublayers on the side of the silicon carbide buffer layer away from the silicon carbide substrate. The thickness of the silicon carbide epitaxial sublayers is 25 um, and the reaction chamber is purged for 45 s between two adjacent silicon carbide epitaxial sublayers. The growth time of the silicon carbide epitaxial layer is 110 min, the thickness of the silicon carbide epitaxial layer is 100 um, and the carbon-silicon ratio of the silicon carbide epitaxial layer (the second carbon-silicon ratio w2) is 0.8.

[0164] Step S17: The temperature of the reaction chamber is cooled from 1580° C. (the second preset temperature T2° C.) to 850° C. (the standby temperature T0° C.) within 10 minutes to obtain an epitaxial wafer.

[0165] Example 2

[0166] The preparation method of Example 2 is the same as that of Example 1, except that: Step S16: 120 sccm of ethylene (the second carbon source) and 300 sccm of trichlorosilane (the second silicon source) are introduced into the reaction chamber to form three silicon carbide epitaxial sublayers on the side of the silicon carbide buffer layer away from the silicon carbide substrate, the thickness of the first silicon carbide epitaxial sublayer is 30 um, the thickness of the second silicon carbide epitaxial sublayer and the third silicon carbide epitaxial sublayer are 15 um, respectively, the reaction chamber is purged for 45 s between two adjacent silicon carbide epitaxial sublayers, the growth time of the silicon carbide epitaxial layer is 70 min, the thickness of the silicon carbide epitaxial layer is 60 um, and the carbon-silicon ratio of the silicon carbide epitaxial layer (the second carbon-silicon ratio w2) is 0.8.

[0167] Example 3

[0168] The preparation method of Example 3 is the same as that of Example 1, except that: Step S16: 120 sccm of ethylene (the second carbon source) and 300 sccm of trichlorosilane (the second silicon source) are introduced into the reaction chamber to form two silicon carbide epitaxial sublayers on the side of the silicon carbide buffer layer away from the silicon carbide substrate, and the thickness of the silicon carbide epitaxial sublayers is 20 um. The reaction chamber is purged for 45 s between two adjacent silicon carbide epitaxial sublayers. The growth time of the silicon carbide epitaxial layer is 45 min, the thickness of the silicon carbide epitaxial layer is 40 um, and the carbon-silicon ratio of the silicon carbide epitaxial layer (the second carbon-silicon ratio w2) is 0.8.

[0169] Comparative Example 1

[0170] The preparation method of Comparative Example 1 is the same as that of Example 1, except that: Step S16: 120 sccm of ethylene (the second carbon source) and 300 sccm of trichlorosilane (the second silicon source) are introduced into the reaction chamber to form a silicon carbide epitaxial layer on the side of the silicon carbide buffer layer away from the silicon carbide substrate, the growth time of the silicon carbide epitaxial layer is 110 min, the thickness of the silicon carbide epitaxial layer is 100 um, and the carbon-silicon ratio of the silicon carbide epitaxial layer (the second carbon-silicon ratio w2) is 0.8.

[0171] Comparative Example 2

[0172] The preparation method of Comparative Example 2 is the same as that of Example 1, except that: Step S16: 120 sccm of ethylene (the second carbon source), 300 sccm of trichlorosilane (the second silicon source), and 200 sccm of nitrogen (the second doping source) are introduced into the reaction chamber to form two silicon carbide epitaxial sublayers on the side of the silicon carbide buffer layer away from the silicon carbide substrate, and the thickness of the silicon carbide epitaxial sublayers is 50 um, and the reaction chamber is purged for 45 s between two adjacent silicon carbide epitaxial sublayers. The growth time of the silicon carbide epitaxial layer is 110 min, the thickness of the silicon carbide epitaxial layer is 100 um, and the carbon-silicon ratio of the silicon carbide epitaxial layer (the second carbon-silicon ratio w2) is 0.8.

[0173] Comparative Example 3

[0174] The preparation method of comparative example 3 is the same as that of example 1, except that: step S12: raising the temperature of the reaction chamber from 850°C (standby temperature T0°C) to 1580°C (second preset temperature T2°C) within 10 minutes, and keeping the temperature for 2 minutes;

[0175] Step S13: hydrogen (etching gas) is introduced into the reaction chamber to etch the silicon carbide substrate for 8 minutes.

[0176] Comparative Example 4

[0177] The preparation method of Comparative Example 4 is the same as that of Example 1, except that: Step S16: 19 sccm ethylene (second carbon source), 75 sccm trichlorosilane (second silicon source) and 200 sccm nitrogen (second doping source) are introduced into the reaction chamber to form four silicon carbide epitaxial sublayers on the side of the silicon carbide buffer layer away from the silicon carbide substrate, and the thickness of the silicon carbide epitaxial sublayers is 25 um, and the reaction chamber is purged for 45 s between two adjacent silicon carbide epitaxial sublayers. The growth time of the silicon carbide epitaxial layer is 750 min, the thickness of the silicon carbide epitaxial layer is 100 um, and the carbon-silicon ratio of the silicon carbide epitaxial layer (the second carbon-silicon ratio w2) is 0.5.

[0178] Measurement method:

[0179] (1) The BPD defect density of the epitaxial layer was tested using a surface defect tester (Candela8520 from KLA-Tencor). The test results are as follows: Figures 3 to 7 shown.

[0180] (2) The film thickness was measured by Fourier transform infrared spectrometer, and the doping concentration was measured by mercury probe (mercury CV) tester.

[0181] (3) Doping concentration uniformity: standard deviation of the doping concentration of 10 measurement points on the epitaxial layer / arithmetic mean of the doping concentration of 10 measurement points on the epitaxial layer×100%.

[0182] (4) Thickness uniformity: standard deviation of thickness at 10 measurement points on the epitaxial layer / arithmetic mean of thickness at 10 measurement points on the epitaxial layer×100%.

[0183] Table 1 shows the test results of Examples 1 to 3 and Comparative Examples 1 to 4.

[0184]

[0185] Result analysis:

[0186] By comparing Examples 1 to 3 with Comparative Example 1, it can be seen that the present application forms multiple epitaxial sublayers, that is, forms the silicon carbide epitaxial layer in multiple times, and performs a purging step between adjacent silicon carbide epitaxial sublayers, which can effectively reduce particulate foreign matter on the surface of the silicon carbide epitaxial layer and reduce defect density, thereby improving the quality of the epitaxial wafer.

[0187] By comparing Examples 1 to 3 with Comparative Example 2, it can be seen that for an epitaxial layer having a thickness greater than 70 μm, the epitaxial layer is divided into silicon carbide epitaxial sublayers and formed four times, and a purging step is performed between adjacent silicon carbide epitaxial sublayers. This can effectively reduce particulate foreign matter on the surface of the silicon carbide epitaxial layer and reduce defect density, thereby improving the quality of the epitaxial wafer.

[0188] By comparing Example 1 with Comparative Example 3, it can be seen that by adopting a suitable etching temperature to perform reasonable heat treatment on the surface of the silicon carbide substrate, the surface of the silicon carbide substrate can be etched more uniformly, and the thickness uniformity of the silicon carbide epitaxial layer can be improved.

[0189] By comparing Example 1 and Comparative Example 4, it can be seen that by making the first carbon-silicon ratio w1 and the second carbon-silicon ratio w2 satisfy: 1.4w1≤w2≤1.6w1, the growth rate of the silicon carbide epitaxial layer can be adjusted to control the thickness of the silicon carbide epitaxial layer, improve the uniformity of the doping concentration of the silicon carbide epitaxial layer, and thus improve the crystal quality.

[0190] The above is a detailed introduction to the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A method for preparing an epitaxial wafer, characterized in that: For forming an epitaxial layer (20) on a substrate (10), the epitaxial layer (20) comprising a plurality of epitaxial sublayers (21), the preparation method comprising: Determining the number n of layers of the epitaxial sublayer (21) according to a preset thickness D0 μm of the epitaxial layer (20); Forming the epitaxial layer (20) on the substrate (10), wherein the epitaxial layer (20) comprises n epitaxial sublayers (21) stacked in layers; The average thickness of the epitaxial sublayer (21) is H0 μm, which satisfies: 2≤D0 / H0≤5, and D0=nH0, where n is a positive integer greater than or equal to 2.

2. The method for preparing an epitaxial wafer according to claim 1, characterized in that: The preset thickness D0 μm satisfies: 30 μm≤D0≤100 μm; and / or the average thickness H0 μm satisfies: 10 μm≤H0≤35 μm.

3. The method for preparing an epitaxial wafer according to claim 1, characterized in that: During the process of forming the epitaxial layer (20) on the substrate (10), a purging step is performed between adjacent epitaxial sublayers (21).

4. The method for preparing an epitaxial wafer according to claim 1, characterized in that: The preset thickness D0 μm satisfies: 30 μm≤D0≤50 μm, and the number of layers n of the epitaxial sublayer (21) satisfies n=2; or, The preset thickness D0 μm satisfies: 50 μm≤D0≤70 μm, and the number of layers n of the epitaxial sublayer (21) satisfies n=3; or, The preset thickness D0 μm satisfies: 70 μm≤D0≤100 μm, and the number n of layers of the epitaxial sublayer (21) satisfies n=4.

5. The method for preparing an epitaxial wafer according to claim 1, characterized in that: Before forming the epitaxial layer (20) on the substrate (10), the method further comprises: Placing the substrate (10) in a reaction chamber; A buffer layer (30) is formed on the substrate (10).

6. The method for preparing an epitaxial wafer according to claim 5, characterized in that: After placing the substrate (10) in the reaction chamber, the method further comprises: The temperature of the reaction chamber is raised to a first preset temperature T1° C., so as to perform an etching process on the substrate (10).

7. The method for preparing an epitaxial wafer according to claim 6, characterized in that: After etching the substrate (10), the method further comprises: The temperature of the reaction chamber is lowered from the first preset temperature T1°C to the second preset temperature T2°C; Wherein, the first preset temperature T1°C and the second preset temperature T2°C satisfy: 1.0125T2≤T1≤1.05T2.

8. The method for preparing an epitaxial wafer according to claim 7, characterized in that: The first preset temperature T1°C satisfies: 1600°C≤T1≤1680°C; and / or, The second preset temperature T2°C satisfies: 1580°C≤T2≤1600°C.

9. The method for preparing an epitaxial wafer according to claim 5, characterized in that: introducing a first carbon source and a first silicon source into the reaction chamber to form a buffer layer (30) on the substrate (10); A second carbon source and a second silicon source are introduced into the reaction chamber to form the epitaxial layer (20) on the side of the buffer layer (30) facing away from the substrate (10).

10. The method for preparing an epitaxial wafer according to claim 9, characterized in that: The first carbon source includes a first carbon element, the second carbon source includes a second carbon element, and the atomic ratio of the first carbon element to the second carbon element is 0.1 to 0.3; and / or, The first silicon source includes a first silicon element, the second silicon source includes a second silicon element, and the ratio of the number of atoms of the first silicon element to the number of atoms of the second silicon element is 0.

25.

11. The method for preparing an epitaxial wafer according to claim 9, characterized in that: The first carbon source includes a first carbon element, the first silicon source includes a first silicon element, the ratio of the number of atoms of the first carbon element to the first silicon element is a first carbon-silicon ratio w1, the second carbon source includes a second carbon element, the second silicon source includes a second silicon element, the ratio of the number of atoms of the first carbon element to the first silicon element is a second carbon-silicon ratio w2, and the first carbon-silicon ratio w1 and the second carbon-silicon ratio w2 satisfy: 1.4w1≤w2≤1.6w1.

12. The method for preparing an epitaxial wafer according to claim 11, characterized in that: The first carbon-to-silicon ratio w1 satisfies: 0.4≤w1≤0.6; and / or, The second carbon-to-silicon ratio w2 satisfies: 0.64≤w2≤0.

96.

13. The method for preparing an epitaxial wafer according to claim 9, characterized in that: The flow rate of the first carbon source is 15 to 22.5 sccm; and / or, The flow rate of the first silicon source is 75 sccm; and / or, The flow rate of the second carbon source is 96 to 144 sccm; and / or, The flow rate of the second silicon source is 300 sccm.

14. The method for preparing an epitaxial wafer according to claim 9, characterized in that: During the process of forming the buffer layer (30) on the substrate (10), a first doping source is also introduced; during the process of forming the epitaxial layer (20) on the side of the buffer layer (30) away from the substrate (10), a second doping source is also introduced; wherein the flow rate of the first doping source is 50 to 300 sccm; and / or the flow rate of the second doping source is 150 to 450 sccm.

15. An epitaxial wafer, characterized in that: The epitaxial wafer is prepared by the method for preparing an epitaxial wafer according to any one of claims 1 to 14, wherein the epitaxial wafer comprises: A substrate (10); A buffer layer (30), the buffer layer (30) being located on one side of the substrate (10); An epitaxial layer (20), the epitaxial layer (20) being located on a side of the buffer layer (30) facing away from the substrate (10), the epitaxial layer (20) comprising a plurality of epitaxial sublayers (21) stacked in layers.

16. The epitaxial wafer according to claim 15, characterized in that: The buffer layer (30) has a first carbon-to-silicon ratio w1, and the epitaxial layer (20) has a second carbon-to-silicon ratio w2, satisfying: 1.4w1≤w2≤1.6w1.

17. The epitaxial wafer according to claim 16, characterized in that: The first carbon-to-silicon ratio w1 satisfies: 0.4≤w1≤0.6; and / or, The second carbon-to-silicon ratio w2 satisfies: 0.64≤w2≤0.96; and / or, The thickness of the substrate (10) is 340 to 360 μm; and / or, The thickness of the buffer layer (30) is 0.8 to 1 μm; and / or, The thickness of the epitaxial layer (20) is 30-100 μm.

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