Fault current loop circuit, multi-source oscillation experiment loop circuit and control method thereof

Abstract

The invention provides a fault current loop, a multi-source oscillation experiment loop, a control method of the multi-source oscillation experiment loop, electronic equipment and a non-instantaneous computer readable storage medium. The fault current loop circuit comprises at least one fault current branch, and the at least one fault current branch comprises a discharge end which is connected to the first common end; the charging ends are connected to the second common end; the grounding ends are connected to the third common end; the fault current branch comprises a fault current energy storage branch, the negative electrode end of the fault current energy storage branch is electrically connected to the third common end, and the fault current energy storage branch comprises an energy storage capacitor; and the energy storage capacitor overturning branch circuit is connected in parallel with the energy storage capacitor and is used for performing voltage correction on the energy storage capacitor. According to the embodiment of the invention, the energy storage capacitor is subjected to multiple times of voltage correction through the energy storage capacitor overturning branch until the energy of the energy storage capacitor is consumed completely, so that the problem of multiplexing of the LC oscillation branch in the fault current loop circuit can be solved, and the cost is saved.

Description

Technical Field

[0001] The present application relates to the technical field of high-voltage direct current transmission, and in particular to a fault current loop, a multi-source oscillation experimental loop and a control method thereof, an electronic device, and a non-transient computer-readable storage medium. Background Art

[0002] In order to solve the problem of commutation failure on the receiving side of the HVDC transmission system, some scholars have proposed in recent years to use a converter valve with controllable shutdown capability on the receiving system side, that is, to add a controllable shutdown device to the original converter valve bridge arm to achieve forced commutation, thereby effectively avoiding the occurrence of commutation failure.

[0003] In order to verify the ability of the converter valve to forcibly shut off large currents in the laboratory, a fault current loop is required to simulate the multi-cycle fault current generated when the AC system is short-circuited. There are usually two types of short-circuit current generation systems currently used: one is to use a generator, but this solution has high equipment cost and occupies a large area; the other is to use a capacitor and inductor oscillation (also known as LC oscillation) circuit, which has low cost and small footprint, and is a relatively economical solution. However, each fault current in the LC oscillation circuit needs to be configured with an LC oscillation branch. Existing test systems are usually only configured with three oscillation branches to meet the needs of three-cycle fault currents. For fault current requirements of more than three cycles, configuring multiple LC oscillation branches will bring about a large construction cost.

[0004] Therefore, it is necessary to propose a multi-source oscillation test circuit and its control method and control device to solve the problem of multiplexing of LC oscillation branches in the current fault current system, save equipment costs, and be more in line with the characteristics of short-circuit current oscillation attenuation during actual faults. Summary of the invention

[0005] The present application aims to propose a fault current loop, a multi-source oscillation experimental loop and a control method thereof, an electronic device, and a non-transient computer-readable storage medium to solve the problem of multiplexing of LC oscillation branches in a fault current loop circuit.

[0006] According to one aspect of the present application, a fault current loop circuit is provided, comprising at least one fault current branch, wherein the at least one fault current branch comprises: a discharge terminal, each connected to a first common terminal; a charging terminal, each connected to a second common terminal; and a ground terminal, each connected to a third common terminal;

[0007] The fault current branch includes a fault current energy storage branch, the negative end of the fault current energy storage branch is electrically connected to the third common end, wherein the fault current energy storage branch includes: an energy storage capacitor; and an energy storage capacitor reversal branch, which is connected in parallel with the energy storage capacitor and is used to reverse the voltage of the energy storage capacitor.

[0008] According to some embodiments, the energy storage capacitor flipping branch includes a fault current voltage flipping inductor; and a fault current voltage flipping valve connected in series with the fault current voltage flipping inductor, and the anode end of the fault current voltage flipping valve is electrically connected to the third common terminal.

[0009] According to some embodiments, the fault current energy storage branch further includes an energy storage capacitor discharge branch connected in parallel with the energy storage capacitor for discharging the energy storage capacitor.

[0010] According to some embodiments, the energy storage capacitor discharge branch includes a discharge resistor and a grounding isolation switch connected in series.

[0011] According to some embodiments, the fault current branch further includes a fault current discharge branch, a negative terminal of the fault current discharge branch is electrically connected to the first common terminal, and a positive terminal of the fault current discharge branch is electrically connected to the positive terminal of the fault current energy storage branch.

[0012] According to some embodiments, the fault current discharge branch includes a discharge isolation switch; a fault current phase selection valve connected in series with the discharge isolation switch, and a negative terminal of the valve is electrically connected to the first common terminal.

[0013] According to some embodiments, the fault current branch further includes a fault current charging branch, wherein a first end of the fault current charging branch is electrically connected to a positive terminal of the fault current energy storage branch, and a second end of the fault current charging branch is electrically connected to the second common terminal.

[0014] According to some embodiments, the fault current charging branch comprises a charging isolation switch.

[0015] According to some embodiments, an oscillating inductor and a fault current isolation valve are further included, wherein the oscillating inductor and the fault current isolation valve are connected in series, one end of the oscillating inductor is electrically connected to the fourth common terminal, and the other end of the oscillating inductor is electrically connected to the first common terminal.

[0016] According to some embodiments, the fault current loop circuit further includes a high voltage DC power supply, one end of which is electrically connected to the ground terminal of the fault current branch, and the other end of which is electrically connected to the second common terminal.

[0017] According to some embodiments, the fault current isolation valve, the fault current phase selection valve, and the fault current voltage reversal valve are power semiconductor units with reverse blocking capability, and the power semiconductor units include at least one of a thyristor and a reverse-blocking IGCT connected in series and parallel, or a combination of at least one of an IGBT, a MOSFET, and a reverse-conducting IGCT and a diode connected in series and parallel.

[0018] According to one aspect of the present application, a multi-source oscillation experimental loop circuit is proposed, which includes a fault current loop circuit as described in any of the previous embodiments, characterized in that the multi-source oscillation experimental loop circuit also includes a high voltage loop circuit, a large current loop circuit and a test valve, wherein: the high voltage loop circuit, the large current loop circuit, the test valve and the fault current loop circuit are connected in parallel, and one end of the high voltage loop circuit, the large current loop circuit, the fault current loop circuit and the test valve are electrically connected to a fourth common terminal, and the other end is electrically connected to a third common terminal.

[0019] According to one aspect of the present application, a control method for a multi-source oscillation experimental loop circuit as described in any of the previous embodiments is provided, comprising the following steps:

[0020] S1: disconnect the grounding isolating switch and the discharging isolating switch in the fault current loop circuit, and close the charging isolating switch in the fault current loop circuit;

[0021] S2: Using a high voltage DC power supply to charge the energy storage capacitor in the fault current loop circuit;

[0022] S3: disconnecting the charging isolating switch in the fault current loop circuit, and closing the discharging isolating switch in the fault current loop circuit;

[0023] S4: During the test valve opening stage, the fault current phase selection valve and the fault current isolation valve in the fault current loop circuit are opened to apply the superposition of the fault current and the large current loop circuit current to the test valve;

[0024] S5: Turn on the fault current voltage reversal valve of the discharged fault current branch to realize the voltage reversal of the energy storage capacitor;

[0025] S6: Determine whether the energy storage capacitor voltage meets the preset trigger condition. If the energy storage capacitor voltage meets the trigger condition, execute step S4 after a preset delay.

[0026] According to some embodiments, the fault current isolation valve is turned on while any one of the fault current phase selection valves is turned on.

[0027] According to one aspect of the present application, a control device for a multi-source oscillation circuit is provided, characterized in that it is used to execute the control method as described in any of the previous embodiments, and the control device includes:

[0028] A high voltage loop control unit, used for status monitoring, output voltage control and fault protection of each converter of the high voltage loop circuit;

[0029] A high current loop control unit, used for status monitoring, output current control and fault protection of each converter of the high current loop circuit;

[0030] A coordination control unit, used for coordinating and controlling the high voltage loop circuit, the high current loop circuit, the test valve, and the fault current loop circuit;

[0031] A fault current loop control unit, used for status monitoring and triggering conduction, energy storage capacitor charging voltage control and fault protection of the fault current isolation valve, fault current phase selection valve, high-voltage DC power supply, and fault current voltage reversal valve of the fault current loop circuit;

[0032] An input-output unit, used to perform data exchange with the high voltage loop control unit, the high current loop control unit, the fault current loop control unit, and the coordination control unit, so as to send trigger pulses to the high voltage loop circuit, the high current loop circuit, the test valve, and the fault current loop circuit, and receive status information output by the high voltage loop circuit, the high current loop circuit, the test valve, and the fault current loop circuit;

[0033] The human-machine interface unit is used to perform signal interaction with the input-output unit and the external PC, receive input instructions from the external PC and status information from the input-output unit, and send control instructions to the input-output unit.

[0034] According to one aspect of the present application, an electronic device is provided, comprising a processor; and a memory storing a computer program, wherein when the computer program is executed by the processor, the processor executes the control method as described in any of the previous embodiments.

[0035] According to one aspect of the present application, a non-transitory computer-readable storage medium is provided, on which computer-readable instructions are stored. When the instructions are executed by a processor, the processor executes the control method described in any of the previous embodiments.

[0036] According to the embodiments of the present application, the voltage of the energy storage capacitor is reversed multiple times through the energy storage capacitor flipping branch until the energy of the energy storage capacitor is consumed. This can solve the problem of multiplexing of LC oscillation branches in the fault current loop circuit, thereby saving costs.

[0037] It should be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. By describing the exemplary embodiments in detail with reference to the drawings, the above and other objectives, features and advantages of the present application will become more apparent.

[0039] Figure 1 A block diagram of a fault current loop circuit according to an exemplary embodiment of the present application is shown.

[0040] Figure 2 A circuit block diagram of a multi-source oscillation experimental loop according to an exemplary embodiment of the present application is shown.

[0041] Figure 3 A schematic diagram of a multi-source oscillation experimental loop circuit according to an exemplary embodiment of the present application is shown.

[0042] Figure 4 A schematic diagram of a multi-source oscillation experimental loop circuit structure according to an exemplary embodiment of the present application is shown.

[0043] Figure 5 A flow chart of a control method for a multi-source oscillation experimental loop circuit according to an exemplary embodiment of the present application is shown.

[0044] Figure 6 A block diagram of a control device for a multi-source oscillation loop according to an exemplary embodiment of the present application is shown.

[0045] Figure 7 A triggering timing diagram of each valve group of a multi-source oscillation test circuit according to an exemplary embodiment of the present application is shown.

[0046] Figure 8 An electronic device according to an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0047] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this application will be comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. In the figures, the same figures show the same or similar parts, and thus their repeated description will be omitted.

[0048] The user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0049] The described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of these specific details, or other modes, components, materials, devices or operations may be adopted. In these cases, known structures, methods, devices, implementations, materials or operations will not be shown or described in detail.

[0050] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0051] The terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0052] The specific embodiments of the present application are described in detail below in conjunction with the accompanying drawings.

[0053] Figure 1 A block diagram of a fault current loop circuit according to an exemplary embodiment of the present application is shown. According to an embodiment of the present application, the fault current loop circuit includes at least one fault current branch. Among them, at least one fault current branch includes a discharge terminal, a charging terminal and a grounding terminal. Among them, the discharge terminal is connected to the first common terminal, the charging terminal is connected to the second common terminal, and the grounding terminal is connected to the third common terminal.

[0054] In some embodiments, the fault current branch includes a fault current energy storage branch, wherein a negative terminal of the fault current energy storage branch is electrically connected to the third common terminal.

[0055] In a specific embodiment, the fault current energy storage branch includes an energy storage capacitor and an energy storage capacitor reversal branch, wherein the energy storage capacitor reversal branch is connected in parallel with the energy storage capacitor to perform voltage reversal on the energy storage capacitor.

[0056] according to Figure 1In the embodiment shown, the voltage of the energy storage capacitor is reversed multiple times by the energy storage capacitor flipping branch until the energy of the energy storage capacitor is consumed, which can solve the problem of multiplexing of LC oscillation branches in the fault current loop circuit, thereby saving costs.

[0057] In a specific embodiment, the energy storage capacitor reversal branch includes a fault current voltage reversal inductor and a fault current voltage reversal valve. The fault current voltage reversal valve is connected in series with the fault current voltage reversal inductor, and the anode terminal of the fault current voltage reversal valve is electrically connected to the third common terminal. In this embodiment, the voltage of the energy storage capacitor is reversed by using the fault current voltage reversal valve, thereby realizing the continuous oscillation output of the fault current, solving the problem of multiplexing the LC oscillation branch in the fault current loop circuit, and saving costs.

[0058] According to an embodiment of the present application, the fault current energy storage branch further includes an energy storage capacitor discharge branch, wherein the energy storage capacitor discharge branch is connected in parallel with the energy storage capacitor for discharging the energy storage capacitor.

[0059] In a specific embodiment, the energy storage capacitor discharge branch includes a discharge resistor and a grounding isolation switch connected in series.

[0060] According to an embodiment of the present application, the fault current branch further includes a fault current discharge branch, wherein the negative terminal of the fault current discharge branch is electrically connected to the first common terminal, and the positive terminal of the fault current discharge branch is electrically connected to the positive terminal of the fault current energy storage branch.

[0061] In a specific embodiment, the fault current discharge branch includes a discharge isolating switch and a fault current phase selection valve, wherein the fault current phase selection valve is connected in series with the discharge isolating switch, and the negative terminal is electrically connected to the first common terminal.

[0062] According to an embodiment of the present application, the fault current branch further includes a fault current charging branch, wherein a first end of the fault current charging branch is electrically connected to the positive terminal of the fault current energy storage branch, and a second end of the fault current charging branch is electrically connected to the second common terminal.

[0063] In a specific embodiment, the fault current charging branch includes a charging isolation switch.

[0064] According to an embodiment of the present application, Figure 1 The fault current loop circuit shown also includes an oscillating inductor and a fault current isolation valve, wherein the oscillating inductor and the fault current isolation valve are connected in series, wherein one end of the series connection is electrically connected to the fourth common terminal, and the other end is electrically connected to the first common terminal.

[0065] According to an embodiment of the present application, Figure 1The fault current loop circuit shown also includes a high-voltage DC power supply, wherein one end of the high-voltage DC power supply is electrically connected to the grounding end of the fault current branch, and the other end is electrically connected to the second common end.

[0066] In some embodiments, the fault current isolation valve, fault current phase selection valve, and fault current voltage reversal valve are power semiconductor units with reverse blocking capability, and the power semiconductor units include at least one of a thyristor or a reverse-blocking IGCT connected in series / parallel, or a combination of at least one of an IGBT, a MOSFET, and a reverse-conducting IGCT and a diode in series / parallel.

[0067] Figure 2 A circuit block diagram of a multi-source oscillation experimental loop according to an exemplary embodiment of the present application is shown. Figure 2 The multi-source oscillation experimental circuit shown includes: Figure 1 The fault current loop circuit 201, the high voltage loop circuit 203, the large current loop circuit 205 and the test valve 207 are shown. Among them, the high voltage loop circuit 203, the large current loop circuit 205 and the test valve 207 are connected in parallel with the fault current loop circuit 201, and one end of the high voltage loop circuit 203, the large current loop circuit 205, the test valve 207 and the fault current loop circuit 201 is electrically connected to the fourth common terminal, and the other end is electrically connected to the third common terminal.

[0068] Figure 3 A schematic diagram of a multi-source oscillation experimental circuit according to an exemplary embodiment of the present application is shown. Figure 3 The multi-source oscillation test loop circuit shown includes a high voltage loop, a large current loop, a fault current loop circuit and a test valve connected in parallel.

[0069] like Figure 3 As shown, one end of the high voltage circuit, the high current circuit, the fault current circuit and the test valve is electrically connected to the common terminal A. The other end of the high voltage circuit, the high current circuit, the fault current circuit and the test valve is electrically connected to the common terminal D.

[0070] exist Figure 3 In the embodiment shown, the fault current loop circuit includes an oscillating inductor L R , Fault current isolation valve V 60 , at least one fault current branch and a high-voltage DC power supply. The discharge ends of the fault current branches are electrically connected to the common terminal A, the charging ends of the fault current branches are electrically connected to the common terminal A, and are electrically connected to the positive terminal of the high-voltage DC power supply, and the grounding ends of the fault current branches are electrically connected to the negative terminal of the high-voltage DC.

[0071] In a specific embodiment, the high voltage circuit is used to apply voltage to the test valve, and the high current circuit and the fault current circuit are used to apply current to the test valve.

[0072] Figure 4 FIG. 4 shows a schematic diagram of a circuit structure of a multi-source oscillation experimental loop according to an exemplary embodiment of the present application. Figure 4 The multi-source oscillation experimental loop circuit shown includes multiple fault current branches, wherein the fault current branch includes a fault current energy storage branch, a fault current discharge branch, and a fault current charging branch.

[0073] like Figure 4 As shown, the negative end of the fault current energy storage branch is electrically connected to the common terminal D, and the negative end of the fault current discharge branch is connected to the common terminal A. One end of the fault current charging branch is electrically connected to the positive end of the fault current discharge branch and the positive end of the fault current energy storage branch, and the other end of the fault current charging branch is electrically connected to the positive end of the high voltage DC voltage at the common terminal B.

[0074] In some embodiments, the fault current energy storage branch includes an energy storage capacitor (ie, C s1 , C s2 , ... or C sn ), an energy storage capacitor discharge branch and an energy storage capacitor voltage reversal branch connected in parallel with the energy storage capacitor.

[0075] like Figure 4 The energy storage capacitor discharge branch includes a discharge resistor (ie, R G1 , R G2 , ... or R Gn ) and grounding disconnect switch (also known as K G1 , K G2 , ... or K Gn ); the energy storage capacitor voltage reversal branch includes a series-connected fault current voltage reversal inductor (ie, L R1 , L R2 , ... or L Rn ) and the fault current voltage reversal valve (also known as V 611 、V 621 , ... or V 6n1 ), the anode terminal of the fault current voltage reversal valve is electrically connected to the common terminal D.

[0076] According to some embodiments, the fault current discharge branch includes a fault current phase selection valve (ie, V 61 、V 62 , ... or V 6n ) and the discharge isolating switch (also known as K F1 , K F2 , ... or K Fn ).

[0077] According to some embodiments, the fault current charging branch includes a charging isolation switch. Figure 4 K shownC1 , K C2 , ... or K Cn .

[0078] According to some embodiments, the fault current isolation valve, the fault current phase selection valve, and the fault current voltage reversal valve are power semiconductor units with reverse blocking capability, and the power semiconductor units include at least one of a thyristor and a reverse-blocking IGCT connected in series and parallel, or a combination of at least one of an IGBT, a MOSFET, and a reverse-conducting IGCT and a diode connected in series and parallel.

[0079] Figure 5 A flow chart of a control method of a multi-source oscillation experimental loop circuit according to an exemplary embodiment of the present application is shown below. Figure 5 Taking as an example, a control method for a multi-source oscillation experimental loop circuit in an exemplary embodiment of the present application is described in detail.

[0080] like Figure 5 The control method shown includes steps S1 to S6.

[0081] In step S1, the grounding isolating switch and the discharging isolating switch in the fault current loop circuit are opened, and the charging isolating switch in the fault current loop circuit is closed.

[0082] According to an embodiment of the present application, before step S1, at least one fault current branch needs to be determined according to the number of fault current cycles.

[0083] For example, when the number of fault current cycles is 3, three fault current energy storage branches, fault current discharge branches and fault current charging branches that are electrically connected are selected respectively, and a plurality of non-overlapping current waves applied to the test valve are generated in sequence respectively using a preset delay.

[0084] For another example, when the number of fault current cycles is 3, one fault current energy storage branch, one fault current discharge branch and one fault current charging branch that are electrically connected are selected respectively, and a preset delay is used to generate multiple non-overlapping current waves applied to the test valve.

[0085] In step S2, a high voltage DC power supply is used to charge the energy storage capacitor in the selected fault current loop circuit.

[0086] In step S3, the charging isolating switch in the fault current loop circuit is opened, and the discharging isolating switch in the fault current loop circuit is closed.

[0087] In step S4, during the test valve opening stage, the fault current phase selection valve and the fault current isolation valve in the selected fault current loop circuit are opened to apply the superposition of the fault current and the large current loop circuit current to the test valve.

[0088] In step S5, the fault current voltage reversal valve of the discharged fault current branch is turned on to realize the voltage reversal of the energy storage capacitor.

[0089] In step S6, it is determined whether the energy storage capacitor voltage meets the preset triggering condition. If the energy storage capacitor voltage meets the triggering condition, step S4 is executed after a preset delay (eg, 20 ms). If the energy storage capacitor voltage does not meet the re-triggering condition, the process ends.

[0090] According to the embodiment of the present application, in order to prevent the fault current loop current pulse from overlapping, it is necessary to apply the fault current and the high current loop circuit current to the test valve after a preset delay. That is, when the energy storage capacitor voltage meets the triggering condition, step S4 is executed after a preset delay (for example, 20ms).

[0091] In a specific embodiment, the voltage of the energy storage capacitor of the discharged fault current branch will change from positive to negative. When the fault current voltage reversal valve of the branch is turned on, the voltage of the energy storage capacitor will change from negative to positive, and the branch will meet the discharge conditions again.

[0092] For example, Figure 4 As shown, assuming that the energy storage capacitor C S1 When the voltage is positive at the top and negative at the bottom, V 61 、V 60 The conduction condition is met, and the condition for applying the fault current to the test valve is met. After the fault current is applied, the energy storage capacitor C S1 The voltage is negative at the top and positive at the bottom. 611 With conduction conditions, V 611 After conduction, the energy storage capacitor C S1 The voltage goes up positive and down negative again, and now it is connected to C S1 Connected fault current branches (including V 61 and K F1 ) The condition for the test valve to apply a fault current is met again, that is, the trigger condition is met.

[0093] For example, Figure 4 As shown, assuming that the energy storage capacitor C S1 , C S2 When the voltage is positive at the top and negative at the bottom, V 61 、V 62 The conduction condition is met, and the condition for applying fault current to the test valve is met. 60 、V 61 、V 62 After the fault current is applied, the voltage of the energy storage capacitor C S1 , C S2 Negative on top and positive on bottom, at this time V 611 and V 621The conduction condition is met. 611 After the on command is applied, the energy storage capacitor C S1 The voltage goes up positive and down negative again, and now it is connected to C S1 Connected fault current branches (including V 61 and K F1 ) again meets the conditions for the test valve to apply fault current, that is, the trigger condition is met. Before the conduction command is applied, the capacitor C S2 The voltage is still negative at the top and positive at the bottom.

[0094] According to the embodiments of the present application, Figure 5 In the illustrated embodiment, the fault current isolation valve is turned on at the same time when any one of the fault current phase selection valves is turned on.

[0095] Figure 6 A block diagram of a control device for a multi-source oscillation circuit according to an exemplary embodiment of the present application is shown, which is used to perform the following steps: Figure 5 The control method shown.

[0096] like Figure 6 The control device shown includes a high voltage circuit control unit 1 , a high current circuit control unit 2 , a coordination control unit 3 , a fault current circuit control unit 4 , an input and output unit 5 and a human-machine interface unit 6 .

[0097] like Figure 6 As shown, the high voltage loop control unit 1 is used to perform status monitoring, output voltage control and fault protection on each converter of the high voltage loop circuit; the high current loop control unit 2 is used to perform status monitoring, output current control and fault protection on each converter of the high current loop circuit; the coordination control unit 3 is used to coordinate and control the high voltage loop circuit, the high current loop circuit, the test valve and the fault current loop circuit; the fault current loop control unit 4 is used to monitor the status of the fault current isolation valve, the fault current phase selection valve, the high voltage DC power supply and the fault current voltage reversal valve of the fault current loop circuit and trigger the conduction, the energy storage capacitor charging valve The input-output unit 5 is used for data exchange with the high-voltage loop control unit, the high-current loop control unit, the fault current loop control unit, and the coordination control unit to send trigger pulses to the high-voltage loop circuit, the high-current loop circuit, the test valve, and the fault current loop circuit, and receive status information output by the high-voltage loop circuit, the high-current loop circuit, the test valve, and the fault current loop circuit; the human-machine interface unit 6 is used for signal exchange with the input-output unit and the external PC, receive input instructions from the external PC and status information from the input-output unit, and send control instructions to the input-output unit.

[0098] like Figure 6The control device shown also includes a power supply unit 7 to provide power to the high voltage circuit control unit 1 , the high current circuit control unit 2 , the coordination control unit 3 , the fault current circuit control unit 4 , the input and output unit 5 and the human-machine interface unit 6 .

[0099] Figure 7 A triggering timing diagram of each valve group of a multi-source oscillation test circuit according to an exemplary embodiment of the present application is shown.

[0100] like Figure 7 As shown, CP Vt is the test valve trigger pulse, CP 60 Trigger pulse for fault current isolation valve, CP 61 , CP 62 ,…,CP 6n are the fault current phase selection valve trigger pulse, CP 611 , CP 621 ,…,CP 6n1 They are respectively the fault current reversal valve trigger pulses.

[0101] In a specific embodiment, during the test valve opening stage, the fault current phase selection valve and the fault current isolation valve of the fault current are opened, and the fault current and the large current loop current are superimposed and applied to the test valve. When the fault current phase selection valve of any fault current branch is turned on, the fault current isolation valve is turned on at the same time. After the energy storage capacitor is discharged, the fault current voltage reversal valve of the discharged fault current branch is turned on to realize the positive voltage reversal of the energy storage capacitor, and it is judged whether the energy storage capacitor voltage has the re-triggering condition. If the re-triggering condition is met, after a preset delay, the fault current phase selection valve and the isolation valve are opened again to superimpose the fault current and the large current loop current and apply them to the test valve again. At this time, due to the existence of loop impedance, the second oscillation current will be lower than the first oscillation current. The fault current voltage reversal valve of the discharged fault current branch is turned on again to realize the positive voltage reversal of the energy storage capacitor, and this cycle is repeated until the energy of the energy storage capacitor is consumed.

[0102] like Figure 7 As shown, the interval between the current waves of adjacent fault current loops is 20ms.

[0103] Figure 8 An electronic device according to an exemplary embodiment of the present application is shown. Figure 8 The electronic device 200 according to this embodiment of the present application is described. Figure 8 The electronic device 200 shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0104] like Figure 8As shown, the electronic device 200 is in the form of a general computing device. The components of the electronic device 200 may include, but are not limited to: at least one processing unit 210, at least one storage unit 220, a bus 230 connecting different system components (including the storage unit 220 and the processing unit 210), a display unit 240, etc.

[0105] The storage unit stores program codes, which can be executed by the processing unit 210, so that the processing unit 210 executes the methods described in this specification according to various exemplary embodiments of the present application. For example, the processing unit 210 can execute the following: Figure 1 The method shown in .

[0106] The storage unit 220 may include a readable medium in the form of a volatile storage unit, such as a random access memory unit (RAM) 2201 and / or a cache memory unit 2202 , and may further include a read-only memory unit (ROM) 2203 .

[0107] The storage unit 220 may also include a program / utility 2204 having a set (at least one) of program modules 2205, such program modules 2205 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0108] Bus 230 may represent one or more of several types of bus structures, including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

[0109] The electronic device 200 may also communicate with one or more external devices 300 (e.g., keyboards, pointing devices, Bluetooth devices, etc.), may also communicate with one or more devices that enable a user to interact with the electronic device 200, and / or communicate with any device that enables the electronic device 200 to communicate with one or more other computing devices (e.g., routers, modems, etc.). Such communication may be performed via an input / output (I / O) interface 250. Furthermore, the electronic device 200 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) via a network adapter 260. The network adapter 260 may communicate with other modules of the electronic device 200 via the bus 230. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the electronic device 200, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0110] Through the description of the above implementation methods, it is easy for those skilled in the art to understand that the example implementation methods described here can be implemented by software or by combining software with necessary hardware. The technical solution according to the implementation method of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, including several instructions to enable a computing device (which can be a personal computer, a server, or a network device, etc.) to execute the above method according to the implementation method of the present application.

[0111] The software product may use any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0112] Computer readable storage media may include data signals propagated in baseband or as part of a carrier wave, wherein readable program codes are carried. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. The readable storage medium may also be any readable medium other than a readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, device, or device. The program codes contained on the readable storage medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination thereof.

[0113] Program code for performing the operations of the present application may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0114] The computer-readable medium carries one or more programs. When the one or more programs are executed by a device, the computer-readable medium implements the aforementioned functions.

[0115] Those skilled in the art will appreciate that the above modules can be distributed in the device according to the description of the embodiment, or can be changed accordingly and only used in one or more devices different from the embodiment. The modules of the above embodiments can be combined into one module, or further divided into multiple sub-modules.

[0116] According to an embodiment of the present application, a computer program is provided, including a computer program or an instruction. When the computer program or the instruction is executed by a processor, the method described above can be executed.

[0117] The embodiments of the present application are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and its core idea of ​​the present application. At the same time, changes or deformations made by those skilled in the art based on the ideas of the present application, the specific implementation methods and the scope of application of the present application, all belong to the scope of protection of the present application. In summary, the content of this specification should not be construed as a limitation on the present application.

Claims

1. A fault current loop circuit, characterized in that: The invention comprises at least one fault current branch, wherein the at least one fault current branch comprises: The discharge terminals are connected to the first common terminal; The charging terminals are all connected to the second common terminal; The ground terminals are all connected to the third common terminal; The fault current branch includes a fault current energy storage branch, the negative terminal of the fault current energy storage branch is electrically connected to the third common terminal, The fault current energy storage branch comprises: Energy storage capacitors; and The energy storage capacitor reversing branch is connected in parallel with the energy storage capacitor and is used for reversing the voltage of the energy storage capacitor.

2. The fault current loop circuit according to claim 1, characterized in that: The energy storage capacitor flipping branch comprises: Fault current voltage reversal inductance; and A fault current and voltage reversal valve is connected in series with the fault current and voltage reversal inductor, and an anode terminal of the fault current and voltage reversal valve is electrically connected to the third common terminal.

3. The fault current loop circuit according to claim 1, characterized in that: The fault current energy storage branch also includes: The energy storage capacitor discharge branch is connected in parallel with the energy storage capacitor and is used to discharge the energy storage capacitor.

4. The fault current loop circuit according to claim 3, characterized in that: The energy storage capacitor discharge branch includes a discharge resistor and a grounding isolation switch connected in series.

5. The fault current loop circuit according to claim 2, characterized in that: The fault current branch further includes a fault current discharge branch, a negative terminal of the fault current discharge branch is electrically connected to the first common terminal, and a positive terminal of the fault current discharge branch is electrically connected to the positive terminal of the fault current energy storage branch.

6. The fault current loop circuit according to claim 5, characterized in that: The fault current discharge branch comprises: Discharge isolating switch; A fault current phase selection valve is connected in series with the discharge isolating switch, and a negative terminal thereof is electrically connected to the first common terminal.

7. The fault current loop circuit according to claim 5, characterized in that: The fault current branch further includes a fault current charging branch, wherein a first end of the fault current charging branch is electrically connected to the positive terminal of the fault current energy storage branch, and a second end of the fault current charging branch is electrically connected to the second common terminal.

8. The fault current loop circuit according to claim 7, characterized in that: The fault current charging branch includes a charging isolation switch.

9. The fault current loop circuit according to claim 6, characterized in that: Also included are oscillating inductors and fault current isolation valves, wherein The oscillating inductor and the fault current isolation valve are connected in series, one end of the oscillating inductor is electrically connected to the fourth common terminal, and the other end of the oscillating inductor is electrically connected to the first common terminal.

10. The fault current loop circuit according to claim 9, characterized in that: Also includes: A high-voltage direct current power supply has one end electrically connected to the ground terminal of the fault current branch, and the other end electrically connected to the second common terminal.

11. The fault current loop circuit according to claim 9, characterized in that: The fault current isolation valve, the fault current phase selection valve, and the fault current voltage reversal valve are power semiconductor units with reverse blocking capability, and the power semiconductor units include at least one of a thyristor and a reverse-blocking IGCT connected in series and parallel, or a combination of at least one of an IGBT, a MOSFET, and a reverse-conducting IGCT and a diode connected in series and parallel.

12. A multi-source oscillation experimental loop circuit comprising the fault current loop circuit according to any one of claims 1 to 11, characterized in that: The multi-source oscillation experimental loop circuit also includes a high voltage loop circuit, a high current loop circuit and a test valve, wherein: The high voltage loop circuit, the high current loop circuit, the test valve and the fault current loop circuit are connected in parallel. One end of each of the high voltage loop circuit, the high current loop circuit, the fault current loop circuit and the test valve is electrically connected to the fourth common terminal, and the other end is electrically connected to the third common terminal.

13. A control method for a multi-source oscillation experimental loop circuit as claimed in claim 12, characterized in that: The following steps are involved: S1: disconnect the grounding isolating switch and the discharging isolating switch in the fault current loop circuit, and close the charging isolating switch in the fault current loop circuit; S2: Using a high voltage DC power supply to charge the energy storage capacitor in the fault current loop circuit; S3: disconnecting the charging isolating switch in the fault current loop circuit, and closing the discharging isolating switch in the fault current loop circuit; S4: During the test valve opening stage, the fault current phase selection valve and the fault current isolation valve in the fault current loop circuit are opened to apply the superposition of the fault current and the large current loop circuit current to the test valve; S5: Turn on the fault current voltage reversal valve of the discharged fault current branch to realize the voltage reversal of the energy storage capacitor; S6: Determine whether the energy storage capacitor voltage meets the preset trigger condition. If the energy storage capacitor voltage meets the trigger condition, execute step S4 after a preset delay.

14. The control method according to claim 13, characterized in that: The fault current isolation valve is turned on at the same time when any one of the fault current phase selection valves is turned on.

15. A control device for a multi-source oscillation circuit, characterized in that: For executing the control method according to any one of claims 13 to 14, the control device comprises: A high voltage loop control unit, used for status monitoring, output voltage control and fault protection of each converter of the high voltage loop circuit; A high current loop control unit, used for status monitoring, output current control and fault protection of each converter of the high current loop circuit; A coordination control unit, used for coordinating and controlling the high voltage loop circuit, the high current loop circuit, the test valve, and the fault current loop circuit; A fault current loop control unit, used for status monitoring and triggering conduction, energy storage capacitor charging voltage control and fault protection of the fault current isolation valve, fault current phase selection valve, high-voltage DC power supply, and fault current voltage reversal valve of the fault current loop circuit; An input-output unit, used to perform data exchange with the high voltage loop control unit, the high current loop control unit, the fault current loop control unit, and the coordination control unit, so as to send trigger pulses to the high voltage loop circuit, the high current loop circuit, the test valve, and the fault current loop circuit, and receive status information output by the high voltage loop circuit, the high current loop circuit, the test valve, and the fault current loop circuit; The human-machine interface unit is used to perform signal interaction with the input-output unit and the external PC, receive input instructions from the external PC and status information from the input-output unit, and send control instructions to the input-output unit.

16. An electronic device, comprising: processor; as well as A memory storing a computer program, which, when executed by the processor, enables the processor to execute the control method according to any one of claims 13 to 14.

17. A non-transitory computer-readable storage medium having computer-readable instructions stored thereon, which, when executed by a processor, causes the processor to execute the control method according to any one of claims 13 to 14.

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