Radar monolithic microwave integrated circuit with context-based programming

Abstract

The invention relates to a radar monolithic microwave integrated circuit with context-based programming. A method of configuring a radar monolithic microwave integrated circuit (MMIC) and executing a command of an activated downloadable programming context is provided. The method includes receiving and storing a plurality of downloadable programming contexts sequentially received from an external controller, wherein each subsequent downloadable programming context received from the external controller is stored in a random access memory (RAM) partition of the radar MMIC that is different from a random access memory (RAM) partition of the radar MMIC for storing the latest downloadable programming context received from the external controller; sequentially activating and disabling the plurality of downloadable programming contexts according to the context execution sequence; executing a command of the activated downloadable programming context stored in the corresponding RAM partition; and downloading the next downloadable programming context prior to the time slot assigned to the next downloadable programming context in the context execution sequence.

Description

Background Art

[0001] Radar sensors are used in many applications to detect objects, where the detection typically includes measuring the distance, speed, or angle of arrival associated with the detected target. In particular, in the automotive field, there is an increasing demand for radar sensors, which can be used, for example, in driver assistance systems (e.g., advanced driver assistance systems (ADAS)), such as, for example, in adaptive cruise control (ACC) or radar cruise control systems. Such systems can automatically adjust the speed of a motor vehicle in order to maintain a safe distance from other motor vehicles traveling in front of the motor vehicle (as well as from other objects and pedestrians). Other exemplary applications of radar sensors in the automotive field include blind spot detection, lane change assistance, etc. Summary of the invention

[0002] In some embodiments, a radar monolithic microwave integrated circuit (MMIC) includes: at least one of a transmit channel for transmitting a radar signal or a receive channel for receiving a reflected radar signal; a communication interface configured to sequentially receive a plurality of downloadable programming contexts from an external controller, wherein each downloadable programming context includes a corresponding program and associated data; a random access memory (RAM) including a plurality of partitions configured to sequentially store the plurality of downloadable programming contexts received from the external controller, wherein each subsequent downloadable programming context received from the external controller is stored in a partition different from a partition for storing a most recent downloadable programming context received from the external controller; and a configuration and sequencing circuit configured to: sequentially activate and deactivate the plurality of downloadable programming contexts according to a context execution sequence, and execute an activated downloadable programming context stored in a corresponding partition of the plurality of partitions, wherein the communication interface is configured to receive a subsequent downloadable programming context before a time slot allocated to the subsequent downloadable programming context in the context execution sequence, and the RAM is configured to store the subsequent downloadable programming context.

[0003] In some embodiments, a method for configuring a radar MMIC and executing commands of an activated downloadable programming context includes: receiving and storing a plurality of downloadable programming contexts sequentially received from an external controller, wherein each downloadable programming context includes a corresponding program and associated data, wherein each subsequent downloadable programming context received from the external controller is stored in a RAM partition of the radar MMIC that is different from the RAM partition of the radar MMIC used to store the most recent downloadable programming context received from the external controller; sequentially activating and deactivating the plurality of downloadable programming contexts according to a context execution sequence; executing commands of the activated downloadable programming context stored in the corresponding RAM partition; and downloading the next downloadable programming context before a time slot allocated to the next downloadable programming context in the context execution sequence. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Embodiments are described herein with reference to the accompanying drawings.

[0005] Figure 1 is a diagram of an example application of a frequency modulated continuous wave (FMCW) radar sensor.

[0006] Figure 2 An example of frequency modulation of a transmitted radar signal transmitted by a FMCW radar sensor is illustrated.

[0007] Figure 3 is a block diagram illustrating an example structure of an FMCW radar sensor.

[0008] Figure 4 A schematic block diagram of a radar system according to one or more embodiments is shown.

[0009] Figure 5 A schematic block diagram of a radar system according to one or more embodiments is shown.

[0010] Figure 6 A flowchart illustrating an example process associated with context-based programming in accordance with one or more implementations.

[0011] Figure 7 A schematic block diagram of a radar system according to one or more embodiments is shown.

[0012] Figure 8 A flowchart illustrating an example process associated with context-based programming in accordance with one or more implementations.

[0013] Fig. 9 An example application cycle is illustrated in accordance with one or more implementations. DETAILED DESCRIPTION

[0014] In the following, details are set forth to provide a more thorough explanation of the example embodiments. However, it will be apparent to those skilled in the art that these embodiments may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form or in schematic form rather than in detail in order to avoid making the embodiments unclear. In addition, unless otherwise explicitly noted, the features of the different embodiments described below may be combined with each other.

[0015] In addition, equivalent or similar reference numerals are used in the following description to represent equivalent or similar elements or elements having equivalent or similar functions. Since the same or functionally equivalent elements are given the same reference numerals in the drawings, repeated descriptions of the elements having the same reference numerals may be omitted. Therefore, the descriptions provided for the elements having the same or similar reference numerals may be interchangeable.

[0016] Each of the x-axis, y-axis, and z-axis shown is substantially perpendicular to the other two axes. In other words, the x-axis is substantially perpendicular to the y-axis and the z-axis, the y-axis is substantially perpendicular to the x-axis and the z-axis, and the z-axis is substantially perpendicular to the x-axis and the y-axis. In some cases, a single reference numeral is shown to refer to a surface, or a small portion of all instances of a component may be labeled with all surfaces of the component. All instances of a component may include associated surfaces of the component, although not every surface is labeled.

[0017] The orientation of various elements in the accompanying drawings is shown as an example, and the examples shown can be rotated relative to the depicted orientation. The description provided herein and the subsequent claims relate to any structure having the relationship between various features, whether these structures are in the specific orientation of the accompanying drawings, or rotated relative to this orientation. Similarly, for ease of description, the spatial relative terms such as "top", "bottom", "below", "below", "below", "above", "upper", "middle", "left", and "right" are used herein to describe the relationship between an element and one or more other elements as shown in the figure. Spatial relative terms are intended to cover different orientations of elements, structures, and / or assemblies in use or operation except for the orientation depicted in the accompanying drawings. Structures and / or assemblies can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly. In addition, in order to simplify the accompanying drawings, unless otherwise indicated, the cross-sectional views in the accompanying drawings only show the features in the cross-sectional plane, without showing the material behind the cross-sectional plane.

[0018] It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Other words used to describe the relationship between elements (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.) should be interpreted in a similar manner.

[0019] In the embodiments described herein or shown in the accompanying drawings, any direct electrical connection or coupling (e.g., any connection or coupling without additional intermediate elements) may also be achieved through an indirect connection or coupling (e.g., a connection or coupling with one or more additional intermediate elements), and vice versa, as long as the general purpose of the connection or coupling, such as transmitting a certain signal or transmitting certain information, is substantially maintained. Features from different embodiments may be combined to form further embodiments. For example, unless otherwise indicated, variations or modifications described with respect to one embodiment of the embodiments may also apply to other embodiments.

[0020] As used herein, the terms "substantially" and "approximately" mean "within reasonable tolerances of manufacturing and measurement." For example, without departing from aspects of the embodiments described herein, the terms "substantially" and "approximately" may be used herein to illustrate small manufacturing tolerances or other factors (e.g., within 5%) that are considered acceptable in the industry. For example, a resistor having an approximate resistance value may actually have a resistance within 5% of the approximate resistance value. As another example, an approximate signal value may actually have a signal value within 5% of the approximate signal value.

[0021] In the present disclosure, expressions including ordinal numbers such as "first", "second", etc. can modify various elements. However, such elements are not limited by the above expression. For example, the above expression does not limit the sequence and / or importance of the elements. The above statement is only used for the purpose of distinguishing an element from other elements. For example, the first frame and the second frame indicate different frames, although both are frames. For another example, without departing from the scope of the present disclosure, the first element can be referred to as the second element, and similarly, the second element can also be referred to as the first element.

[0022] Radar MMICs, sometimes referred to as single radar chips, can combine all the core functions of the radio frequency (RF) front end of a radar transceiver (e.g., local oscillator, power amplifier, low noise amplifier (LNA), mixer, etc.), analog pre-processing of intermediate frequency (IF) or baseband signals (e.g., filters, amplifiers, etc.), and analog-to-digital conversion in a single package. The RF front end typically includes multiple receive (RX) and transmit (TX) channels, especially in applications using beam steering technology, phased antenna arrays, etc. In radar applications, phased antenna arrays can be used to sense the angle of incidence (also known as the "direction of arrival" or DOA) of the incoming RF radar signal.

[0023] The microcontroller acts as a supervisor for the radar MMIC by sending commands and receiving responses over one or more communication channels (e.g., a bus system such as a serial peripheral interface (SPI)). Therefore, the radar MMIC is controlled by the microcontroller. The microcontroller can be a different chip or can be integrated into the same chip as the radar. When the microcontroller is integrated into the same chip as the radar MMIC, the microcontroller can be connected to the radar MMIC via a fast data bus (e.g., an advanced high-performance bus (AHB) or an advanced extensible interface (AXI)), and the memory of the radar MMIC can be directly accessed by the microcontroller.

[0024] The radar MMIC contains one or more central processing units (CPUs) to execute firmware (FW) for implementing various radar MMIC operations, such as receiving, processing, and responding to commands from the microcontroller, startup routines, initialization configuration and settings, error handling, calibration of various radar MMIC hardware blocks, and monitoring one or more radar MMIC operations. The firmware can be embedded in the non-volatile memory (e.g., read-only memory (ROM) or flash memory) of the radar MMIC, downloaded from the microcontroller to the volatile memory (e.g., RAM) of the radar MMIC, or a combination of both.

[0025] However, as radar MMICs become more complex, firmware size is increasing. Therefore, there is an increasing need for larger on-chip memory to store the firmware. Larger on-chip memory generally makes the radar MMIC more expensive to manufacture and increases the size of the radar MMIC, both of which increase system cost. In addition, the firmware stored in the ROM of the radar MMIC cannot be changed after the radar MMIC is manufactured, which can limit the radar MMIC to only execute those radar MMIC operations and settings configured in the ROM. In addition, executing larger firmware in RAM may require increased MMIC startup time because the larger size firmware needs to be transferred to the radar MMIC from an external device such as a microcontroller before the firmware is executed.

[0026] Some embodiments disclosed herein relate to a radar MMIC using multiple programming contexts (e.g., a programming bundle of MMIC firmware and a set of application-specific data), which are executed by the radar MMIC. The microcontroller can be configured to upload the programming context to the radar MMIC (e.g., the radar MMIC can be configured to download the programming context from the microcontroller) to execute a portion of the microcontroller application. The microcontroller can be configured to upload multiple programming contexts sequentially to the radar MMIC for execution by the radar MMIC. The radar MMIC can be configured to remove or overwrite the programming context when the programming context is no longer needed (e.g., after the programming context has been executed) so that memory space can be used for additional programming contexts. Therefore, the microcontroller application can be decomposed into multiple downloadable programming contexts, which are sequentially provided to the radar MMIC from the microcontroller and are overwritten at the radar MMIC as the execution of the downloadable programming context is completed. For example, the radar MMIC can include two or more RAM partitions in its volatile memory to store different downloadable programming contexts one by one. When the microcontroller transmits another programming context to the radar MMIC, the RAM partitions can ensure that the active programming context being executed and the inactive programming context not being executed are not interfered. In addition, a RAM partition (e.g., an inactive RAM partition) can be used to download a downloadable programming context while another RAM partition (e.g., an active RAM partition) is used to execute the active programming context.

[0027] Thus, commands that are only needed in a specific part of the microcontroller application are loaded into volatile memory only when needed, which can reduce the size of the firmware stored at the radar MMIC at any given moment. The programming context can be built and verified before execution, which can reduce the runtime overhead for checking the validity of each configured command. New or updated commands can be included in the downloadable programming context, making the radar MMIC more flexible than radar MMICs that use only ROM-based firmware. Only a small portion of the firmware is transferred to the RAM of the radar MMIC at a time, which can reduce the memory size of the radar MMIC and the MMIC startup time.

[0028] Figure 1 1 is a diagram illustrating an example application of an FMCW radar sensor in the form of a radar sensor 100 for measuring a range, velocity, or angle of arrival (AoA) associated with an object (referred to as a target). Figure 1 As shown, radar sensor 100 may have one or more TX antennas 102 and one or more RX antennas 104. In some implementations, a single antenna may be used that serves as both TX antenna 102 and RX antenna 104.

[0029] In operation, the TX antenna 102 continuously emits an RF signal s RF (t) (also referred to as the transmitted radar signal), which is frequency modulated, for example, by a periodic linear frequency ramp signal (also referred to as a frequency sweep or chirp signal). The transmitted radar signal s RF (t) is backscattered at the target T, and the reflected signal y RF (t) (eg, a backscattered signal, an echo signal, a received RF signal, or a received radar signal) is received by the RX antenna 104 . Figure 1 A simplified example is shown - in practice, the radar sensor 100 may include multiple TX antennas 102 and RX antennas 104 in order to be able to determine the received RF signal y RF The AoA of (t) is improved, and thus the target T can be located with increased accuracy compared to a radar sensor that can use a single TX antenna and / or signal RX antenna.

[0030] It should be understood that "(t)" represents an analog signal, which is defined as a continuous time signal that can vary over a period of time t, and "[n]" represents a digital signal, which is defined as a discrete time signal, where n is an integer and can represent the nth sample or a signal containing n samples. A signal can be represented by or without its continuous time or discrete time domain identifier (t) and [n], respectively. It should also be understood that RF circuits such as radar sensor 100 can be used in areas other than radar. For example, RF circuits can be used in RF communication systems. Therefore, in some embodiments, radar sensor 100 can be used in RF applications other than radar, such as RF communication.

[0031] As shown above, provide Figure 1 As an example. Other examples can be related to Figure 1 Different than described.

[0032] Figure 2 The RF signal s RF (t) is an example of frequency modulation. Figure 2 As shown in the upper view 200, the RF signal s RF (t) comprises multiple frequency ramps or a series of "chirs"; that is, the RF signal s RF (t) A sequence of sinusoidal signal curves (e.g., waveforms) having an increasing frequency (referred to as up-chirp) or a decreasing frequency (referred to as down-chirp). Figure 2 In the example shown, the instantaneous frequency of the chirp, f LO (t) in time interval T CHIRP Internal starting frequency f START Increase linearly to the stop frequency fSTOP ,like Figure 2 210. Such a chirp is also called a linear frequency ramp. For the measurement, a sequence of frequency ramps is emitted and the resulting echo signal is evaluated in baseband to detect one or more radar targets.

[0033] A frequency modulated ramp signal (such as a local oscillator signal used to generate a radar signal) may include multiple radar frames, which may also be referred to as radar operating cycles or chirp frames. A sequence of ramps may constitute each radar frame. For example, a radar operating cycle may include hundreds of radar ramps (sweeps) that take a total of 10-30 milliseconds (ms). The frame length of a radar frame may correspond to one radar operating cycle. Successive ramps may have shorter pauses in between, and longer pauses may be used between consecutive radar frames. The longer pauses between consecutive radar frames may be referred to as a configuration interval, during which the RF signal s may be adjusted for subsequent radar frames. RF (t) One or more ramp parameters. Ramp start time T START The start time for each chirp is indicated and may occur at predetermined intervals according to, for example, a number of clock cycles.

[0034] The starting frequency of the ramp is f START and stop frequency f STOP can be at a minimum frequency F min and the maximum frequency F max Therefore, the minimum frequency F min and the maximum frequency F max defines an operating frequency range or band that can be used for the ramp signal and, therefore, defines a frequency range or band for radar applications of the radar MMIC. In some embodiments, a ramp signal having a start and stop frequency f START and f STOP The frequency range defined by a single ramp of may be smaller than the available radar frequency band. However, all ramps generated during operation may be at frequencies F of the radar frequency band used to generate the ramp signals. min With F max between (e.g., between 76-81 GHz).

[0035] Figure 2 Three identical linear frequency ramps or chirps are shown. However, the parameter f START 、f STOP , T CHIRP, and / or the pauses between individual frequency ramps may vary depending on the actual implementation and / or use of radar sensor 100. In practice, the frequency variation may be, for example, linear (linear ramp, frequency ramp), exponential (exponential ramp), or hyperbolic (hyperbolic ramp). In some embodiments, the frequency may be varied over a time interval T. CHIRP Furthermore, in some embodiments, the center frequency of each ramp (and therefore f START and f STOP ) can be varied (e.g., by ramping or after interference is detected) to allow use of all or a portion of the frequency band. In one example, the frequency band has a minimum frequency F of 76 gigahertz (GHz). min and a maximum frequency F of 81 GHz max .

[0036] Therefore, although in Figure 2 The diagram shows the same starting frequency f START and stop frequency f STOP Three identical linear frequency ramps or chirps, but with a starting frequency f START and stop frequency f STOP The local oscillator signal S can vary within a radar frame or across multiple radar frames. LO (t) can be used to generate the RF signal SRF(t). Therefore, it can be said that the local oscillator signal S LO (t) and the RF signal SRF(t) are frequency modulated ramp signals generated within an operating frequency range (e.g., a predefined radar frequency range). For example, the local oscillator signal S LO (t) may be a frequency modulated ramp signal including a plurality of frequency ramps, each frequency ramp starting at a corresponding ramp start frequency and ending at a corresponding ramp stop frequency, and the corresponding ramp start frequencies and the corresponding ramp stop frequencies of the plurality of frequency ramps define a frequency range within the boundaries of the operating frequency range. The frequency range of the plurality of frequency ramps may be determined by the lowest starting frequency f among the frequency ramps within a given time interval. START and the maximum stop frequency f STOP As described above, the starting frequency f of the frequency ramp sequence is defined as follows (eg, in one embodiment, the frequency increases within each frequency ramp). START and stop frequency f STOP can be the same, so the center frequency of each ramp can be constant. Alternatively, the center frequency of each ramp (and therefore f START and f STOP ) can vary from ramp to ramp or change after interference is detected. The bandwidth (e.g., frequency range) of each ramp can also vary from ramp to ramp or change after interference is detected.

[0037] As shown above, provide Figure 2 As an example. Other examples can be related to Figure 2 Different than described.

[0038] Figure 3 1 is a block diagram illustrating an example structure of a radar sensor 100. As shown, the radar sensor 100 may include one or more TX antennas 102, one or more RX antennas 104, a radar MMIC 106 (including an RF front end 108, a baseband signal processing circuit 110, and an analog-to-digital converter (ADC) 112), a digital signal processor (DSP) 114, and a controller 116. In some embodiments, the MMIC may include a digital front end (DFE) coupled downstream of the ADC 112. The digital front end may include circuit components associated with performing signal processing (e.g., digital filtering) on ​​a digital signal generated by the ADC 112. In some cases, the DFE may include the DSP 114.

[0039] In the radar sensor 100, one or more TX antennas 102 and one or more RX antennas 104 are connected to an RF front end 108. The RF front end 108 may include circuit components associated with performing RF signal processing. These circuit components may include, for example, a local oscillator (LO), one or more RF power amplifiers, one or more LNAs, one or more directional couplers (e.g., ring couplers, circulators, etc.), or one or more mixers for mixing down (e.g., down-converting or demodulating) RF signals to baseband or an intermediate frequency band (IF band). The RF front end 108 may be integrated into the radar MMIC 106 along with one or more other components, such as Figure 3 The IF band is sometimes referred to as the baseband. Therefore, "baseband" and "IF band" are used interchangeably in this article. The baseband signal is the signal on which the radar target is detected.

[0040] An antenna array can be used instead of a single antenna. The depicted example shows a dual-base (or pseudo-monobase) radar system with separate RX and TX antennas. In the case of a monobase radar system, a single antenna or a single antenna array can be used to receive and transmit electromagnetic (radar) signals. In this case, a directional coupler (e.g., a circulator) can be used to separate the RF signal to be transmitted to the radar channel from the RF signal received from the radar channel. In practice, a radar system typically includes several TX and RX channels, which allow the direction (e.g., direction of arrival) of the received radar echo to be measured.

[0041] In some embodiments, the radar sensor 100 may include multiple TX antennas 102 and multiple RX antennas 104, which enables the radar sensor 100 to measure the AoA of received radar echoes. In the case of such a system, a single TX channel and RX channel may be constructed identically or similarly and may be distributed over one or more radar MMICs 106.

[0042] In some embodiments, the signal emitted by TX antenna 102 can be in the range of about 20 GHz to about 100 GHz, such as in the range between about 76 GHz to about 81 GHz. As mentioned, the radar signal received by RX antenna 104 includes radar echoes (e.g., chirp echo signals); that is, those signal components backscattered at one or more targets.

[0043] Received RF signal y RF (t) is mixed down to, for example, baseband to generate a baseband signal y BB (t), and the baseband signal y BB (t) is further processed in baseband by means of analog signal processing performed by baseband signal processing circuit 110. In some embodiments, baseband signal processing circuit 110 may be configured to filter and / or amplify the baseband signal y BB (t) to generate the baseband signal y BB (t) is the analog (baseband) output signal y(t) derived from the baseband signal y BB (t) may also be referred to as analog radar data. If the received RF signal is down-converted to an IF band, the baseband signal processing circuit 110 may be referred to as an IF signal processing circuit. Therefore, the baseband signal processing circuit 110 may also be generally referred to as an analog signal processing circuit.

[0044] ADC 112 may be configured to convert the baseband signal y BB (t) or the analog output signal y(t) is digitized to generate a digital baseband signal y[n], which is also referred to as a digital output signal. The digital baseband signal y[n] represents the received RF signal y RF (t). The DSP 114 may be configured to further process the digital baseband signal y[n] in the digital domain. For example, the DSP 114 may be configured to receive the digital radar data in the digital baseband signal y[n] and process the digital radar data using ramp parameters (e.g., a corresponding ramp start frequency, a corresponding ramp stop frequency, a bandwidth of a frequency range, a ramp start time, or a sampling start time) that are used to generate the received RF signal y RF(t) to generate a range-Doppler map, which can then be further used by the DSP 114 for object detection, classification, etc.

[0045] In some embodiments, the controller 116 is configured to control the operation of the radar sensor 100 (eg, by controlling one or more other components of the radar sensor 100, such as Figure 3 Controller 116 may include, for example, a microcontroller unit (MCU).

[0046] In some embodiments, the RF front end 108, the baseband signal processing circuit 110, the ADC 112, and / or the DSP 114 may be integrated into a single radar MMIC 106 (e.g., an RF semiconductor chip). Alternatively, two or more of these components may be distributed across multiple radar MMICs 106. In some embodiments, the DSP 114 may be included in the controller 116. In some embodiments, techniques associated with TX monitoring and / or RX monitoring may be performed by one or more components of the radar sensor 100, such as by the DSP 114, the controller 116, etc.

[0047] As shown above, provide Figure 3 As an example. Other examples can be related to Figure 3 Different than described. Figure 3 The number and arrangement of devices and components shown are provided as examples. In practice, there may be Figure 3 The devices or components shown may include additional devices or components, fewer devices or components, different devices or components, or differently arranged devices or components. Figure 3 Two or more of the devices or components shown may be implemented in a single device or component, or Figure 3 The single device or component shown may be implemented as multiple distributed devices or components. Additionally or alternatively, Figure 3 The illustrated set of devices or components (e.g., one or more devices or components) may perform the operations described as being performed by Figure 3 Another group of devices or components shown performs one or more functions.

[0048] Figure 44 shows a schematic block diagram of a radar system 400 according to one or more embodiments. The radar system 400 includes a radar MMIC 106 (e.g., a semiconductor chip) and an MCU 405. The radar MMIC 106 includes a transmitter 410 and an MCU 405, wherein the transmitter 410 includes at least one transmit channel 411 for radar signals and / or at least one receive channel 420 for radar signals. The radar MMIC 106 can be considered as part of a radar sensor. The MCU 405 can correspond to a combination of Figure 3 Controller 116 is described.

[0049] The transmit channel 411 may include one or more circuit components and is configured to generate a radar transmit signal and output the radar transmit signal to one or more antennas. Figure 4 As shown, the transmitter 410 may include one or more transmit channels 411. The receive channel 420 may include one or more circuit components and is configured to receive and process one or more radar receive signals from one or more antennas. Figure 4 As shown, the receive channel 420 may include one or more receivers 421 , an analog front end 422 , an ADC 423 , a digital front end 424 , and an interface 425 .

[0050] The analog front end 422 may include all circuit components required for RF signal processing. Such circuit components may (but not necessarily) include, for example, LO, RF power amplifier, LNA, directional coupler (such as ring coupler and circulator), and mixer for down-converting RF signal to baseband or IF band.

[0051] An antenna array can be used instead of a single antenna. The depicted example shows a bistatic (or pseudo-monostatic) radar system with separate RX and TX antennas. In the case of a monostatic radar system, a single antenna or a single antenna array can be used to receive and transmit electromagnetic (radar) signals. In this case, a directional coupler (e.g., a circulator) can be used to separate the RF signal to be transmitted to the radar channel from the RF signal received from the radar channel. In practice, a radar system typically includes several TX and RX channels, which allow the direction (e.g., DoA) of the received radar echo to be measured.

[0052] In the case of an FMCW radar system, the transmitted RF signal radiated by the TX antenna may be in the range between about 20 GHz and 100 GHz (e.g., in the 21 to 26 GHz band or in the 76 to 81 GHz band). As mentioned, the RF signal received by the RX antenna includes radar echoes, such as signals backscattered at so-called radar targets.

[0053] The received RF signal is down-converted to baseband (or IF band) and further processed in baseband using analog signal processing at the analog front end 422, which basically includes filtering and amplification of the baseband signal. If the received RF signal is down-converted to an IF band, the baseband signal processing chain of the analog front end 422 can be referred to as an IF signal processing chain. Therefore, the processing chain of the analog front end 422 can generally be referred to as an analog signal processing chain.

[0054] The baseband signal is finally digitized using an ADC 423 and further processed in the digital domain at a digital front end 424. The digital front end 424 comprises a digital signal processing chain implemented, for example, in a DSP.

[0055] In addition, the radar MMIC 106 may include a configuration and sequencing circuit 430 that is centrally configured to handle configuration requests, execution of commands, storage of programming contexts, execution of programming contexts, activation and deactivation of programming contexts and / or RAM partitions, and return responses to the MCU. The configuration and sequencing circuit 430 may include one or more CPUs that are configured to execute programming contexts (e.g., programs and / or firmware) for implementing various MMIC operations. The configuration and sequencing circuit 430 may also include one or more memory devices, including non-volatile memory (e.g., ROM), volatile memory (e.g., RAM), and one or more hardware registers. In addition, the volatile memory may include multiple volatile memory partitions (e.g., RAM partitions). The volatile memory partitions may be physical partitions with physical memory addresses, or logical partitions, where each logical partition is assigned a different subset of the logical memory addresses of the volatile memory. The non-volatile memory may be used to store a default programming context, which may be copied or loaded into one of the volatile memory partitions for execution by the CPU. Additionally, the volatile memory partition may receive a downloadable programming context from the MCU 405 , which may then be executed by the CPU.

[0056] The configuration and sequencing circuit 430 may include a FW command handler that processes configuration requests and execution requests from the MCU 405, respectively. The FW command handler may be a processing module of the configuration and sequencing circuit 430. The configuration and sequencing circuit 430 may send the results of the executed configuration request and execution request back to the MCU 405. Here, the MCU 405 is configured as a radar driver for driving the radar function of the radar MMIC 106.

[0057] In particular, the configuration and sequencing circuit 430 may determine a sequencing scheme for (e.g., all) time-related functions of the transmitter 410 (i.e., one or more transmit channels 411) and / or the receive channel 420, and also drive circuit elements of the transmitter 410 (i.e., one or more transmit channels 411) and / or the receive channel 420 according to the sequencing scheme. The time-related functions of the transmit channel 411 and / or the receive channel 420 are functions that are executed or implemented in a time-coordinated or synchronized manner with one or more other time-related functions of the transmit channel 411 and / or the receive channel 420 in order to ensure correct operation of the radar sensor or radar system. Therefore, the sequencing scheme represents the execution order of the individual time-related functions in a time-coordinated or synchronized manner.

[0058] For example, the time-related functions may include functions of transmit channel 411 related to generating a radio frequency radar transmit signal, functions of receive channel 420 related to processing a radio frequency radar receive signal, monitoring functions for one or more circuit components of transmit channel 411 and / or receive channel 420, monitoring functions for signals processed by transmit channel 411 and / or receive channel 420, or calibration of transmit channel 411 and / or receive channel 420. For example, the time-related functions may include a transmit calibration function for calibrating the transmit channel, a receive calibration function for calibrating the receive channel, a transmit monitoring function for monitoring the transmit channel, a receive monitoring function for monitoring the receive channel, a ramp function for generating a ramp segment of a ramp signal (e.g., a radar signal), an event monitoring function for monitoring a trigger event, a read function for reading data from a read memory location of radar MMIC 106, or a write function for writing data to a write memory location of radar MMIC 106.

[0059] The configuration and sequencing circuit 430 may receive configuration commands from the MCU 405, each configuration command being directed to one or more executable commands or operation types (e.g., calibration, ramp, monitoring, reading, writing, etc.) and / or configuration parameters for establishing (i.e., configuring) the configured commands. The configured commands may include a single executable command or operation type (referred to as a "handle") or multiple handles, such as a "batch" or "fork". Thus, batch or fork commands may be configured as a bundle of handles (i.e., bundled configuration commands), where each handle corresponds to a different time-related function (i.e., a unique combination of an operation type and a parameter set).

[0060] The read command may instruct the radar MMIC 106 to read data from a specific memory location (e.g., an area including one or more specified registers) of the radar MMIC 106 and transmit the data to the MCU 405. The write command may instruct the radar MMIC 106 to write data received from the MCU 405 to a specific memory location (e.g., an area including one or more specified registers) of the radar MMIC 106.

[0061] Each configured command may include one or more sequence sets or execution flows of time-related functions. Each sequence set may include a command type and one or more configuration parameters constituting a configuration parameter set.

[0062] The execution flow may correspond to a batch command that triggers multiple time-dependent functions to be implemented in a sequential order, in parallel, or a combination thereof. Alternatively, the execution flow may correspond to a forked command that triggers one or more time-dependent functions to be implemented on a conditional basis based on a trigger condition or event.

[0063] The configuration parameters may include calibration parameters of circuit components for the transmit channel 411 , frequency parameters, phase parameters, amplitude parameters, filter configurations, or power parameters for the radar signal, which are ultimately stored in registers of the configuration and sequencing circuit 430 .

[0064] Configuration parameters for the calibration command may include calibration parameters for one or more circuit components (e.g., ADC, power amplifier, voltage controlled oscillator (VCO), filter, etc.), including circuit components of transmit channel 411 and receive channel 420. The calibration parameters may include offset current, anti-kickback, amplification of the VCO, activation of a signal source, etc.

[0065] Configuration parameters for a monitoring command may include parameters for performing a monitoring function, and may identify one or more circuit components targeted for monitoring, and receive and evaluate monitoring feedback from the one or more circuit components.

[0066] Furthermore, the radar signal comprises a plurality of consecutive signal segments. The configuration parameters for the ramp command may include a parameter for indicating a starting frequency f START , stop frequency f STOP The frequency parameter of the corresponding signal segment of the transmission signal, the phase parameter indicating the phase setting for the transmission signal, the duration T of the consecutive signal segments, RAMP, the slope of the frequency ramp, and / or the duration of the pause between adjacent signal segments. For example, the signal segment may correspond to a ramp segment of the frequency ramp of the radar signal. The ramp segment may be a ramp with an increasing frequency (upward ramp) or a decreasing frequency (downward ramp). Whether the ramp segment is an upward ramp or a downward ramp may be implied by the start frequency and the stop frequency, or may be indicated by a configuration parameter.

[0067] The configuration parameters for the read command may specify a memory area or register location of the radar MMIC 106 from which data is to be read.

[0068] The configuration parameters for the write command may specify a memory area or register location of the radar MMIC 106 to which data is to be written.

[0069] The programming context may include a corresponding program (e.g., firmware) and associated data. For example, the corresponding program may include one or more commands and program functions used by these commands. When the programming context is downloaded from the MCU 405 to the radar MMIC 106, its commands are loaded into the executable portion of the RAM partition. Only when the programming context is activated by the configuration and sequencing circuit 430 (e.g., under the instruction of the MCU 405), the radar MMIC 106 can execute the commands of the programming context. The associated data of the programming context may be context-sensitive application data, which may define one or more variables or one or more data sets of the corresponding program. The context-sensitive application data may include radar application cycle data, which includes ramp scenarios, settings, or configurations applicable to the programming context, configured commands, and / or other features of the programming context, such as automatic run information and validity checks. A "different" programming context may be defined as having different corresponding programs and / or different associated data compared to another programming context. Therefore, the configuration and sequencing circuit 430 may execute the same programming context or a different programming context according to the context execution sequence defined by the MCU 405.

[0070] For example, configuration and sequencing circuit 430 may be implemented as dedicated circuitry or circuitry for executing software in conjunction with associated implemented software configured to determine a sequencing scheme and drive circuit elements of transmit channel 411 and / or receive channel 420 according to the sequencing scheme.

[0071] By instructions from the MCU 405, the configuration and sequencing circuit 430 may be configured to add a programming context to a RAM partition of the radar MMIC 106. When a programming context is added to a RAM partition, the programming context is downloaded from the MCU 405 to the radar MMIC 106 and stored in one or more RAM partitions of the radar MMIC 106. However, adding a programming context to the radar MMIC 106 does not change any configuration of the radar MMIC 106 until the programming context is activated. When the radar MMIC 106 downloads the programming context, the programming context may be initially set to a disabled state.

[0072] In some embodiments, a default programming context is stored in a ROM of the radar MMIC 106. The default programming context may include a default program and associated default data stored in the ROM. The configuration and sequencing circuit 430 may automatically load the default programming context from the ROM into one of the RAM partitions for execution. For example, the default programming context may be automatically loaded into one of the RAM partitions during startup or reset of the radar MMIC 106 (e.g., during a boot sequence of the radar MMIC 106). To distinguish the default programming context from the programming context received from the MCU 405, the programming context received from the MCU 405 (e.g., downloaded from the MCU 405) and stored in one of the RAM partitions of the radar MMIC 106 may be referred to as a "downloadable programming context".

[0073] By instructions from the MCU 405, the configuration and sequencing circuit 430 can be configured to activate a programming context. When a programming context is activated, the radar MMIC 106 can use the program and associated data of the programming context to perform, for example, time-related functions defined by the program. In some embodiments, the configuration and sequencing circuit 430 can perform one or more additional actions when activating a programming context. For example, the configuration and sequencing circuit 430 can automatically disable the previous active programming context when activating the next programming context. The programming context can be activated by activating a RAM partition in which the programming context is stored. For example, the RAM partition can be activated by writing the address or index of the RAM partition to a hardware register or fixed memory location of the radar MMIC 106 storing the active context information. Therefore, only one programming context can be activated at a time.

[0074] In some embodiments, a default programming context may be automatically added to a RAM partition during startup or reset of the radar MMIC 106 (e.g., during a boot sequence of the radar MMIC 106), and the RAM partition storing the default programming context may be automatically activated when one or more programming contexts are downloaded from the MCU 405 to the radar MMIC 106. In other words, the default programming context may be automatically loaded from the ROM into a RAM partition and activated for execution during startup or reset of the radar MMIC 106. Thus, a faster startup time of the radar MMIC 106 may be achieved.

[0075] The configuration and sequencing circuit 430 can be configured to disable a programming context by instructions from the MCU 405. Disabling a programming context can invalidate the program and associated data of the programming context so that the program and associated data of the programming context are no longer available. In some embodiments, the disabling of one programming context and the activation of another programming context can be automatically performed in a sequence (e.g., first disabling the current active programming context and then activating the next programming context). In some embodiments, when no additional programming context is downloaded from the MCU 405, a default programming context can be loaded from the ROM to the RAM partition for activation.

[0076] The programming context may be disabled by disabling the RAM partition storing the programming context. For example, the RAM partition may be disabled by deleting or overwriting the address or index of the RAM partition from a hardware register or fixed memory location of the radar MMIC 106 storing the active context information.

[0077] The configuration and sequencing circuitry 430 may be configured to delete a disabled programming context by an instruction from the MCU 405. For example, after a programming context has been executed and disabled, the configuration and sequencing circuitry 430 may delete the programming context from the RAM partition storing the programming context to free up the RAM partition for receiving another programming context from the MCU 405. In some implementations, the programming context may be deleted from the RAM partition by overwriting the programming context with another programming context received from the MCU 405.

[0078] Radar operations of at least one transmit channel 411 on the radar MMIC 106 and / or at least one receive channel 420 on the radar MMIC 106 may be centrally controlled by configuration and sequencing circuitry 430 disposed on the radar MMIC 106 .

[0079] For example, the radar MMIC 106 may be used for a (phase or frequency) modulated continuous wave radar system. Thus, the transmit channel 411 and / or the receive channel 420 may be part of a modulated continuous wave radar system, such as a FMCW radar in the automotive sector. Thus, the configuration and sequencing circuit 430 may be understood as a central sequencing unit that may coordinate all important time-critical functions of an automotive FMCW radar front end, such that the radar operation is an autonomous process that does not require the involvement of an external processor to perform time-critical functions.

[0080] In addition to controlling the desired frequency profile of the radar transmit signal, Figure 4 The configuration and sequencing circuit 430 shown may control various other aspects of a radar sensor or radar system in a synchronized manner.

[0081] For example, in the transmitter 410, and in particular in the transmit channel 411, a power amplifier may be switched on and off in a synchronized manner, or a phase shift of the radar transmit signal (implemented by a phase shifter) may be implemented in a synchronized manner.

[0082] Monitoring of the transmit channel 411 and / or the receive channel 420 may be implemented by the monitoring circuit 440. Thus, the monitoring circuit 440 may be driven by the configuration and sequencing circuit 430 to trigger or activate or disable the channel monitoring function in a synchronized manner according to the sequencing scheme. For example, the monitoring function may be activated or disabled in a synchronized manner during ramp formation, during calibration (e.g., amplification of a voltage-controlled oscillator), during cascade operation, or during configuration of an external component or slave device (e.g., via SPI or demultiplexing).

[0083] In the signal generation circuit 450, for example, the bandwidth of the phase-locked loop (PLL) can be set in a synchronized manner (e.g., charge pump current) or a more extensive modulation concept (e.g., 2-point modulation, reset current) can be activated or disabled. Similarly, for example, the loop filter reset circuit can be activated or disabled in a synchronized manner or the monitoring function can be activated or disabled. In addition, for example, voltages can be roughly set, calibration parameters (e.g., offset current, anti-kickback, amplification of a voltage-controlled oscillator) can be set, or signal sources can be selected (e.g., when multiple PLLs are used).

[0084] In the receiver 421, for example, a digital or analog filter can be set (reset, configure, bypass, etc.) or a decimation rate can be set in a synchronized manner. A low voltage differential signal (LVDS) mode can be selected or calibrated in a synchronized manner. Similarly, the receive channel 420 can also be activated or disabled as a whole or a receive frame delay can be set in a synchronized manner. For example, the ADC 423 can also be configured, calibrated, activated, or disabled in a synchronized manner.

[0085] Likewise, general purpose input / outputs (GPIOs) can be configured in a synchronous manner, circuit components for generating frequency ramps can be triggered, or different circuit components (eg, ADC 423) can be turned on or off. Additionally, interrupts can be generated or other chip functions can be triggered.

[0086] In order to synchronize the time-dependent functions presented by the above examples, the configuration and sequencing circuit 430 may include an instruction processing unit (not shown) having a specific instruction set for determining the sequencing scheme. The instruction set may describe a configuration flow over time and is, for example, similar to an instruction set of a general-purpose processor. For example, the instruction set may include a first specific instruction for configuring the circuit elements of the transmit channel 411 and / or the receive channel 420, and a second specific instruction for configuring the frequency parameters of the radio frequency radar transmit signal generated by the transmit channel 411.

[0087] Therefore, the configuration and sequencing circuit 430 may be understood as a radar-specific sequencing unit having an instruction set associated with a specific purpose in order to handle time-critical configuration in a highly integrated radar chip.

[0088] Figure 4 The controller / MMIC interface 460 shown in FIG. 4 may additionally be used to transmit commands and responses between the MCU 405 and the configuration and sequencing circuit 430 via a communication channel or communication bus, such as SPI, LVDS, or another type of communication interface.

[0089] Power supply unit 470 provides power to chip components and may be configured by configuration and sequencing circuit 430 .

[0090] Various transactions may be performed between the MCU 405 and the configuration and sequencing circuitry 430 through the controller / MMIC interface 460. A transaction is defined by one or more messages that are sent and received between the MCU 405 and the radar MMIC 106 to trigger a command to perform a single task or a group of tasks, and to receive the results of the task(s) performed. Results derived from the type of command performed may be provided from the radar MMIC 106 to the MCU 405 using an SPI channel, an LVDS channel, or a digital output pin of the controller / MMIC interface 460.

[0091] As shown above, provide Figure 4 As an example. Other examples can be related to Figure 4 Different than described. Figure 4 The number and arrangement of devices and components shown are provided as examples. In practice, there may be Figure 4The devices or components shown may include additional devices or components, fewer devices or components, different devices or components, or differently arranged devices or components. Figure 4 Two or more of the devices or components shown may be implemented in a single device or component, or Figure 4 The single device or component shown may be implemented as multiple distributed devices or components. Additionally or alternatively, Figure 4 The illustrated set of devices or components (e.g., one or more devices or components) may perform the operations described as being performed by Figure 4 Another group of devices or components shown performs one or more functions.

[0092] Figure 5 1 shows a schematic block diagram of a radar system 500 according to one or more embodiments. The radar system 500 includes a radar MMIC 106 (eg, a semiconductor chip) and an MCU 405. Figure 4 The diagram of the radar MMIC 106 has been simplified compared to the diagram of the radar MMIC 106 shown in FIG. 4 in order to focus on components corresponding to the configuration and sequencing circuitry 430 and to the storage and execution of programming contexts.

[0093] MCU 405 includes CPU 505 and non-volatile memory 510 (e.g., flash memory). CPU 505 may be configured to control non-volatile memory 510 to perform a write operation for transferring (e.g., uploading) a downloadable programming context to radar MMIC 106 via communication bus 515. For example, non-volatile memory 510 may be configured to store multiple downloadable programming contexts, and non-volatile memory 510 may be configured to transmit the multiple downloadable programming contexts to radar MMIC 106 via communication bus 515 based on instructions received from CPU 505. In some embodiments, non-volatile memory 510 may be configured to sequentially transmit the multiple downloadable programming contexts to radar MMIC 106 one at a time, or in some cases in parallel. In some embodiments, non-volatile memory 510 may be configured to sequentially transmit the multiple downloadable programming contexts to radar MMIC 106 according to a context execution sequence, which is a sequence in which the multiple downloadable programming contexts are to be executed by radar MMIC 106. For example, a time slot may be assigned to each downloadable programming context. The time slot may indicate the time order in which multiple downloadable programming contexts will be executed. Thus, a downloadable programming context may be activated during the time slot assigned to the downloadable programming context in the context execution sequence, and may be disabled in all other instances.

[0094] Multiple downloadable programming contexts may be created at build time of the application software of the MCU 405 so that minimal runtime overhead occurs. Multiple downloadable programming contexts may be stored in the non-volatile memory 510 unencrypted or with some encryption, scrambling, compression, or any combination thereof.

[0095] The CPU 505 may be configured to communicate with the radar MMIC 106 via the communication bus 515. For example, the CPU 505 may transmit commands to the radar MMIC 106. In some embodiments, the commands may indicate a context execution sequence of a plurality of downloadable programming contexts. In some embodiments, the commands may instruct the radar MMIC 106 to report back the results of the executed downloadable programming contexts.

[0096] The radar MMIC 106 includes a CPU 520, a non-volatile memory 525 (e.g., ROM), and a volatile memory 530 (e.g., RAM), the volatile memory 530 including a plurality of partitions, including a first partition P1 and a second partition P2. Although only two partitions are illustrated, the volatile memory 530 may include three or more partitions. The partitions may be physical partitions having physical memory addresses, or logical partitions, where each logical partition is assigned a different subset of the logical memory addresses of the volatile memory 530. The CPU 520 may form a combination of Figure 4 Depicted as part of configuration and sequencing circuitry 430. In some implementations, non-volatile memory 525 and volatile memory 530 may also be considered part of configuration and sequencing circuitry 430.

[0097] In some embodiments, the default programming context may be stored in an external source (e.g., a source external to the volatile memory 530). The default programming context may include a default program and associated default data stored in the external source. The external source may be the non-volatile memory 525, the MCU 405, or another external device (e.g., an external flash memory device). The external source may be configured to load or copy the default programming context into one of the partitions (e.g., the first partition P1 or the second partition P2) at startup or reset of the radar MMIC 106 as part of a boot sequence of the radar MMIC 106 controlled by the CPU 520.

[0098] For example, the non-volatile memory 525 may be configured to store a default programming context. The non-volatile memory 525 may be configured to automatically load or copy the default programming context into one of the partitions (e.g., the first partition P1 or the second partition P2) at startup or reset of the radar MMIC 106 as part of a boot sequence of the radar MMIC 106 controlled by the CPU 520. Thus, as part of the boot sequence, the CPU 520 may be configured to automatically activate the partition storing the default programming context so as to activate the default programming context and execute the activated default programming context. When executing the default programming context, the radar MMIC 106 may be configured to download one or more downloadable programming contexts from the MCU 405 via the communication bus 515 and store the one or more downloadable programming contexts in corresponding partitions of the volatile memory 530.

[0099] The downloadable programming context may be downloaded into an inactive partition of the volatile memory 530. The partitions are configured to store the programming contexts one by one. In other words, each partition is configured to store only a single programming context at a time. Since only one partition may be active at a time, only one programming context may be active at a time. In addition, the number of multiple downloadable programming contexts may be greater than the number of multiple partitions. Therefore, the multiple downloadable programming contexts may be transmitted sequentially to the volatile memory 530.

[0100] In some embodiments, the volatile memory 530 may include or may be associated with a hardware register 535, which is configured to store activation information indicating which partition is activated. For example, the partition may be activated by writing the address or index of the partition into the hardware register 535. All other partitions that do not write the corresponding address or corresponding index into the hardware register 535 may be considered to be disabled. Therefore, the partition may be disabled by removing or overwriting the corresponding address or corresponding index from the hardware register 535. The address or index of the activated partition may be written into the hardware register 535 by the CPU 520. For example, the CPU 520 may be configured to write the address or index of the partition to be activated according to a command or context execution sequence received from the CPU 505 of the MCU 405. Alternatively, the CPU 505 may access the hardware register 535 via the communication bus 515. Therefore, the CPU 505 may be configured to write into the hardware register 535 so as to activate and / or disable the partition of the volatile memory 530 according to the context execution sequence. Thus, when the activation information in the hardware register 535 is updated, the hardware register 535 activates and disables the partition. The CPU 520 can determine which programming context (e.g., which partition) is activated by referring to the hardware register 535. The CPU 520 can be configured to execute the programming context stored in the activated partition identified in the hardware register 535. In addition, the CPU 520 can be configured to transmit the execution result of the activated programming context to the CPU 505 in response to completing the execution of the activated programming context.

[0101] The radar MMIC 106 includes a communication interface (e.g., a controller / MMIC interface 460) configured to sequentially receive multiple downloadable programming contexts from the MCU 405 (e.g., from the non-volatile memory 510). Each downloadable programming context includes a corresponding program and associated data. Multiple partitions of the volatile memory 530 can be configured to sequentially store multiple downloadable programming contexts received from the MCU 405. In some embodiments, one or more of the multiple downloadable programming contexts can be received in parallel. For example, multiple downloadable programming contexts can be transmitted in batches (e.g., one at a time, two at a time, three at a time, etc.). In some embodiments, multiple downloadable programming contexts can be sequentially received according to a context execution sequence to be executed by the CPU 520.

[0102] Each subsequent downloadable programming context received from the MCU 405 is stored in a partition different from the partition used to store the most recent downloadable programming context received from the MCU 405. For example, if the second partition P2 is used to store the most recent downloadable programming context, the first partition P1 (or a third partition, not explicitly shown) may be used to store the next subsequent downloadable programming context received from the MCU 405. Because the programming context stored in the activated partition is being executed, the activated partition cannot be written to.

[0103] Therefore, the configuration and sequencing circuit 430 is configured to sequentially activate and disable multiple downloadable programming contexts according to the context execution sequence, and execute the activated downloadable programming contexts stored in the corresponding activated partitions. The communication interface can be configured to receive the subsequent downloadable programming context before the time slot allocated to the subsequent downloadable programming in the context execution sequence, and the volatile memory 530 can be configured to store the subsequent downloadable programming context.

[0104] The configuration and sequencing circuit 430 may be configured to disable a previously executed downloadable programming context immediately before activating and executing the next downloadable programming context in the context execution sequence. In some embodiments, the volatile memory 530 may be configured to overwrite the previous downloadable programming context with the subsequent downloadable programming context by storing the subsequent downloadable programming context in the same partition as the previous downloadable programming context. Thus, the context execution sequence may include executing the previous downloadable programming context, then executing the next downloadable programming context, then executing the subsequent downloadable programming context. In some embodiments, the download sequence (e.g., the transmission sequence) of multiple downloadable programming contexts may include receiving the previous downloadable programming context, then receiving the next downloadable programming context, then receiving the subsequent downloadable programming context. In some embodiments, the next downloadable programming context to be activated and executed may be the latest downloadable programming context received from the MCU 405.

[0105] In some embodiments, the configuration and sequencing circuitry 430 may be configured to, in response to completing execution of a previous downloadable programming context in the context execution sequence, activate the next downloadable programming context and disable the previous downloadable programming context. In some embodiments, the communication interface may be configured to receive the next downloadable programming context during execution of the previous downloadable programming context, and the volatile memory 530 may be configured to store the next downloadable programming context. In some embodiments, the configuration and sequencing circuitry 430 may be configured to disable the previous downloadable programming context by disabling a partition in the plurality of partitions in which the previous downloadable programming context is stored.

[0106] In some embodiments, the configuration and sequencing circuitry 430 may be configured to activate the subsequent downloadable programming context by activating a partition of the plurality of partitions storing the subsequent downloadable programming context.

[0107] In some embodiments, the plurality of partitions includes only two partitions (e.g., a first partition P1 and a second partition P2) configured to store the plurality of downloadable programming contexts in an alternating sequence according to a context execution sequence. During a startup operation or reset of the radar MMIC 106, the configuration and sequencing circuit 430 may be configured to load a default programming context from an external source (such as the non-volatile memory 525) to the first partition P1 and execute the default programming context from the first partition P1. During execution of the default programming context from the first partition P1, the communication interface of the radar MMIC 106 may be configured to receive a first downloadable programming context of the plurality of downloadable programming contexts from the MCU 405, and the volatile memory 530 may be configured to store the first downloadable programming context in the second partition P2.

[0108] In response to completing execution of the default programming context, the configuration and sequencing circuitry 430 may be configured to disable the default programming context stored in the first partition P1, activate the first downloadable programming context stored in the second partition P2, and execute the activated first downloadable programming context from the second partition P2. In addition, during execution of the first downloadable programming context from the second partition P2, the communication interface of the radar MMIC 106 may be configured to receive a second downloadable programming context of the plurality of downloadable programming contexts from the MCU 405, and the volatile memory 530 may be configured to store the second downloadable programming context in the first partition P1.

[0109] In response to completing execution of the first downloadable programming context, the configuration and sequencing circuitry 430 may be configured to disable the first downloadable programming context stored in the second partition P2, activate the second downloadable programming context stored in the first partition P1, and execute the activated second downloadable programming context from the first partition P1. Additionally, during execution of the second downloadable programming context from the first partition P1, the communication interface of the radar MMIC 106 may be configured to receive a third downloadable programming context of the plurality of downloadable programming contexts from the MCU 405, and the volatile memory 530 may be configured to store the third downloadable programming context in the second partition P2. A similar pattern may be used to receive, store, and execute additional downloadable programming contexts.

[0110] Furthermore, in some implementations, at least one of the plurality of downloadable programming contexts may be configured to access and execute a default program stored in non-volatile memory 525 .

[0111] In some embodiments, one or more of the plurality of downloadable programming contexts may define at least one corresponding frequency ramp sequence of the corresponding ramp signal. Thus, the transmit channel 411 may be configured to generate a corresponding ramp signal corresponding to the activated downloadable programming context as a radar signal.

[0112] In some embodiments, the first downloadable programming context defines a first ramp function for generating a first ramp segment of a first ramp signal to be generated by the transmit channel 411 based on the first downloadable programming context executed by the configuration and sequencing circuit 430 (e.g., by the CPU 520). In addition, the second downloadable programming context may define a second ramp function for generating a second ramp segment of a second ramp signal to be generated by the transmit channel based on the second downloadable programming context executed by the configuration and sequencing circuit 430 (e.g., by the CPU 520). The first ramp signal may be defined by a first parameter set provided in the associated data of the first downloadable programming context. The second ramp signal may be defined by a second parameter set provided in the associated data of the second downloadable programming context. The first parameter set may be different from the second parameter set, such that the first ramp signal is different from the second ramp signal.

[0113] In some embodiments, each of the plurality of downloadable programming contexts includes a set of time-related functions, the time-related functions including at least one of a transmit calibration function for calibrating a transmit channel, a receive calibration function for calibrating a receive channel, a transmit monitoring function for monitoring a transmit channel, a receive monitoring function for monitoring a receive channel, a ramp function for generating a ramp segment of a ramp signal, an event monitoring function for monitoring a trigger event, a read function for reading data from a read memory location of the radar MMIC, or a write function for writing data to a write memory location of the radar MMIC.

[0114] In some implementations, CPU 520 may be configured to transmit the results of the execution of the activated downloadable programming context to MCU 405 (eg, to CPU 505) in response to completing execution of the activated downloadable programming context.

[0115] As shown above, provide Figure 5 As an example. Other examples can be related to Figure 5 Different than described.

[0116] Figure 6 A flow chart of an example process 600 associated with context-based programming according to one or more implementations is illustrated. In some implementations, Figure 6 One or more process blocks of are performed by a radar MMIC (e.g., radar MMIC 106). For example, Figure 6 One or more process blocks of may be performed by configuration and sequencing circuitry 430. In some implementations, Figure 6 One or more process blocks of may be performed by another device or another group of devices separate from or including the radar MMIC, such as the MCU 405. Additionally or alternatively, Figure 6 One or more process blocks of may be performed by one or more components of the radar MMIC, such as the CPU 520 (or another processor), the non-volatile memory 525, and / or the volatile memory 530.

[0117] like Figure 6 As shown, process 600 may include adding a first programming context Context1 to a first RAM partition (block 605), activating the first programming context Context1 (block 610), and running commands from the first programming context Context1 (e.g., executing) (block 615). When the first programming context Context1 is active and executed, process 600 may include adding a second programming context Context2 to a second RAM partition (block 620). After completing the execution of the first programming context Context1, process 600 may include disabling the first programming context Context1 (block 625), activating the second programming context Context2 (block 630), and running commands from the second programming context Context2 (e.g., executing) (block 635). During the disabling of the first programming context Context1, the first programming context Context1 may be deleted from the first RAM partition.

[0118] As shown above, provide Figure 6 As an example. Other examples can be related to Figure 6 Different than described.

[0119] Figure 7 1 shows a schematic block diagram of a radar system 700 according to one or more embodiments. The radar system 700 may be similar to a combination of Figure 5 Radar system 500 is depicted. Thus, radar system 700 includes radar MMIC 106 (eg, semiconductor chip) and MCU 405 .

[0120] The radar MMIC 106 has two or more RAM partitions in the volatile memory 530 (e.g., in RAM). For example, two partitions are shown including a first partition P1 and a second partition P2. Each partition stores context-specific application data and a program corresponding to a corresponding programming context. The partitions can be implemented by physical or logical separation of RAM blocks. There can be more than one RAM block allocated to context-specific application data and a program for a corresponding programming context. For example, the first partition P1 can have more than one RAM block for storing context-specific application data and more than one RAM block for storing programs.

[0121] To activate one of the RAM partitions, the radar MMIC 106 may store active context information (such as the address or index of the RAM partition) in hardware registers 535 or in a fixed memory location. Only one context may be active at a time.

[0122] At startup, a boot routine of the radar MMIC 106 may load a default programming context from the non-volatile memory 525 (eg, ROM) into one of the RAM partitions and set the active context information to correspond to the RAM partition containing the default programming context.

[0123] The MCU 405 may interact with the radar MMIC 106 by adding a new programming context to the inactive RAM partition, interacting with the current programming context by executing commands and obtaining results using context-specific application data, changing the active programming context by writing active context information to hardware registers 535, and / or triggering the radar MMIC to perform other MMIC features not handled by the firmware (e.g., hardware triggers).

[0124] In addition to the programming context, the radar MMIC 106 may have common application data and programs. The common application data and programs are always available regardless of which programming context is loaded or activated. The common programs may include necessary routines or functions required by many contexts (e.g., for reading and writing registers). The common application data may include a program stack and global variables.

[0125] As shown above, provide Figure 7 As an example. Other examples can be related to Figure 7 Different than described.

[0126] Figure 8 A flow chart of an example process 800 associated with context-based programming according to one or more implementations is illustrated. In some implementations, Figure 8One or more process blocks of are performed by a radar MMIC (e.g., radar MMIC 106). For example, Figure 8 One or more process blocks of may be performed by configuration and sequencing circuitry 430. In some implementations, Figure 8 One or more process blocks of may be performed by another device or another group of devices separate from or including the radar MMIC, such as the MCU 405. Additionally or alternatively, Figure 8 One or more process blocks of may be performed by one or more components of the radar MMIC, such as the CPU 520 (or another processor), the non-volatile memory 525, and / or the volatile memory 530.

[0127] like Figure 8 As shown, process 800 may include performing power-on initialization (block 805) and power-on calibration (block 810). During power-on initialization, MCU 405 may initialize radar MMIC 106, including configuring power, clock, and other system functions. During power-on calibration, MCU 405 may run a calibration of radar MMIC 106, referred to as power-on calibration.

[0128] After power-on initialization and power-on calibration, MCU 405 can use radar MMIC 106 to execute multiple application cycles 1-7 (boxes 815-845). Each application cycle runs by executing a corresponding programming context (e.g., a default programming context or a downloadable programming context). For example, each application cycle can configure radar MMIC 106 to perform a corresponding radar measurement, such as by transmitting a corresponding radar signal to perform a corresponding radar measurement, which radar signal may include a plurality of frequency ramp sequences constituting a ramp scenario. In some embodiments, application cycle 1 may be a default application cycle, during which a default programming context is loaded, activated, and executed. Depending on the measurement requirements controlled by MCU 405, application cycles 1-7 may use the same or different programming contexts. In other words, all programming contexts may be the same, some programming contexts may be the same and some programming contexts may be different, or all programming contexts may be different.

[0129] When an error is encountered anywhere in the application flow, the MCU 405 can reset the application cycle loop or reset the radar MMIC 106.

[0130] As shown above, provide Figure 8 As an example. Other examples can be related to Figure 8 Different than described.

[0131] Fig. 9An example application cycle 900 according to one or more embodiments is illustrated. The application cycle 900 may include a radar operation duty cycle, including an on period and an off period. During the on period, the radar MMIC 106 may be configured to perform a warm-up calibration before running a ramp scenario defined by a programming context. In addition, during the on period, the radar MMIC 106 is configured to perform a ramp scenario, during which multiple frequency ramp sequences (e.g., frequency ramp sequence 1, frequency ramp sequence 2, and frequency ramp sequence 3) are transmitted according to the ramp parameters defined in the associated data of the programming context. In this example, the frequency ramp sequence is generated according to different ramp parameter sets. Different programming contexts may define the same or different frequency ramp sequences. The radar MMIC may perform a setup operation between frequency ramp sequences, which may be used to change one or more settings or may be used to perform calibration between frequency ramp sequences.

[0132] In addition, during the on period, the radar MMIC 106 is configured to perform monitoring of the reflected radar signal. During the off period, the radar MMIC 106 may continue to monitor the reflected radar signal, but no longer transmit the radar signal. Therefore, during the off period, the radar MMIC 106 may be configured to enter a reduced power consumption mode. During the off period, the MCU 405 may process the monitoring results reported to the MCU 405 by the radar MMIC 106 via signal processing.

[0133] The application cycles can differ in the following ways: by the type of calibration and monitoring performed, and which ramp scenario is used. Typically, calibration and monitoring are time consuming. Therefore, calibration and monitoring can be split into more than one application cycle, which is specified in multiple programming contexts. A ramp scenario includes a frequency ramp sequence, which further includes a ramp set (e.g., shown as a triangular waveform). The ramp setting can be at a starting frequency f START , frequency ramp slope, stop frequency f STOP , Ramp start time T START , time interval T CHIRP , transmit power, and transmit phase. In addition, if there are multiple transmit channels, a ramp set can be defined based on which transmit channel is used to transmit the ramp set.

[0134] As shown above, provide Fig. 9 As an example. Other examples can be related to Fig. 9 Different than described.

[0135] The following provides an overview of some aspects of the disclosure:

[0136] Aspect 1: A radar monolithic microwave integrated circuit (MMIC), comprising: at least one of a transmit channel for transmitting a radar signal or a receive channel for receiving a reflected radar signal; a communication interface configured to sequentially receive a plurality of downloadable programming contexts from an external controller, wherein each downloadable programming context includes a corresponding program and associated data; a random access memory (RAM) including a plurality of partitions configured to sequentially store the plurality of downloadable programming contexts received from the external controller, wherein each subsequent downloadable programming context received from the external controller is stored in a partition different from a partition for storing a latest downloadable programming context received from the external controller; and a configuration and sequencing circuit configured to: sequentially activate and deactivate the plurality of downloadable programming contexts according to a context execution sequence, and execute an activated downloadable programming context stored in a corresponding partition of the plurality of partitions, wherein the communication interface is configured to receive a subsequent downloadable programming context before a time slot allocated to the subsequent downloadable programming context in the context execution sequence, and the RAM is configured to store the subsequent downloadable programming context.

[0137] Aspect 2: The radar MMIC according to aspect 1, wherein the configuration and sequencing circuit is configured to disable a previously executed downloadable programming context immediately before activating and executing a next downloadable programming context in the context execution sequence.

[0138] Aspect 3: The radar MMIC according to aspect 2, wherein the RAM is configured to overwrite a previous downloadable programming context with a subsequent downloadable programming context by storing the subsequent downloadable programming context in the same partition as the previous downloadable programming context.

[0139] Aspect 4: The radar MMIC according to aspect 2, wherein the configuration and sequencing circuit is configured to activate the next downloadable programming context and disable the previous downloadable programming context in response to completion of execution of the previous downloadable programming context in the context execution sequence.

[0140] Aspect 5: The radar MMIC according to aspect 2, wherein the communication interface is configured to receive a next downloadable programming context during execution of a previous downloadable programming context, and the RAM is configured to store the next downloadable programming context.

[0141] Aspect 6: The radar MMIC of aspect 2, wherein the configuration and sequencing circuit is configured to disable the previously downloadable programming context by disabling a partition of the plurality of partitions in which the previously downloadable programming context is stored.

[0142] Aspect 7: The radar MMIC according to any of aspects 1-6, wherein the plurality of partitions consists of two partitions configured to store the plurality of downloadable programming contexts in an alternating sequence according to a context execution sequence.

[0143] Aspect 8: The radar MMIC according to any of aspects 1-7, wherein the configuration and sequencing circuit is configured to activate the subsequent downloadable programming context by activating a partition of the plurality of partitions in which the subsequent downloadable programming context is stored.

[0144] Aspect 9: A radar MMIC according to any of Aspects 1-8, wherein: during a startup operation or reset of the radar MMIC, the configuration and sequencing circuit is configured to load a default programming context from an external source to a first partition of the plurality of partitions and execute the default programming context from the first partition, wherein the default programming context includes a default program and associated default data, and wherein, during execution of the default programming context from the first partition, the communication interface is configured to receive a first downloadable programming context of the plurality of downloadable programming contexts from an external controller, and the RAM is configured to store the first downloadable programming context in a second partition of the plurality of partitions.

[0145] Aspect 10: The radar MMIC according to any of Aspects 1-9 further includes: a non-volatile memory configured to store a default programming context including a default program and associated default data, wherein, during a startup operation or reset of the radar MMIC, the configuration and sequencing circuit is configured to load the default programming context from the non-volatile memory to a first partition of the plurality of partitions and execute the default programming context from the first partition, and wherein, during execution of the default programming context from the first partition, the communication interface is configured to receive a first downloadable programming context of the plurality of downloadable programming contexts from an external controller, and the RAM is configured to store the first downloadable programming context in a second partition of the plurality of partitions.

[0146] Aspect 11: The radar MMIC of aspect 10, wherein at least one of the plurality of downloadable programming contexts is configured to access and execute a default program stored in the non-volatile memory.

[0147] Aspect 12: A radar MMIC according to aspect 10, wherein, in response to completing execution of the default programming context, the configuration and sequencing circuit is configured to disable the default programming context stored in the first partition, activate the first downloadable programming context stored in the second partition, and execute the activated first downloadable programming context from the second partition, and wherein during execution of the first downloadable programming context from the second partition, the communication interface is configured to receive a second downloadable programming context of the plurality of downloadable programming contexts from an external controller, and the RAM is configured to store the second downloadable programming context in the first partition.

[0148] Aspect 13: A radar MMIC according to aspect 12, wherein, in response to completing execution of the first downloadable programming context, the configuration and sequencing circuit is configured to disable the first downloadable programming context stored in the second partition, activate the second downloadable programming context stored in the first partition, and execute the activated second downloadable programming context from the first partition, and wherein during execution of the second downloadable programming context from the first partition, the communication interface is configured to receive a third downloadable programming context of the plurality of downloadable programming contexts from an external controller, and the RAM is configured to store the third downloadable programming context in the second partition.

[0149] Aspect 14: A radar MMIC according to any of Aspects 1-13, wherein one or more of the plurality of downloadable programmable contexts define at least one corresponding frequency ramp sequence of a corresponding ramp signal, and wherein the transmit channel is configured to generate a corresponding ramp signal corresponding to the activated downloadable programmable context as a radar signal.

[0150] Aspect 15: A radar MMIC according to any of Aspects 1-14, wherein a first downloadable programmable context defines a first ramp function for generating a first ramp segment of a first ramp signal to be generated by a transmit channel based on the first downloadable programmable context executed by a configuration and sequencing circuit, wherein a second downloadable programmable context defines a second ramp function for generating a second ramp segment of a second ramp signal to be generated by a transmit channel based on the second downloadable programmable context executed by the configuration and sequencing circuit, wherein the first ramp signal is defined by a first parameter set provided in associated data of the first downloadable programmable context, wherein the second ramp signal is defined by a second parameter set provided in associated data of the second downloadable programmable context, and wherein the first parameter set is different from the second parameter set.

[0151] Aspect 16: A radar MMIC according to any of Aspects 1-15, wherein each of the multiple downloadable programmable contexts includes a set of time-related functions, wherein the time-related functions include at least one of the following: a transmit calibration function for calibrating a transmit channel, a receive calibration function for calibrating a receive channel, a transmit monitoring function for monitoring a transmit channel, a receive monitoring function for monitoring a receive channel, a ramp function for generating a ramp segment of a ramp signal, an event monitoring function for monitoring a trigger event, a read function for reading data from a read memory location of the radar MMIC, or a write function for writing data to a write memory location of the radar MMIC.

[0152] Aspect 17: The radar MMIC according to any of aspects 1-16, wherein the configuration and sequencing circuit is configured to transmit a result of the execution of the activated downloadable programming context to the external controller in response to completion of the execution of the activated downloadable programming context.

[0153] Aspect 18: The radar MMIC according to any of aspects 1-17, wherein the communication interface is configured to sequentially receive the plurality of downloadable programming contexts from the external controller according to a context execution sequence.

[0154] Aspect 19: The radar MMIC according to any of aspects 1-18, wherein the communication interface is configured to receive a subsequent downloadable programming context during execution of the activated downloadable programming context, and the RAM is configured to store the subsequent downloadable programming context.

[0155] Aspect 20: The radar MMIC according to any one of aspects 1-19, wherein the activated downloadable programming context is the latest downloadable programming context received from the external controller.

[0156] Aspect 21: A method for configuring a radar monolithic microwave integrated circuit (MMIC) and executing commands of an activated downloadable programming context, the method comprising: receiving and storing a plurality of downloadable programming contexts sequentially received from an external controller, wherein each downloadable programming context includes a corresponding program and associated data, wherein each subsequent downloadable programming context received from the external controller is stored in a random access memory (RAM) partition of the radar MMIC that is different from the RAM partition of the radar MMIC used to store the most recent downloadable programming context received from the external controller; sequentially activating and deactivating the plurality of downloadable programming contexts according to a context execution sequence; executing commands of the activated downloadable programming context stored in the corresponding RAM partition; and downloading the next downloadable programming context before a time slot allocated to the next downloadable programming context in the context execution sequence.

[0157] Aspect 22: The method according to Aspect 21, further comprising: before executing the command of the activated downloadable programming context, disabling a previous downloadable programming context that has been executed immediately before activating and executing the activated downloadable programming context in the context execution sequence.

[0158] Aspect 23: The method according to any one of Aspects 21-22 further includes: during a startup operation or reset of the radar MMIC, loading a default programming context from a non-volatile memory of the radar MMIC to a first RAM partition of the radar MMIC, and executing the default programming context from the first RAM partition; and during execution of the default programming context from the first RAM partition, receiving a first downloadable programming context of a plurality of downloadable programming contexts from an external controller, and storing the first downloadable programming context in a second RAM partition of the radar MMIC.

[0159] Aspect 24: A system configured to perform one or more operations described in one or more of Aspects 1-23.

[0160] Aspect 25: An apparatus comprising means for performing one or more operations described in one or more of Aspects 1-23.

[0161] Aspect 26: A non-transitory computer-readable medium storing an instruction set, the instruction set comprising one or more instructions, which when executed by a device causes the device to perform one or more operations described in one or more of aspects 1-23.

[0162] Aspect 27: A computer program product comprising instructions or codes for performing one or more operations described in one or more of Aspects 1-23.

[0163] The foregoing disclosure provides illustration and description, but is not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. Modifications and variations may be made in light of the above disclosure or may be acquired from practice of the embodiments.

[0164] As used herein, the term "component" is intended to be broadly interpreted as hardware, firmware, or a combination of hardware and software. Obviously, the systems and / or methods described herein can be implemented in different forms of hardware, firmware, or a combination of hardware and software. The actual dedicated control hardware or software code used to implement these systems and / or methods does not limit the implementation. Therefore, the operation and behavior of the system and / or method are described herein without mentioning specific software code-it should be understood that software and hardware can be designed based on the description herein to implement the system and / or method.

[0165] Any component in the processing component can be implemented as a central processing unit (CPU) or other processor, reading and executing a software program from a non-transient computer-readable recording medium such as a hard disk or a semiconductor memory device. For example, instructions can be executed by one or more processors, such as one or more CPUs, DSPs, general-purpose microprocessors, application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic controllers (PLCs), or other equivalent integrated or discrete logic circuit devices. Therefore, the term "processor" as used herein refers to any structure in the aforementioned structure or any other structure suitable for implementing the technology described herein. Software can be stored on a non-transient computer-readable medium, so that the non-transient computer-readable medium includes a program code or a program algorithm stored thereon, and the program code or program algorithm causes the processor to perform the steps of the method via a computer program when executed.

[0166] A controller including hardware may also perform one or more of the techniques of the present invention. A controller including one or more processors may use electrical signals and digital algorithms to perform its reception, analysis, and control functions, which may further include correction functions. Such hardware, software, and firmware may be implemented in the same device or in separate devices to support the various techniques described in the present invention.

[0167] Signal processing circuits and / or signal conditioning circuits may receive one or more signals (e.g., measurement signals) from one or more components in the form of raw measurement data, and may derive further information from the measurement signals. As used herein, signal conditioning refers to manipulating an analog signal in a manner that causes the signal to meet the requirements of further processing at the next stage. Signal conditioning may include conversion from analog to digital (e.g., via an analog-to-digital converter), amplification, filtering, conversion, biasing, range matching, isolation, and any other process required to make the signal suitable for processing after conditioning.

[0168] Some embodiments may be described herein in conjunction with a threshold value. As used herein, satisfying a threshold value may refer to a value greater than a threshold value, more than a threshold value, higher than a threshold value, greater than or equal to a threshold value, less than a threshold value, less than a threshold value, lower than a threshold value, less than or equal to a threshold value, equal to a threshold value, etc.

[0169] Although the specific combination of features is recorded in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of the embodiments described herein. Many of these features can be combined in a manner not specifically recorded in the claims and / or not disclosed in the specification. For example, the disclosure includes the combination of each dependent claim in the claim set with each other individual claim in the claim set and each combination of multiple claims in the claim set. As used herein, the phrase "at least one" in the reference project list refers to any combination of these projects, including a single member. For example, "at least one of a, b, or c" is intended to cover a, b, c, a+b, a+c, b+c, and a+b+c, and any combination of multiple identical elements (for example, a+a, a+a+a, a+a+b, a+a+c, a+b+b, a+c+c, b+b, b+b+b, b+b+c, c+c, and c+c+c, or any other order of a, b, and c).

[0170] In addition, it should be understood that the disclosure of multiple actions or functions disclosed in the specification or claims cannot be interpreted as being in a specific order. Therefore, unless these actions or functions are not interchangeable due to technical reasons, the disclosure of multiple actions or functions will not limit them to a specific order. In addition, in some embodiments, a single action may include or may be decomposed into multiple sub-actions. Unless explicitly excluded, sub-actions may be included in the disclosure of this single action and may be part of the disclosure of this single action.

[0171] Any element, action or instruction used herein should not be interpreted as critical or necessary, unless clearly described in this way. In addition, as used herein, the article "one" and "an" are intended to include one or more projects, and can be used interchangeably with "one or more". In addition, as used herein, the article "the" is intended to include one or more projects quoted in conjunction with the article "the", and can be used interchangeably with "the one or more". In the case of only being intended to a project, phrases "only one", "single" or similar language are used. In addition, as used herein, the term "have", "have", "contain" etc. are intended to be open terms, and the open terms do not limit the elements modified by them (for example, "the element with" A can also have B). In addition, the phrase "based on" is intended to mean "at least partially based on", unless otherwise clearly stated. In addition, as used herein, the term "or" is intended to be inclusive when used in series, and can be used interchangeably with "and / or", unless otherwise clearly stated (for example, if used in combination with "or" or "only one of them").

Claims

1. A radar monolithic microwave integrated circuit MMIC, comprising: at least one of a transmit channel or a receive channel, the transmit channel being used to transmit the radar signal and the receive channel being used to receive the reflected radar signal; a communication interface configured to sequentially receive a plurality of downloadable programming contexts from an external controller, wherein each downloadable programming context includes a corresponding program and associated data; a random access memory RAM comprising a plurality of partitions configured to sequentially store the plurality of downloadable programming contexts received from the external controller, wherein each subsequent downloadable programming context received from the external controller is stored in a partition different from a partition used to store a most recent downloadable programming context received from the external controller; as well as Configuration and sequencing circuitry, configured to: sequentially activating and deactivating the plurality of downloadable programming contexts according to a context execution sequence, and executing an activated downloadable programming context stored in a corresponding partition of the plurality of partitions, The communication interface is configured to receive a subsequent downloadable programming context prior to a time slot allocated to the subsequent downloadable programming context in the context execution sequence, and the RAM is configured to store the subsequent downloadable programming context.

2. The radar MMIC of claim 1 , wherein the configuration and sequencing circuitry is configured to disable a previously executed downloadable programming context before activating and executing a next downloadable programming context in the context execution sequence.

3. The radar MMIC of claim 2 , wherein the RAM is configured to overwrite the previous downloadable programming context with the subsequent downloadable programming context by storing the subsequent downloadable programming context in the same partition as the previous downloadable programming context.

4. The radar MMIC of claim 2 , wherein the configuration and sequencing circuitry is configured to, in response to completion of execution of the previous downloadable programming context in the context execution sequence, activate the next downloadable programming context and disable the previous downloadable programming context. 5 . The radar MMIC of claim 2 , wherein the communication interface is configured to receive the next downloadable programming context during execution of the previous downloadable programming context, and the RAM is configured to store the next downloadable programming context. 6 . The radar MMIC of claim 2 , wherein the configuration and sequencing circuitry is configured to disable the previously downloadable programming context by disabling a partition of the plurality of partitions in which the previously downloadable programming context is stored. 7 . The radar MMIC of claim 1 , wherein the plurality of partitions consists of two partitions configured to store the plurality of downloadable programming contexts in an alternating sequence according to the context execution sequence.

8. The radar MMIC of claim 1 , wherein the configuration and sequencing circuit is configured to: activate the subsequent downloadable programming context by activating a partition of the plurality of partitions in which the subsequent downloadable programming context is stored.

9. The radar MMIC of claim 1, wherein: During a startup operation or reset of the radar MMIC, the configuration and sequencing circuit is configured to: load a default programming context from an external source into a first partition of the plurality of partitions and execute the default programming context from the first partition, wherein the default programming context includes a default program and associated default data, and Wherein, during execution of the default programming context from the first partition, the communication interface is configured to: receive a first downloadable programming context of the multiple downloadable programming contexts from the external controller, and the RAM is configured to store the first downloadable programming context in a second partition of the multiple partitions.

10. The radar MMIC of claim 1, further comprising: a non-volatile memory configured to store a default programming context, the default programming context comprising a default program and associated default data, wherein, during a startup operation or reset of the radar MMIC, the configuration and sequencing circuit is configured to: load the default programming context from the non-volatile memory to a first partition of the plurality of partitions and execute the default programming context from the first partition, and Wherein, during execution of the default programming context from the first partition, the communication interface is configured to receive a first downloadable programming context of the plurality of downloadable programming contexts from the external controller, and the RAM is configured to store the first downloadable programming context in a second partition of the plurality of partitions. 11 . The radar MMIC of claim 10 , wherein at least one of the plurality of downloadable programming contexts is configured to access and execute the default program stored in the non-volatile memory.

12. The radar MMIC according to claim 10, wherein: In response to completing execution of the default programming context, the configuration and sequencing circuitry is configured to: disable the default programming context stored in the first partition, activate the first downloadable programming context stored in the second partition, and execute the activated first downloadable programming context from the second partition, and wherein during execution of the first downloadable programming context from the second partition, the communication interface is configured to receive a second downloadable programming context of the plurality of downloadable programming contexts from the external controller, and the RAM is configured to store the second downloadable programming context in the first partition.

13. The radar MMIC according to claim 12, wherein: In response to completing execution of the first downloadable programming context, the configuration and sequencing circuitry is configured to: disable the first downloadable programming context stored in the second partition, activate the second downloadable programming context stored in the first partition, and execute the activated second downloadable programming context from the first partition, and wherein during execution of the second downloadable programming context from the first partition, the communication interface is configured to receive a third downloadable programming context of the plurality of downloadable programming contexts from the external controller, and the RAM is configured to store the third downloadable programming context in the second partition.

14. The radar MMIC of claim 1 , wherein one or more of the plurality of downloadable programming contexts define at least one corresponding frequency ramp sequence of a corresponding ramp signal, and The transmit channel is configured to generate the corresponding ramp signal corresponding to the activated downloadable programmable context as a radar signal.

15. The radar MMIC of claim 14 , wherein a first downloadable programmable context defines a first ramp function for generating a first ramp segment of a first ramp signal to be generated by the transmit channel based on the first downloadable programmable context executed by the configuration and sequencing circuitry, wherein a second downloadable programmable context defines a second ramp function for generating a second ramp segment of a second ramp signal to be generated by the transmit channel based on the second downloadable programmable context executed by the configuration and sequencing circuitry, wherein a first ramp signal is defined by a first set of parameters, said first set of parameters being provided in said associated data of said first downloadable programming context, wherein the second ramp signal is defined by a second set of parameters, the second set of parameters being provided in the associated data of the second downloadable programming context, and The first parameter set is different from the second parameter set.

16. The radar MMIC of claim 1 , wherein each of the plurality of downloadable programming contexts comprises a set of time-dependent functions, The time-related functions include at least one of the following functions: a transmit calibration function for calibrating the transmit channel, a receive calibration function for calibrating the receive channel, a transmit monitoring function for monitoring the transmit channel, a receive monitoring function for monitoring the receive channel, a ramp function for generating a ramp segment of a ramp signal, an event monitoring function for monitoring a trigger event, a read function for reading data from a read memory location of the radar MMIC, or a write function for writing data to a write memory location of the radar MMIC. 17 . The radar MMIC of claim 1 , wherein the configuration and sequencing circuit is configured to transmit a result of the execution of the activated downloadable programming context to the external controller in response to completing the execution of the activated downloadable programming context. 18 . The radar MMIC of claim 1 , wherein the communication interface is configured to sequentially receive a plurality of downloadable programming contexts from the external controller according to the context execution sequence.

19. The radar MMIC of claim 1, wherein the communication interface is configured to receive the subsequent downloadable programming context during execution of the activated downloadable programming context, and the RAM is configured to store the subsequent downloadable programming context.

20. The radar MMIC of claim 1, wherein the activated downloadable programming context is a most recent downloadable programming context received from the external controller.

21. A method for configuring a radar monolithic microwave integrated circuit (MMIC) and executing commands of an activated downloadable programming context, the method comprising: receiving and storing a plurality of downloadable programming contexts sequentially received from an external controller, wherein each downloadable programming context includes a respective program and associated data, wherein each subsequent downloadable programming context received from the external controller is stored in a random access memory (RAM) partition of the radar MMIC that is different from a random access memory (RAM) partition of the radar MMIC used to store a most recent downloadable programming context received from the external controller; sequentially activating and deactivating the plurality of downloadable programming contexts according to the context execution sequence; executing the command of the activated downloadable programming context stored in the corresponding RAM partition; and The next downloadable programming context is downloaded prior to a time slot allocated to the next downloadable programming context in the context execution sequence.

22. The method according to claim 21, further comprising: Prior to executing the command of the activated downloadable programming context, a previous downloadable programming context that had been executed immediately before activating and executing the activated downloadable programming context in the context execution sequence is disabled.

23. The method according to claim 21, further comprising: during a startup operation or reset of the radar MMIC, loading a default programming context from a non-volatile memory of the radar MMIC to a first RAM partition of the radar MMIC, and executing the default programming context from the first RAM partition; and During execution of the default programming context from the first RAM partition, a first downloadable programming context of the plurality of downloadable programming contexts is received from the external controller and the first downloadable programming context is stored in a second RAM partition of the radar MMIC.

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